ourdev 598703 tpwcm7
TRANSCRIPT
© 2010 Altera Corporation—Confidential
Designing Embedded Systems Easily and Quickly with FPGAs
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.2
Agenda
System Design Challenge
How to tackle the Challenge●
Diversity of options integrating FPGA and CPU technologies
o Altera Nios II, ARM Cortex-M1 and -A9, and MP32 processorso Intel’s Atom-based processor
●
Single FPGA design flow through Quartus II softwareo New Qsys system-level integration tool
Nios II Processor
Summary
© 2010 Altera Corporation—Confidential
“Embedded Systems” in Altera FPGAs?
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.4
Flash
SDRAM
CPU
DSP
I/O
I/O
CPU
I/O FPGA
I/O I/O I/O
CPU DSP
System Design Challenges
FPGA
Too expensive, need to reduce
cost
Changing standard requires new device and board redesign
Marketing requires new
features to stay competitive
Need to reduceboard size to meet form
factor requirements
16-week lead time, must qualify 2nd
source
Obsolete in two years, must
support for seven
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.5
System-Level Integration
Flash
SDRAM
CPU
DSP
I/O
I/O
CPU
I/O FPGAFPGA
I/O I/O I/O
CPU DSP
Solution: integrate external devices within programmable device
CPU
System Design Challenges
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
How Altera tackles the challenge?
Altera is launching an Embedded Initiative providing embedded system designers:●
Diversity of options integrating FPGA and CPU technologies
o In alliance with major embedded processor partners
●
Single FPGA design flow for these optionso New system-level integration toolo Support for range of devices using Altera FPGA technology
6
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Widest Array of FPGA-Enabled Embedded Options Unified with a Single FPGA Tool Flow
7
MP32 Cortex-M1 Cortex-A9
Atom E600Configurable
Processor
NewQsys
RTL Synthesis
Place and Route
PowerPlay
TimeQuest
….
NewNew New
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
What is Driving this Initiative?
Trends Needs
More combinations of CPU and reconfigurable accelerators
Continued bill of materials (BoM) reduction
More OS options for FPGA-based CPUs
Single FPGA design flow targeting the widest array of options
Multicore + hardware acceleration - CPUs at power limit - Power-efficiency
more critical
FPGAs increasingly used in embedded systems
More FPGA-enabled embedded options
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
New Offering: ARM Cortex-A9 + FPGA
Altera will deliver a family of devices that integrates hardened ARM®
Cortex™-A9-based subsystems with
28-nm FPGA technology●
Earlier this year, Altera signed an agreement with ARM Ltd. to license a range of technologies, including the Cortex-A9 MPCore™
●
One of ARM’s highest performance cores, with multi-core capability
●
More detailed information will be made available in 2011
9
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
New Offering: MP32 + FPGA
Altera is broadening its portfolio of soft processor cores with the MP32 soft core●
Based on MIPS32®
processor architecture from MIPS®
Technologies
●
MP32 will complement Altera’s Nios II processor and the portfolio of partner soft CPUs available for Altera devices ●
Altera deeply committed to Nios II. Remains preferred option for most applications, which can leverage existing Nios II ecosystem.
●
MP32 extends Operating Systems available for soft CPUs beyond what is currently available on Nios II.
10
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
New Offering: Qsys System-Level Integration Tool
Powerful productivity tool for quickly assembling a system●
Successor to Altera’s SOPC Builder tool
Introduces FPGA-optimized network-on-a-chip technology●
Up to 2X performance increase of memory-mapped and datapath interconnects compared to SOPC Builder
Hierarchical design●
Improved system-level design productivity●
Supports effective design reuse
Support
of industry-standard IP interfaces (eg: AMBA)
Shipping later this year
11
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.12
FPGA
Nios IICPU
On-chip ROM
On-chip RAM
UART
GPIO
Timer
Custom logic
SDRAMcontrollerSy
stem
inte
rcon
nect
fabr
ic
Debug Cac
he
Existing offering: Nios II+FPGA
Nios II processor + peripherals = your exact-fit custom embedded processor
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Addressing the NeedsSolutionsTrends Needs
More combinations of CPU and reconfigurable accelerators
Continued bill of materials (BoM) reduction
More OS options for FPGA-based CPUs
Single FPGA design flow targeting the widest array of options
Multicore + hardware acceleration - CPUs at power limit - Power-efficiency
more critical
FPGAs increasingly used in embedded systems
More FPGA-enabled embedded options
Altera devices with ARM Cortex-A9
Intel’s Atom-based processor
Altera devices with ARM Cortex-M1
Altera devices with MP32
Altera devices with Nios II
More OS options available for FPGA-based soft CPUs
Quartus II software + Qsys
13
© 2010 Altera Corporation—Confidential
Nios II Processor
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.15
Over 20,000 licensees worldwide
Used by each of the top 20 OEMs
Industry’s #1 soft-core CPU –
Gartner Dataquest
Vibrant Nios Forum community (over 10,000 )
Used by developers in all Altera markets
Nios II Processor Adoption 2001
2002
2003
2004
2005
2006
2007
2008
2009
Nios CPUintroducedNios CPU
introduced
Nios II CPUintroducedNios II CPUintroduced
C2H Compilerintroduced
C2H Compilerintroduced
DO-254certification
DO-254certification
SynopsysASIC
SynopsysASIC
uCLinuxuCLinux
uC/OS-IIuC/OS-II
ThreadXThreadX
eCoseCos
NucleusNucleus
OSEK/VDXOSEK/VDX
Wind River LinuxWind River Linux
SeggerSegger
uITRONuITRON
uCLinuxuCLinuxToppersToppers
MMU/MPUMMU/MPU
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.16
Automotive
Infotainment
Car networking
Driver assistance
Audio processing
Networking
Ethernet MACs
Universal front end
Traffic management
Access flow processor
Industrial
Serial field bus protocol
Industrial Ethernet
Industrial automation
Drives and PLCs
Consumer
Display and projector
Home media networking
Home appliance
Military
COTS embedded
Guidance and control
DO-254 compliance
Medical
Diagnostic imaging
Cardiac rhythm management
Patient monitoring
“Nios II: Industry’s Most Widely Used Soft Processor”- Forbes Magazine
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.17
Scaling System Performance
Programmemory
Nios II processor
Datamemory
Arbiter
Custom instruction
C2H generated HW accelerator
Programmemory
Nios IIprocessor
Datamemory
Arbiter
Embedded systems in FPGAs can scale performance by leveraging parallelism
10x..20x..30x..
40x..
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.18
Protecting SW Investment From Obsolescence
Nios IICPU
On-chip ROM
On-chip RAM
UART
GPIO
Timer
Custom logic
SDRAMcontrollerSy
stem
inte
rcon
nect
fabr
ic
Debug Cac
he
No change to software applicationNo need to requalify processor
No change to design tools or flowNios II processor is soft IP.
Your entire system can be easily migrated to another device, preserving your software investment.
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.19
FPGA as a coprocessor
ExternalCPU or
DSP
ExternalCPU or
DSP Ext I
/F (e
.g. P
CI)
Ext I
/F (e
.g. P
CI)
CustomfunctionCustomfunction
Video IPVideo IP
EthernetEthernet
DDR2 SDRAMDDR2 SDRAM
FPGA
CPUCPU
CPUCPU
Adding Value to Your Existing System
Processor + FPGA coprocessor: low-risk adoption path to flexibility
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.20
Nios II Processor: Most Popular Soft Processor Ever
Over 20,000 kits shipped
Over 5,000 unique Nios licensees (companies)
More than all other soft-core processors combined *
Nios Design Community
www.niosforum.com
Over 5,000 active participants
Open source hardware and software
Nios Wiki site launched 2006
www.nioswiki.com
Development kit -
key to success
Complete kit
Simple, capable CPU
Easy to use
Low cost (~$995)
Perpetual license
No royalties* Other soft core processors include MicroBlaze and ARM soft core processors
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.21
CPU core size (logic elements)
Nios II Processor: Faster or Smaller
Results based on Stratix III FPGA
0 500 1,000 1,500 2,000
Perf
orm
ance
(DM
IPS)
Economy
Fast
Standard
0.2 DMIPS/MHz
0.7 DMIPS/MHz
1.1 DMIPS/MHz
0
50
100
150
200
250
300
© 2010 Altera Corporation—Confidential
Hardware Architecture
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.23
Nios II Processor
Program controller
andaddress
generation
clockreset
Status andcontrol
registers
Instruction masterport
Instruction cache
Data cache
Data masterport
General purpose registers
Nios II processor core
= Optional = Configurable
= Debug Options= Fixed
Tightlycoupled I-memory
Tightlycoupled I-memory
Tightlycoupled
D-memory
Tightlycoupled
D-memoryirq[31..0]
Arithmetic logic unit
Interrupt controller
Exception controller
Trace memoryTrace
memory
Instruction anddata trace
Instruction anddata trace
High-speed connection to trace pod
Trace portTrace port
Hardware- assisted
debug module
JTAG interface to software debugger
HW
breakpoints
HW
breakpoints
Custom instruction
logicCustom
I/O signals
MMU
MPU
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.24
Binary Compatibility/Flexible Performance
Nios II/ffast
processor
Nios II/sstandard
processor
Nios II/eeconomyprocessor
Pipeline 6 stage 5 stage None
Hardware multiplier and barrel shifter 1 cycle 3 cycle Emulated
in software
Branch prediction Dynamic Static None
Instruction cache Configurable Configurable None
Data cache Configurable None None
Custominstructions Up to 256
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.25
Custom Instructions
0
5,000,000
10,000,000
15,000,000
20,000,000
25,000,000
Clo
ck c
ycle
s
Softwareonly
Custominstruction
27 times faster
27 timesfaster
Accelerating software
Adds ALU functionality
No compiler impact
Ideal for complex math and logical operations
Example:
CRC algorithm (64 Kbytes)
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.26
Hardware Accelerators
CRCcoprocessor
CRCcoprocessor
Programmemory
CPU
Datamemory
ArbiterArbiter
Datamemory
ArbiterArbiter
Coprocessor0
5,000
1,000
1,500
2,000
2,500
Itera
tions
/sec
ond
Software only
Custominstruction
530x faster 530x faster
Data transformation coprocessor
Best for block data operations
Run concurrently with CPU
Example:
CRC algorithm (64 Kbytes)
© 2010 Altera Corporation—Confidential
ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.
Summary
Altera’s
Embedded Initiative provides embedded
system designers:●
Diversity of options integrating FPGA and CPU technologies
o Altera
Nios
II, ARM Cortex-M1 and -A9, and MP32 processorso Intel’s Atom-based processor
●
Single FPGA design flow through Quartus
II softwareo New Qsys
system-level integration tool
More embedded offerings coming in 2011
27
© 2010 Altera Corporation—Confidential
Thank You!
Any Questions?