overview - njit sosrlopes/mod8.3.pdf · – need additional reference cells for program / read •...

Overview

Intel was the first FLASH manufacturer to develop NOR memory in 1988. Toshiba was the first manufacturer to develop NAND FLASH memory in 1989.

Overview

UV eraseable EPROM

Memory array

Quartz UV window

SD card teardown

2GB FLASH Memory controller

NOR The NOR architecture is currently the 2nd most popular flash architecture. It is commonly used in EPROM and EEPROM designs. Aside from active transistors, the largest contributor to area in the cell array is the metal to diffusion contacts. NOR architecture requires one contact per two cells, which consumes the most area of all the flash configuration alternatives. Electron trapping in the floating gate is done by hot-electron injection. Electrons are removed by Fowler-Nordheim tunneling*. The world’s two leading manufacturers of flash devices (Intel and AMD) use NOR cell configurations.

Overview

NAND To reduce cell area, the NAND configuration was developed.The NAND structure is considerably more compact. A drawback to the NAND configuration is that when a cell is written, the sense amplifier sees a signal eight times weaker than for a NOR configuration. This is because eight transistors are in series. The weak signal slows down the speed of the read circuitry, which can be overcome by operating in serial access mode. This memory will not be competitive for random access applications.

*Field emission - also called Fowler-Nordheim tunneling - is the process whereby electrons tunnel through a barrier in the presence of a high electric field. This quantum mechanical tunneling process is an important mechanism for thin barriers as those in metal-semiconduictor junctions on highly-doped semiconductors. **Hot carrier injection is the phenomenon in solid state devices or semiconductors where either an electron or a "hole" gains sufficient kinetic energy to overcome a potential barrier, becoming a "hot carrier", and then migrates to a different area of the device.

Flash Memory Device – NAND & NOR

–  Stacked Gate NMOS Transistor •  Poly1 Floating Gate for charge storage •  Poly2 Control Gate for accessing the transistor •  Tunnel-oxide for Gate oxide •  Oxide-Nitride-Oxide (ONO) for the inter Poly Dielectric •  Source/Drain Junctions optimized for Program/Erase/Leakage

Inter Poly Dielectric ONO

N+ SOURCE N+ DRAIN

POLY1 FLOATING GATE

POLY2 CONTROL GATE

P-WELL

Tunnel Oxide

Deep N-Well

P-Substrate

D

S

CG

FG

NAND vs. NOR Cross-sections

–  Two of the Most Popular Flash Memory Types •  Both have Dual Gate NMOS with charge storage in Poly1

floating gate •  Lack of contacts in NAND cell makes it inherently smaller

in size

Bitline

Sourceline String of 16 cells S e l e c t Transistors

String of 16 cells Bitline N

OR

NAND

sel 0 1

1 0 2 2

14 15

15 14

sel

sel sel sel sel

bitline

bitline

0

1

2

14

15

0 1 2 14 15

Flash Memory Device – Basic Operation

–  Programming = Electrons Stored on the FG = High Vt –  Erasing = Remove electrons from the FG = Low Vt –  Threshold Voltage shift = DQFG/CCG

Ids

Vcg

“1” “0”

Erased “1”

Stored Electrons

Programmed “0”

D

S

CG

FG

D

CG

S

FG

CDRN

CSRC

CCG

CSUB

Programming Comparison

Nand Flash Programming – FN Tunneling

–  Tunnel Programming from channel by biasing the Top Gate positive with respect to the ground

–  Program Time ~300us –  Program current ~ Displacement plus Tunneling current. Low

current allows large parallelism.

“0”-Program

P-well

N+

20V

0V 0V

N+

Ec Ev

Ec Ev

Channel Floating Gate

Y. S. Yim, et al. IEDM 2003

NOR Flash Programming – Channel Hot Electron

–  Channel Hot Electron Programming - Gate voltage inverts channel; drain voltage accelerates electrons towards drain; gate voltage pulls them to the floating gate

–  In Lucky Electron Model, electron crosses channel without collision, gaining > 3.2eV, hits Si atom, bounces over barrier

–  Program Time ~ 0.5-1ms. Program current ~50mA/cell

10V

P-well

0V

Program

N+ N+ N+ N+ N+

P-Well

5V 0V

Floating Gate

Substrate

Channel

“Lucky” Electron Ec Ev

Ec Ev

Vgate = 10V

1 2 3 4 5 6 7 8 9

1.E-07 1.E-06 1.E-05 1.E-04 Time (s)

Vt (

V)

Vd=3.0V Vd=3.25V Vd=3.5V Vd=3.75V Vd=4.0V

FLASH programming

Floating Gate Electrons vs. Lithography

30nm Lithography

Single-Level Cell (SLC) vs. Multi-Level Cell (MLC)

–  Take advantage of the threshold voltage difference between the erased and programmed states of the single-level-cell case

•  Two levels = 1 bit/cell •  Four levels = 2 bits/cell •  In general: n bits/cell = log2(#levels)

–  Need additional reference cells for program / read

•  One read reference cell for 1 bit/cell •  Three read reference cells for 2bits/cell

(R1 – R3) •  N-1 reference cells for n bits/cell •  Corresponding reference cells for

program (P1 – P3)

1

10

100

1000

10000

100000

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6Cell Threshold Voltage in Volts

Num

ber

of C

ells

Erase

Program

Data = 1 0

Count

R2 R3 R1

11 00 01 10

P3 P2 P1

SLC

MLC

Multi-Level Cell Design –  Why MLC? Cost

•  Effectively cuts cell area per bit in half •  Provides the same cost improvement from an array area

perspective as a litho generation –  Three Key MLC Considerations

•  Precise Charge Placement (Programming) –  Cell programming must be accurately controlled, which requires a

detailed understanding of cell physics, voltage control and timing –  Precision voltage generation for stable wordline and drain voltage

•  Precise Charge Sensing (Read) –  MLC read operation is an analog to digital conversion of the charge

stored in the cell –  Device and capacitance matching, Collapsing sources of variation,

Precision wordline and drain voltage generation, Low current sensing

•  Stable Charge Storage –  Leakage rate needs to be less than one electron per day

Architecture Comparison

Architecture Comparison

The phrase "flash memory" often is used interchangeably with the phrase "NOR-based memory." Many in the industry are unaware of the competing NAND flash technology and its advantages over NOR because most flash devices are used to store and run small amounts of code--for which NOR flash is more suitable. NAND is an ideal solution for high-capacity data storage.

A feature of NOR is eXecute In Place (XIP), which allows an application to be run directly from flash instead of reading the application code into system RAM. NOR delivers high read performance and is most cost effective in lower capacities--1 to 4 Mbytes--but suffers from extremely low write-and-erase performance. NAND architecture competes by offering extremely high cell densities that translate to high storage capacity, combined with fast write and erase rates. The difficulty using NAND revolves around the need for flash management and special requirements for system interface.

Performance

Flash memory is nonvolatile memory that can be erased and reprogrammed in units of memory called blocks. A write operation in any flash device can only be performed on an empty/erased unit, so in most cases an erase operation must precede the write operation. The erase operation is fairly straightforward for NAND devices, whereas NOR technology mandates that all bytes in the target block be written with zeros before they can be erased. Since the size of an erase block in NOR ranges from 64 to 128 Kbytes, such a write/erase operation can take up to 5 s. By contrast, using erase blocks 8 to 32 Kbytes in size, NAND performs the identical operation in a maximum of 4 ms. The erase block-size difference further increases the performance gap between NOR and NAND, as statistically more erase operations must be performed in NOR-based units per any given set of write operations (especially when updatingsmall files). Therefore, when selecting a local storage solution, designers need to weigh the following factors: • NOR reads slightly faster than NAND. • NAND writes significantly faster than NOR. • NAND erases much faster than NOR--4 ms vs. 5 s, respectively. • Most writes require a preceding erase operation. • NAND has smaller erase units, so fewer erases are needed.

Interface Differences

NOR flash has an SRAM interface. It has enough address pins to map its entire media, allowing for easy access to every byte contained in it. NAND devices are accessed serially via a complicated I/O interface, which may vary from one device or vendor to another. The same eight pins are used to convey control, address, and data information. NAND read-and-write operations occur in bursts of 512 bytes, which is similar to how hard drives manage these operations. This positions NAND-based memory tobe a logical choice to use for hard drive or block-device replacement.

Capacities and cost

The cell size of NAND flash is almost half the size of a NOR cell. In combination with a simpler production process, NAND architecture can be offered with higher capacity for a given die size, resulting in a lower price tag. NOR flash dominates the market in memory capacity ranging between 1 and 64 Mbytes, while NAND flash is used in capacity ranges between 1Gbyte to 64Gbytes and higher. This again stresses the roles of NOR devices as a code-storage media and NAND devices as ideal for data storage--NAND has its strongest market presence in the memory card market (CompactFlash, Secure Digital, PC Cards, and MMC).

Reliability and Endurance

Life span (endurance) The maximum allowed number of erase cycles per erase block in a NAND device is one million cycles, compared with 100,000 cycles for a NOR device. In addition to the 10-to-1 block-erase-cycle advantage of NAND memory devices, the typical NAND block size itself is about 8 times smaller than that of a NOR device—each NAND memory block will be erased fewer times over a given period of time. Bit flipping All flash architectures today suffer from a phenomenon known as "bit flipping."On some occasions (rare, yet more common in NAND than in NOR), a bit either gets reversed or is reported reversed. One bit change may seem insignificant, but this minor glitch may hang the system altogether if it corrupts a critical file. When the problem is just one of reporting, repeating the read operation may solve it. However, if the bit has actually been changed, an error detection/error correction (EDC/ECC) algorithm must be applied. Problems associated with bit flipping are more common with NAND devices than NOR and all NAND vendors now recommend using an EDC/ECC algorithm with their devices. This problem is not as critical when using NAND to store multimedia information. However, when used as a local storage device storing the operatingsystem, configuration files, or other sensitive information, an EDC/ECC system must be implemented to ensure reliability.

Bad-block handling

NAND devices are shipped with bad blocks randomly scattered within them. An early attempt to ship NAND devices free of bad blocks was found not to be economically practical due to the very high price tag caused by low-production yield rates. NAND devices require an initial scanning of the media for bad blocks, which are mapped as unusable within the memory controller. Failing to perform this process in a reliable way results in high-failure rates in the finished device.

Software

Using a NOR-based flash is a straightforward process. It is connected like other memory devices, and code can be run directly from it. NAND, however, is complicated with its requirement for an I/O interface. Accessing rules for NAND interfaces may differ depending on the NAND vendor. A driver must be written and used for performing any operation on a NAND device. Writing information to a NAND device is a particularly tricky issue, since the designer must not write to a bad block—meaning that virtual mapping must be implemented on NAND devices at all times. When discussing software support, two levels of support are distinguished: basic for read/write/erase operations and high level software for disk emulation and flash management algorithms—including performance optimization. Running code from NOR devices requires no special software support. Doing the same thing in NAND requires a driver, usually referred to as a memory technology driver (MTD). Both NAND and NOR require MTDs for write and erase operations. Working with NOR does not require much more than MTDs. Higher-level software isavailable for NOR devices from many vendors, including M-Systems' TrueFFS drivers--used by vendors such as Wind River Systems, Microsoft, QNX Software Systems, Symbian, and Intel. The drivers also implemented in the company's DiskOnChip products provide both disk emulation and NAND flash management, including bit-error correction, bad-block handling, and wear leveling.

NAND vs. NOR

Santa Clara, CA USAAugust 2008 4

random access serial access

Access speed:Random: 10-50µs

serial (page mode): 25-50ns

write speed:random: 200µs/byte

page: 200µs/page (0,4µs/byte)

Access time:Random: 60-120ns

page mode/burst mode: 30ns/15ns

write speed:random: 10µs/byte or word

• Low Cost

• small cell size

• High sustained write

• page write

• High Performance optimized

• fast random read

• fast random write

Flash Memory

NANDNOR

• High Performance optimized • fast random read • fast random write

• Low Cost • small cell size • High sustained write • page write

NAND vs. NOR

NROM Technology(aka Charge Trap Flash CTF) - The most cost-effective Flash solution (~2x better silicon efficiency)

comprises a nitride layer, surrounded by two insulating oxide layers. The nitride layer serves as a trapping dielectric for two separate localized charge packets at each end of the cell, effectively storing two bits. Each charge can be maintained in one of two states, either “programmed” or “erased,” represented by the presence or absence of a pocket of trapped electrons. This enables the storage of two bits of information without the complexities associated with multi-level-cell technology.

Conceptual Diagram of an NROM Cell Photo of an Actual NROM Wafer

NROM vs. Floating Gate

• localized storage in nitride traps • 2 physical bits per cell • multi-level cell storage allows storage of 2 or more electrical bits per cell

NROM vs. Floating Gate


NROM Floating Gate

Bit 2Bit 1

Floating Gate (Poly) Gate Oxide

Poly

Oxide

• localized storage in nitride traps

• 2 physical bits per cell

• multi-level cell storage allows storage of 2 electrical bits per cell

• physical storage of charge in floating gate

•multi-level cell storage allows storage of 2 or more electrical bits per cell

Bit 1

• physical storage of charge in floating gate • multi-level cell storage allows storage of 2 or more electrical bits per cell

Program and erase.

Each storage area in an NROM cell can be programmed or erased independently of the other storage area. An NROM cell is programmed by applying a voltage that causes negatively charged electrons to be injected into the nitride layer near one end of the cell. Erasing is accomplished by applying voltages to a cell that cause positive charges, referred to as “holes” – the electrical opposite of electrons – to be injected into the nitride layer and cancel the effect of the electrons previously stored there during programming. As a consequence of using a localized charge trapped in the non-conducting nitride and reading the information in a direction opposite to the direction it was programmed, a smaller total charge may be used to represent a bit. Because a significantly smaller amount of trapped charges is needed to program a device, and due to the physical mechanisms used for program and erase, the device can be both programmed

Because the stored charge is confined close to the ends of an NROM cell device, numerous program-erase cycles may be performed without significantly degrading cell performance. Single bit failures that are common to floating gate technology are avoided even after 100,000 cycles. As a result, it is possible to achieve estimated data retention of at least 10 years and, unlike floating gate cells, NROM cells are not generally susceptible to oxide defects. In addition, the relatively thick oxide layers surrounding the trapping layer of the NROM cell prevent the trapped charge from leaking-out of the cell by a tunneling mechanism. This enhances the data retention ability of NROM cells when compared to floating gate devices.

Our proprietary technology addresses architectural aspects of the NROM array, such as segmentation of the array to handle disruption in its operation, and symmetric architecture and nonsymmetric architecture for specific products, as well as the use of NROM array as a virtual ground array. We also hold patents directed to additional aspects at the architecture level, including the peripheral circuits that control the NROM array, for example, multiple select transistors per one bit line to improve the functionality and operation of the array. We have also developed methodologies directed to several key methods of operation of the NROM arrays, such as algorithms related to programming, erasing, and reading NROM arrays. Our proprietary processes include methods to control a programming level or to complete the programming of a cell at the lowest drain level that we believe are generic to the NROM technology. Further protection has been obtained for our method of erasing a memory cell by hitting it with an extra pulse. Features of our NROM technology include less cumbersome manufacturing process technology that reduces costs and improves reliability, and array architecture that increases density, shortens programming and improves read times without sacrificing reliability. We have developed manufacturing processes, such as the process of forming a thin nitride layer that traps the hot electrons as they are injected into the nitride layer.

Array architecture and operation.

Process technology.

FLASH memory Trends

Array Architectures Array Architectures


Bit line

Bit line

Word line

Source line

Bit line

Bit line

Sourceline select

Bitline select

Source

Source

Word line

NOR NAND NROM

Source/Drain

• Parallel architecture• 10F2

• Serial architecture• 4F2

• Parallel architecture• 7F2

NAND Flash Cell Size

6

• Need to transition to multi-bit technologies

Santa Clara, CA USAAugust 2008

0

0.05

0.1

0.15

0.2

2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

µm2

NAND Physical Cell size Trend

NAND Flash Cell Size

• As flash cells get smaller, they retain a commensurately smaller amount of residual charge before they must be marked by the controller as useless. The increased density of MLC guarantees that the individual NAND cells will undergo more writes for the same amount of data. A MLC drive has fewer NAND flash transistors for a given amount of storage, so a workload run on a 100GB SLC disk and on a 100GB MLC disk will make the MLC disk work harder; there are simply fewer transistors to bear the write load. The difference is dramatic, too. The average cell life in an SLC SSD is 100,000 writes, while a good 20nm MLC backed by a good controller will bear perhaps 3,000.

Multi-level Cell Storage - NAND



S D

Substrate

FG

CG

1010 1000100111101111 11001101 00100011 0000000101100111 010001011011

# of

cel

ls

110111 100101# of

cel

ls

01# of

cel

ls

4 bits/cell

010011 000001110111 100101# of

cel

ls

3 bits/cell

2 bits/cell

1 bit/cell



S D

Substrate

FG

CG

1010 1000100111101111 11001101 00100011 0000000101100111 010001011011#

of c

ells

110111 100101# of

cel

ls

01# of

cel

ls

4 bits/cell

010011 000001110111 100101# of

cel

ls

3 bits/cell

2 bits/cell

1 bit/cell

Multi-level Cell Storage - NROM


Bit 2Bit 1

Bit 4Bit 3

Bit 2Bit 1

110111 100101# of

cel

ls

01# of

cel

ls

2 bits/cell

4 bits/cell



Bit 2Bit 1

Bit 4Bit 3

Bit 2Bit 1

110111 100101# of

cel

ls

01# of

cel

ls

2 bits/cell

4 bits/cell


Multi-level Cell Storage Cost Advantage

9

4Gb SLC NAND

70nm

156mm2

4Gb SLC NAND

70nm

145mm2

8Gb MLC NAND

70nm

146mm2

Samsung Hynix Toshiba

8Gb Quad NROM

75nm

120mm2

Saifun

Images: Semiconductor Insights, Inc., Saifun Semiconductors, Toshiba

16Gb 4b/c NAND

70nm

168mm2

Toshiba

Multi-level Cell Storage Cost Advantage

MLC NAND flash is a flash memory technology using multiple levels per cell to allow more bits to be stored using the same number of transistors. Most MLC NAND flash memory has four possible states per cell, so it can store two bits of information per cell. This reduces the amount of margin separating the states and results in the possibility of more errors. The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density. However, software complexity can be increased to compensate for a larger bit error ratio. The higher error ratio requires an algorithm that can correct errors up to five bits and detect the condition of more than five bad bits. The most commonly used algorithm is Bose-Chaudhuri-Hocquenghem (BCH code). Other drawbacks of MLC NAND are lower write speeds, lower number of program-erase cycles and higher power consumption compared to SLC flash memory. A few memory devices go the other direction, and use two cells per bit, to give even lower bit error rates.

Images: Intel Corp.

13

2002 - 130nm

2004 - 90nm

2000 - 180nm

2006 - 65nm

2008 - 45nm

NOR Flash Technology Evolution


NOR Flash Technology Evolution

14

2006 - 60nm

2007 - 50nm

2004 - 90nm

2008 - 40nm

Images: Samsung, Semiconductor Insights, Toshiba

NAND Flash Technology Evolution


NAND Flash Technology Evolution

15

2004 - 110nm

2006 - 90nm

2002 - 230nm

Images: Spansion

2008 - 65nm

2009 - 45nm

NROM Flash Technology Evolution


NROM Flash Technology Evolution

Code Flash Roadmap

16Santa Clara, CA USAAugust 2008

128

256

512

1024

2048

4096

64

128

256

512

1024

10

100

1000

10000

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Den

sity

(Mb)

Code Flash Density Trend

MLC NOR NROM Code Source: Forward Insights

• NROM code to be superseded by Eclipse

Code FLASH roadmap

Data Flash Roadmap


1024

2048

4096

8192

16384

32768

65536

2048

8192

16384

100

1000

10000

100000

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Den

sity

(Mb)Data Flash Density Trend

MLC NAND NROM QUAD Source: Forward Insights

Data FLASH roadmap

20Santa Clara, CA USAAugust 2008

Scaling Challenges

NOR Flash NAND Flash NROM

•Short channel effect

•Contact and isolation fill

•Charge storage reduction

•Inter-cell interference

•CG-FG coupling

•Gap fill

•Charge storage reduction

•Short channel effect

•Bit disturbs

Scaling Challenges

External To chip

Internal To chip

External To chip

Older FLASH nodes Newer FLASH nodes

•  NOR and NROM most suitable for code storage; NAND for data storage

•  Move to multi-bit storage to drive further cost reductions as technology scaling slows

•  Cost benefits of 3bit/cell & 4bit/cell to materialize in next few years (arrived)

Summary

overview - njit sosrlopes/mod8.3.pdf · – need additional reference cells for program / read •...

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