ovonicunifiedmemoryppt-13165481555981-phpapp02-110920145719-phpapp02
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Pratik Rathod
8th
Sem E.C.
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Semiconductors form the fundamental building blocks of the
modern electronic world providing the brains and the memory of
products all around us from washing machines to supercomputers.
Current memory technologies have a lot of limitations
One of the fundamental approaches to manage challenge is usingnew materials to build the next generation transistors.
The new memory technologies have got all the good attributes
for an ideal memory.
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The current memorytechnologies have a lot of
limitations.
Flash slower writes &lesser num. of
write/erase cycles
RAM high cost & volatile
when needed to expandwill allow expansion onlytwo-dimensional space.
Hence area required willbe increased.
DRAM-volatile & difficultto integrate
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Many new memory technologies were
introduced when it is understood that
semiconductor memory technology has to bereplaced, or updated by its successor since
scaling with semiconductor memory reached
its material limit.
So, next generation memories are tryingtradeoffs between size and cost.
These make them good possibilities for
development.
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¶Next Generation Memoriesµ
The fundamental idea of all thesetechnologies is the bistable nature possible
for of the selected material.
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Next Generation
Memories
FeRAM
PolymerMemory
OvonicUnifiedMemory
ETOX-4BPC
NROM
MRAM
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Most Promising One.
Material Used is called CHALCOGENIED.
The Group VI elements of the periodic
table.
Refers to alloys containing at least one ofthese elements such as the alloy of
Germanium, Antimony, and Tellurium
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Phase change technology uses a thermally
Activated, Rapid, Reversible change in the
structure of the alloy to store data.
The two structural states are Amorphous
State and Polycrystalline State.
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Resistive heating is used to change the phase
of the chalcogenide material.
Amorphous State - by taking temp abovemelting point.(Tm)
Polycrystalline State - holding temp at a
lower temp for slightly longer period of
time.(Tx)
The time needed to program either state is
= 400ns
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Once programmed, the memory state of the
cell is determined by reading its resistance. Expected to be impervious to ionizing
radiation effects.
One billion Write cycles between these two
States were demonstrated. Reading the stateof the device is nondestructive and has no
impact on device wear out
So it has Unlimited Read cycles.
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The base of the heater is
connected to a diode. Thermal insulators are
also attached to thememory structure inorder to avoid data losedue to destruction of
material at hightemperatures.
To write- heated past itsmelting point and thenrapidly cooled to makeit amorphous.
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The initial goal of CMOS integration was to
develop the processes necessary to connectthe memory element to CMOS transistors and
metal wiring, without degrading the
operation of either memory elements or the
transistors.
Access Device Test Chip (ADTC)
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We are placing the memory element above
the CMOS transister and below 1st levelmetal.
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Short loop (partial flow) experiments
full flow experiment1T1R
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The voltage is applied to one of the two terminals of
the chalcogenide resistor, and the access transistor
(biased on) is between the other resistor terminal
and ground.
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Figure shows the operation of a 1T1R memory, again
with the access transistor biased on.
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CTCV ² Chalcogenide Technology Chararecterization Vehicle.
It contains memory with different architecture, circuit andlayout variation.
Key goals of CTCV are
1. to make the read and write circuits robust wrt potential
variations in cell electrical charecteristics.
2. to test the effect of the memory cell layout onperformance.
3. to maximize the amount of useful data obtained that
could later be used for product design
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Single ended
sense amplifier.
The differential
amplifier. Conservative Cell.
Aggressive Cells.
Process
Monitoring.
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no effect on measured CMOS transistor
parametricindicate full functionality of the 64 kbit
memory arrays.
Companies working with Ovonic Unified
memory have their ultimate goal to gather
enough data to begin a product designtargeting a 1²4 Mbit C-RAM device.
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OUM uses a reversible structural phase change.
· Small active storage medium.
· Simple manufacturing process.
· Simple planar device structure.
· Low voltage single supply.
· Reduced assembly and test costs.
· Highly scalable- performance improves with scaling
· Multistate are demonstrated.
· High temperature resistance.· Easy integration with CMOS.
· It makes no effect on measured CMOS transistor
parametric.
· Total dose response of the base technology is not affected