P09311: P09311: FPGA Based Multi-FPGA Based Multi-

Purpose Purpose Driver / Data Acquisition Driver / Data Acquisition

SystemSystem

Sponsor: Dr. Marcin Lukowiak

Team Member Discipline Role

Adam Van Fleet EE Project Manager/Documentation

David Howe EE Hardware System Development

Michael Doroski CE FPGA Buffer Subsystem Programming and Digital/Analog Interfacing

Andrew Weida CE Bluetooth and GUI Development

T.J. Antonoff CE USB Development

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Project Description Goal:

Design and implement a functional FPGA-based interface for the multi-purpose driver/data acquisition system. The interface must allow for data acquisition via USB and Bluetooth communication interfaces.

Utility: The project is to be utilized in Robotics and ASIC testing for research at the Rochester Institute of Technology.

High Level Customer High Level Customer RequirementsRequirements

• System• Utilizes FPGA interface.• Capable of transferring data via Bluetooth and USB communication

channels. Option for Ethernet and Wireless communication channels.• Infinite sampling time desired (data streaming).• GUI displays data transfer statistics.• Text-file format for data storage.

Input Capabilities

Digital 12 Channels

Analog Voltage 16 Channels

Output Capabilities

Digital 12 Channels

Analog Voltage 8 Channels

Analog Current 8 Channels

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Data Transfer Capabilities

Bluetooth 1.2 kb/s minimum (100% transfer rate)

USB 1.5 Mb/s minimum (100% transfer rate)

Sampling Rate 20,000 samples/second

Hardware ImplementationHardware Implementation

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Parani ESD210SK Bluetooth Dev. Kit

DLP-USB245M USB Adapter

ASIC or Robotics Input

Windows-Based PC

P08311 DAQ Board

Spartan-3 FPGA

Top Level Architecture Top Level Architecture DesignDesign

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FPGA

USB Data Routing Logic

USB FIFO

USB Cable

Bluetooth Modules

Rx

Tx

Rx

Tx

RS232200 kbps

Bluetooth

Wireless

Serial

PC

USB8 Mbps

Input Conditioning

Output Conditioning

Output Subsystem

Input Subsystem

UART

Control UnitDAQ

Product Development Process Phase

Phase 0: Planning Phase 1: Concept Development

Phase 2: System Level Design Phase 3: Detailed Design

Phase 4: Testing and Refinement

Concept SummaryConcept Summary

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Theory:

The buffers can only empty as fast as the communication channel allows, but can load as fast as we choose. The buffer size is 216kb.

The length of time for which we can transfer data is equal to the total memory size (216 kb) available, divided by the rate the memory is filled (Input Rate – Output Rate). Therefore, if the output rate is greater than the input rate, we can transfer information for an infinitely long period of time.

OI

Mt

Concept Summary (Bluetooth)Concept Summary (Bluetooth)

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The Bluetooth device can only handle theoretical bit rates of 330 kb/s, limited by baud rate, and is seeing 200 kb/s in testing. Under full load, over 6 Mb/s is required. Therefore, the BT device will not be sufficient for data transfer under full load.

Input Rate (kb/s) Time (t)

Input Rate (kb/s) Time (t)

199.99 1E+15 250 4.32

200.01 21600 300 2.16

200.1 2160 350 1.44

201 216 400 1.08

205 43.2 500 0.72

210 21.6 1000 0.27

220 10.8 2000 0.12

230 7.2 3000 0.077

240 5.4 4000 0.057

05000

10000150002000025000

200

…20

0.1

201

205

210

220

230

240

250

300

350

400

500

1000

2000

3000

4000

5000

BT Output Rate: 200 kb/s

0

10

20

30

40

50

BT Output Rate: 200 kb/s

Concept Summary (USB)Concept Summary (USB)

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The USB system allows for an 8 Mb/s transfer rate, thus the buffer is never filled and data transfer can be streamed (infinite time length).

Under full load, the maximum output rate required for streaming is 6,724 kb/s.

Input Rate (kb/s)

Time (t)

Input Rate (kb/s)

Time (t)

0 1E+15 2500 1E+15

100 1E+15 3000 1E+15

200 1E+15 3500 1E+15

300 1E+15 4000 1E+15

400 1E+15 4500 1E+15

500 1E+15 5000 1E+15

1000 1E+15 5500 1E+15

1500 1E+15 6000 1E+15

2000 1E+15 6500 1E+15

USB Output Rate: 8000 kb/s

02E+144E+146E+148E+141E+15

1.2E+15

010

020

030

040

050

010

0015

0020

0025

0030

0035

0040

0045

0050

0055

0060

0065

0067

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Design SummaryDesign Summary

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The packet structure is broken down into:

-MSB (B7): Determines if data is Analog or Digital

-B6 to B4: Used to reassemble data on PC side

-LSB’s (B3 to B0): Contain the data from DAQ or PC

If the top nibble is set to ‘1111’, the last 4 data bits determine which analog channel the data is being received from.

Graphical User Interface (GUI)Graphical User Interface (GUI)

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Analog I/O TestingAnalog I/O TestingA 3.3Vpp sin wave is fed to the analog inputs of the DAQ, then through

the Spartan-3 FPGA. The analog outputs are as shown.

It is noted that as the frequency approaches 1kHz (left), the signal begins “stair-stepping”, as seen in P08311’s work. As the frequency increases to 2kHz and above (right), the stepping becomes much more apparent.

Digital I/O TestingDigital I/O TestingA 1.5Vpp square wave is fed to the digital inputs of the DAQ, then

through the Spartan-3 FPGA. The digital outputs are as shown.

Status of DesignStatus of Design Bluetooth System

Meets customer specifications

USB System In system-level debugging to achieve customer

specifications.

Graphical User Interface Meets customer display specifications Accurately depicts transfer rate and connection settings,

allows for file selection.

Under budget of ~$500 Schedule: 2 weeks behind schedule on USB, Bluetooth on

schedule, ahead of schedule on GUI Interface.

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Bluetooth limited by memory sizeBaud rate allows for 360kb/s max.

transfer rate16 Mb additional memory requires

project reworkUSB Transmission ErrorsDigital Output 2 stuck at ‘1’

May require a new IC chipAnalog Data Transfer

Signals misrouted, likely due to timing errors.

Unresolved IssuesUnresolved Issues

MSDII Project Milestones

4/03 – Concept Review 4/10 – Finalize Design, Review System Concept 4/20 – Subsystems Finalized, Begin Test & Debug 5/05 – Entire System Finalized, Begin Test & Debug 5/08 – Finalize and Submit Documentation 5/15 – Project Review 5/18 – Field Demo and Project Wrap-up

Q&A

Questions?