pa0 guide · 2020-05-17 · pa0 guide ece 3401 – spring 2020 course ta contact information:...
TRANSCRIPT
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StartVivado
2
SearchforVivado2018.3
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CreateaNewProject
3
ClickHereonNewProject(andletWizardcreateanewproject)
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ProjectWizard
4
• Theprojectwizardwillopen.Giveanynametoyourproject(e.g.lab0)andleavetherestasis
Thenclicknext
YoucanworkfromyourPdrivewheredataissavedacrossmultiplemachinelogins
P://
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ProjectWizard
5
• Theprojectwizardwillopen.Giveanynametoyourproject(e.g.lab0)andleavetherestasis
Thenclicknext
IfPdrivedoesnotletyousaveyourwork,thenworkinthemachine’sCdrive.Beforeloggingout,copytheprojectfolderinyourPdrive.OnthesubsequentlogincopytheprojectbacktoCdrivetoworkonit.Repeatthisprocessacrossmultiplemachinelogins
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ProjectSettings
6
• SelectRTLProject,thenclicknext• AndthenFinish
ChooseRTLProjectandclickNext
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CreatingSourceFiles
7
Createanewsourcefile
ChangetoVHDL
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CreatingSourceFiles
8
SelectVHDLandtypethename.ThenclickOK
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CreatingSourceFiles
9
ThenclickNext
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CreatingSourceFiles
10
LeavetheIPandConstraintspartsasisClickNext
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PartSelection
11
ChoosethedefaultFPGAxc7k70tfbv676-1ThenclicknextThenclickfinishTheprojectwillthenbecreated
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PortDefinitions
12
LeavethispartasisandclickOKYouwillbeaddingtheportdefinitionsintheVHDLcodelater
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StartProgramming
13
2.Copy&Pastethecodefromlab0.vhdhere(Itisa1-bitadderthatisdownloadablefromthecoursewebpage).Savelab0.vhdusingCtrl+S.TheleftpanelshouldnowsayBIT_ADDER–BHVunderDesignSources
1.Double-clickon‘lab0–Behavioral’forthelab0.vhdfiletoopenintherightpanel
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AddingaTestBench
14
2.SelectSimulationSourceshereandclickNext
1.Clickheretoaddanewfile
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AddingaTestBench
15
1.ClickCreateFile
2.AddthenameofthetestbenchandclickOK.ThenclickFinish
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AddingaTestBench
16
1.ClickOK2.ClickYestoignorethewarning.You’lladdtheportdefinitionslater
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CopythetestbenchCode
17
1.ClickSimulationSourcesthensim_1,andthendouble-clickon‘test0-Behavioral’forthetest0.vhdfiletoopenintherightpanel
2.Copy&Pastethecodefromtest0.vhdhere(Itisa1-bitadderthatisdownloadablefromthecoursewebpage).Savetest0.vhdusingCtrl+S.TheleftpanelshouldnowsayTEST_ADD–TESTunderSimulationSourcesandsim_1
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RunningSimulation
18
ClickonRunSimulation,andthenRunBehavioralSimulation
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BehavioralSimulation
19
• AwaveformwindowshouldautomaticallyopenafteryouclickRunSimulation
• Enablesonetovisualizewaveformsforthedigitaldesign– Runsforthetimespecifiedinthetestbench– Allowsonetovisualizeinterfaceaswellasinternalstateofthesimulateddesign
– Simulatesinputconfigurationsspecifiedinthetestbench
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RunningtheSimulation
20
ClicktoZoomFit
Theseinterfacesignalsshouldautomaticallyappear
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CheckWaveform
21
• Youshouldstudylab0.vhdcodeandthenunderstandhowtest0.vhdsensitizesinputstocreateatestbenchtotestthe1-bitaddercircuit
• TheSUMandCOUToutputscanbeverifiedbyvisuallyinspectingtheA,BandCINinputsatvarioustimestamps