PAC-DesignerUsage

1. IntroductionSystem RequirementsTo run PAC-Designer software efficiently, a system comp

rised of the following hardware and software is recommended:

HardwareA 486/Pentium-based IBM or compatible computerAt least 16 megabytes of memoryA hard disk with 10 megabytes of free space (typical inst

allation)A CD-ROM drive

SoftwareMicrosoft Windows® 98, Windows 95 or Windows NT

® 4.0 (with Service Pack 3)

Installation1. Insert the PAC-Designer CD-ROM in the appropriate

CD-ROM drive.

2. Insure that all open applications are closed before proceeding. System files that need updating as part of the installation process will cause the procedure to fail if they are in use by an open application.

3. Press Start and then select Settings ⇒Control Panel ⇒Add-Remove Programs.

4. Follow the instructions on the screen.

5. When finished, be sure to exit and then restart Windows to initialize the changes made during the installation process.

Starting PAC-Designer The procedure for starting and quitting PAC-Desig

ner is the same as for other Windowsbased applications. Before proceeding, ensure a valid license file has been obtained per the installation notice. The next section describes registration if this has not been accomplished.

1. From the Start menu button, select Programs ⇒Lattice Semiconductor ⇒PAC-Designer.

2. After the initial program loads, select the File ⇒New menu command or press the New Toolbar button.

3. The New dialog box is now displayed. To open a schematic for design select the ispPAC10 Schematic and press OK. If new devices are available, select the desired device.

4. To quit PAC-Designer, choose the File ⇒Exit menu command.

2. DesignPAC-Designer is a graphical design entry interface

that allows complete control over the configuration of ispPAC products.

Design Entry ScreenDesign entry consists of making internal connections and choosing parametric circuit values. When complete, the circuit can be simulated, saved or downloaded to an isp-PAC10 device. As an alternative to complete configuration, standard circuit functions areavailable from a library of stored designs.

ispPAC10 Definitions

The PAC-Designer schematic window provides access to all configurable ispPAC10 elements via its graphical user interface. All input and output pins are represented. Static or non-configurable pins such as power, ground, VREFOUT and the serial digital interface are purposely omitted. Any element in the schematic window can be accessed via mouse operations as well as by menu commands.

The following ispPAC10 definitions provide the terminology necessary to describe the operation of PAC-Designer in configuring a device. Please refer to product literature, such as the ispPAC10 Data Sheet, for technical specifications and pecific applications information.

Table 1. ispPAC10 Definitions

Cursor FeedbackConfigurable ispPAC elements are either component values (gain/polarity, feedback, capacitors, etc.) or interconnect options. In an active schematic window, the appearance of the cursor gives visual feedback to what operations are possible for a given location. The following table describes the various cursor representations and their meanings.

Table 2. PAC-Designer Cursor Descriptions

Design Entry ExampleThe steps required to configure a circuit that sums two inputs are implemented in the following example. A gain of four is applied to the first input and a gain of ten to the second, as shown in Figure 1.

Figure 1. Example Circuit Function

Beginning with the initial ispPAC10 schematic window, external input pins must be chosen. A portion of the ispPAC10 schematic window is shown in Figure 2 and contains the completed circuit of this example. Elements referred to by number (n) in the following paragraphs are shown in Figure 2-2. For this example, IN1 and IN2 are used. Next, an output pin is chosen. The input stages directly accessible to IN1 and IN2 belong to PACblocks 1 and 2, which correspond to OUT1 and OUT2. For this example PACblock 1, and therefore OUT1, is used. The area around PACblock 1 should be enlarged by either maximizing the schematic window or by using the Zoom Selection tool.

Figure 2. Example Implemented in ispPAC10

To make the first input connection, the mouse pointer is positioned over the upper input node of PACblock 1. At this time, the pointer changes to an “open switch” symbol. By pressing the mouse button and dragging horizontally back from this point, a line is extended and dropped on the line corresponding to IN1 (by releasing the mouse button). A line is now formed between these two points. By the same process, a connection is formed between the lower input node of PACblock 1 and IN2 (2).

To complete the required circuit connections, the mouse pointer is positioned above the left-hand dot of the “open” in the amplifier feedback path (3). The pointer again changes to an open switch symbol, after which a click and drag operation draws a line between the two points completing the circuit.

Next, the parametric values for gain applied to each input must be selected. Positioning the mouse pointer above the input stage symbol (triangular buffer) (4) and double clicking on a number will cause the polarity/gain level dialog box to open. Any value from –10 to +10 can be selected from the list of choices. For the first input, a value of +4 is selected. When the OK button is clicked (or <enter> pressed on the keyboard), the default gain of 1 is replaced with the selected value of +4. This process is repeated for the second input, where a value of +10 is chosen. Following configuration, the design should be saved by pressing the Save button on the toolbar or using the File ⇒Save menu command. This completes the configuration of the example circuit which should appear the same as the portion shown in Figure 2.

Editing Symbols In addition to the point and click method for editing the schematic window, menu commands exist for editing all portions of a design. Access to all connections and parametric values such as gain and capacitors can be obtained by using the Edit ⇒Symbol menu command and then selecting the item to be edited. When an item is selected, a dialog box will appear allowing access to all available choices.

Double-clicking in the area of a component, parameter or connection node will also open the dialog box.

Design Library In a subdirectory labeled \LIBRARY under the main directory containing PACDesigner, is a group of files made up of preconfigured designs. Files stored in this directory can be browsed for summary information using the File ⇒Browse Library menu command. The library contains possible implementations of common analog functions. These circuits demonstrate basic techniques and can serve as starting points for more complex designs. In addition to reference designs placed here during the install procedure, users may place their own reference designs here for easy future access.

Cascading PACblocks

Outputs from one PACblock can be routed internally to the input(s) of successive PACblocks to incorporate more advanced functions. Phase can be checked by running the simulator, discussed in Chapter 3, and compared to expected results.

With an ispPAC10, it is possible to cascade all four PACblocks. The outputs of two PACblocks (PACblock 2 and PACblock 4) are connectable to all possible input stages. By carefully selecting starting points, these cells can be used to form connections between both halves of an ispPAC10.

3. Simulation

PAC-Designer has built-in simulation capability and can display AC gain/phase plots for user-selected input to output combinations. The following subjects are described in this chapter:

Simulating a Design

Active Curve

Simulator Options

Gain and Phase Readout

Simulating a Design

After a design has been configured, it may be simulated to verify performance and compared to expected results. The simulator can also be used during design entry to try various options or compare alternate configurations. The simulator is capable of computing and displaying the AC response of up to four combinations of inputs to outputs at once. Simulations can be performed at any time after a path exists between at least one input pin and any output.

Once a design is completed, or at least the initial connections have been made, a simulation plot can be initiated by pressing the Run Simulator button on the toolbar. It could also be initiated by using the Tools ⇒Run Simulator menu command.

Once the plot window is opened, the gain plot of signal response versus frequency is displayed. To see phase response versus frequency, position the mouse pointer over the splitter bar located above the horizontal scroll bar at the bottom of the plot window. When the cursor changes to a sizing tool, the bar separating the gain plot and phase plot can be dragged to open and size the vertical height of the two resulting window panes.

Figure 3-1. PAC-Designer Gain/Phase Plot Window

Active Curve

Only one plot curve is considered active at any given time. The active curve is indicated by the corresponding depressed curve button on the toolbar and within a plot window by an outline around the active curve’s “presence indicator” text. The active curve can be changed by pressing any of the deselected curve buttons on the toolbar, by clicking on the corresponding curve’s presence indicator in a plot window or by selecting the Curve ⇒Activate-# menu command when a plot window is active.

Note: Only the active curve is updated when the Tools ⇒Run Simulator menu command is chosen or the Run Simulator toolbar button is pressed. Conditions for each simulation are determined by settings made under the Options ⇒Simulator menu command. To update more than one curve in a plot window, each must be activated and then updated individually. This allows changes to be made to the schematic and the comparison of previous results to present.

Simulator Options

Simulation options for each of the four possible curves per plot can be accessed through the simulator dialog box, opened by the Options ⇒Simulator menu command. A checkbox at the bottom of the window gives the option of recalculating the active curve each time any item in the schematic window is changed.

Gain and Phase ReadoutIt is possible to directly read the gain and phase magnitude f

or any point along a plot by using the crosshair cursor feature. The cursor within a plot window is activated by pressing the Activate Crosshair toolbar button or by selecting the View ⇒Cross Hair menu command. When activated, a readout of gain and phase versus frequency appears in the lower right-hand corner (status bar) of the main window. The position of the cursor is controlled by dragging the mouse cursor anywhere within the plot window or by using the left or right arrow keys. This readout of the active curve can be made to correspond to the actual computed points designated in the Options ⇒Simulator dialog box by selecting the View ⇒Data Points and View ⇒Snap to Points menu commands.

4. Device Programming A defining feature of the ispPAC product family is in-system programmability which allows devices to be programmed “in-circuit” on the application board. This provides an alternative to traditional methods such as pre-assembly machine programming.

PAC-Designer is capable of all programming requirements when properly connected to an in-circuit device. This chapter contains the following sections:OverviewDownloading a DesignUpload and Verify OperationsJTAG IDCODESecurityUser Electronic Signature (UES) Bits

Overview The hardware programming interface of the ispPAC10 is the IEEE 1149.1-1990 JTAG test access port (TAP). To program a device, no special programming voltages or conditions must exist other than a standard +5V power connection and access to a four-wire serial JTAG interface. For further information on JTAG operations, refer to the IEEE specification or the ispPAC Data Sheet for product-specific details.

All programming operations require a PC properly connected to a powered circuit containing an ispPAC device. To communicate with the ispPAC device, an appropriately configured download cable must be installed between a parallel port of the PC and the JTAG serial port of the ispPAC device (refer to the ispDOWNLOAD Cable Data Sheet).

Setup of the parallel printer port and the driver that constrains programming times is accessed via the Options ⇒JTAG Interface menu command. The software installation procedure uses operating system information to configure PAC-Designer accordingly. The printer port is assigned to be compatible with a majority of computers, but is not tested by the install procedure. For details on printer port and download driver configuration, refer to Appendix E , Parallel Port and Download Driver.

Downloading a Design

Any design configuration created in PAC-Designer can be downloaded to an ispPAC device. A download is accomplished by pressing the Download button on the toolbar or by selecting the Tools ⇒Download USR menu command. Programming circuitry in the ispPAC device is then enabled and the downloaded configuration is stored in E2CMOS memory on the chip. This process takes approximately 100ms and is dictated by programming constraints that guarantee proper E2CMOS operation.

Upload and Verify Operations

The upload operation is accessed via the Tools ⇒Upload menu command. When executed, the configuration stored in the ispPAC device is read and transferred to the schematic window of the current design.

The Verify command causes the configuration stored in an ispPAC device to be read and compared to the current design without making changes. The verify option is accessed by selecting Tools ⇒Verify.

Both operations can be initiated anytime PAC-Designer is running and there is an open design file. Setting the security bit and performing a download to the device will cause all subsequent verify operations to fail. See the Security section of this chapter for more information.

JTAG IDCODEAll ispPAC devices contain an internal 32-bit JTAG identification code unique for eachmodel number. The format of the code for the ispPAC10 is shown in Figure 4-1:

It is possible to read the JTAG optional IDCODE string from any device that contains such identification. When activated, the Tools ⇒Read IDCODE menu command will report results similar to the following:

SecurityA bit can be set inside an ispPAC device to prevent all future upload or verify operations from yielding valid data. The security bit provides an option to prevent unauthorized access to a device. Once set and loaded to a device via a download operation, the only way it can be removed is by reprogramming the device. Setting the security bit is performed by selecting the Edit ⇒Security menu command.

User Electronic Signature (UES) Bits

Within ispPAC devices, bits are made available for storing user specific information. These are called UES bits. These bits can be used to store device configuration, design related data or any information the user wishes to remain with the individual device. Please note that once the security bit has been set, however, these bits can no longer be accessed. For the ispPAC10, eight bits are available for user configuration and are set by selecting the Edit ⇒Symbol menu command and scrolling down to the User Electronic Signature line and pressing OK. This dialog can also be accessed by double-clicking on the UES text at the bottom of the design entry schematic screen.