packaging and pcb/package co/design - cst · pdf filepackaging and pcb/package co/design . cst...
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![Page 1: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/1.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Packaging and PCB/Package
Co/Design
![Page 2: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/2.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Introduction
CST flow for packaging design
Simplifying complex models
Model decomposition and partitioning approach
PCB/package co-design
Conclusions
Outline
![Page 3: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/3.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Memory interfaces have single-ended data rates in
the 1GHz-plus range and serial links are running
upwards of 10 Gb/s.
A precise design is required at the chip/package and
PCB level.
The analysis and optimization must be done in a
global context.
Physical design issues come into play as a full 3D
problem.
Introduction
![Page 4: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/4.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Packaging Design Overview
Bond wires
Flip chip bumps or wire bonds
Transmission lines
Micro vias
PTH vias
BGA balls
Horizontal and vertical discontinuities
![Page 5: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/5.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Package EM Simulation Workflow
Pre layout
analysis
Fast post layout
analysis
3D full wave post
layout analysis
and verification
![Page 6: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/6.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Package EM Simulation Workflow
Pre layout
analysis
Fast post layout
analysis
3D full wave post
layout analysis
and verification
![Page 7: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/7.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Parameter Sweep/Optimization BGA — Micro via to PTH optimization
TDR
![Page 8: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/8.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Package EM Simulation Workflow
Pre layout
analysis
Fast post layout
analysis
3D full wave post
layout analysis
and verification
![Page 9: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/9.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Package IBIS Model Header
![Page 10: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/10.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Fast Post Layout Workflow Select Nets
![Page 11: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/11.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
RLCG Extraction Macro
![Page 12: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/12.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Package EM Simulation Workflow
Pre layout
analysis
Fast post layout
analysis
3D full wave post
layout analysis
and verification
![Page 13: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/13.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
3D Full Wave Analysis
output
NEXT NEXT
in
![Page 14: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/14.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
3D Full Wave Extraction R/2 R/2 L/2 L/2
G C BGA DIE
![Page 15: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/15.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Field plots
Surface current – 10GHz
H-field (10GHz) H-field (1GHz)
![Page 16: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/16.jpg)
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PCB/Package Co/Design Overview
Memory
Int.
Antenna
SiP
PCB
RF/
Analogue Die
Digital Block
3
2
1
4
2
4
2
1
Courtesy Dr. I. Ndip, Fraunhofer Institute, Berlin Germany
![Page 17: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/17.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Package-PCB Interface (#) Where to truncate PCB and/or package?
(#) X.Jiang, H. Shi, “Effective Die-package-PCB Co-Design methodology and its deployment in 10Gbps serial link
transceiver FPGA packages”, on IEEE Proceedings of IMS 2009
![Page 18: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/18.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Test Structure
Model decomposition
![Page 19: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/19.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Results — S-Parameters
... Full model
__ partitioned model
At higher frequencies
results of full model differ
from results of partitioned
models
![Page 20: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/20.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Surface Current
10 GHz
![Page 21: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/21.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
PCB/Package Co-Design
Package PCB
PCB/package merge operation
Copy/paste
Import as sub project
SAM (System Assembly Modeling)
![Page 22: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/22.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
SAM Modeling
Product selection
Template selection for customized
settings
Solver choice
Reference model for settings
![Page 23: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/23.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Example
Package PCB
![Page 24: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/24.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Time and Frequency Domain Results
Return loss Insertion loss
NEXT
FEXT
Package PCB
Input
Output NEXT FEXT
![Page 25: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/25.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Eye Diagram
Eye diagram properties
![Page 26: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/26.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Field Plot Field well defined in isolated GND
![Page 27: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/27.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Sim time on 4 GPU system: 14h, 37min
Board size: 313x300mm
Smallest trace distance: 0.02mm
Full Model
![Page 28: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/28.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Effect of Model Truncation
![Page 29: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/29.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
Surface Current Full Model — 10 GHz
![Page 30: Packaging and PCB/Package Co/Design - CST · PDF filePackaging and PCB/Package Co/Design . CST ... global context. ... Package IBIS Model Header . CST](https://reader031.vdocument.in/reader031/viewer/2022021421/5a9b39fb7f8b9adb5c8de138/html5/thumbnails/30.jpg)
CST – COMPUTER SIMULATION TECHNOLOGY | www.cst.com
CST solutions has been demonstrated for package
simulation
From pre-layout to 3D full wave post layout CST offers
complete EM workflow
SAM can be used to simplify PCB/package co-design
workflow
Conclusions