packaging - · pdf filepackaging magazine on 3dic, tsv, wlp & embedded die technologies...

PackagingMagazine on 3DIC, TSV, WLP & Embedded die Technologies

3DISSUE N°26FEbruary 2013

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F r e e s u b s c r i p t i o n o n www.i-micronews.com

InDuSTry rEVIEWPackaging beyond

the mainstream

COMPany InSIGHTVisEra: WLP

promises LED price and performance

benefits

anaLyST COrnErHEV/EV market

power devicepackaging

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Dr Howard E Rhodes, Chief Technical Offi cer, OMNIVISION, USA

Jim De Filippis, CGO, Consultancy in Media & Broadcast, (formerly FOX TV), USA

Prof Franco Zappa, POLITECNICO DI MILANO, Italy

Alan Roberts, Colour Science Consultant (formerly BBC R&D), UK

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E D I T O R I A L

Packaging…What else?

Dear Advanced Packaging Community,

2013 started off like a rocket for us and for the 3D community, with a big

event held in Grenoble that was fully dedicated to 3DIC technologies: the

first European TSV Summit, organized by SEMI Europe. It was a great

show, involving all of the major 2.5 Interposer and 3DIC players, along

with 350+ attendees and two days of rewarding seminars and fruitful

discussions.

In addition to all of the traditional presentations, i.e. showing nice

demonstrator pictures, talking about electrical results, design, reliability,

inspection, metrology, supply chain evolution etc., many speakers pointed

out that we’re entering a critical phase where cost of ownership must be

seriously discussed -- and that the time for worrying about technological

bottlenecks and the motivations/drivers of 3D is definitely (almost)

over. What does this mean? It means these are exciting times for

Microelectronics! 3D is becoming a reality and I can’t wait to have a silicon

interposer in my tablet (but please, please, at a reasonable price!)

However, 3D is not the only interesting platform out there (this is good

news for us; otherwise business would be a bit slow). As you probably

know by now, Yole Développement investigates every mainstream

advanced packaging technology, i.e. flip-chip, FOWLP, WLCSP, Embedded

IC, etc. - but what you might not know is that we also provide a

transverse packaging activity (which we call “non-mainstream” or

derivative”) in which we analyze technological evolutions, challenges and

drivers of packaging technologies for LED, MEMS and Power Devices.

These derivative application areas are a real gold mine of technological

innovations, driven by different challenges which we usually meet in

mainstream packaging!

This special issue on non-mainstream packaging was prepared in

collaboration with several Yole Développement analysts across three

different business units: Eric (MEMS), Pars (LED) and Alex (Power Devices).

We hope you enjoy it!

Lionel Cadix,Market & Technology Analyst, Advanced Packaging,Yole Dé[email protected]

3 D P a c k a g i n g 3

F E b r u A r Y 2 0 1 3 I S S U E N ° 2 6

PLATInuM PArTnErS:

…These derivative application areas are a

real gold mine oftechnological

innovations, driven by different challenges

which we usuallymeet in mainstream

packaging!...

• 9th International Conference and Exhibition on. Device PackagingMarch 11 to 14, 2013 - Scottsdale, AZ • SEMICON ChinaMarch 19 to 21, 2013 - Shanghai, China • Successful Semiconductor FablessApril 10 to 12, 2013 - Paris, France

E V E n T S

SuccessfulSemiconductorFabless 2013

flyer_SSF_2013_Mise en page 1 19/02/13 10:39 Page3

For more information, please contact S. Leroy ([email protected])

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

GOLD ParTnErS:

INDUSTRY REVIEW • Two very different approaches to MEMS packaging 6

• Silicon photonics looks for 2.5D assembly at OSATs 8

• New packaging technology and new business models impact power module design 10

COMPANY INSIGHT

• VisEra: WLP promises LED price and performance benefits 12

• Danfoss: Keeping inverters cool puts EV/HEVs on the right course 14

• SUSS MicroTec: Spray coating in wafer-level packaging 16

YOLE ASKS • Packaging at STATS ChipPAC: A closer look 20

ANALYST COrNEr• Fast growing consumer market is changing the MEMS packaging business 24

• LED packaging: A $5 billion collection of little niches 26

• HEV/EV market power device packaging 28

EVENT REVIEW 30

C O n T E n T S

4 3 D P a c k a g i n g

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Please visit our website to discover the last top stories in advanced Packaging:

> eSilicon enables 2.5/3D architecture and the supply chain

> STATS ChipPAC and UMC unveil World’s first 3D IC developed under an open ecosystem model

> Besi: Datacon 2200 evo

(Courtesy of Yole Développement)

SuccessfulSemiconductorFabless

2013Novotel Vaugirard, Paris, FranceApril 10 to 12

Technology & supply chain challengesfor fabless semiconductor companies

Industrialization – Design –Overview of the fabless companies –Fabless in the Power Electronics industry

grandepub_fabless_ok_2013_Mise en page 1 15/01/13 13:01 Page1

INDUSTRY REVIEW – FOCUS ON MEMS PACKAGING

F E b R U A R Y 2 0 1 3 I S S U E N ° 2 6

3 D P a c k a g i n g6

Two very different approaches to MEMS packaging

While MEMS is clearly moving towards smaller, lower cost, more standard packaging solutions, there are widely different paths

to these same ends.

Robert bosch (bosch) and Silex Microsystems (Silex) epitomize the wide variation in possible successful approaches to MEMS packaging. While the major IDM continues to push traditional wire bonding to new limits, the leading MEMS foundry now supplies half its customers with through-silicon-via solutions.

As one of the top three MEMS producers, Robert bosch fabs well over a 1.5 million MEMS devices a day for annual sales approaching $800 million. And it’s turned that well developed in-house expertise to pushing fairly conventional packaging technology to new generations of smaller devices, co-designing the MEMS, the ASIC and the packaging to allow stacking and wire bonding ASIC to MEMS to laminate substrate in a plastic LGA package for almost all its products.

“It’s been a question of how far you can push the limits of the package and its manufacture,” says Georg bischopink, bosch VP of engineering, who’s responsible for MEMS packaging. “We’ve found we can push further than we thought before. Two to three years ago we thought that a 2 x 2mm2 package was the absolute limit, but now 2 x 2mm2 is standard and our newest mold package with wire bonding is 1.2 x 1.5mm2.” The IDM can improve the MEMS design and tune its volume manufacturing processes to tighter tolerances, while also driving the ASIC design to better handle smaller signals from the smaller structures.

Then it works closely with its assembly subcontractors to simulate all the effects and adjust the molding compounds, temperatures and pressures to manage the stresses. It has outsourced all assembly of mold packages since the mid 1990s to its own lines at subcontractors in Asia, starting with mold technology for automotive sensors. “It would be too expensive to do it in Germany,” notes Frank Schaefer, product manager, automotive sensors.

bosch roadmap is mostly wire bonding, while Silex aims to facilitate use of TSV.

The WLCSP magnetometer BMM150.(Courtesy of Robert Bosch)

Packaging beyond the

mainstreamby 3D Packaging Editorial Team

Emerging volume markets in MEMS, LEDs, power devices and even silicon photonics mean an increasing diversity

of demands and opportunities for

semiconductor packaging technology.

Despite some bumps along the way, MEMS,

LEDs and power devices are maturing into high

volume consumer markets on track

to reach a combined $40 billion over the

next five years. Silicon photonics is emerging

towards commercial growth.

That means growing demand for more

standard and lower cost packaging solutions

for volume production across these markets,

and also plenty of new, high value technical

problems to solve for their highly diverse

requirements.

This issue we look at some key developments and trends across these growth markets outside

of the mainstream IC world.

The company expects stacking of chips with wire bonding to continue to be its main approach even as sensors move increasingly to multichip combinations in single packages, that integrate some combination of accelerometers, gyroscopes, and magnetometers for full motion sensing, plus a microcontroller for more sophisticated processing and perhaps a rF chip for wireless. That means more thinning of the chips — of the CMOS more readily than the more sensitive MEMS — for triple stacking to still stay under the 1mm package height limit expected for mobile consumer products. “Our roadmap is that the standard LGA works fine,” says Schaefer, arguing that direct wafer-to-wafer or chip-to-wafer bonding or bumping won’t work well with multiple chips of very different sizes. “And TSV is too expensive,” he notes. “We’re still fine with wire bonding.”

On the automotive side, customers are discussing alternatives to SOIC packages, but concern for the reliability of the soldering in smaller packages outweighs the limited interest in reducing size. Here too the main emphasis is on pushing the conventional technology, to eliminate pre-mold and optimize the molding compound and process specifications.

Bosch has, however, recently made its first foray into wafer-level chip sized packaging, with its latest tiny 3-axis magnetometer. The magnetic sensor elements are integrated into the aSIC and solder bumps added on top. The combination of ASIC and solder bumps has a height of 0.6mm. “This is our only WL CSP so far without any mold,” notes bischopink, suggesting some caution about how widely applicable the technology will be, as it requires more robust sensors than for an LGA.

Silex pushes low-density TSVs to next generation

at the other end of the spectrum, the leading pure-play MEMS foundry Silex Microsystems has seen double digit growth in recent years, to close to $40 million in annual sales, in large part by providing its small fabless MEMS customers with an established through-silicon via interconnect to distinguish their products. Peter Himes, Silex VP of marketing and strategic alliances, says that about half its customers now use its low density, all-silicon TSV process, either for an interposer between the MEMS and aSIC chips, or as an element of the MEMS for its I/O to

the aSIC or the board, allowing reduction of the pad area for smaller, lower cost devices. These via-first connections are made in full-thickness wafers by isolating plugs of low-resistance silicon by etching around them and filling the trench with dielectric. TSVs for MEMS are generally low density, with typical pitches of 100 to 200µm and anywhere from 2 to 20 TSVs per device, on full-thickness wafers that avoid the need for thin wafer handling or special carriers, a much simpler and lower cost solution than the thin interposers for high density ICs.

The Swedish company is now introducing a new generation of copper-filled vias in full thickness wafers, pushing the low-density TSV approach towards smaller pitch and lower resistance, to extend application to smaller MEMS devices, and potentially to other analog, mixed signal, LED and power devices that also need 10s or 100s, not 1000s of vias. These 90µm-diameter copper vias use technology licensed from Swedish supplier ÅAC Microtec. A small etch from the front and a deep etch from the back create a waist in the middle of the full-wafer via profile that serves as a locking pin to prevent the relatively large plug from popping out during temperature cycling. The copper filling has a hollow core to compensate for the TCE mismatch between the copper and the silicon to improve reliability.

Next on the roadmap is a 50µm version, and a technology to build embedded passives into the silicon along with the copper vias, developed in conjunction with an European-funded research program. An inductor, for example, could be built through the vertical TSV to take up less substrate surface area than the usual horizontal coil, providing high inductance-per-unit-area integrated passive capabilities.

Silex is currently working to develop complete characterization of the thermal and frequency and other properties for the final packaging and assembly of these wafer-level TSV stacks, to offer customers a complete engineered solution of the whole system to ease design and speed transfer to production of the packaged device.

Paula Doe for Yole Développement

I S S U E N ° 2 6

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F E b r u a r y 2 0 1 3

(Courtesy of Silex Microsystems)

“Our roadmap is that the standard LGA works fine. we’re still fine with wire bonding,”says Dr Frank Schaefer, Bosch.

Dr. Georg Bischopink, Vice President, Bosch Engineering Sensors for External Customers and Sensor Packages, BoschGeorg hold in 1992 a Ph. D. in semiconductor physics, university of Freiburg, Germany. He has

worked at bosch since 1992 at various positions such as Section Manager - Development MEMS Sensor Products, Director, bosch MEMS-Production or Vice President, bosch Corporate Research Microsystem-Technology.

Peter Himes, VP Marketing & Strategic Alliances, Silex MicrosystemsPeter has over 25 years’ experience in helping startups and public companies establish their strategic direction and industry position. Experienced in IC and MEMS alike,

Peter has held VP of Sales and/or Marketing positions at QuickSil, SiTime, and Winbond Corporations.

Dr. Frank Schaefer, Senior Manager for Product Management Automotive MEMS, Bosch Franck hold in 1999 a Ph.D. in semiconductor physics, university of Wuerzburg, Germany. He has

been working with bosch since 1999 at various positions in the field of MEMS. Since 2012, he is head of product management for automotive MEMS sensors.

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

8

Silicon photonics looks for 2.5D assembly at OSATs

Silicon photonics is still a small emerging market, but growing demand for high speed data communication is starting to spur serious

interest. Yole Développement sees silicon photonic systems sales of some $215 million by 2017. The sector got a recent boost when Facebook announced plans to move to silicon photonics for its server interconnect, to enable disaggregation of computing into separate units for more efficient sharing of memory among multiple processors. Leading supplier Luxtera says it has shipped more than half a million of the optics-and-transistors-on-silicon devices to date, primarily for active optical cables in data centers, and sees demand for >10M units a year by 2016.

One key enabler of this growth will be moving from the electrical system-on-a-chip approach to an electrical and optical system in a package solution, made possible by the recent advances in 3D packaging technology. “The silicon infrastructure’s development of 2.5D heterogeneous integration is a key technology path forward for photonics,” says Chris Bergey, Luxtera VP of marketing. “Instead of putting the high value aSIC on a blank silicon interposer with vias and interconnects, we could put the photonics on the interposer and connect it directly to the upstairs

die. This allows the silicon to have optical I/O with much lower system power consumption, terabits of speed and >100 meters of reach.” Cisco Systems recently similarly announced that it was prototyping such a 2.5D silicon interposer solution.

Integrating optics into electronics for higher speed transmission requires optical waveguides, modulators and receivers in silicon, integrated with CMOS transistors, which silicon photonics suppliers now make on a single chip. More complicated is getting the optical power supply of light into the system, whether by also integrating III-V laser devices into the silicon, or bonding on the compound semiconductor devices, or micro packaging a MEMS mirror device on top, or by connecting a separate laser component to the chip by optical fiber. Getting the light out of the system means connecting the chip to optical fiber.

Integrating the diverse optics and electronics at the package level could be a simpler volume production solution, now that 2.5D heterogeneous integration technology for short, fast connections is emerging. A silicon photonics foundry could process the large photonic device, making waveguides, modulators, receivers, optical I/Os to connect to the aSIC, and

Though silicon photonics has so far relied on one-chip integration of optics with electronics to start to get real traction in the data communications market, sector pioneer Luxtera sees the evolving packaging technology for heterogeneous 2.5D integration as the next generation solution to scale integrated photonics to high volume production. The company is working to build up a scalable back end silicon photonics infrastructure with OSATs and assembly and test tool suppliers.

Optical ASIC foor plan & packaging. (Courtesy of Luxtera)

INDUSTRY REVIEW – FOCUS ON SIL ICON PHOTONICS PACKAGING


Optical fibers provide high-speed interconnect and provide supply of DC light to transmitters

Optical coupler:interfaces betweeninterposerand MT-ferrules

PhotonicInterposer

Package Substrate:• High & low speed IO• Power supply and• Mechanical support

to interposer

MT-Ferrules as example for pluggable fiber (MCF)interconnect

Heat sink mountedon package

“Instead of putting the high value

ASIC on a blank silicon interposer

with vias and interconnects,

we could put the photonics on the

interposer and connect it directly

to the upstairs die,” says ChrisBergey, Luxtera.

I S S U E N ° 2 6

9

Optical ASIC foor plan & packaging. (Courtesy of Luxtera)

F E b r u a r y 2 0 1 3

Chris Bergey, Vice President of Marketing, LuxteraPrior to joining Luxtera, Chris was a Vice president at

broadcom, responsible for establishing and managing broadcom’s WLan combo business, which he grew into one of broadcom’s largest lines of business. Prior to spending nine years at broadcom, bergey worked for Multilink Technology Corporation and Advanced Micro Devices. Chris received his Mba from the university of Maryland and a bS in Electrical and Computer Engineering from Drexel University.

adding a limited number of TSVs for power and ground to the printed circuit board. The interposer wafer could be full thickness or thinned, depending on application requirements. A packager could then micro bump an advanced CMOS control die and a little glass connector component on to the photonic/interposer-- either chip-on-chip or chip-on-wafer--then plug in and align the optical fiber bundle to that connector. “Very little new needs to be developed beyond the natural evolution of the mainstream 2.5D packaging processes,” argues Bergey. The vias would need to be made through SOI wafers for the photonics/interposer, but there don’t appear to be major issues there. Assembly equipment will need to be modified to very precisely align the glass plug to the photonics substrate, and then to align the fiber into the connector. The required precision is on the order of that of copper pillar bumping, more precise than that for flip chip. Bergey figures commercial die attach tools could be customized to do the job, doing first pass alignment by machine vision, then running light though the fibers for final optical alignment.

Luxtera has been busy finding partners to help in its strategy of leveraging the existing semiconductor manufacturing infrastructure to ramp silicon photonics quickly to low-cost volume production, including for packaging, assembly and test. It has designed its photonics to use standard processes and tools, and is licensing its technology to encourage others to develop products to add to the volumes as well. The company is now producing on 200mm wafers at Freescale Semiconductor, and developing

a 300mm process at STMicroelectronics. ST plans to design and manufacture its own products for its customers with the process, as well as fab devices for Luxtera. Luxtera also has supplied its process to OpSIS for an open foundry service with design kit and multi-product wafers run at IME in Singapore and at Luxtera’s own fab, to help bring down the cost of photonics development for other users. It’s working with an OSaT to build a standard process for optical attach and test. It has partnered with Tokyo Electron to customize a standard probe tool for high speed wafer-scale optical testing, with fast alignment using prober cameras. After developing the needed volume technologies with the first key partner, Luxtera expects that partner to sell to other users as well, while Luxtera rolls the technologies out to more suppliers to create a more robust supply chain. “There’s a whole ecosystem that has to be built out as systems move from copper to optical interfaces for 25Gbps and beyond—it’s a big transition,” says Bergey.



Optical coupler:interfaces betweeninterposerand MT-ferrules

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6


New packaging technology and new business models impact power module designPotential volume markets in alternative energy applications have attracted investment into both new packaging technologies and new business models that could have a big impact on the power device market. We check in with International Rectifier on technology for replacing wire bonding with modular solderable components, and with iQXPRZ on the rise of the fabless/foundry option.

The potentially high volumes and extreme

performance demands of the hybrid and

electric vehicle market will have significant

impact on power device technology. One recent

example of the innovation being driven by this

market is International Rectifier’s new modular

IGbT and diode co-pack building block that can

be surface mounted in different combinations,

simplifying power module construction and allowing

systems makers to more easily create their own

optimized power circuit topologies.

Ir has replaced the wire bonds with solderable

metal on both sides of the thin IGbT and diode

dies, and attached both to a direct bonded copper

substrate. These pre-assembled and pre-tested

building blocks are then attached to a DbC—singly

or in multiples, either face up, or face down flip-chip

style for shorter connections and flexible design.

Eliminating the wire bonds improves reliability

and makes a more compact device, while the

double-sided cooling signifiantly improves thermal

performance. After attaching the leadframe, this

compact unit is then overmolded. Compared to

a conventional module wirebonded in a gel-sealed

plastic package, this process adds a top layer of

DbC, but eliminates the wirebonds, gel and base

plate, although a base plate can be added as an

option.

Jack Marcinkowski, Sr. Technical Marketing and

Applications Manager for International Rectifier’s

automotive business unit, says this building-

block approach significantly reduces overall

system cost, by improving mechanical, electrical

and thermal performance, but especially by

providing a standardized and tested building block

that simplifies power module customization and

assembly and improves yields. IR will both use the

technology in its own modules and sell the devices

to outside customers.

“This intermediate co-pack fills the gap between

discretes and modules,” he says, noting that the

compact modules can replace a number of discrete

packaged devices. “There’s no precedent in the

industry. Manufacturers can use the co-pack like

a surface-mounted component to create their own

optimized custom topology, instead of trying to

design their system around an existing commercial

module.” The compact module is reportedly

roughly half the size and a quarter of the weight of

a similarly-rated wire-bonded gel package, opening

design possibilities such as putting the inverter

inside the electric motor housing, for example.

Key to the development was selecting proper

device metallization, die attach, materials with

well matched thermal expansion properties,

and devising a high yielding manufacturing

process. The company says the payoff is major

improvements in performance for EV/HEV inverter

demands. Marcinkowski reports the devices have

held up through some one million thermal cycles so

far in company tests, while wirebonds—the most

common failure mechanism for power devices—

may start to crack or delaminate at 100,000 cycles.

INDUSTRY REVIEW – FOCUS ON POWER DEVICE PACKAGING

IGBT and diode dies with solderable metal on both sides can be easily assembled into co-packs and modules. (Courtesy of International Rectifier)

I S S U E N ° 2 6


F E b r u a r y 2 0 1 3

The lower resistance of these direct soldered

interconnects also reduces losses and means about

a 5%-7% decrease in power dissipation, he says.

The DbC sandwiching the dies provide double-

sided cooling capability, though initial applications

using conventional heat sink approaches won’t get

the full advantage of it. “To switch to double-sided

cooling, the mechanical design of the inverter

cooling system will have to be adapted,” notes

Marcinkowski. “But it will soon be necessary to

do that, to improve the heat transfer from more

compact packages.” The IBGT-and-diode co-pack

can run at a 25°C higher junction temperature

than the current typical 150°C. With the double-

sided cooling, IR figures the device can potentially

achieve as much as 80% higher current rating

than a single-side cooled device with a maximum

junction temperature rating of 150°C.

Fabless iQXPrZ designs power modules for foundry production

also relatively new to the traditionally IDM-

driven power device business is the rise of fabless

companies and foundries, also expanding the

options for module design and manufacture. The

boom of investment in solar and wind energy in

China attracted a crowd of new entrants to the

market for inverters and their component power

devices and modules. Many of these players had

the expertise and capital to focus on only one step

in what looked to be a big volume opportunity

to bring down manufacturing costs in the power

sector. Though the recent downturn in the

renewable energy sector has hurt these suppliers,

some are successfully expanding the power

sector’s options for lower cost production.

One of these fabless module design companies

now breaking into the European market is QXPrZ

(pronounced IQ Express). The Manila-based

company works closely with a local established

power device assembly subcontractor to prototype

and manufacture the devices in low volume. The

business got its start in the alternative energy

bubble five years ago, designing complex power

modules using off-the-shelf discrete devices

for small inverter makers. With the plunge in

renewable energy demand, the company has lately

been focusing largely on smart power modules for

the home appliance sector, integrating IC drivers

with IGBTs and MOSFETs into compact packaging.

VP and COO Cherie Sasan says the company

strategy is targets small companies who need

complex customized power modules in very small

quantities, aiming to offer lower cost products

than the technology-leading European module

makers, but better quality than its fabless/foundry

Chinese competitors. “Most of our customers are in

Europe,” says Sasan. “And most of our competition

is in China. Most of our customers have used

Chinese products before they turned to us.”

To make manufacture of the custom products more

efficient, the company aims to use a standard

plastic housing which has multiple different holes

to accommodate different leads for different

products, and a standard leadframe inside, whose

different pins can be connected or not as needed.

It also sticks to conventional technologies, producing

some legacy products obsoleted by the big IDMs.

“We’re not innovators,” says Sasan, though she does

note that the company is working on developing an

alternative substrate material to AlN.


Jack Marcinkowski, Sr. Technical Marketing and Applications Manager, International rectifier’s Automotive Business Unit.Jack is responsible for development of power modules with focus on HEV and EV applications. Jack first joined IR in 2003

as an applications Design Manager working for the automotive Business Unit for 4 years and re-joined IR in July of 2011. Jack holds a MSEE degree from Technical university in Warsaw, Poland as well as an MBA degree from UCLA in Los Angeles, California.

Cherie Sasan, Vice-president & COO, iQXPrZ PowerCherie worked in the semiconductor industry for more than 20 years. She joined iQXPrZ Power Inc in 2008 and is responsible for corporate strategy, business development and commercial operations.

Prior joining iQXPrZ Power Inc, she was the Development Engineering Manager of Team Pacific Corporation. She holds a degree in Electronics and Communications Engineering from the Mapua Institute of Technology and is currently taking up MBA at the Ateneo de Manila-Regis University.

SuperSOT (Courtesy of iQXPRZ Power)

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

12

C O M P a n y I n S I G H T

WLP promises LED price and performance benefits

Could a device packaging technology well-known in the rest of the semiconductor industry prove revolutionary in the LED

sector? That’s what Hsinchu, Taiwan’s Visera Technologies hopes, as it continues adapting the wafer-level packaging (WLP) it uses in CMOS image sensors to LEDs. WLP differs from mainstream LED packaging, where emitter die are surrounded by electrical and optical components they need in leadframe, chip-on-board and ceramic packages. Instead, Visera puts these components onto a circular wafer that it then dices into individual packages. That promises to raise output and lower LED unit costs, explains T. H. Lin, director of R&D for Visera’s LED business.

“The automation rate is not very high with conventional LED packages,” Lin said. “Improving that would lower cost. Usually, LEDs are produced in a room full of benches. In conventional packages one bench may make a hundred units at a time, but using WLP with 8-inch wafers, each bench can produce around 2000 units, for 1mm x 1mm die. Also, in LEDs an important part of the performance comes in binning for package color. If your component is outside customer application requirements, they cannot use them, so improving the binning yield can help reduce costs.”

WLP lets Visera use in-line controls to compensate for color correlated temperature (CCT) variations and put more packages into desirable bins. “The incoming LED chips have some variation in wavelength and chip power, but we have very solid technology to check that distribution,” Lin explained. “Though the chip dominates white light performance, phosphors also play a role. Many

packaging houses mix the phosphor powder into an encapsulant in a controlled ratio, but that makes it difficult to work on the phosphor coverage. We’re directly coating the phosphor onto the LED chip, which means that we can control the white light output by varying the coating thickness and phosphor coverage.

and though optical technology is an important consideration for packaging designs, Lin warned against over-stating its capabilities. “Packaging only can reduce the efficiency loss and improve light quality,” Lin said. “To improve the lumen output, we have to improve our light extraction efficiency. We are using lenses, optical design and manufacturing to enhance this. For light quality, we are compensating CCT. To get color rendering index (CRI) into warmer areas means using different phosphors, and for that customers still need to accept higher costs.”

Initially Visera developed its WLP technology for 8-inch silicon wafers, where it delivered encouraging results, for example with high-end die from Durham, North Carolina’s Cree, Inc. “We adopted different chip providers, including local Taiwanese and worldwide first-tier manufacturers and compared them,” Lin said. “Cree chips in Visera silicon-base WLP actually delivered better brightness, light-extraction efficiency, and less yellow emission than Cree packaging.”

Silicon WLP also delivers lower lumen output degradation than conventional packages. “LED white light lumen output degradation mostly comes from phosphor decay at high temperature,” Lin explained. The improvement comes because silicon’s high thermal conductivity helps keep LED chips and phosphors cool, and because its coefficient of thermal expansion is similar to GaN LED chips, reducing stresses in the packages.

but in October 2011 Visera started switching its LED WLP processes to 8-inch aln wafers, and is now in production on that technology. “It’s for two main reasons: breakdown voltage and thermal conductivity,” Lin explained. The shift boosts breakdown voltage from 300V to 6000V and thermal conductivity from 150 W/mK to 170 W/mK. While improved thermal conductivity brings further

Visera Technologies’ director of R&D, LED business, T. H. Lin explains how his company’s wafer level packaging economically delivers more uniform color and improved thermal properties.

T. H. Lin, Director of R&D, LED business organization, VisEra Technologies

Wafer level progression: VisEra’s AlN wafer-level packaging substrate (centre), after LED chip mounting and phosphor coating (right) and lens mounting and finishing (left).

(Courtesy of VisEra Technologies)


device lifetime benefits, the higher breakdown voltages allow Visera to develop higher-power products, more capable of withstanding power surges and lightning strikes.

Thanks to this step Visera has progressed from originally serving the 1W-5W market segment to now producing 90 mm x 90 mm ‘9090’ packages rated up to 50W, and set to reach 90W. Such performance moves the company nearer to top LED makers, like Cree and San Jose, California’s Philips Lumileds. “Our 9090 20W emitter has just gained Energy Star LM80 certification after a 6000 hour reliability test,” Lin said. “For the 9090 the competitor will be Cree’s MT-G package, and maybe now Lumileds’ Luxeon M. We provide similar performance with a very competitive price.”

now that it can deliver lighting-class devices, the Taiwanese company is also moving on to providing compact light engine modules. “Our 11W, 16W and 20W light engines are in mass production already, and we have 36W, 50W and 90W in development,” Lin said. “For PAR 38 bulbs, for example, our small packages, driven up to 20W, compete against light engines based on traditional packages that can only be driven only up to 12W maximum. As our emitters are quite small, we can integrate them with a driver IC and all other light engine components on one board. That all means our customers can integrate them into their products more simply and flexibly.”

www.viseratech.com

I S S U E N ° 2 4 a u G u S T 2 0 1 2


Solution evolution: Silicon WLP substrates originally combined high thermal conductivity and a similar coefficient of thermal expansion to

GaN. Now AlN substrates provide similar CTE, as well as higher thermal conductivity and breakdown voltage. (Courtesy of VisEra Technologies)

T. H. Lin, Director of R&D, LED business organization, VisEra Technologies Prior to joining VisEra in 2003, T. H. Lin worked at Taiwan Semiconductor Manufacturing Company (TSMC) and Industrial Technology Research Institute (ITRI) for more than 14 years. He received his B.S. degree in Geophysics from National Central University in 1985 and M.S. degree in Material Science from National Chiao Tung University in 1995.

http://www.i-micronews.com/reports

www.viseratech.com

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

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C O M P a n y I n S I G H T

Keeping inverters cool puts EV/HEVs on the right course

In early 2013, two leading electric or hybrid electric vehicle (EV/HEV) producers tackled a major obstacle to these cars’ wider use,

by signalling major price cuts. That’s partly down to improved motor designs, and given inverters’ central role in EVs’ power train, it’s reasonable to assume that they have contributed to that improvement. But Siegbert Haumann, senior director, automotive and industrial power modules at Danfoss Silicon Power in Flensburg, Germany, noted cost savings must not sacrifice reliability or compactness. And though power transistor die used in these applications are shrinking, this adds to the reliability challenge. “The cooling surface gets smaller, so the heat you need to remove from the system per area increases,” Haumann told 3D Packaging. “The requirement for efficient module and inverter thermal management becomes key to meet stringent cost targets without jeopardizing lifetime.”

To provide optimal solutions to these needs Danfoss Silicon Power collaborates closely with its customers. “We can do a full custom design

that offers required power density and life-time while still providing flexibility in design to offer the desired room for differentiation,” Haumann said. “Designs, from topology to thermal and physical design, are done in close collaboration with customers and optimized for their system. An OEM says how much room is available, and if we cannot put it in there then we are out of business.”

In meeting such demanding specifications Danfoss Silicon Power realised early it would have to diverge from established indirect cooling solutions. “They are fully sealed systems, with liquid coolant flowing through piping in a metal plate,” Haumann explained. “Modules are mounted and bolted on top, with thermal interface material in between, which is a marginal heat conductor. after a couple of years it becomes a reliability risk, because it is pushed out by the pump effect you get with temperature cycling between materials with different coefficients of thermal expansion. That brings a terrible degradation of thermal conductivity and therefore lifetime. So, our intention was to get rid of this thermal interface material.”

and while Haumann’s company targeted the performance that hedgehog-looking pin fin heat sinks achieve, it also hoped to improve on them too. “Pin-fin coolers are very expensive, and can have gradients in temperature across the surface,” he said. «This can lead to semiconductor devices in different places in the module operating at different temperatures, which leads to degradation.»

Danfoss Silicon Power’s answer to these problems is an innovative cooling solution that it calls ShowerPower. “ShowerPower guides coolant in a highly efficient laminar flow along the bottom of the module base plate,” Haumann said. “It prevents temperature gradients across the module at highest efficiency. It also allows the use of flat base plates, which makes introducing a dual sourcing strategy for the module simpler. To keep coolant where it is we developed a double-walled gasket. Extensive life-time testing for wind applications has confirmed its reliability for long-life applications in harsh environments.”

ShowerPower also allows manufacturers to move away from two-dimensional module designs, with

Siegbert Haumann, Senior Director Customer Relations, Danfoss Silicon Power


Power density and life-time: Danfoss Bond Buffer Technology offers a leap in power and temperature cycle capability. (Courtesy of Danfoss Silicon Power)

Packaging utilizing molded power modules with Danfoss Silicon Power’s ShowerPower cooling allows carmakers to shrink their power trains, according to Siegbert Haumann, the company’s senior director, automotive and industrial power modules.

power electronics on a single cooler. Instead, three-dimensional stacks offer significant improvements in power density by incorporating several cooling units. “We’re using transfer molding technology, which is an established technology, but we’ve been first to bring it to power modules,” Haumann commented. The resulting rugged modules can be slotted between layers containing ShowerPower inserts, he explained. “Such a stack design offers a completely new level of design freedom in inverter design.” Though ShowerPower is also used in power modules beyond the automotive industry, it’s well suited to how EV/HEV manufacturers address the size-reliability-cost challenge. “A trend that we are trying to accommodate is a move towards a complete automotive power train in one box,” Haumann observed.

At the PCIM power electronics exhibition in nuremburg, Germany, in 2012 Danfoss Silicon Power also introduced its latest bond buffer joining technology. Soon to be released, it uses silver sintering to attach a thin copper foil onto a semiconductor die’s top metallization surface. Copper wire bonding to the copper foil avoids damaging the sensitive die like other interconnect approaches can. This also improves thermal performance and promises a significant leap in lifetime, Haumann explained. “We now have the complete technology set in place to meet power density and performance targets in automotive traction for 2016 and beyond,” Haumann said. “To fully benefit from these technologies, inverter

design on a system level must be considered. Danfoss is aiming to utilize this technology in multiple applications in our industry and renewable energy segments. However, for automotive traction we are starting to actively look for the right partners.”

aiding power electronic integration in this way, Haumann is excited to see the improvements that Danfoss Silicon Power’s technology promises. “The big question mark is always timing, having technology ready when a new program starts. But once designs are qualified, the potential is enormous.”

www.danfoss.com

I S S U E N ° 2 6 F E b r u a r y 2 0 1 3


Even flow: Unlike pin-fin or indirect water coolers, Danfoss Silicon Power’s ShowerPower coolers offer completely even cooling across a surface. (Courtesy of Danfoss Silicon Power)

Siegbert Haumann, Senior Director Customer Relations, DanfossSilicon Power Siegbert Haumann is responsible for Power Modules for industrial and automotive applications at Danfoss Silicon Power in Flensburg, Germany. Siegbert holds a bS in Mechanical Engineering from the Fachhochschule Konstanz and a Masters in International Marketing from the Export Academy Reutlingen. He started his career in the back-end assembly of power electronics in 1991. Prior to Danfoss he held positions at robert bosch GmbH and Kulicke and Soffa.

“An OEM says how much room is available, and if we cannot put it in there then we are out of business,” says Siegbert Haumann.

www.danfoss.com

F e b r u a r y 2 0 1 3 I S S U E N ° 2 6

16

c o m p a n y i n s i g h t

Spray coating in wafer-levelpackaging

however, there is no standard WLp, as each chip varies in thickness, material composition, structure and size. this leads to a growing variety of packaging technologies and, thus, the need of flexible processes. Most of the required process steps are performed on standard wafer processing equipment limiting the methods to common processes.

spray coating of organic materials is one of the key technologies to overcome the current barriers and is more and more becoming standard. It is already commonly used in printed circuit board technology or for the coating of large panels. in wafer fabrication it is less common because spin coating is the superior technology as long as the wafer surface is flat. In fact, the adoption of spray coating for wafer processing was pioneered by microsystems applications with its need for conformal coated resist films across severe topographies. Remarkably, it is today the advanced packaging technology that is responsible for much of the added capacity in spray coating.

As long as wafer-level packaging only requires to add a redistribution layer, copper posts or solder spheres on the front side of a wafer, engineers can choose from a set of relatively standardized processes. this is the case for many purely electronic devices. Wafer-level packaging of devices that include optical or mechanical functions however, require more specialized processes. The package must for example, satisfy the requirements for transparency without optical degradation over time or support the mechanical function. these kinds of wafer-level packages drive the need for conformal resist deposition on topographic structures like through-silicon vias (TSV). Also, conductor traces have to be routed conformal from the i/o pad onto the 3-dimensional body of the package (e.g. a cap die). Advanced interposers have cavities that are etched into the substrate and for instance, require a conformal routing of electrical traces from top to bottom of the cavity or metal structures in the bottom of the cavity.

up to now the only standard method for covering topographies has been electrophoretic resist deposition. this technology has some major

drawbacks such as the necessity of a conductive layer on the wafer surface, the needs for special resist formulations. plus, it is a self-limiting process in regard to the resist thickness. in contrast, the spray coating technology offers a wide variety of materials for coating on almost any type of topography. Furthermore, it does not require any special layer underneath. all this leads to reduced process complexity and a cost-competitive solution.

Wafer-level packaging processes that include spray coating can for example, be found in the fabrication of image sensors[1] and saW (surface acoustic wave) devices[2].

Figure 1 shows the cross section through a tsV of an image sensor die[1]. the thickness of the wafer is approximately 100 µm and the TSV is etched from the backside of the wafer and ends on one of the metal contact pads of the sensor device on the front side. the purpose of these packaging-scale tsVs is to route the electrical contact into an area array on the back side of the wafer. This is necessary because the device is a front side illuminated image sensor so that the ball grid array cannot be placed directly onto the front side of the wafer as it would block the light from the sensor.

The packaging design requires a conformal organic stress buffer layer inside the TSV and a conformal photoresist film in order to pattern the redistribution layer. Spray coating has been successfully applied for the wafer-level packaging of image sensors and is used in high volume production today.

Dr. Dietrich Tönnies, Director of Process Technology, SUSS MicroTec

3 D p a c k a g i n g

Driven by the need for form factor reduction of components used in mobile devices, technologies like wafer-level packaging and high density interposers are increasingly adopted.

Katrin Weilermann, International Product Manager Coater Systems, SUSS MicroTec

Figure 1: Through-silicon via of image sensor with spray coated inner dielectric layer and spray coated

resist film[1] (Courtesy of SUSS MicroTec)

“Spray coating is an enabling

technology that offers new

dimensions in Wafer Level

Packaging” says Dietrich tönnies.

An example for a wafer-level package that has to support a mechanical function is the die-size SAW-Package developed by Epcos[2]. the working principle of a surface acoustic wave (SAW) filter is that the surface of a piezoelectric substrate is caused to vibrate, thereby inducing a voltage between conducting surface structures in dependence of the frequency of the vibration. the package has to maintain the mechanical and electrical performance of the surface structures so that common wafer-level packaging by simply adding a rerouting layer on top of the wafer is not possible. In this case a cap die is attached to a polymer structure that frames the device. the cap die protects the active layer but requires rerouting of traces from the original electrical contacts of the device onto the cap die (Figure 2).

Figure 3 shows a sem image of a Dssp device before wafer dicing. The metal interconnects from the i/o pads on the cap die have to run across a severe topography defined by the thickness of cap die and polymer frame. common photolithographic processes applying spin coating do not provide a resist layer of sufficient quality in regards to conformal coverage.

the performance of spray coating strongly depends on the resist. generally, spray coat resists are prepared by diluting standard spin coating materials to lower their viscosity. novolak resists have long

been identified to be very suitable for spray coating. reason is that the glass transition temperature of typical Novolak resins is above the softbake temperature. This is important because the resist has to be softbaked after it has been deposited onto the wafer. If the resist film becomes soft during softbake surface tension starts to pull back the resist from protruding corners thus, having a contrarian effect on the conformality of the coating. negative acting resists with polymers that crosslink during exposure often have the tendency to become soft during the softbake. In many cases it is difficult to achieve good conformal coating results. unfortunately, materials like su8, thb151n and polyimide fall into this category (Figure 4, top).

I S S U E N ° 2 6 F e b r u a r y 2 0 1 3

173 D p a c k a g i n g

Figure 2: Design of Epcos’ die sized SAW package (DSSP)[2]

(Courtesy of SUSS MicroTec)

Figure 3: SEM image of DSSP packages before wafer dicing[2] (Courtesy of SUSS MicroTec)

Figure 4: Cross section of KOH etched silicon wafer spray coated with Polyimide HD4110 (top) and with

PBO HD8820 (bottom). Coverage of the top corner is significantly better with PBO than with Polyimide.

(Courtesy of SUSS MicroTec)

F e b r u a r y 2 0 1 3 I S S U E N ° 2 6

The deposition of thick resists for electroplating (such as the THb151N) and of permanent dielectric layers[3] however, is essential for advanced packaging. The search for suitable organic dielectric materials in particular has been an important milestone for the successful introduction of spray coating. The positive acting WPr5100 and epoxy based solder mask materials were among those passivation and stress buffer materials that were successfully spray coated. The positive acting PbO (e.g. HD8820 from HD Microsystems) is another example of a photo-dielectric that allows achieving good conformal coatings as can be seen in Figure 4 (bottom). The material stays on the top corner of the KOH etched structure even during the softbake leading to a film thickness of almost 10µm at this critical position. recent process developments indicate that the results with negative acting materials can still be optimized.

In conclusion, spray coating is an enabling technology that offers new dimensions in wafer-level packaging and forces a rethinking in design. For the packaging of optical and MeMS devices in particular spray coating is of fundamental importance. SuSS MicroTec offers the spray coating technology on a 200 mm and 300 mm fully automated equipment platform for high volume production.

The fully automated system for spin / spray coating, baking and developing of substrates from 2” to 200 mm is specifically designed for volume production.

www.suss.com

References[1] Dzafir Shariff, Nathapong Suthiwongsunthorn, Florian

Bieck, Dr Jürgen Leib, “Via Interconnections for Wafer Level Packaging: Impact of Tapered Via Shape and Via Geometry on Product Yield and Reliability”, Proceedings of the 58th Electronic Components and Technology Conference (ECTC), pp. 858 - 863 (2007).

[2] Barbara L’huillier, Michael Hornung, Dietrich Tönnies, Michael Jacobs, Christian Bauer, Frank Hammer, Thorsten Heuser and Gregor Feiertag, “Application of an Angular Exposure System to Fabricate True-Chip-Size Packages for SAW Devices”, 18th European Microelectronics and Packaging Conference (EMPC), 12.-15. September 2011.

[3] Michael Töpper, Thorsten Fischer, Tobias Baumgartner, Herbert Reichl, “A Comparison of Thin Film Polymers for Wafer Level Packaging”, Proceedings of the 60th Electronic Components and Technology Conference (ECTC), pp. 769-778 (2010).

Dr. Dietrich Tönnies, Director of Process Technology, SUSS MicroTec He is head of the applications Department and Demo Lab at SuSS MicroTec’s headquarter in Garching, Germany. He joined SuSS in 1997 as Product Manager for Mask aligners and for many years was responsible for developing the company’s advanced Packaging market.

Katrin Weilermann, International Product Manager Coater Systems, SUSS MicroTecShe studied chemistry at the NTa Isny. She worked in the r&D department at the Fraunhofer Institute IIS-b in erlangen, before joining SuSS MicroTec in 2001 as a Production and r&D Manager. Since 2005 she has the position of an International Product Manager Coater Systems and graduated with an Mba at the university of Ingolstadt in 2007.

www.suss.com


SEMI Networking Day GrenobleFocus on Printed Electronics19 March 2013 - Minatec, Grenoble (France)www.semi.org/seu

Organized by: SEMI Europe Grenoble OfficeAnne-Marie DutronPhone +33 4 38 78 39 [email protected]

Net

wor

king

Day

This Networking Breakfast is a SEMI Europe initiative to support European companies, start ups, laboratories involved in the emerging Printed Electronics market.

The Networking Breakfast will feature 4 invited speakers:

• French actors and actions in Printed Electronics Jean-Yves Gomez, President, AFELIM

• Introduction of CEA-Liten openned Platform for Printed Electronics development Christophe Serbutoviez, PICTIC Platform Director, CEA-LITEN

• The new kid on the block for the opto-electronics and imaging industry Laurent Jamet, Business Development Director, ISORG

• Printed Electronics: From hype to real business Jean-Christophe Eloy, President and CEO, Yole Developpement

A Speed Networking session will allow member companies that are interested to present themselves in front of the attendees for 5 minutes.

Partners:

www.semi.org/seu

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

20

Y O L E A S K S

Packaging at STATS ChipPAC: A closer look

Yole Développement: Dr. Han before we start talking about SCL, can you share a little on your educational and employment. Many of us remember your early career at Bell Labs and later at Anam Semiconductor.

BJ Han: While pursuing my Doctoral and Master of Philosophy degree in Chemical Engineering at Columbia university, I worked in the research department of IbM where I had my first opportunity to work on advanced semiconductor technology. After graduating from Columbia, I joined aT&T bell Laboratories where I spent the next 8 years working in the Research Division on material physics, including the development of organic and inorganic materials used in electronic circuits such as hybrid ICs and MCMs. The next step in my career took me to anam Semiconductor where I was the Director of Product Development. I joined STATS as Chief Technology Officer in 1999 and became Executive Vice President and Chief Technology Officer of STATS ChipPAC in 2004.

YD: For our younger readers, can you remind us about the STATS merger with ChipPAC back in 2004 and how that is going.

BJH: Prior to 2004, STaTS and ChipPaC were two mid-tier players that didn’t have the technology or manufacturing scale to be a leader in the Outsourced Semiconductor assembly and Test (OSAT) industry. The merger was significant because it provided us with increased scale and

technology offering, complementary assembly and test capabilities, and a broader geographic footprint. We have transformed STATS ChipPAC into a technology leader in the mobile convergence market.

YD: What are your job responsibilities in the SCL organization?

BJH: My responsibilities include driving our research and development activities, technology and cost innovation, package design and characterization, corporate test engineering, product and technology marketing, and Intellectual Property (IP) management as well as co-management of our operational process engineering.

YD: STATS ChipPAC has been deeply involved with scaling up the Infineon ewLB fan out technology. Can you share with us where that stands and where you see that going? (Figure 1)

BJH: Just one year after successfully ramping Infineon’s first generation eWLB on 200mm wafers, we became the first company in the world to implement 300mm eWLB manufacturing. We have shipped more than 400 million packages and have been rapidly developing eWLb into a versatile technology platform for the semiconductor industry’s evolution from 2D package designs to 2.5D interposers and 3D IC integration. We have also been working on a larger scale panel manufacturing approach to further increase the yield, throughput and cost-effectiveness of eWLB. although the initial adoption of eWLb was focused on the mobile market, we are now seeing a wider adoption in networking, microcontroller, embedded and automotive applications. eWLB is one of the key wafer level platform technologies to bridge advanced node fab technology and advanced high performance packaging.

YD: It appears that your version of copper pillar bump technology is your fcCuBETM. What would you like to share with us about this exciting technology? (Figure 2)

BJH: fcCubETM is a unique technology pioneered by STaTS ChipPaC nearly ten years ago that has a powerful combination of packaging features such as copper (Cu) column bump with Pb-free solder cap, bond-on-lead (BOL) substrate pad design with

Byung Joon (BJ) Han, Executive VP and CTO, STATS ChipPAC


Figure 1: Evolution of eWLB from 2D to 2.5D/3D. (Courtesy of STATS ChipPAC)

Yole Développement recently had an opportunity to interview Byung Joon (BJ) Han about his long career in microelectronics packaging and the current activities of STATS ChipPAC, Ltd. (SCL).

open solder resist (Open SR) and the use of a Molded Underfill (MUF) process. fcCuBE offers natural scalability to advanced fab nodes such as 28nm or 20nm, compatibility with various flip chip package types including fcbGa and fcCSPs, and supports a wide range of bump pitches all the way to the sub 80µm range by either using a conventional mass reflow (MR) process or thermo-compression bonding (TCB). fcCuBE squarely addresses the requirements of performance, form factor and cost in the most optimal way by leveraging the HVM capability of a lower cost substrate technology.

fcCubE is one of the key technologies in our platform of packaging solutions that address performance, power and form factor requirements across a wide range of products and applications. We are in volume production and anticipate adoption of fcCubE into a majority of the next generation mobile and consumer products, particularly in smartphone and tablet application processors, as well as in many consumer products such as GPS processors, STb applications, etc.

YD: As the industry moves to more advanced technology nodes the use of ULK dielectrics (ultra low K) is becoming more and more prevalent. It is well known that during FC interconnection of such die these materials are susceptible to cracking. We understand that SCL has a new technology “BOL” (bump on lead) which addresses this problem. Can you share some of the details with us?

BJH: advanced Si nodes tend to employ materials with a lower dielectric constant (K value) for performance reasons. However, the process of lowering the K value often involves compromising the mechanical properties of the material thereby increasing the risk of packaging-induced damage to the Si. The challenge is further exacerbated by the use of stiffer Cu bumps which are required to achieve higher I/O and current densities with finer bump pitches.

fcCuBE’s unique BOL pad design enables an interconnect geometry that is fundamentally more compliant and dramatically reduces the stresses induced in the die which in turn relieves the stress being transferred to the ELK or ULK materials. Our thermo-mechanical simulation models show a 30-35% reduction in principal stress on ELK by using BOL over conventional SMD+SOP substrate pad structures. We have substantiated the results with extensive package characterization and have confirmed the robustness of BOL in field applications as well.

YD: The industry certainly acknowledges the leadership of SCL in integrated passives technology (IPD), how has customer acceptance been on this technology? Can you tell us where the focus has been application wise?

BJH: We work with a number of companies on rF packages for mobile and hand-held devices where small form-factor, light weight features as well as low-loss are demanded. IPDs are primarily used to make accurate filters, baluns, matching circuits, etc, which are indispensible parts of rF transmission and reception in cellular phones, power amplification devices or short-range wireless links. Because inductor, capacitor, and resistor components of an IPD can be implemented in a more compact format (short interconnection) with high precision wafer-processing and advanced simulation tools can be used to accurately predict electrical performance, IPD solutions are desirable for customers who need faster cycle-time development and more reliable performance, especially in RF applications.

YD: Back in your days at AT&T the leading edge was silicon MCM technology. Now-a-days the world is a buzz about 3DIC and the use of TSV. What are your general thoughts on this technology?

BJH: The commercial availability of 3D IC and TSV is driven by economies of scale and return-on-investment (ROI). 3D ICs can achieve higher bandwidths and performance

with TSV, delivering more functionality in a smaller footprint for application processors, image sensors, logic, DRAM, analog, RF flash and MEMS. 3D ICs also provide the platform to integrate different process nodes such as 28nm for high speed logic and 130nm for analog within a single package. 3D ICs with TSV are expected to benefit areas such as networking, graphics, mobile communications, and computing, especially for applications that require ultra-light, small and low-power devices such as multi-core CPus, GPus, packet buffers/routers, smartphones, tablets, netbooks, cameras, DVD players and set-top boxes. The challenge the industry faces is to provide 3D or 2.5D technologies that deliver the promised performance at cost effective price points.

YD: Staying with 3D what technical issues do you think still need to be resolved?

BJH: During the qualification process for our 3D TSV mid-end of line (MEOL) processing with back-end of line (BEOL), we investigated multiple process options and technical issues. From our experience, each process should be well aligned and integrated for a successful 3D TSV manufacturing process that requires a close collaboration with a front-end fab. Thin wafer handling is one of the key challenges in the MEOL process along with bonding/debonding materials and low temperature process. Each of these areas requires extensive process characterization and optimization in order to achieve the most cost effective manufacturing environment.

YD: What is SCPs position on interposer use? Will they only be used for very high density solutions like FPGAs? or will they have broad application? Will SCP fabricate interposer substrates or will they come from the foundries or some other source?

BJH: We see the use of interposers as a key enabler for higher performance networks and mobile applications due to the memory bandwidth improvement and the ability to integrate IPDs or passives. Since the TSV interposer business model is not well established yet in industry, there will be several business models based on IDM or foundry players working together with OSaT or 3rd party suppliers. We are focusing on MEOL and backend assembly of TSV technology in partnership with our foundry partners to provide the best interposer supply chain.

I S S U E N ° 2 6 F E b r u a r y 2 0 1 3


Figure 2: fcCuBE interconnect of 80um/40um pitch TV using (a) MR and (b) TCB processes. (Courtesy of STATS ChipPAC)

(a) (b)

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

22

although FPGa is a standard solution for high-end products, de-partitioning a Si device and combining key technology building blocks together on an interposer is a more cost effective approach that delivers improved yields for high-end network or communication devices used in cloud computing or backbone networking. Our 2.5D TSV solutions are based on eWLb technology which is cost-effective, scalable and proven from a manufacturing standpoint with the design flexibility to support heterogeneous integration across a broad range of applications. The market size is dependent on the final cost achieved as opposed to the cost of more conventional technologies.

YD: What can you say about your standard 3DIC assembly process? Cu/Sn bonding? underfill?, expected initial pitch? Anything that makes the SCL approach different or more reliable than your competitors? Can you share your technology roadmap? (Figure 3)

BJH: We have a complete set of integrated 3D process capabilities covering MEOL through bEOL while working with foundry partners for interposer assembly. Our MEOL assembly services include microbump technology down to 40um, temporary bonding/de-bonding, backside via reveal, isolation and metallization. Our BEOL services include chip-to-chip and chip-to-wafer assembly with stealth dicing and fine pitch micro-bump bonding down to 40um. We use Cu/Sn bonding along with other interconnect approaches as well as a capillary underfill process and Non-Conductive Paste. We also work with our customers and suppliers on a Non-Conductive Film (NCF) approach.

To support the industry trend of increasing IO density at new silicon nodes, traditional substrate based packaging has to migrate to a thin-film based package utilizing wafer level technology such as eWLb, IPD and TSV. For very fine line and space routing requirements, advanced eWLB combined with TSV capabilities provides an exciting low cost 2.5D option.

YD: TSMC is publicly stating that they want 3DIC customers to come to them for the complete solution, i.e. complete component fabrication including design through test. What is SCL’s position on this?

BJH: There are different business models being developed to address 3D ICs. In a

captive model, one foundry would control the entire supply chain including the packaging integration process. If a customer’s memory chips are being fabricated by another foundry, their wafers would be sent to primary foundry for 2.5D/3D packaging integration. The level of information that would need to be shared between foundries may be a concern as this is typically considered confidential and competitive data. Another consideration is how much the industry wants to develop standard vs. proprietary technology.

We believe some customers will prefer the advantages of a collaborative business model where foundries and OSaTs work closely together to provide 3D IC solutions. By combining a foundry partner’s FEOL process technologies with an OSaT provider’s MEOL and back-end-of-line bEOL processes, customers can have a full-scale 3D IC solution with proven reliability. As this business model continues to evolve, higher capital intensity will be required and a higher level of R&D expense as a percentage of revenue. OSaTs with the ability to invest in advanced integration technology will be able to provide customers with a 2.5D/3D solution that is more cost effective than other competing business models. YD: Can you share with our readers some of the 3DIC applications that SCL sees moving forward?

BJH: The market for portable and mobile data access devices such as smartphones, tablets and ultrabooks connected to a virtual cloud access point will continue to drive increased functional convergence as well as increased packaging complexity and sophistication. We believe this will in turn accelerate an unprecedented demand in wafer level, thin POP, and TSV interposer packaging solutions.

YD: What unresolved issues do you see in the current 3DIC infrastructure?

Han: One important area is the business model and responsibilities of Si foundry, OSAT and third party service providers. With the capital intensity of 3D IC technology, the lack of a clear business model makes it harder for companies to focus their investment dollars and resources, possibly delaying the availability of robust manufacturing processes. Another factor is the financial ownership of memory devices in the integration process. With OSATs being relatively “small” players in the overall supply chain, they cannot assume liability for memory devices. Finally, the sheer pace of technology development and production readiness could be a challenge for companies to keep pace with. Overall, the biggest challenge the industry faces with 3DIC is delivering all of the promised performance at an affordable cost which hasn’t been demonstrated yet.

YD: Any other advanced packaging topics that our readers might be interested in?

BJH: Our advanced package portfolio always includes ‘cost effective’ ways of doing the same function. The portfolio includes multi-row lead-frame products that replace many current laminate products and lower cost substrate technology such as low cost interposers. There are many activities to reduce the thickness of products and to enhance thermal and electrical performance. We are achieving these objectives by combining our full portfolio of advanced building blocks.

YD: Thank you so much for fielding these questions.

www.statschippac.com


Figure 3: SEM micrograph of 3D TSVstacked package.

(Courtesy of STATS ChipPAC)

www.statschippac.com

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Fast growing consumer market is changing the MEMS packaging business

The fast growing market for sensors in smart phones and other mobile consumer gear means significant growth for the

MEMS packaging business, which will expand into a market that could total as much as 5% of the huge IC market in a few years. The fast growth of high volume consumer applications, and the increasing concentration of a few types of devices means critical mass for some MEMS packaging technologies. And the maturing sector’s move from competing on process technology to competing on functions and systems, means a move towards more standard solutions to keep driving down package size and cost. MEMS packaging is already a $1.6 billion sector, with more than 7 billion units shipped in 2012. Fast growth in demand will propel ~20% CAGR to reach a 14 billion unit market by 2016, though price pressures and the increasingly dominance of

low cost consumer units will hold down revenues to ~10% CAGR, to $2.6 billion. But by either measure, MEMS packaging is likely see about twice the growth rate of the mainstream IC packaging market. Though MEMS includes a highly diverse range of products with wildly varying packaging requirements from windows to air openings, market volume is increasingly dominated by a quite limited set of devices. Consumer applications now account for more than 50% of total MEMS revenues. And four main devices - accelerometers, gyroscopes, magnetometers and icrophones — now account for more than 50% of all MEMS units shipped.

This move to more standard needs in higher volumes creates plenty of headroom for change. yole estimates that OSaTs so far have captured only about 40% of MEMS packaging business by value, as the IDMs that dominate much of the business have counted on their specialty packaging

The traditionally fragmented MEMS market is increasingly dominated by consumer devices demanding small sizes and short product cycles at high volumes. It’s also increasingly concentrated on only a few device types, and moving rapidly towards multichip packaging. That’s pushing the sector to mature from competing on process technology to competing on functions, and driving it towards more standard packaging solutions at last.


F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

Eric Mounier, Senior Analyst, MEMS, Yole Développement

0

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Pack

ag

ing

an

d t

est

valu

e in

$B

Global IC packaging value MEMS packaging value

$4

3B

$4

4B

$4

5B

$4

6B

$4

8B

$5

0B

$5

2B

$1

,2B

$1

,4B

$1

,6B

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,8B

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,1B

$2

,3B

$2

,6B

MEMS packaging versus IC packaging / market forecast(In $B, including final test value)

(MEMS Packaging report, April 2012, Yole Développement)

“There’s currently a wide variety

of individual companies’ unique

wafer stacking solutions... But

we expect that as MEMS companies

increasingly move beyond competing on manufacturing

technology to competing on functionality, that more of

these packaging solutions will become more

widely-used platforms,”

says Eric Mounier.

I S S U E N ° 2 4 a u G u S T 2 0 1 2


technology to distinguish their products. The growing consumer volumes of the MEMS market, however, may drive more makers to outsourcing packaging and assembly to establish a secure supply chain with second sources at the OSATs.

Price is also of course crucial in these consumer markets, and makers have driven manufacturing costs down sharply by steadily reducing die size. Leading consumer devices now in 2 x 2mm packages with a 1mm height limit, and headed smaller. But packaging still accounts for some 35%-45% of the manufacturing cost of a basic MEMS accelerometer. That’s starting to push the industry away from custom packages for each device, towards more standard families of packaging that can be largely re-used for similar devices to speed development of new generations.

both cost and performance demands will move inertial sensors from discrete packages to integrated multichip modules. These emerging combo units will account for most of the growth in inertial sensor demand going forward, putting new demands on packaging, assembly and test. Effectively managing increasing volumes of sensor data from these combos, such as to reduce sensor drift for more accurate position sensing, will require shorter, faster connections between the components. These modules will also need to be assembled with high yields from known good die to be economic, and then all six or nine or ten sensor axes tested and cross-calibrated. Manufacturers will also need to figure out how to assure users of second sources for these complex multi component systems.

Slow move away from wire bonding towards 3D WLP

The vast majority of MEMS devices – about 75% of units – are wire-bonded systems in a package, then wire bonded side by side or stacked with their controlling aSICs on to a standard leadframe or bGa/LGa laminate substrate, and this will likely remain a major approach for a long time. Another 20% or so of MEMS integrate the MEMS directly on chip in the CMOS flow with the ASIC as a system on one chip. Though many once thought most MEMS would go to this SoC approach, it is now apparent that it’s best suited for particular types of devices that need very short connections, such as arrays of micromirrors or microbolometers that need direct response at each pixel unit, or very tiny

devices like oscillators. Most MEMS systems will continue to most efficiently connect their heterogenous components at the package level—but demand for smaller devices and shorter interconnects is driving a push towards some sort of bonding, bumping or 3D connections between the MEMS and the aSIC and/or the motherboard.

There’s currently a wide variety of individual companies’ unique wafer stacking solutions now in coming into use with inertial sensors, from bumping, to metal-to-metal bonding, to silicon- or polysilicon-filled vias in the MEMS device, to vias in interposers. But we expect that as MEMS companies increasingly move beyond competing on manufacturing technology to competing on functionality, that more of these packaging solutions will become more widely-used platforms, making more use of the outsourced infrastructure to bring down costs and speed development time.

Fabless InvenSense made its big inroads in the consumer gyroscope market thanks in part to its efficient low cost method of capping and interconnecting the MEMS to the aSIC by al/Ge metal-to metal bonding at TSMC and Global Foundries. More interestingly, the company is now openly licensing this interconnect technology, along with the rest of its fab qualified process and multi project wafer runs using it, figuring the technology will have more applications than it can itself develop. Similarly, the two leading specialty MEMS foundries each target coarse TSV platforms for use by all their customers. Silex Microsystems has long offered a TSV module to its customers (see Industry Review - MEMS Packaging Focus article), while Teledyne DaLSa is also working on developing a low cost wet-plated copper TSV platform, for wafer–level MEMS to aSIC connection for its MEMS foundry customers. DALSA is using a plating process technology licensed from alchimer that integrates the via isolation and filling in the same process modules for better cost efficiency, and working with that company towards production volume development.

STMicroelectronics’ more unique approach is to make TSVs in its MEMS die in-house to attach the die to the motherboard. It eliminates the area needed for the bond pads by replacing them with polysilicon vias isolated by etched-out air gaps, made with its basic MEMS process but on about a 10X larger scale. The MEMS can then be either wire bonded or more likely flip-chip attached to the ASIC. It reports the 20%-30% reduction

in die size more than counters the modest added cost of the TSV process, for lower total cost. The company is currently producing accelerometers with the technology in volume and says it plans to next introduce it for gyroscopes, and then use it for more compact multi-die modules, flip chipping multiple TSV MEMS chips to the ASIC.

bosch and Murata/VTI, meanwhile, also use proprietary technologies, but take advantage of the outsourced infrastructure. Bosch takes a relatively conventional solder bumping approach to connect the MEMS and ASIC (see accompanying article). Murata caps its MEMS inertial sensor with a silicon interposer, the matrix around the vias etched and filled with borosilicate glass, then flip chips on the thinned aSIC and adds larger solder balls around it to attach the whole stack to the motherboard. The interposer could be made by its MEMS foundry or an engineered substrate supplier like PlanOptik, the bumping done by the aSIC supplier or a bumping subcontractor, and the final chip-to-wafer bonding, balling and underfilling likely at Unisem in Malaysia.

www.yole.fr

Dr. Eric Mounier has a PhD in microelectronics from the INP in Grenoble. Since 1998 he is a co-founder of yole Développement, a market research company based in France. He is in charge of market analysis for MEMS, equipment & material. He is Chief Editor of Micronews, and MEMS’Trends magazines.

www.yole.fr


LED packaging: A $5 billion collection of little niches

The increasing penetration of solid-state lighting will drive healthy 5 to 10% annual growth in demand for LED devices for the

next several years, pushing total revenues to $17 billion by 2018. Packaging, assembly and test accounts for a particularly high 40%-60% of manufacturing costs in this business, according to our teardowns, suggesting those processes are worth some $5 billion already. The very high unit volumes of the general lighting market will drive strong growth in packaging. We estimate 23% CAGR in net die surface area to be packaged, driving 20% CAGR for LED packaging materials to $2.7 billion by 2016. Demand for LED packaging equipment will also pick up from the middle of this year, as overcapacity is worked off, to see steady growth for the next few years, to peak at some $650 million in 2016.

We expect a fast cycle of conversion to LED lighting and then a maturing of the market within the next few years. While wide adoption still requires further cost reductions, prices are falling rapidly and we see plenty of headroom for more reductions from a range of innovative technologies coming to market. The standard high power 1W single-chip packaged device has plunged in price by a third in the last two years, and low cost, mid level chips in oversupply from the TV backlight world — in standard, low costplastic leaded chip carrier packages — have recently started to see wide adoption in commercial and industrial fluorescent lighting. Luminaires designed specifically for LEDs are already cost effective and

are seeing increasing adoption in new construction. but once the mass conversion happens, the long-lasting bulbs won’t need replacement for years to come, so demand will likely level off after 2018 or so. Innovative packaging technology solutions for the complex demands of getting out more light, providing the right color and distribution of light, and handling high heat at low cost have been a key enabler of LED market growth to date and will continue to be so in the future. But the market remains a challenge for companies used to the standard requirements and high volumes of the IC market. Each of the multitude of different lighting applications requires a distinctive packaging solution, and each LED maker counts on own distinctive packaging technology for much of their competitive advantage, so the market demands a hodgepodge assortment of low volume materials and processes. It’s mostly smaller suppliers who found it worth investing in these niche markets early on, and now that they have built a head start of several years of knowledge of the business, they will likely be the ones to best capitalize on the near term growth—or they will be acquired by larger players, especially if their technologies appear to have wider applications.

Niche opportunities in outsourced packaging, substrates, equipment

Though the LED industry has drawn a crowd of new entrants in its recent boom years, it remains dominated by the top ten big names, who still account

Demand for LED packaging, materials and equipment will surge for the next few years but then rapidly mature, peaking at a $2.7 billion opportunity for packaging materials and $650 million for packaging equipment.


F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

Pars Mukish, Market and Technology Analyst, LED, Yole Développement

0

1

2

3

4

2010 2011 2012 2013 2014 2015 2016 2017

$ B

illio

n

Material Equipment

LED packaging equipment and material revenues (2010 - 2017)(LED Packaging report, February 2013, Yole Développement)

“Each of the multitude of

different lighting applications

requires a distinctive

packaging solution, and each LED

maker counts on own distinctive

packaging technology for much of their

competitive advantage,”

explains Pars Mukish.

I S S U E N ° 2 4 a u G u S T 2 0 1 2


for make more than 80% of the packaged LED market. Still, outsource packaging and assembly of LEDs and modules remains an attractive niche for small companies, with high value technical problems to solve for a wide range of varied, small volume applications, using widely available bare LED die.

Package substrates are another interesting opportunity, on track to reach some $900 million in a few years. The high thermal management requirements mean the LED devices need expensive substrates, and the wide range of different applications all have different requirements. Leading solutions are moving to more expensive AlN for better performance on the one hand, and to traditional COb direct attachment to metal-core circuit board for low cost manufacturing on the other hand. With the growing market, suppliers of ceramic substrates are now developing a wider range of products optimized for different applications, that might offer performance and cost somewhere between that of traditional AlN and Al2O3. These materials may then also find wider markets in power electronics or other demanding thermal semiconductor applications as well.

After the buildup of excess capacity in 2010-2011, demand for LED packaging tools plunged in 2012, but we expect demand to recover later this year and see healthy growth for a few more years to supply production of the volumes demanded for general lighting. Dicing technology that reduces the kerf loss may indeed be the one of the best available to reduce back end costs. With the very small LED die, a huge amount of real estate is lost in dicing. Laser scribing dominates the LED dicing market, but both laser and mechanical dicing continue to jockey for position with variations and improvements to best handle different options among the highly diverse variety of stacks and substrates. Growing use of vertical LED technology will continue to propel sales of equipment for substrate removal and wafer bonding. Inspection and test is the largest LED packaging opportunity, with challenges ranging from wafer defect inspection to die probe and sort, to package test and sort, to yield management.

Semiconductor makers, GaN on silicon, and WLP could eventually change the industry

Wafer-level packaging could have a revolutionary impact on bringing down LED packaging costs, with its potential

for drastically improving the efficiency of integrating the phosphors, the optics, and the ESD protection with the die. However, WLP has yet to get much traction, due to the cost of investment in the alternative equipment, some apparent issues with process control in volume, and particularly to the multitude of other competitive alternatives such as COB.

but the more the LED industry moves towards the semiconductor sector, the more likely these more radical integration approaches are to be adopted. As more companies move to making LEDs in GaN on silicon, on six or eight inch silicon wafers, wafer-level packaging could start to look more attractive. Semiconductor players like TSMC, Toshiba and Micron entering the LED business could also bring more semiconductor-like business models to the sector as well, with fabless or fab-light players and outsourced packaging.

But so far, LED makers turn to COB instead of wLP for lower costs

So far, however, the extreme pressure for cost reduction in the LED industry has meant a sharp focus on the simple and cheap, suggesting the LED sector will be unlikely to adopt the complexities of wafer level packaging quite yet. Most indicative of the trend in LED packaging technology may be the way Cree has markedly improved efficiency by its new nominally 200lm/W efficiency device by turning all the available knobs to really optimize die production, while leaving the packaging the same. Similarly, familiar COB packaging is the growing trend. Mounting the LEDs as bare dies directly on ceramic, Fr4, or metal core printed circuit board, saves on materials and reduces the interfaces between the chip and the heat sink for better cooling, skipping the die-level packaging and moving directly towards the module level for assembly, perhaps presenting more room for value-added innovation at the module makers.

Despite considerably initial interest in wafer-level packaging for its potential to significantly reduce packaging costs in theory, the industry hasn’t moved yet to much actual commercial adoption. The quality of ceramic substrates has improved greatly, so thermal performance is starting to approach that of silicon. While circles of these ceramic substrates can be processed in mature wafer tools, that approach will likely have a hard time competing with the well established infrastructure for convenient

population of chips on standard rectangular ceramic panels. More of a show stopper could be that traditional LED makers would have to go to a foundry for the patterning of the base wafer for redistribution for WLP on silicon, and they’re likely reluctant to give up control and margins in this key area. It also turns out that redistributing the LED die from a 4-inch wafer with the required spacing for packaging on to an 8-inch wafer doesn’t really provide enough volume per wafer for really significant cost savings from the wafer-level processing.

Integration of additional semiconductor functions with the LED is also often suggested as a way to improve cost and performance. and while some have looked at integrating very small diodes for ESD or power amplifiers, using the expensive LED real estate to make what are very cheap discrete components may turn out not to be very cost effective.

www.yole.fr

Pars Mukish holds a master degree in Materials Science & Polymers and a master degree in Innovation & Technology Management (EM Lyon – France). He works at Yole Développement as Market and Technology Analyst in the fields of LED, Lighting Technologies, Compound Semiconductors and OLEDs to carry out technical, economic and marketing analysis. Previously, he has worked as Marketing & Techno-Economic Analyst at the CEA (French Research Center).

www.yole.fr


HEV/EV market power device packaging

These demanding markets have brought demands for technologies that can handle more power and more heat, and their

potential volumes have drawn a crowd of new entrants with a diversifying mix of business models that means more options and potentially lower cost production.

The packaging of power modules is about a $0.8B market, and can expect steady growth as the $2.9B power device sector climbs to $4.2B over the next five years. High power semiconductors have traditionally been a stable market, growing at a steady 4%-6% annual rate, driven largely by small volumes of unique products for industrial automation. But revenues plunged 20%-25% in 2012, as Chinese spending for wind power and trains plummeted, worldwide government incentives for solar installations stopped, and the economic downturn stalled factory investment. We expect that this was an unusual perfect storm of events, and that going forward the sector should return to the steady 4%-6% growth it has typically seen in the past.

big changes in the nature of this market will come, however, as hybrid and electric vehicles take over more of the automotive business. We expect sales

of HEV/EV power modules to reach some $2.5B by 2020—to account for almost half of the total power module market. This volume automotive market means that for the first time, single power-module products may be shipped not just in typical industrial niche volumes, but in consumer volumes. These volumes could make the power semiconductor packaging and assembly business of more interest to traditional semiconductor suppliers and assembly companies, who could potentially apply their expertise to bring a lot of innovation to this sector.

The HEV/EV market also makes new technical demands on its power electronics devices, requiring wider temperature range and wider cycling range than most applications, as well as smaller size and better cooling. All the big names in automotive, power devices and materials are investing heavily in the technology. It as yet remains unclear, however, how these devices will be packaged, or by whom. Most major makers of the key insulated-gate bipolar transistor devices (IGBT) now do their own module packaging and assembly in house as a core technology, or use one of handful of module assemblers. Leading module suppliers Semikron and Danfoss also invest heavily in advancing the technology, and

Volatile alternative energy markets have shaken up the once steady power electronics business, and the big potential volumes of the hybrid/electric vehicle market will bring more changes still.


F E b r u a r y 2 0 1 3 I S S U E N ° 2 6

Alexandre Avron, Market and Technology Analyst, Power Electronics, Yole Développement

Annual demand for EV/HEV by type in Munits(October 2012, Yole Développement)

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Micro mild HEV Micro HEVMild HEVFull HEVPlug in HEV / EV

HIGHLIGHTS

n41 Technical sessions including:

•4 Interactive Presentation sessions

•1 Student Poster session

n16 CEU-approved professional development courses

nTechnology Corner Exhibits, featuring over 90 industry-leading vendors

n5 Special Invited sessions

nSeveral evening receptions

nWednesday luncheon speaker

nMany opportunities for networking

nGreat location

Conference Sponsors:

MORE THAN 300

TECHNICAL PAPERS COVERING:

3D/TSV

Advanced Packaging

Modeling & Simulation

Optoelectronics

Interconnections

Materials & Processing

Applied Reliability

Assembly & Manufacturing Technology

Electronic Components & RF

Emerging Technologies

I S S U E N ° 2 4 a u G u S T 2 0 1 2

still do most of this specialized assembly in Europe. But the PV and wind energy bubble drew an influx of new entrants in asia, including fabless and fab-light power device companies in China now using a new crop of power chip foundries and module assemblers to produce their products, all now looking for new markets.

Looking for new materials for bonding, die attach and package substrates

Key issues for the power sector are thermal cycling and thermal mismatch that cause delamination, concerns that are driving a search for better technologies for die interconnect to replace wire bonding, for new materials for die attachment, and for new alternatives direct bonded copper substrate and baseplates.

There’s a big push to replace aluminum wire bonding with some alternative, but the winning technology is still up for grabs. Copper wire bonding is perhaps the top contender, a proven technology in other areas with thin wires, and would improves resistivity, thermal conductivity and lifetime,

but despite planned introduction two years ago, it has proved extremely difficult to actually ramp the thick wires and big pads to high volume production with good yields, apparently because of difficulty finding the right die metallization to prevent copper contamination. Aluminum ribbon bonding is in production, and it improves the thermal cycling lifetime with its larger pads, but it doesn’t do much to improve resistivity or thermal conductivity, and remains expensive. another contender nearing production is sintering with silver particles, either to a sheet of copper-polyimide foil, or to aluminum bonding ribbon, which may greatly improve lifetime, while maintaining resistivity and thermal conductivity.

Conventional solder for die attach is also being replaced by higher temperature alternatives to better withstand thermal cycling. Eutectic soldering with Cu/Sn is in production at Infineon. Thin layers of tin and copper are built up, then heated to melt the tin and diffuse it into the copper, for an alloy of equal parts of each material, but with a much higher melting point. Semikron promotes sintering with paste of micro-silver powder, which also greatly improves

thermal cycling lifetime, but requires a rather slow and cumbersome process of maintaining even heat and pressure for relatively inefficient mass production. Sintering with nano particle silver instead, now in the research stage, would allow lower temperature and pressure and faster processing, but migration of the silver at high temperature remains a problem, and the material could be costly.

One option for better thermal performance at the substrate level is to replace the al2O3 or Si3n4 carrier for the direct bonded copper with aln, but that would be more costly. More effective could be to eliminate the baseplate, to attach the DbC substrate directly to the heat sink for more direct cooling.

www.yole.fr

Alexandre Avron is a full time analyst in power electronics at Yole Développement. He was granted a Master degree in Electrical engineering, with a major in power electronics and microelectronics processes, from Applied Sciences National Institute (INSA) of Lyon, France.

www.yole.fr

www.ectc.net

In 2013, Yole Développement’s advanced packaging analysts team chose to attend the following key events covering the supply chain:

• IMAPS Global Business Council’s 2013 Spring ConferenceMarch 10 to 11 – Scottsdale, AZww.imaps.org/programs/gbc13spring.htmYole Développement will present a paper on Medical Packaging

• Int. Conf. & Exhibition on Device PackagingMarch 11 to 14 – Scottsdale, AZwww.imaps.org/DevicePackaging/index.htmYole Développement will present a paper on Flip Chip. Feel free to visit our booth on the exhibition area.

• SEMICON ChinaMarch 19 to 21 – Shanghai, Chinawww.semiconchina.orgYole Développement will present papers on MEMS and Advanced Packaging. Feel free to visit our booth on the exhibition area.

• Successful Semiconductor Fabless - Powered by Yole DéveloppementApril 10 to 12 – Paris, Francewww.ssf2013.frProgram is now available

• ECTCMay 28 to 31 – Las Vegas, CAwww.ectc.net Feel free to visit our booth on the exhibition area.

yole Développement will present papers during the following events and will be present on the exhibition area too.

• SEMICON westJuly 9 to 11 – San Francisco, CAwww.semiconwest.org

• SEMICON TaiwanSeptember 4 to 6 – Taipei, Taiwanwww.semicontaiwan.org

• European Microelectronics Packaging Conferences (EMPC) September 9 to 12 – Grenoble, Francewww.empc2013.com

• SEMICON EuropaOctober 8 to 10 – Dresden, Germanywww.semiconeuropa.org

• SEMICON JapanDecember 4 to 5 – Tokyo, Japanwww.semiconjapan.org

• 3-D Architectures for Semiconductor Integration and Packaging December 11 to 13 – Burlingame, CAwww.techventure.rti.org

Feel free to contact Camille Favre ([email protected]) in charge of the Advanced Packaging Communication at Yole Développement, for any questions.

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6


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3DPackaging Magazine on 3DIC, TSV, WLP & Embedded die Technologies

ISSUE N°24AUGUST 2012

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INDUSTRY REVIEWEquipment makers say tools are ready for initial volumes of 2.5D/3DIC production

COMPANY INSIGHTSekisui Chemical: Reliability innovation in large size & fi nepitch WLCSP

ANALYST CORNERThe place of “middle-end” in the future landscape of 2.5D / 3DIC chip-to-package manufacturing


www.yole.fr

F E b r u a r y 2 0 1 3 I S S U E N ° 2 6


Editorial StaffManaging Editor: Jean-Christophe Eloy - Editor in chief: Dr Eric Mounier - Editors: Alexandre Avron, Lionel Cadix, Paula Doe, Andy Extance, Phil Garrou, Dr Eric Mounier, Pars Mukish- Media & Communication Manager: Sandrine Leroy - Media & Communication Coordinator: Camille Favre - Production: atelier JbbOX

About Yole Développement

CONTACTS

beginning in 1998 with yole Développement, we have grown to become a group of companies providing market research, technology analysis, strategy consulting, media in addition to finance services. With a solid focus on emerging applications using silicon and/or micro manufacturing Yole Développement group has expanded to include more than 50 associates worldwide covering MEMS, MedTech, Advanced Packaging, Compound Semiconductors, Power Electronics, LED, Imaging and Photovoltaics. The group supports companies, investors and R&D organizations worldwide to help them understand markets and follow technology trends to develop their business.

CUSTOM STUDIES• Market data, market research and marketing analysis• Technology analysis• Reverse engineering and reverse costing• Strategy consulting• Corporate Finance Advisory (M&A and fund raising)

For more information about:• Services: Jean-Christophe Eloy ([email protected])• Reports: David Jourdan ([email protected])• Media: Sandrine Leroy ([email protected])

MEDIA• Critical news, Bi-weekly: Micronews, the magazine• In-depth analysis & Quarterly Technology Magazines: MEMS Trends – 3D Packaging – iLED – Power Dev’ - NEW: Image Sensors Industry• Online disruptive technologies website: www.i-micronews.com• Exclusive and editorial webcasts• Live event with Market Briefings

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