packaging technology conference - gbv · electricalfunctionalizationofthermoplastic materials...

2013 IEEE 15th Electronics

Packaging Technology Conference

(EPTC 2013)

Singapore11-13 December 2013

IEEE IEEE Catalog Number: CFP13453-POD

ISBN: 978-1-4799-2835-4

Al. Advanced Packaging 1

Riverfront 1&2

Cforir5 " '

Zhang Xiaowu, IME,A*STAR, Singapore

2L OMEDFC Development for Larger Package to Die Size Ratio in Thinner Core 1

Peter Chen, M. Bachman, John Osenbach, Feng Kao, Eason Chen and C. T. Huang

£ Wire Sweep Characterization of Multi-Tier Palladium-Copper (Pd-Cu) Wire Bonding on LQFP Package

using Low Alpha Green Mold Compound 5

S. S. Skh AH, Serene Teh Seoh Hian and B. C. Ang

CVQFN Package Development 11

JKHo

£ Thermosonic Ball Bonding Behavior of Ag-Au-Pd Alloy Wire 15

Santosh Kumar, Hoontae Kwon, Young IL Heo, Seung Hyun Kim, June Sub Hwang andJeong Tak Moon

Al. Materials & Processes 1

Riverfront 3

David Hutt, Loughborough University, UK

Effects of Metallic Nanoparticle Doped Flux on Interfacial Intermetallic Compounds between Sn-3.0Ag-0.5Cu and Copper Substrate 21

S. K. Ghosh, A. S. M. A. Haseeb andAmalina Afifi

9 Photo-Dielectric Polymers Material Characterizations for 3D Packaging Applications 27

Nacima Allouti, Pascal Chausse, Christophe Aumont, Helene Issele, Lionel Vignoud, Nevine Rochat, ChristophePoulain, Magalie Gasiglia, Claire Sourd, Maxime Argoud, Perceval Coudrain, Raluca Tiron and Yorick

Trouiller

A Novel Manufacturing Technology for Tensile Test Specimens for the Characterization of Copper in

Plated Through Holes (PTH) 33

Georg Konstantin, Heinz Kiick and Reinhold Munch

Session ;^ A3. Quality & Reliability 1

Room Waterfront 1

Chair Alastair David TRIGG, IME, A *STAR, Singapore

* Applications of XPS and TOF-SIMS in the Investigation of PCB Package Delamination 37

Feng Yang, Shen Yiqiang, Lee Hwang Sheng and Fu Chao

* A Novel Damage Test Evaluation of IC Bond Pad Stack Strength 40

Alfred Yeo, Eric Yong, Dan Swee Tong and Georg M. Reuther

i Environmental Ageing Effects on the Electrical Resistance of Silver-Epoxy Electrically Conductive

Adhesive Joints to a Molybdenum Electrode 44

Vitalii Ivanov andKlaus-Juergen Wolter

it Development of Low-Temperature Drop Shock Resistant Solder Alloys for Handheld Devices 48

Morgana Ribas, Sujatha Chegudi, Anil Kumar, Ranjit Pandher, Rahul Raut, Sutapa Mukherjee, Siuli Sarkar and

Bawa Singh

xxvi

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

A4. Wafer Level Packaging 1

Waterfront 2

John. H Lau, ITRI, Taiwan

2 Developments in 2.SD: The Role of Silicon Interposers 53

Timothy G. Lenihan, Linda Matthew and E. Jan Vardaman

* Signal Integrity Study of High Density Through Silicon Via (TSV) Technology 56Bok Eng Cheah, Jackson Kong, Chee Kit Chew, Kooi Chi Ooi and Shanggar Periaman

2 An Innovative and Low Cost Bi-Layer Method for Temporary Bonding 62

Jiirgen Burggraf, Harald Wiesbauer, Julian Bravin, Thomas Uhrmann, Herman Meynen, Yann Civale, RanjithJohn, Sheng Wang, Peng-Fei Fu and Craig Yeakle

Simultaneous Molding and Under-filling for Void Free Process to Encapsulate Fine Pitch Micro BumpInterconnections of Chip-to-Wafer (C2W) Bonding in Wafer Level Packaging 67Dexter Velez Sorono, Srinivasa Rao Vempati, Lin Bit, Ser Choong Chong, Calvin Tea Wei Liang and Seit WenWei

A5. Thermal Characterization and Cooling Solutions 1

Waterfront 3

KokChuan TOH, TemasekLaboratories, NTU

£ Comparative Investigation of Double-Layer and Double-Side Micro-Channel Cooling for PowerElectronics Packaging 73

Assel Sakanova and Shan Yin

Package-Level Thermal Management of a 3D Embedded Wafer Level Package 78

Yong Han, Boya Zheng, Chong Ser Choong, Boo Yang Jung and Xiaowu Zhang£ Thermal Management of Hotspots Using Upstream Laminar Micro-Jet Impinging Array 83

Yong Han, Yong Jiun Lee, Boon Long Lau, Xiaowu Zhang, Yoke Choy Leong, Kok Fah Choo and Poh KeongChan

mm„ J(Mliga>

IllllSlssiji

Bl. Emerging Technology 1

Riverfront 1&2

Charles Lee, ASE, Singapore

What's inside my USB drive? - X-Ray Microscopy and X-Ray nano CT for 3d packaging 88Martin Oppermann, Holger Roth, Tobias Neubrand and Thomas Zerna

£ Chip Package Interaction(CPI) Risk Assessment On 28nm Back End Of Line(BEOL) Stack Of A LargeI/O Chip Using Compact 3D FEA Modeling 93

Chirag Shah, Fahad Mirza and Premachandran CS

£ An Advanced MEMS Sensor Packaging Concept for use in Harsh Environments 98Jochen von Berg, Claudio Cavalloni, Biswajit Mukhopadhyay, Piotr Mackowiak, Oswin Ehrmann, Klaus-DieterLang and Ha-Duong Ngo

£ Technology for Bipolar Polycarbonate Electrodes Applied for Intraoperative Neuromonitoring 103Melinda Varga, Marco Luniak and Klaus-Jurgen Walter

XXVII


Electrical Functionalization of Thermoplastic Materials by Cold Active Atmospheric Plasma Technology

R. Schramm andJ. Franke

B2. Advanced Packaging 2

Riverfront 3

Yeow Chon Ong, Micron, Singapore

it Study of Power Integrity Challenges in High-Speed I/O Design Using Power Rails Merging Scheme 114

Li Wern Chew andPaik Wen Ong

£ Polymeric Packaging of High Power Semiconductor Devices: Material Selection & Reliability Assessment

N. S. Nobeen, K. Ahmad, D. C. Whalley, D. A Hutt and B. Haworth

£ Developing Underfill Process in Screening of No-Flow Underfill and Wafer-Applied Underfill Materials

for 3D Stacking 124

A:. J. Rebibis, G. Capuz, R. Daily, C. Gerets, F. Duval, W. Teng, H. Struyf, R. A. Miller, G. Beyer, E. Beyne and

B. Swinnen

4t Optimization ofEtch-hole Design for the Thin Film Packaging 130

Jae-Wung Lee, Jaibir Sharma, Wang Man, Lim Leng Khoon andNavab Singh

£ Chip to Chip Hermetic Bonding and Multi-Chip Stacking using CuSn Bonding Technology 135

V. N. Sekhar, Lee Jun Su, Justin See Toh Wai Hong and Chen Bangtao

B3. Quality & Reliability 2

Waterfront 1

Tong-Yan Tee, Silecs International, Singapore

£ Investigation of Fluorine Induced Probe Marker Discoloration 139

P. Chang, H. L. Hsiao, C. H. Cheng, S. I. Chu, H W. Tai, Y. Y. Shieh and C. Y. Sun

J? Comparative Study on Delineation of Cu-Al Intermetallic using Chemical Treatment and Ion Milling 143

Lai-Seng Yeoh, Kok-Cheng Chong andSusan Li

£ Single Current Source Electromigration system and its Application to Copper Pillars with Tin based

Solder 147

Alastair Trigg, Chai Tai Chong, Hsiao Hsiang Yao and Yawjyh Tzong

£ Effects of Soft Solder Materials and Die Attach Process Parameters on Large Power Semiconductor Dies

Joint Reliability 152

Vernal Raja Manikam, Samsun Paing andAmy Ang

£ Assessment of Refinishing Processes for Electronic Components in High Reliability Applications 156

Chris Bailey, Stoyan Stoyanov, Chris Best, Chunyan Yin, M. O. Alam, Peter Tollafield, Paul Stewart andJohn

Roulston

xxviii


B4. Interconnect Technologies 1

Waterfront 2

Ricky S.-W. Lee, HKUST, Hong Kong

ft High Density Chip-to-wafer Integration using Self-assembly: On the Performances of DirectlyInterconnected Structures made by Direct Copper/Oxyde Bonding 162

S. Mermoz, L. Sanchez, L. Di Cioccio, J. Berthier, E. Deloffre, P. Coudrain and C. Fretigny9t A New Copper Wire Ball Bonding Process Methodology 168

Mark Luke Farrugia

£ Signaling Scheme for High Speed Die-to-Die Interconnection in Multi-Chip Package (MCP) Technology 173

Khang Choong Yong, Bok Eng Cheah, Wil Choon Song and Mohd Fadzil Ain

* Comparison of SLICF with C4 for Flip Chip Bonding with Au, Cu, Pd and Ag Studs with SAC Solder 178

Lee Teck Kheng, Ser BokLeng, Chong Wee Ling, Khin Sandar Tun and Yan Guo Qiang£ Bare Copper and PaUadium Coated Copper Wire Chip to Chip Bonding Feasibility Study 183

Ong Chen Ho, Lee Chai Ying and Gan Pei Se

B5. Materials & Processes 2

Waterfront 3

James How, Singapore

£ Mold compound Fracture Mode Study for High Reliability Package 189

Bob Lee andFrank Yu

£ Solder Joint Structure and Reliability of Board Level BGA Package using No-Clean Curable Solder PasteChoi Han, Jung Eunteak, Lee Sojung, BangJunghwan and Kim Junki

£ Lead Frame Fanning and Broken Connecting Bars Elimination Through Design Change and MoldingOptimization 197

Lay Yeap Lim and Tai Chiew Li

£ Performance Enhancement of Au-Ge Eutectic Alloys for High-Temperature Electronics 202Vivek Chidambaram, Eric Phua Man Rong, Gan Chee Lip and Min Woo Daniel Rhee

£ The Characteristics and Factors of a Wafer Dicing Blade and its Optimized Interactions Required for

Singulating High Metal Stack LowK Wafers 208

Koh Wen Shi andK. Y. Yow

193

Session CI. Interconnect Technologies 2; '< V< &

Room' ~Vi Riverfront 1&2

<V ;-x !

Chair » N" Dr. Hans-Joerg Timme, Infineon, Germany^^^t^^^^^^^F-^^'' ^^^^^^^^

Thermo-Mechanical Properties of Isotropic Conductive Adhesive Filled with Metallized Polymer Spheres 213Jakob Gakkestad, Zhuo Li, Tore Helland and CP. Wong

£ Intuitive and Inexpensive Method to Evaluate Flip Chip Bonding Parameters of Micro Bump with Wafer-Level Underfill Material using Glass Substrate 219

Jie Li Aw, Ser Choong Chong, Daniel Ismael Cereno, Keng Hwa Teo and Vempati Srinivasa Rao

xxix


i Direct Eutectic AuSn Solder Bumping on Al Bond Pad Surface Using Laser Solder Ball Jetting 224

Mian Zhi Ding, Jie Li Aw, Li Shiah Lim, Leong Ching Wai and Vempati Srinivasa Rao

C2. Electrical Modelling& Simulations 1

Riverfront 3

Wui-Weng Wong

£ Power Distribution Network Modeling using Block-based Approach 230

Li Wern Chew

£ X-Parameter Techniques for Signal Integrity in High-Speed Links 235

Jose Schutt-Aine and Thomas Comberiate

£ Analytical Interconnect Modeling Based on Equivalent Circuit Method 240

Guiqiang Zhu, Wenjuan Zhang, Liguo Sun and FujiangLin

Packaging 3

Chris Bailey, University ofGreenwich, UK

£ Copper Wire Bonded Package Characterization and Reliability for QFN Package from iNEMI

Collaborative Project 244

Masahiro Tsuriya, Alissa Cote, Jae Hak Yee, Stuwart Fan and Johnny Yeung

31 Chip to Wafer Bonding for Three-Dimensional Integration of Copper Low K Chip by Stacking Process 250

Ser Choong Chong, Jie Li Aw, Eva Wai Leong Ching, Daniel Ismael Cereno, Hong Yu Li, Srinivasa Rao Vempatiand Keng Hwa Teo

£ A Mold Flow Model with Method of Cells to Better Understand IC Packaging 255

BYLow, Serene Teh, Pei-Fan Tong andSFZhao

C4. Mechanical Modelling & Simulation 1

Waterfront 2

_s,

_r Andrew Tay, National University ofSingapore, Singapore^.-^j^-V^

£ Thermal and Reliability Analysis of Clip Bonding Package using High Thermal Conductivity Adhesive 259

YejunZhu, Haibin Chen, KeXue, Martin Li andJingshen Wu

£ 2D/3D Cohesive Zone Modeling of a Mixed-Mode Delamination Experiment 264

Bingbing Zhang, Daoguo Yang and Leo Ernst

£ Modeling and Characterization of Cu Wire Bonding Process on Silicon Chip with 45nm Node and

Cu/Low-K Structures 270

F. X. Che, Leong Ching Wai, Xiaowu Zhang and T. C. Chai

xxx


C5. Materials & Processes 3

Waterfront 3

Alvin Lee, Brewer Science, USA

it Effect of Palladium on the Mechanical Properties ofCu and Cu-Al Intermetallic CompoundsAdeline B. Y. Lim, Xin Long, Lu Shen, Xi Chen, Raju Ramanujan, Chee Lip Gan andZhong Chen

* Cu-Cu Wire Bonding Challenges on MOSFET Wafer Technology 282

Tai Keen Chee, Kee Siew Theen and Tham Moong Sin

£ Wire Bonding and Reliability Challenges ofGel Filled TPMS Packaging 288

Lent Teck Beng, Job Doraisamy Stanley, Calvin Lo and Koh Wen Shi

276

Dl. Quality & Reliability 3

Riverfront 1&2

Stevan Hunter, Onsemi

it Rl - A Reliability Comparison Study between 14 Lead Free Alloys 292

Heinz Wohlrabe and GundolfReichelt

it The Effect of Cu and Ag on the Yielding Behaviour of Lead-Free Solders at High Strain Rates 298

K. Meier, M. Roellig andK. -J. Walter

£ Analysis of Thermal Evolution in Power Semiconductor Modules as Lifetime and Reliability Tool 304

M. Pieschel, Y. C. Gerstenmaier, G. Mitic, M. Neumeister andJ. Seidel

9 Early Detection for Cu Wire Bonding Corrosion using Accelerated Autoclave Reliability Test 309

C. T. Tai, H. Y. Lim, C. H. Teo and P. J. Audrey Swee

A Robust Development for QFP Cu Wire Necking Prevention in Automotive Grade 0 Temperature CycleReliability 313

C. T. Tai

Session D2. Materials & Processes 4

Hn. -»-» r* , *\

pooni Riverfront 3

J hair Y. C. Mui, Advanced Micro Devices, Singapore

Microstructure Investigation of Cu/SnAg Solid-Liquid Interdiffusion Interconnects by Electron

Backscatter Diffraction 318

Iuliana Panchenko, Juergen Grafe, Maik Mueller andKlaus-Juergen Wolter

Jfc Substrate Transfer for GaN-based LEDs on 200mm Si 324

Nga. P. Pham, Maarten Rosmeulen, Zilan Li, Deniz Sabuncuoglu and Haris Osman

J? A Comparative Analysis on Physical and Chemical Plasma Cleaning Effects on Surfaces 329

Wong Jun Hao and Lim Yuan Ming

£ Study on Silver Sintered Die Attach Material with Different Metal Surfaces for High Temperature and

High Pressure (300°C/30kpsi) Applications 335

Leong Ching Wai, Wen Wei Seit, Eric Phua Jian Rong, Mian Zhi Ding, Vempati Srinivasa Rao and Daniel Rhee

Min Woo

xxxi


£ Study of Die Bond on Roughened NiPdAu-Ag Pre-Plated Frame with Anti-EBO 341

Raymond Solis Cabral, Joseph Aaron Mesa Baquiran, Wu-Hu Li, ArielLizaba Miranda andMary Grace

Mercado

§ D3. Thermal Characterization and Cooling Solutions 2

l^pyllji Dr. Han Yong, IME, A *STAR, Singapore

£ Graphene Based Heat Spreader for High Power Chip Cooling using Flip-chip Technology 347

Shirong Huang, Yong Zhang, Shuangxi Sun, Xiaogang Fan, Ling Wang, Yifeng Fu and Johan Liu

* Thermal Performance of a Double-Action Pulsed Jet CPU Cooler 353

Tilak T. Chandratilleke and Dibakar Rakshit

£ Investigation of a Microchannel-based Cooling Interposer for High-Performance Memory-on-Logic 3DIC

Design 358

Samson Melamed, Masaru Hashino, Fumiki Kato, Shunsuke Nemoto, Tung Thanh Bui, Katsuya Kikuchi, Hiroshi

Nakagawa and Masahiro Aoyagi

£ Thermal Characterization and Simulation Study of 2.5D Packages with Multi-Chip Module on Through

Silicon Interposer 363

H. Y. Zhang, X. W. Zhang, B. L. Lau, Sharon Lim, Liang Ding, M. B. Yu and Y. J. Lee

'Session '' D4. Advanced Packaging 4

£ Flexible Printed Two-Element Antenna Array with Enhanced Isolation Performance 369

Jun Wu Zhang, Kye Yak See and Eng Kee Chua

9 Film Assisted Technology for the Advanced Encapsulation of MEMS/Sensors and LEDs 373

Johan Hamelink

9 Extreme High Pressure and High Temperature Package Development 379

Hwang How Yuan, Eva Wai Leong Ching, Chan Yuen Sing, Vivek Chidambaram, Lee Jong Bum, Eric Phua Jian

Rong, Gan Chee Lip and Daniel Rhee Min Woo

yt Low Temperature Bonding Studies of Au-Studs and AuSn-Solder Bumps on Au-Surface using Ultrasonic

Energy 384

JieLiAw, Jong Bum Lee, Norhanani Jaafar, Mian Zhi Ding, Li-Shiah Lim, Chong Ser Choong, VempatiSrinivasa Rao

£ The Role of Cu-Al IMC coverage and Aluminum Splash in Pd-copper wire HAST Performance 389

Ming-chuan Han, Jun Li, Bei-Yue Yan, J. Z. Yao andMei-Jiang Song

H Martin Oppermann, Dresden University ofTechnology, Germany

xxxii


D5. Wafer Level Testing 1

Waterfront 3

Zhao Huapeng, IHPC, A*STAR, Singapore

£ AFM Based Methods for Mechanical Characterization of Nanothin Films in Electronics 394

Malgorzata Kopycinska-Muller, Andre Striegler, Nataliya Kuzeyeva, Bernd Kohler and Klaus-Jiirgen Wolter

2 An Implementation of Domain Specific Languages to Microprocessor's Memory Built in Self Repair

Testing 399

Taufan Harist Dwijatmiko andRadford Nguyen

JP A Case study of Package Delamination with Combination of EDX and MiniSIMS 403

Huan Xu, Haishu Zhang and MingXue

* JTAG Debug Tool for Efficient Debugging on V93K 407

G. G. Naveen Kumar, Gary Cousines and Mike Sprayberry

J* Non-linear Deflection Analysis of Pin-on-Packagc Testing using FEA 410

N. R. Subramanian, Koo Kok Kiat and Tye Ching Yun

ion El. Wafer Level Packaging 2

Wafer Reconstruction: An Alternative 3D Integration Process Flow 415

Teng Wang, Jose Luis Silva, Robert Daily, Giovanni Capuz, Mario Gonzalez, Kenneth June Rebibis, SteffenKroehnert and Eric Beyne

2 Effect of Cu Seed Layer Aging on Cu Filling Failure in Through Si Vias (TSVs) 420

Jae Woong Choi, Ong Lee Guan, Mao Yingjun, XieJielin, Chow Choi Lan, Soon-WookKim, Ramana Murthy,Eugene Tan Swee Kiat and Sunil Wickramanayaka

Process Integration of Solder bumps and Cu Pillar Microbumps on 2.5D Fine Pitch TSV interposer 424

Sharon Lim Pei-Siang, L. Ding, MingBin Yu, Mian Zhi Ding, Sorono Dexter Velez and Vempati Srinivasa Rao

i Demonstration of OSAT Compatible 300 mm through Si Interposer 430

L. Ding, Linda Liew, Guan Kian Lau, Hongyu Li, Mingbin Yu and G. Q. Lo

£ Polymer-based Fine Pitch Cu RDL to Enable Cost-Effective Re-routing for 2.5D Interposer and 3D-IC 435

S. W. Ho, L. Ding, Song How Lim, Soon Ann Sek, Mingbin Yu and G. Q. Lo

-

Session E2. Mechanical Modelling & Simulation 2

2 Electrochemical Assembly and Molecular Dynamics Simulation of SAM on Copper for Epoxy/CopperAdhesion Improvement 440

Stephen C. T. Kwok and Matthew M. F. Yuen

£ Simulation of Ball Bonding on Various Bond Pad Structures 446

Stevan Hunter, Aditi Mallik, Dustin Whittaker, Russell Alldredge and Tiago Rodrigues

Riverfront 1&2

Vempati Srinivas, IME, A *STAR, Singapore

xxxiii


£ Numerical Simulation ofthe Atomic Migration and Diffusion during Current Stressing in the Cu/Sn-

58Bi/Cu Solder Joints 452

Hongwen He, Liqiang Cao, Wenqi Zhang, Mikai Chen and Haiyan Zhao

Jt Advantage and Current Limitations of Advanced Fracture Mechanics for 3D-Integration and BEoL under

CPI Aspects [Invited] 455

Juergen Auersperg, Rainer Dudek, Sven Rzepka andBernd Michel

E3. Materials & Processes 5

Waterfront 1

L. C. Tan, Freescale, Malaysia

£ Investigation of Dynamic and Mechanical Thermal Behavior of Isotropic Conductive Adhesives 461

R. Durairaj, Chew Chee Sean, Tan Chia Chiun and Liew Man Ping

X Size and Geometry Effects on Microstructural Evolution in Sn Microbumps during Isothermal Aging 466

HuaXiong, Zhiheng Huang andPaul Conway

£ Development of a MEMS Test Platform for Investigating the use of Multi-Walled CNT CompositesElectric Contacts 472

Adam P. Lewis, Chamaporn Chianrabutra, Liudi Jiang, Suan Hui Pu andJohn W. McBride

£ Investigation of Interfacial Phenomena of Alloyed Au Wire Bonding 479

HyoungJoon Kim, Min-Seok Song, Kyung-Wook Paik, Jeong-Tak Moon andJun-Yeob Song

E4. Interconnect Technologies 3

Waterfront 2

g^^^^^Dr Uday Mahajan, Applied Materials, Singapore

«t Lead-Free and Halogen Free Solder Flip Chips on Board using SMT Processes and Materials for

Miniaturization and Lower Cost 483

Jonas Sjoberg, Ranilo Aranda, Dick Pang, David A. Geiger and Murad Kurwa

Evaluation of Mechanical Property of Sn-Ag Bonding Layer Adopting Ni(P)/Cu Bi-layer Diffusion Barrier

for 3D integration 489

Byimghoon Lee, Gan Chee Lip andHoo-Jeong Lee

* Process Development of lOum Pitch Cu-Cu Low Temperature Bonding for 3D IC stacking 493

LingXie, Sunil Wickramanayaka, Hongyu Li, Boo Yang Jung, Jie Li Aw and Ser Choong Chong£ Thermal-Mechanical Considerations of a Novel Power Module with High Junction Temperature 498

Ho Siow Ling, Lee YongJiun, Hwang How Yuan, Zhang Heng Yun andDaniel Rhee

£ Interconnection Challenge of Wire Bonding - Ag Alloy Wire [Invited] 504

Chin-Yu (Max) Lu, Jensen Tsai, Joseph Huang and Otis Hung

>

xxxiv


Waterfront 3

E5. Advanced Packaging 5

Prof. Young-Bae Park, Andong National University in Korea

*t Integrated Passive Filters Based on Silicon Substrate for SiP Application 510

Tongyu Zhao, Man Cai, Yinan Li, Qian Wang and Dejun Wang

ft Investigating the Temperature Effect of Reliability on Integration IC 3D Packaging under Drop Test 516

Hao-Chih Chen, Yi-Che Chiang, Tuan-Yu Hung andKuo-Ning Chiang

ft "Front-end-ization" of the Back-End 520

Rajiv Roy

ft Reliability Study on Through Mold Via (TMV) for 3D Microelectronic Packaging under Thermal and

Moisture Loadings 524

Zhaohui Chen, Ser Choong Chong, Boyu Zheng, Boo Yang Jung, Tai Chong Chai andXiaowu Zhang

It Electrical, Thermal and Warpage Investigation on High Bandwidth PoP [Invited] 530

Calvin Lee, Chang-Chi Lee, Hung-Hsiang Cheng, Morris Cheng, Timmy Lin, Ying-Chih Lee, Chin-Li Kao and

Po-Chih Pan

i Effect of Processing on the Microstructure and Fracture of Solder Microbumps in 3D Packages 534

Z. Chen, B. Talebanpour, Z. Huang, P. Kumar and I. Dutta

4 Challenges and Approaches of Ultra-Fine Pitch Cu Pillar Assembly on Organic Substrate using WaferLevel Underfill 538

Sharon Pei-Siang Lim, Li Yan Siow, Tai Chong Chai, Vempati Srinivasa Rao, Kohei Takeda, Toshio Enami,Chee Guan Koh, Xiangfeng Wang, Hongqi Sun and Tomoyuki Ando

£ Development of Bonding Process for High Density Fine Pitch Micro Bump Interconnections with WaferLevel Underfill for 3D Applications 543

Vempati Srinivasa Rao, Ser Choong Chong, Chen Zhaohui, Jie Li Aw, Eva Wai Leong Ching, Hwang Gilho and

Daniel Moses Fernandez

£ Die Attach Delamination Resolution for Exposed Pad LQFP with Large Package Size 549

Khoo Ly Hoon, Lau Teck Beng and Au Yin Kheng

Chair Mark Huang, Unisteel, Singapore\ b > b f

ft Anti-Corrosion Effect of Thiol Self-Assembled Monolayers on Ag Plate 555

He Wei, Huang Zhaohong and Zhou Qin*t Sequentially Formed Underfills: Thermo-Mechanical Properties of Underfills at Full Filler Percolation 560

Gerd Schlottig, Florian Schindler-Saefkow, Jonas Ziircher, Bruno Michel, Thomas Branschwiler

I Fl. Advanced Packaging 6

Riverfront 1&2

Hyoung Joonn Kim, Korean institute ofMachinery & Materials, Korea

xxxv


i Challenges and Resolutions of Pd-Cu Wire Bond Biased Hast Failures from Additive Particle in the Green

Mold Compound 565

Serene Teh Seoh Hian, Sheila Chopin andS. S. Skh Ali

it Considerations and Benefits of Plasma Etch Based Wafer Dicing 569

Richard Barnett, Oliver Ansell andDave Thomas

jfesslon F3. Electrical Modelling & Simulations 2

Waterfront 1

Dr. JIN Cheng, IME, A*STAR, Singapore

9 Systematic Modeling of On-chip Power Grids with Decaps in TSV-based 3D Chip Integration 575

Zaw Zaw Oo

£ Elimination of Signal Integrity Problems of Boundary Scan Circuit Based on Frequency Domain Transfer

Coefficient Method 579

Xing-MingLi, Shan-Qing Hu, Kye-Yak See, Eng-Kee Chua

9 Signal Integrity Analysis for High Speed Channels in PCB/Package Co-Design Interface: 3D Full Wave vs.

2D/Hybrid Approach & Full Model vs. Segmentation Approach 585

Antonio Ciccomancini Scogna, ChunTong Chiang, Klaus Krohne, Lian Kheng Teoh andHsuen-Yen Lee

£ Managing BGA Test Socket SI Characterization 589

Chee-Hoe Lin, Hui-YingNgand Wui-Weng Wong

F4. Mechanical Modelling& Simulation 3

Waterfront 2

Juergen Auersperg, Fraunhofer ENAS, Germany

vt Experiment and Modeling of Microstructured Capillary Wicks for Thermal Management of Electronics 592

Qian Liang, Rishi Raj, Solomon Adera, Sivanand Somasundaram, Chuan Seng Tan andEvelyn N. Wangit Stress Simulation and Design Optimal Study for Cu Pillar Bump Structure 598

Vito Lin, Nicholas Kao, Don Son Jiang and C. S. Hsiao

Clarification of Stress Field Measured by Multi-Wavelength Micro-Raman Spectroscopy in the

Surrounding Silicon of Copper-filled Through-Silicon Vias (TSVs) 602

Y. Sing Chan andXiaowu Zhang2 Thermal Cycling Reliability Assessment and Enhancement of Embedded Wafer Level LGA Packages for

Power Applications 606

Yiyi Ma, Kim-Yong Goh, Xueren Zhang and YonggangJinit Simulation Driven Physics-of-failure Analysis for System-in-Package Development [Invited] 612

Xueren Zhang, Kim-Yong Goh, Patrick Laurent, Kevin Formosa and Jerome Teysseyre

xxxvi


F5. Interconnect Technologies 4

Waterfront 3

Mohandass Sivakumar, ASM Technology, Singapore

9 Effect of Die Attach Material on Heavy Cu Wire Bonding with Au Coated Pd Bond Pad in Automotive

Applications 618

B. Senthil Kumar, Acuesta Albert andLim Lay Hong Geraldine

Assembly of Optoelectronics for Efficient Chip-to-Waveguide Coupling 625

E. Bosman, K. S. Kaur, J. Missinne, B. Van Hoe and G. Van Steenberge

it Patterning of Electroless Copper Deposition on Low Temperature Co-fired Ceramic 630

Dilshani Rathnayake-Arachchige, DavidA. Hutt, Paul P. Conway, Mario D 'Auria, Stepan Lucyszyn, Razak M.

Lee and lan D. Robertson

It An Innovative Composite Solder Preform for TLP Bonding - Microstructure and Properties of Die Attach

Joints 635

Weiping Liu, Ning-Cheng Lee and Paul Bachorik

it Interconnect Technologies for System-in-Package Integration [Invited] 641

Hans-Joerg Timme, Klaus Pressel, Gottfried Beer and Robert Bergmann

ion Gl. Interconnect Technologies 5

Transient Liquid Phase (TLP) Bonding using Sn/Ag Multilayers for High Temperature Applications 647

Nadeesh Singh Nobeen, Riko Imade, Byung Hoon Lee, Eric Man Rong Phua, Chee Cheong Wong, Chee Lip Ganand Zhong Chen

£ Challenges and Optimization of 2nd Bond Process for Reliable QFN Packages 653

Norhanani Binte Jaafar, Eva Wai Leong Ching, Michelle Chew Bi-Rong, Vempati Srinivasa Rao andDaniel

Rhee Minwoo

it New Paradigm in Cu Wire Bonding - Design-For-Manufacturing 658

Gan Pel Se, Tan Sze Chee, Kuppusamy Thinagaran and Lee Cher Chia

it The Cost Study of 300mm Through Silicon Interposer (TSI) with BEOL Interconnect 664

H. Y. Li, GuruprasadKatti, L. Ding, Surya Bhattacharya and G. Q. Lo

it Influences of Bonding Parameters on the Tool Wear for Copper Wire Bonding 669

Paul Eichwald, Walter Sextro, Simon Althoff, Florian Eacock, Mark Schnietz, Karsten Guth and Michael

Brokelmann

it Optimization for Temporary Bonding Process in PECVD Passivated Micro-bumping Technology 673

Alvin Lee, Jay Su, H. H. Chang, C. H. Chien.Bor Kai Wang, Leon Tsai andAric Shorey

Riverfront 1&2

Nga Phuong Pham, IMEC, Belgium

XXXVII


£ Immersion Tin for QFN Packages to Create a 3-D Solder Joint for Reliability Enhancement 677

Mustafa ozkok, Hubertus Mertens and Jerome Bender

tfobr^lpl Waterfront 1mmtmmm&&%

G3. Quality & Reliability 4

Jay Ke, Globalfoundries Singapore

£ Fault Isolation with Backside Polish for Trench Schottky Diode 681

Norhazlina Ismail, Muhammad HasifNasaruddin, Bazura Abdul Rahim, Wan Sabeng Wan Adini and MohdRofeiMat Hussin

£ Effects ofAlternating Thermal Stress on Delamination between Die Attach and Leadframe in SOIC

Package 685

Fei long, Zhijie Wang, Yanbo Xu, Jiyong Niu and Yi Che

i Non-Wetting of Electroless Nickel Plating Layer after Reflow Soldering Process 691

L. E. Khoong and T. K. Gan

i An Effective Approach for Failure Analysis of Neighbour Pin Leakage caused by Nano Layer Metallic

Thin Film in LQFP Fine Pitch Packages 697

Ramasubramanian Hari, Zhang Haishu andXue Ming

£ Development of Cu-less TSV Reveal Process using Si/Cu Grinding, Electroless Ni Plating, and Alkaline

Etching of Si 702

Naoya Watanabe, Masahiro Aoyagi, Daisuke Katagawa, Kazuhiro Yoshikawa, Tsubasa Bandoh and Eiichi

Yamamoto

Jt Glass Interposer Substrates: Fabrication, Characterization and Modeling 706

John Keech, Garrett Piech, Scott Pollard, Satish Chaparala, Aric Shorey andBor Kai Wang

Introducing Novel Film Type Adhesives into Thin Wafer Handling Technology for 3D TSV PackagingApplications 710

V. N. Sekhar, Lee Jong Bum, Tomoaki Shibata, Takashi Kawamori, Katsuyuki Masuda, Daniel Rhee Min Woo,Chen Bangtao andKazunori Yamamoto

9 TSV Reveal Process Developments for 2.5D Integration 714

Chongshen Song, Lei Wang, Zhun Wang, Daquan Yu and Wenqi Zhang

Session G5. Wafer Level Testing 2

Room Waterfront 3aS? jsS&S*^1: V. l^'^ifV^M;^^

Chair:

John Hunt, ASE, USA

2 Test-time Reduction Methodology: Innovative Ways to Reduce Test Time for Server Products 718

Eric Dimaandal and Marco Padilla

Yong Gang Jin, STMicroelectronics, Singapore

Waterfront 2

xxxviii


Waiting Time Optimization of Non-deterministic Tests at ATE 723

Florante Garcia, Jaime Padilla andEricson Rosaria

J? Low Impedance Characterization of Power Delivery Network on Substrate Level for High Speed DigitalApplications 726

Wui-Weng Wong, Suat-Mooi Low andBenjamin Beker

£ Chip on Board (COB) Versus Board on Chip (BOC) Memory Packages 731

Chong Chin Hui and WangAi Chie

it Control of Corrosion on Aluminum MEMS Structures after Post Etch Clean 736

Lee Hou Jang Steven, Andrew Tan, Deng Wei, Vladimir Bliznetsov, Tham Dexian, Navah Singh, Ramana Murthyand Eugene Tan

it Development of Package Level Hybrid Silicon Heat Sink for Hotspots Cooling 741

B. L. Lau, Y. J. Lee, Yong Han, Y. C. Leong, K. F. Choo, Xiaowu. Zhang and P. K. Chan

£ Mitigation of Mechanical Fracture of Polycrystalline Silicon Structure in MEMS Capacitive Microphones 747

Tang Kum Cheong and Cheam Daw Don

Jf Double-sided Si-Interposer with Embedded Thin Film Devices 752

Jong-Min Yook, Dong-Su Kim andJun-Chul Kim

J? Mechanical Properties Investigation of Graphene Coated with Ni 756

Youkai Chen, Fulong Zhu, Kai Tang, YingLi, Hengyou Liao, Xiahui Chen and Sheng Liu

Study on Dynamic Modeling and Reliability Analysis of Wafer Thinning Process for TSV Wafer 760

F. X. Che, W. S. VincentLee andXiaowu Zhang2 Investigation on Decap Shift and Incomplete Fill Issues in the Wafer Level Compression Molding Process 766

Lin Bu, Siowling Ho, Sorono Dexter Velez, Boyu Zheng, Ser Choong Chong, Booyang Jung, Taichong Chai and

Xiaowu Zhang

it Evaluation of De-scum Methodology for Through Silicon via (TSV) Etch to Improve TSV Defects

Performance 771

Goon Heng Wong, L. Ding and Woon Leng Loh

it The Study of Backside TSV Reveal Process by Direct Si/Cu Grinding and Polishing 775

KaiXue, Daquan Yu, Yuesheng Li, Feng Jiang, Haiyan Liu, Qibing Wang and Fengwei Dai

Investigation of Die-Attach Degradation using Power Cycling Tests 780

Zoltan Sarkany, Andras Vass-Varnai and Marta Rencz

3t Stress Analysis of Si Lattice near TSV Structures 785

K. Chui, Zhaohui Chen, G. H. Wong, Liang Ding, Mingbin Yu, Xiaowu Zhang and Patrick Lo

£ Analysis of Signal and Power/Ground Pin Assignment in Multi-layer PCB and its Impact on SignalIntegrity and Crosstalk 789

Ka Fai Chang, Joseph Romen Cubillo, Roshan Weerasekera, Cheng Jin, Boyu Zheng and SuryanarayanaShivakumar Bhattacharya

It Integration and Optimization of 300 mm Backside TSV Revealing and Cu Redistribution Process Enabled

by ZoneBOND Temporary Bonding Technology 793

Guan Kian Lau, L. Ding, Hipona Randy Tupaen and G. Q. Lo

I Poster A

12 December 2013 (Thursday) /10:15 to 10:45 hrs & 15:25 to 15:55 hrs

Kiwi Lounge

xxxix


£ Study on Reliability of Ultrathin Device Embedded in Organic Substrate under Drop Impact Loading

using Stresses Monitor and Simulation 799

Zhaohui Chen andXiaowu Zhang

9 A Shielding Structure with Conductive Adhesive Coated on Molding Compound in 3D Package 805

Jan Li, Jie Pan, Liqiang Cao, Xueping Guo, Tianmin Du, Yuan Lu andLixi Wan

2 Fabrication of Low Cost Spherical Alkali Atom Vapor Cells by Combining a Low Temperature Anodic

Bonding and a Chemical Foaming Process (CFP) 809

Youpeng Chen, Jintang Shanga and Yu Ji

Anodic Bonding Technology of Slender Glass Tube and Silicon in Pressure Sensor Packaging 813

Tao Chen, Lining Sun, Mingqiang Pan, Yangjun Wang, Jizhu Liu andLiguo Chen

£ Effect of Vacancy Defects on Thermal Conductivity of Single-walled Carbon Nanotubes 817

Kai Tang, Fulong Zhu, Yoakai Chen, Ying Li, Hengyou Liao, Xiahui Chen and Sheng Liu

£ In-Situ-X-Ray Investigation on Pressure Release during Conventional and Diffusion Soldering 821

Alexander Klemm, PatrickJdhngen, Martin Oppermann and Thomas Zerna

£ Study of Top Paddle Delamination on Cu Leadframe 827

Tee Swee Xian

£ High Thermal Conductive Die Attach Material Process Characterization Challenges 831

Khoo Ly Hoon, Lau Teck Beng andLo Wai Yew

* Effect of IMC Growth on Thermal Cycling Reliability of Micro Solder Bumps 836

Haiyan Liu, ChengXu, Xiaoyang Liu, Daquan Yu, Fengwei Dai, Yuan Lu andDongkai Shangguan

3? High Performance Integrated Passive Devices (IPDs) on Low Cost Through Silicon Interposer (LC-TSI) 840

ChengJin, Boyu Zheng, Liang Ding, Rui Li andKafai Chang

£ Novel High Performance Millimeter-Wave Resonator and Filter Structures using Embedded Wafer Level

Packaging (EWLP) Technology 844

Rui Li, Boo Yang Jung, Cheng Jin, Chang Ka Fai, Soon Wee Ho andDexter Velez Sorono

9 The Process and Thermal Management Performance of the Flushbonading Embedded Active Device in

Organic Substrate 848

Xueping Guo, Zhongyao Yu, Liqiang Cao, Zhiyong Cui, Xia Zhang, Yang Song andHaidong Wang

Lateral Micro Fluidic Channels Array Chip Fabrication for Automated Patch Clamp Application 853

Ding Zhipeng, Patthara Kongsuphol, Teh Poh Giao and Zhang Qingxin

Characterization of Metal Pad Condition after Vapor HF Release Process for MEMS PackagingApplication 857

Li Shiah Lim, Leong Ching Wai, De Xian Tham and Qingxin Zhang

* Via-in-Mold (ViM) Process for Embedded Wafer Level Package (eWLP) 863

Soon Wee Ho, Myo Ei Pa Pa, Chee Heng Fong, Zhonghai Wang, He Tong Kang, Ser Choong Chong and Tai

Chong Chai

3i Reducing Cu/Sn Bonding Wafer Bow for Fabrication of MEMS Devices 869

Li Yan Siow, Huamao Lin and QingXin Zhang

9 Investigations on the Mechanical Stability and Integrity of Chip Components after Picking and Placing in

the Surface Mount Technology Process Chain 873

Sebastian Meyer, Heinz Wohlrabe, Klaus-Jiirgen Wolter, Hartmut Reuter and Mathias Keil

§§§ 13 December 2013 (Friday) /10:10 to 10:30 hrs & 15:40 to 16:00 hrs

xl


£ Study on Thermo-mechanical Reliability of3D Stacked Chip SiP based on Cavity Substrate 878

Fengze Hou, Jun Li, Huiqin Xie, Xueping Guo, Liqiang Cao, Yuan Lu andLixi Wan

Impact of Ag Plated Surface Roughness towards Die Bond and Wire Bond 882

Goh Chen Liew, Khoo Ju Lee, Yeo Kian Hong, Manantan Soriano Aileen andLim Yuan Ming

H Preparation of Wafer-Level LED Packaging Used Uniform Micro Glass Cavities by an ImprovedChemical Foaming Process (CFP) 887

Yu Zou, Jintang Shang, Yu Ji, Li Zhang, Chiming Lai, Dong Chen and Kim-Hui Chen

xli


packaging technology conference - gbv · electricalfunctionalizationofthermoplastic materials...

Documents