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PADS I/O Designer™ for FPGA UserGuide

Release 8.2

November 30, 2009

Document Revision 1

© 2009 Mentor Graphics CorporationAll rights reserved.

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of thisdocument may duplicate this document in whole or in part for internal business purposes only, provided that this entirenotice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonableeffort to prevent the unauthorized use and distribution of the proprietary information.

This document is for information and instruction purposes. Mentor Graphics reserves the right to makechanges in specifications and other information contained in this publication without prior notice, and thereader should, in all cases, consult Mentor Graphics to determine whether any changes have beenmade.

The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth inwritten agreements between Mentor Graphics and its customers. No representation or other affirmationof fact contained in this publication shall be deemed to be a warranty or give rise to any liability of MentorGraphics whatsoever.

MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIALINCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY ANDFITNESS FOR A PARTICULAR PURPOSE.

MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, ORCONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS)ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT,EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OFSUCH DAMAGES.

RESTRICTED RIGHTS LEGEND 03/97

U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirelyat private expense and are commercial computer software provided with restricted rights. Use,duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to therestrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - RestrictedRights clause at FAR 52.227-19, as applicable.

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PADS I/O Designer User Guide, 8.2 3November 30, 2009

Table of Contents

Chapter 1Introduction to I/O Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

I/O Designer Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15I/O Designer Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 2Licensing and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Supported Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

User Definable Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Starting I/O Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Selecting a Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Chapter 3I/O Designer Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Workspace Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Customizing Your Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Selecting Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Signals List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Pins List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Symbol Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Symbol Window Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Device Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Pin Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Bank Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Clock Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35DQ DQS Pins Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Show Layout in Device View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Scrolling and Zooming in the Device Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Device Window Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Console Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Shortcuts in the Console Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Timings Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Properties Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Pin Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Port Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Symbol Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Graphic Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Text Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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Synchronization Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Synchronizing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Synchronization Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

GUI Startup Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Customizing Files and Directories. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Appearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Source Control Preferences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Advanced Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Chapter 4Typical Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

FPGA First . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Chapter 5Working with Projects and Databases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

What is a Project? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Project Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Opening a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Adding a Design to a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

What is a Database? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Adding Databases to a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Chapter 6Adding an FPGA to the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

FPGA Database Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67FPGA Device Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Selecting the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68FPGA Device Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Design Rule Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Defining I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Importing I/O Signals Using HDL/Netlist Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Importing I/O Signals Using a Spreadsheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Creating and Editing Signals in the Signals List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Design for Multiple Devices in a Common Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77PCB Design Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Chapter 7User-defined Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Creating a New Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Chapter 8Making Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Assigning Signals to Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Mark to Assign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Assigning Signals to Pins Using Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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Assign Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Changing Assignments in Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Drag & Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Choosing Signals/Pins to Assign from a List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Assigning Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Combining Pins into a Bus Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Pin Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Pin and Signal Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Clock Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Differential Pins Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89VREFs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Multi-Gigabit Transceiver Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Special Signal/Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Chapter 9Creating, Editing and Updating Symbols and Schematics . . . . . . . . . . . . . . . . . . . . . . . . . 95

Symbol Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Symbol Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Power Symbol Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Building a New Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Adding an Image to a Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Editing Symbol Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Moving and Changing Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Changing Symbol Backgrounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Printing Symbols. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Deleting Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Symbol Editor Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Creating Generic Symbols for Use With I/O Designer . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Exporting Symbols and Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Hierarchical Schematic Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Flat Schematic Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Schematic Scope Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Placing Symbols in a DxDesigner Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Importing Symbols and Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Schematic Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Chapter 10Optimizing the I/O Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Layout Database. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119I/O Planning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Synchronizing the Layout Database with a Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Layout Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Connectivity List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Adjusting Component Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Unravel Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Layout Scenarios Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Creating and Applying a Layout Scenario . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Multi-chip PCB Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

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I/O Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Fan-out Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Chapter 11Data Exchange. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

HDL and EDIF/XML Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131Recognizing Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Synthesis Constraints Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Place and Route Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Place and Route Constraints Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Pin Report Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134FPGA Xchange Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134FPGA Device Library Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Timing Report Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Design Rule Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135SSO Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Generating Device List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Integration with DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Importing an Existing DxDesigner Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Importing Symbols from DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Importing Symbols from the Central Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Exporting Symbols/Schematics to DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Updating Symbols/Schematics from DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139DxDesigner Usage Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Setting Part Data Export Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Exporting to the Central Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Using the Interconnectivity Table Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Integration with Pads Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146Constraints Bus Members Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

Chapter 12I/O Designer Tool Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Pop-up Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Undo and Redo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149Navigating List Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

Operations on Columns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Row Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Sorting Rows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150Filtering Rows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151Filter Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Changing the Pin Name Font Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Global Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Shortcuts in Signal and Pins Lists. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Shortcuts in the Symbol Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Shortcuts in the Device Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Table of Contents


Main Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159View Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Mode Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Layout View Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Zoom Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Symbol Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Source Control Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

Chapter 13TCL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

Creating and Running TCL Scripts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165I/O Designer TCL Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165I/O Designer Defined Scalar TCL Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188I/O Designer Defined TCL Array Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Chapter 14Design Versioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Source Control Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Source Control Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

Getting Existing Databases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193Adding Databases to the Repository. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Additional Files in the Repository . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Getting Latest Database Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Checking Out the Database. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Checking In the Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194Undo Check Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Setting Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Browse Changes History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Showing Differences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Refreshing Source Control Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Chapter 15Dialog and Field Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

Add Signal Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197Database Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198Edit Primitive Value(s) Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200Import Design Wizard Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200Layout Setup Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

IOD Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202Library Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Project Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Rule Manager Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Rules Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Unravel Nets Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

Appendix A

Table of Contents

8November 30, 2009


Preferred Devices List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

Appendix BVendor Support Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

Appendix CDevice-dependant Assignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Actel Assignment Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213Altera Assignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

I/O Pin Placement with Respect to LVDS I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214Xilinx Assignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216Lattice Assignment Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

Appendix DGeneric IO Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Third-Party Information

Index

End-User License Agreement

9November 30, 2009


List of Examples

Example 7-1. Setting a Rule for an FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Example 9-1. Using Central Library Symbols with Schematic Update . . . . . . . . . . . . . . . . 117Example C-1. Xilinx Assignment Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216


List of Figures

Figure 3-1. Signal List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Figure 3-2. Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Figure 3-3. Symbol Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 3-4. Device Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 3-5. Pin Legend Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 3-6. Pin Information Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 3-7. Pin Tool Tip Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 3-8. Clock Region Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 3-9. Device View - Show Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Figure 3-10. Console Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Figure 3-11. Clock Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 3-12. Add/Delete Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 3-13. Pad to Setup Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Figure 3-14. Add Pad to Setup Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 3-15. Clock to Pad Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 3-16. Add Clock to Pad Constraint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 3-17. Pad to Pad Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 3-18. Add Pad to Pad Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 5-1. DxDesigner Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 5-2. Selecting a Design in the I/O Designer Project Window . . . . . . . . . . . . . . . . . . 64Figure 6-1. Differential Pairs Displayed in the Signals Window . . . . . . . . . . . . . . . . . . . . . 75Figure 6-2. Setting the I/O Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 8-1. MGT Channel Reassignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 8-2. Swap Multi-Gigabit Transceiver Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 8-3. Setting Types Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Figure 9-1. Power Signal Generation Based on I/O Standard Assignment . . . . . . . . . . . . . . 101Figure 9-2. Manually Created JTAG Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Figure 9-3. Placing Symbols in DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Figure 9-4. Wiring a Device in DxDesigner Using the “Net Stub” Technique. . . . . . . . . . . 114Figure 9-5. Running Packager in DxDesigner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Figure 9-6. Yellow Synchronization Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Figure 10-1. Components Imported Into Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Figure 10-2. Layout Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Figure 10-3. Show/Hide Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122Figure 10-4. FPGA Nets Prior to Unraveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Figure 10-5. FPGA Nets After Unraveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125Figure 10-6. Fan-out Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129Figure 11-1. I/O Designer Normal Mode - DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Figure 11-2. IOD with Existing Symbols - DxDesigner . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142Figure 11-3. IOD with Existing Symbols and PDB Data . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

List of Figures


Figure 11-4. Design Configuration Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144Figure 11-5. Generation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145Figure 11-6. Constraints Bus Dialog: Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147Figure 11-7. Constraints Bus Dialog: Modified Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . 148Figure 12-1. Change Pin Name Font Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155Figure C-1. Single-Ended Row I/O Pin Placement for LVDS I/O Pins . . . . . . . . . . . . . . . . 215Figure C-2. Single-Ended Column I/O Pin Placement for LVDS I/O Pins. . . . . . . . . . . . . . 215

12November 30, 2009


List of Tables

Table 2-1. User Definable Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 3-1. Signals List Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 3-2. Pins List Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 3-3. Symbol Window Zoom Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Table 3-4. Symbol Window Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 3-5. Pin Display Colors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Table 3-6. Device Window Zoom Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Table 3-7. Quick Mouse Zoom Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 3-8. Device Window Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 3-9. Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 3-10. Pin Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 3-11. Port Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 3-12. Symbol Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 8-1. Pin and Signal Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 10-1. Connectivity List Window Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Table 12-1. Wildcard Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152Table 12-2. Regular Expression Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153Table 12-3. Backslash Character Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154Table 12-4. Global Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156Table 12-5. Shortcuts in Signal and Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Table 12-6. Modifier Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157Table 12-7. Symbol Window Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Table 12-8. Device Window Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158Table 12-9. Main Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159Table 12-10. View Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160Table 12-11. Mode Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Table 12-12. Layout View Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161Table 12-13. Zoom Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162Table 12-14. Symbol Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163Table 12-15. Source Control Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164Table 15-1. Add Signal Dialog Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197Table 15-2. Database Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198Table 15-3. Edit Primitive Value(s) Dialog Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200Table 15-4. Import Design Wizard Dialog Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200Table 15-5. Layout Setup Dialog Contents - IOD Components Tab . . . . . . . . . . . . . . . . . . 202Table 15-6. Layout Setup Dialog Contents - Library Components Tab . . . . . . . . . . . . . . . . 202Table 15-7. Project Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Table 15-8. Rule Manager Dialog Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203Table 15-9. Rules Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204Table 15-10. Unravel Nets Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

List of Tables


Table B-1. Vendor Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209Table D-1. Generic IO Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

List of Tables

14November 30, 2009


PADS I/O Designer User Guide 8.2 15

Chapter 1Introduction to I/O Designer

I/O Designer provides a technology for device optimization on-board, aimed to optimize theoverall final System design.

I/O Designer Capabilities• Broad FPGA Vendor Device Support

Users will benefit from the broad device support from the leading FPGA vendors (Actel,Altera, Lattice, Xilinx) that I/O Designer offers. This device support is kept up-to-datethrough periodic Library Updates.

• Rules Engine

o An automatic Rules Engine supports standard rules and enable users to customizeassignment rules.

• Correct by Construction I/O Assignment

I/O Designer allows you to assign and optimize I/O assignments with confidence thatthey are correct. I/O Designer does not require you to verify pin assignments made inI/O Designer.

• Automation of Error Prone Manual Processes

Manual symbol and schematic creation for high pin count devices can be timeconsuming and error prone. I/O Designer will automatically generate symbols andschematics to efficiently incorporate the FPGA design into the PCB process.

• Improved Quality of Results

I/O Designer will improve overall PCB quality by optimizing the I/O assignments basedon actual PCB component orientation.

A major benefit of system I/O assignment optimization is the reduction of PCB routinglayers, via counts and trace lengths. Faster and easier PCB routing and overall improvedPCB quality implies lower fabrication costs and better signal integrity and timingmargins.

I/O Designer IntegrationI/O Designer generates Place & Route constraints, based on the HDL design and mappingprocess and then allows you to create the necessary symbols, schematics and hierarchicalassociations based on the "post-route" pin data.


Introduction to I/O Designer

November 30, 2009

I/O Designer allows you to:

• Read signals from entities in VHDL files, and modules in Verilog files.

• Define signals within the I/O Designer environment, and generate VHDL entities, orVerilog modules.

• Choose an FPGA device from devices supported by vendors such as Xilinx, Altera,Lattice or Actel.

• Map HDL signals to FPGA pins, and generate FPGA constraints.

• Update mappings based on the files generated by Place & Route software.

• Create and edit functional-level, and board-level symbols in the advanced built-inSymbol Editor.

• Generate symbols and schematics.

• Work in teams through the built-in version control systems interface.

• Optimize I/O pin assignments improving efficiency on the PCB and drastically reducingdesign time.

I/O Designer does not run in standalone mode. It is used in conjunction with other designsolutions such as DxDesigner for Expedition.

I/O Designer Design Process

The initial FPGA signals and/or assignments are typically imported by I/O Designer from theFPGA vendor tools (e.g. Actel, Altera, Lattice, Xilinx). After the PCB process integration andI/O optimization, the new signal assignments are exported to the respective FPGA vendor tool.I/O Designer is knowledgeable of the FPGA vendor specific file formats making datamovement very easy.

I/O Designer will start by importing a signal list in the form of an HDL file or an FPGA vendornetlist. The signals may or may not be assigned at this point. I/O assignment can be easily donein a correct by construction fashion within I/O Designer. I/O Designer provides a device librarythat incorporates most of the vendor-specific pin assignment rules. The benefit comes fromhaving the ability to assign and optimize pin assignments in the PCB design process.

Once an initial pin assignment is made, I/O Designer is used to generate a symbol set for theFPGA. Symbols can be fractured based on a number of different parameters. The symbol setalong with the schematic can be exported directly to the schematic tool. The benefit comes fromautomating two manually intensive activities - symbol and schematic creation.

After a preliminary PCB layout is complete , I/O Designer can import the layout to begin theI/O optimization phase. You can view the actual component orientation and netlines as it



appears in the layout tool. The goal is to use I/O Designer to optimize the pin assignment forthis particular component orientation. This is done by moving pin assignments to shortennetlines and remove cross-overs. Once you feels that this is the best I/O assignment for thiscomponent orientation, I/O Designer will update the symbols and schematics to reflect the newpin assignments. The quality of the PCB is dramatically improved based on the optimized I/Oassignment in the form of fewer layers, shorter traces, less vias and as a derivative improvedsignal integrity. This will also lead to lower PCB costs.



November 30, 2009


Chapter 2Licensing and Configuration

License OptionsWhen I/O Designer is invoked, the Select Licenses dialog is displayed, from which you canselect the product options you require for use during your session. Different options areavailable depending upon which license you have.

• I/O Designer for FPGA

I/O Designer may be used to build and optimize I/O for FPGA devices.

• Multi-Chip PCB Optimization Option

If you have a multi-chip PCB Optimization license, multiple devices may besimultaneously optimized. If you do not hold a multi-chip license, then when applyingoptimization scenarios in a Layout Database, you can work with only one device at atime. For more information, see “Multi-chip PCB Optimization” on page 126.

IOD Lite is a reduced-functionality version of I/O Designer. For further information, see theI/O Designer Release Notes.

Supported PlatformsI/O Designer has been certified against the following operating system baselines:

• Windows Vista (Ultimate Edition, Business Edition, and Enterprise Edition, 32 and 64bit versions of each), Windows XP Professional SP2, Windows Server 2003 (StandardEdition), Windows MWE environment.

Environment VariablesOn Windows platforms, all environment variables necessary to successfully run I/O Designerare set automatically during the installation process.

On Unix/Linux/Sun platforms, you will need to set the following variable manually.

• Set the MGC_IO_DESIGNER_HOME environment variable to point to the followinglocation:

<IOD_INSTALL_FOLDER>/IOD8.2/IODesigner

PADS I/O Designer User Guide 8.220

Licensing and ConfigurationConfiguration File

• In Tools > Preferences > Paths, set the path to the $SDD_HOME variable (this is thelocation for the Mentor PCB flow and must be set in order for successful integrationwith Mentor PCB products).

After you set this variable, you will need to restart the application. The default flow isDxDesigner.

User Definable VariablesThe following variables are automatically set to default locations (determined from, forexample, $MGC_HOME) upon installation of the tool. You can choose to manually set thesevariables to point to a different location. When I/O Designer is invoked and these variables areset, then the tool replaces the background default values with the values that you specified.

To verify what variables are set, choose Tools > Preferences > Paths.

If some of these variables do not work, it is possible that you have some paths manually set, socheck if your configuration file (.ini) contains any preference settings. See “Configuration File”on page 20 for more details.

To set these variables in Windows, use Control Panel > System > Advanced Tab >Environment Variables.

Configuration FileThe configuration file iod8.2.ini contains preference settings for I/O Designer. You can edit thisfile with any text editor to change the settings. I/O Designer saves the settings automaticallyinto this file on exit. There are three locations from which I/O Designer attempts to load theconfiguration file:

1. The I/O Designer installation directory

2. The directory pointed to by the IODESIGNER_INI_DIR environment variable

Table 2-1. User Definable Environment Variables

Variable Description

IOD_PATH_FILE_VD_DX DxDesigner executable file

IOD_PATH_FILE_VD_IDX DxDesigner with iCDB executable file

IOD_PATH_DIR_DEF_DB Default databases directory

IOD_PATH_DIR_WORKING Startup working directory

IOD_PATH_FILE_PDF_VIEWER PDF Viewer

IOD_PATH_FILE_CONSOLE_LOG Console log file

IOD_LIBRARY_PATH FPGA libraries directory

Licensing and ConfigurationStarting I/O Designer


3. Your home directory: C:/Documents And Settings/<username> on Windows.

The locations are searched for the configuration file in the specified order. I/O Designer stops atthe first location that contains the configuration file and reads the settings from this file.

Starting I/O DesignerTo invoke I/O Designer, select Programs > Mentor Graphics SDD > I/O Design > I/ODesigner

When starting in GUI mode for the first time the Startup dialog is displayed, from which youcan select whether to:

• Create a new empty project (see “Creating a New Project” on page 62).

• Open an existing project (see “Opening a Project” on page 62)

• Open a recently used project.

You can set preferences for GUI startup, see “GUI Startup Preferences” on page 53 for moreinformation.

CautionYou may see the following warning message while loading databases created withversions of I/O Designer prior to IOD7.1:

# Some signals cannot be matched with nets on the layout:# signal_name1, signal_name2, signal_name3 . . .# Flow synchronization may be needed.

If you do see this message, you should synchronize your flow using the SynchronizationWizard.

Selecting a SchemeTo choose a scheme, navigate to Tools > Preferences and select it from the drop-down box.The scheme you choose should match the workflow you are using.


Licensing and ConfigurationSelecting a Scheme


Chapter 3I/O Designer Workspace

Workspace WindowsThe I/O Designer workspace is made up of a number of windows, which are used to display andmanipulate information. The windows available depend upon the type of database you arecurrently viewing.

Common windows (available in all database types):

• Pins List

• Project Window

• Console Window

FPGA database windows:

• Timings Window

• Device Window

• Signals List

• Symbol Window

• Properties Window

Layout database windows:

• Connectivity List Window

• Layout Scenarios Window

• Layout Window

Customizing Your WorkspaceWindows can be displayed or hidden at any time, using the menu item View > Windows thenselecting or deselecting the window, or by using the buttons in the View Toolbar.

The layout of windows within your workspace is completely customizable; they can be freelydocked, undocked, put into tabs, and moved around. The show/hide state of each window ispreserved between invocations of the tool.


I/O Designer WorkspaceSignals List

The currently active window is distinguished by a differently colored title bar. Input key pressesare sent to the active window first.

Selecting ObjectsWhen objects like signals, pins, and symbol elements are selected in one window, that selectionis maintained across all relevant windows. For example, the connection between signals andpins is based on pin assignments, so whenever a signal is selected in the Signals List, itsassigned pin is highlighted in the Pins List. Similarly, whenever a pin is selected in the Pins Listand this pin is assigned to a signal, the signal is highlighted in the Signals List.

Graphical elements of symbols do not have their counterparts in other windows, however portsin symbols do have counterparts in signals or pins. When you select a port in the SymbolWindow, the appropriate signal and/or pin is selected in all other windows as well.

Signals ListThe Signal List displays the signals read from an external source file (for example an HDL file),or added in I/O Designer manually. The Signal List may be closed and opened at any time,either using the menu item View > Windows > Signal List, or by clicking the icon on theView Toolbar.

The tabs at the bottom of the list are used to view signals by their assignment or placementstatus.

• All

All available signals are listed.

• Assigned

Signals with assigned pins are listed.

• Unassigned

• Signals without assigned pins are listed.

• Unplaced

Signals that have not been placed on a symbol are listed.

I/O Designer WorkspaceSignals List


Figure 3-1. Signal List Window

Table 3-1 describes the information listed in the Signal List for each signal:

Table 3-1. Signals List Contents

Column Description

PCB Name The signal’s PCB name

HDL Name The signal’s HDL name

Dir The signal’s direction

Pin The pin currently assigned to the signal

Type The signal’s type

I/O Standard The chosen I/O standard for the currently assigned pin,such as GTL or HSTL

Swap Group The swap group of the currently assigned pin

Locked By Indicates whether a signal is locked

Symbol The functional and/or PCB symbol that the signal belongsto

Drive Str. The signal’s drive strength

Termination The signal’s termination type for Xilinx devices

Slew Rate Programmable slew rate control

Tabs


I/O Designer WorkspacePins List

Copying Signal Data to the ClipboardWhen using the Signals List, the Edit > Copy command allows you to copy the content of theselected rows to the clipboard. The content is copied as text, one line for each row. All visiblecolumns are copied, and their contents are separated with the tab character. In this format thedata is easily pasted into a spreadsheet application.

Related Topics

• “Defining I/O Signals” on page 70

• “Making Pin Assignments” on page 83

Pins ListThe Pins List displays the pins available in the currently selected device. The Pins List may beclosed and opened at any time, either by selecting the menu item View > Windows > Pins List,or by pressing the button on the View Toolbar.

Delay Buffer Delay

PCI Clamp On Chip PCI-clamp diode

Pullmode Pin Termination for Lattice devices

OPENDRAIN On/Off Open Drain for Lattice devices

OCT On Chip Termination type for Altera devices

DQ Group Size DQ Group Size

DQS for DQ DQS for DQ information

Table 3-1. Signals List Contents

Column Description



Figure 3-2. Pin List

In an FPGA database, tabs at the bottom of the list are used to view different pins:

• User

Normal pins used for I/O are listed.

• Special

Not used. Tab displaying special pins, e.g. MGT, PLL pins that might have beenassigned to signals.

• PCB

PCB pins are listed.

• All

All pins are listed.

Table 3-2 describes the information listed in the Pins List for each pin on the device.

Table 3-2. Pins List Contents

Column Description

Number The pin’s number.

Name The pin name.

Signal The signal to which the pin is assigned.

Type The type of pin, such as IO, GND, VCC, VSS orVDD .

Tabs



I/O Standard I/O Standard chosen for a pin, such as GTL orHSTL.

Function An additional description of a pin, such as GND orCLK.

Bank The power bank that a pin belongs to.

Swap Group The swap group to which the pin belongs.

VccIO The I/O VCC supply

Vref Input reference voltage

Vref Group Voltage Reference Group Name

Drive Str. The pin’s drive strength.

Symbol The PCB symbol that the pin belongs to.Xilinx devices:

• Termination

• Slew rate

• Delay

Xilinx Virtex2, Virtex2p, Spartan3 devices:• Local Clocks - IOB Columns

• Local Clocks - Interface to CLB Array

Xilinx Virtex4 devices:• Clock Regions

Altera devices:• Slow slew rate

• Power up level

• Fast output register

• Fast input register

• Decrease input delay to internal cells

Termination Pin termination type for Xilinx devices

Slew Rate Programmable slew rate control

Delay Buffer Delay

MGT Channel Serial Transceiver Channel for Altera devices

PCI Clamp On Chip PCI-clamp diode


Column Description

I/O Designer WorkspaceSymbol Window


Copying Pin Data to the ClipboardWhen using the Pins List, the Edit > Copy command allows you to copy the content of theselected rows to the clipboard. The content is copied as text, one line for each row. All visiblecolumns are copied, and their contents are separated with the tab character. In this format thedata is easily pasted into a spreadsheet application.

Printing Signals and Pins

To print a list of signals or pins, select File > Print > Pins. This displays your system’s standardPrint dialog.

Related Topics

• “Making Pin Assignments” on page 83

• “Combining Pins into a Bus Pin” on page 85

• “DQ DQS Pins Display” on page 36

Symbol WindowThe Symbol Window is available when working with FPGA databases, and displays the currentsymbol form. This window may be closed and opened at any time with the menu item View>Windows > Symbol, or by clicking the icon on the View Toolbar.

In addition to displaying generated symbols, the Symbol Window can be used to draw and editsymbols. This is described in the section “Building a New Symbol” on page 102.

Use the scrollbars at the right side and the bottom of the window to navigate around thewindow.

Pullmode Pin Termination for Lattice devices

OPENDRAIN On/Off Open Drain for Lattice devices

OCT On Chip Termination for Altera devices

Clock Regions Clock Regions for Xilinx devices

DQ DQS Regions DQ DQS pins regions information


Column Description



Figure 3-3. Symbol Window

You can arbitrarily zoom in on the Symbol Window. The commands controlling zoom areaccessed on the main toolbar, or by right-clicking in the Symbol Window and using the controlson the pop-up menu.

Table 3-3. Symbol Window Zoom Controls

Zoom InIncreases zoom by 50%

Zoom OutDecreases zoom by 50%.

Zoom to FitShows the symbol in its entirety.

Zoom to SelectionFills the window with the selected symbolelements.

Previous ZoomRestores the zoom to the state of the previouszoom operation.

Next ZoomCancels the Previous Zoom operation.



To zoom in, click the middle mouse button. To zoom out, click the middle mouse button withSHIFT. To zoom to an area, hold down SHIFT, and drag in the symbol window with themiddle mouse button or the right mouse button. If you move to the right, zoom in will beperformed. If you move to the left, zoom out will be performed. Press Esc, or drag into thecancel box in the upper-left corner of the dragging rectangle to cancel the zoom.

You can also put the Symbol Window into Zoom Mode, see Table 3-4.

Symbol Window ModesThe Symbol Window is always in one of the following modes, listed together with the toolbarbutton that selects the mode:

Symbol Window SettingsThe Symbol Editor page under Tools > Preferences contains options for customizing theappearance and behavior of the Symbol Window. It is possible to switch on and off certainsettings on this page, such as rulers, crosshair cursor, grid visibility, snapping to grid and thegrid step. The Unit lists all available units. All sizes used in I/O Designer are displayed in theunit specified there.

The Symbol Editor page also contains the default settings for ports in symbols, such as theirlength, spacing between ports, and texts used as port labels.

Related Topics

• “Creating, Editing and Updating Symbols and Schematics” on page 95

Table 3-4. Symbol Window Modes

Select ModeAllows you to select ports and graphical elements in the SymbolWindow. For details, see the section “Editing Symbol Elements”on page 106.

Zoom ModeWhen enabled, zooming in is performed by a single mouse-click.Zooming out is performed by SHIFT+click. To zoom in on aparticular area, click and drag a rectangle around it. Upon releasingthe mouse button, the selected area fills the entire SymbolWindow.

Pan ModeThe Pan Mode allows you to easily scroll in the Symbol Window.This option is also called a Hand Tool. The mouse cursor in PanMode has the hand shape. Clicking and dragging in Pan Modemoves the entire Symbol Window and its contents.

Drawing Tools


I/O Designer WorkspaceDevice Window

• “Symbol Wizard” on page 95

• “Building a New Symbol” on page 102

• “Editing Symbol Elements” on page 106

Device WindowThe Device Window displays a representation of the physical device in graphical form. Thiswindow may be closed and opened at any time with the menu item View > Windows > Device,or with the button on the view toolbar.

You can select and filter any set of components within the Device Window. In the DeviceWindow below the filter buttons, you can view individual components by selecting them.

You can also change the active FPGA by double-clicking directly from the Device Window (orfrom the Project Window).

Figure 3-4. Device Window

A device can be viewed using Top or Bottom view. To switch between the Top/Bottom view,the menu options View > Device > Top View and View > Device > Bottom View.



A device can be rotated by 0, 90, 180 or 270 degrees. To choose the rotation view for a device,use the menu options under View > Device > Rotate View or right-click on the device andselect the required rotation.

Right-click in the Device Window and select Rotate View by PCB Layout to switch to anExpedition PCB view format. When an active device can be rotated on the board, this optionallows the board and its components to be rotated as in Expedition. If the option is turned off,the layout is rotated to display the active device perpendicularly.

To enable the display of differential pins, choose View > Device > Show Differential Pairsoption from the menu. The differential pairs are then connected with red lines (by default).

Pin DisplayPins in the Device Window are displayed in different colors depending upon their currentstatus.

To change pin colors according to your preference, do the following:

1. Select Tools > Preferences and click Appearance.

2. Choose Device Window from the drop down list in the Category field.

3. Select the pin type from the Subcategory list and edit the colors using the drop downcontrols.

FPGA Pin TypesThe FPGA pin types are described in the Pin Legend box, located at the top of the DeviceWindow:

Table 3-5. Pin Display Colors

Assigned Pin(a pin that is assigned to a signal)

Unassigned Pin(a pin that is free to be assigned to a signal)

USER or SPECIAL unassigned pin

Selected pin

Pin to be assigned using drag and drop (see “AssigningSignals to Pins Using Drag and Drop” on page 84)

Pin marked for assignment(see “Mark to Assign” on page 83)



Figure 3-5. Pin Legend Box

When the mouse pointer is moved over a pin, the pin information (pin number, name, bank andassigned signal name) is displayed in the status bar.

Figure 3-6. Pin Information Status Bar

Additionally, if you hold the mouse pointer over a pin for a while, you will see a tool tipwindow containing the pin number, name, type, bank, function, swap group and assigned signalname (if assigned).

Figure 3-7. Pin Tool Tip Window

Bank DisplayPins that belong to different power banks are displayed with a different background color,which improves visual distinction between pins from different banks. The banks are displayedin three colors in such a way that banks 1, 4, 7, etc. are displayed in one color, banks 2, 5, 8, etc.



are displayed in another color, and banks 3, 6, 9, etc. in yet another color. To disable bankdisplay, uncheck the View > Device > Show Banks menu option.

Clock DisplayI/O Designer allows you to filter the Device Window for various clock information. The optionis available for Xilinx Virtex families, as specified below. To use the clock filtering, use themenu options:

• View > Device > Show Clock Regions: Show Clock Regions (Xilinx Virtex4,QVirtex4, QRVirtex4, Virtex5).

• View > Device > Show Local Clocks - IOB Columns: (Xilinx Virtex2, Virtex2p,Spartan3, Spartan3l, Spartan3e, Spartan3a, Spartan3adsp) Show possible clock pins.Move the mouse over the selected pins to see the corresponding clock regions.

• View > Device > Show Local Clocks - Interface to CLB Array: (Xilinx Virtex2,Virtex2p, Spartan3, Spartan3l, Spartan3e, Spartan3a, Spartan3adsp) Show possibleclock pins. Move the mouse over the selected pins to see the corresponding clockregions.

In order to select an entire clock region for a given pin, follow these steps:

• Select Tools > Preferences + Filters, and enable Regular expressions.

• In the Pins List, right-click the Local clocks column and choose Filter Column fromthe popup menu.

• In the Pins List’s filter edit box enter the desired pin number and press Enter.

Figure 3-8. Clock Region Example



DQ DQS Pins DisplayI/O Designer allows you to filter the Device Window for DQ DQS pins regions information.This option is available for Lattice and Altera families, as specified below. To use the DQ DQSregions filtering, use the menu options:

• View > Device > Show DQ DQS Pins in X4 Mode: (Altera: Arria GX, Arria II GX,Hardcopy II, Stratix II, Stratix II GX, Stratix III, Stratix IV; Lattice: LatticeEC,LatticeECP, LatticeECP2, LatticeECP2M, LatticeECP2MS, LatticeECP2S,LatticeECP3, LatticeXP, LatticeXP2).

• View > Device > Show DQ DQS Pins in X8X9 Mode: (Altera: Arria GX, Arria II GX,Cyclone, Cyclone II, Cyclone III, Hardcopy II, Stratix, Stratix GX, Stratix II, Stratix IIGX, Stratix III, Stratix IV).

• View > Device > Show DQ DQS Pins in X16X18 Mode: (Altera: Arria GX, Arria IIGX, Cyclone II, Cyclone III, Hardcopy II, Stratix, Stratix GX, Stratix II, Stratix II GX,Stratix III, Stratix IV).

• View > Device > Show DQ DQS Pins in X32X36 Mode: (Altera: Arria GX, Arria IIGX, Cyclone III, Hardcopy II, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III,Stratix IV).

Show Layout in Device ViewYou can turn layout view on and off using the button at the top of the Device window.



Figure 3-9. Device View - Show Layout

NoteDevice View can ONLY load a layout. The result of a .lpc or a schematic load is NOTsupported.

Scrolling and Zooming in the Device WindowYou can scroll through the Device Window using the controls on the main toolbar, or by right-clicking in the window to access the controls on the pop-up menu.

Table 3-6. Device Window Zoom Controls

Zoom InIncreases zoom by 50%



Quick Mouse Zoom OperationsYou can use the mouse to change the zoom quickly.

Device Window ModesThe Package Window operates in one of the following modes:

Table 3-8. Device Window Modes

Zoom OutDecreases zoom by 50%.

Zoom to FitShows the device in its entirety.

Zoom to SelectionFills the window with the selected pins.

Previous ZoomRestores the zoom to the state of the previousstate.

Next ZoomCancels the Previous Zoom operation.

Table 3-7. Quick Mouse Zoom Operations

Zoom In Click + middle button

Zoom Out SHIFT + click + middle button

Zoom Area SHIFT + drag + middle button

Zoom Area In SHIFT + drag right + right button

Zoom Area Out SHIFT + drag left + left button

Cancel Zoom Esc

Select ModeSelect Mode allows you to select pins in the Device Window. Toselect a pin, simply click on it. To add a pin to the existingselection, CTRL+click on the pin. Dragging allows you to selectmore than one pin. While dragging, you will see the selectionrectangle displayed. All pins within the rectangle are selected.To zoom in on an area in Select Mode, use SHIFT+click, and draga rectangle around the required area. When the mouse button isreleased, the window will zoom in on the selected rectangle to fillthe entire window.

Table 3-6. Device Window Zoom Controls

I/O Designer WorkspaceConsole Window


Console WindowThe Console Window displays commands executed by I/O Designer, including all output, errormessages and warnings. Also, commands can be entered and executed directly into the ConsoleWindow. The Console window may be closed and opened at any time with the menu item View> Windows > Console, or with the button on the View Toolbar.

Figure 3-10. Console Window

Commands can be entered in the last line of the Console Window. Press Enter to execute thecommand. See “TCL Interface” on page 165 for descriptions of the commands available.

To clear the contents of the Console Window, right-click inside it and select Clear Console.

Zoom Mode. When enabled, zooming in is performed by a singlemouse-click. Zooming out is performed by SHIFT+click. Tozoom in on a particular area, click and drag a rectangle around it.Upon releasing the mouse button, the selected area fills the entirewindow.

Pan Mode allows you to easily scroll in the Device Window. InPan Mode, the mouse cursor has the hand shape. Clicking anddragging in Pan Mode moves the entire Device Window and itscontents.

Assign Mode allows you to assign signals to pins visually. Thismode is especially useful while assigning a bus signal. Select a bussignal in the Signals List and click in the Device Window to startassigning the bus items. You will notice a special mouse cursor inthe Assign Mode. By default, the bus items are assigned MSB toLSB. Press the Shift key to assign the items the other way. Theselection in the Signals List is updated as the consecutive items areassigned.


I/O Designer WorkspaceTimings Window

Errors and Warnings

All errors and warnings are shown in the Console Window. If you choose to work with theConsole Window closed and the options Show warnings in dialogs and Show errors indialogs are not checked in the Tools > Preferences dialog, The Console window can be set toopen automatically if a warning error is reported. To do this:

1. Select Tools > Preferences and click Advanced.

2. Select Open console at warning, and/or Open console at error.

In the Console Window, editing operations such as Cut, Copy, and Paste are available usingkeyboard shortcuts, or using the Edit menu, the toolbar, and by right-clicking in the window andusing the pop-up menu.

Shortcuts in the Console WindowFor operations such as repeating previous commands in the Console Window, the followingshortcut keys are available:

• Up Arrow - If the cursor is in the last line, it displays the previous command. Otherwiseit moves the cursor up.

• Down Arrow - If the cursor is in the last line, it displays the next command after usingthe Up Arrow key. Otherwise it moves the cursor down.

Timings WindowThe Timings Window allows you to add timing constraints for signals in the Signals List. Thereare 4 categories of timing constraints you can specify: Clock Constraints, Pad to SetupConstraints, Clock to Pad Constraints, and Pad to Pad Constraints.

1. Clock Constraints

Figure 3-11. Clock Constraints



You can add or delete constraints by using the Add Timing and Delete Timing optionsfrom the popup menu. Only signals with CLOCK and DIFFCLOCK type are displayedin the Signal Name list.

Figure 3-12. Add/Delete Constraints

2. Pad to Setup Constraints

Figure 3-13. Pad to Setup Constraints

Only signals with IN and INOUT type are displayed in the Signal Name list and onlysignals with CLOCK and DIFFCLOCK are displayed in the Clock Name list.



Figure 3-14. Add Pad to Setup Constraint

3. Clock to Pad Constraints

Figure 3-15. Clock to Pad Constraints

Only signals with OUT and INOUT type are displayed in the Signal Name list and onlysignals with CLOCK and DIFFCLOCK are displayed in the Clock Name list.



Figure 3-16. Add Clock to Pad Constraint

4. Pad to Pad Constraints

Figure 3-17. Pad to Pad Constraints

Only signals with IN and INOUT type are displayed in the Signal In list and only signalswith OUT and INOUT are displayed in the Signal Out list.


I/O Designer WorkspaceProperties Window

Figure 3-18. Add Pad to Pad Constraint

Properties WindowThe Properties Window displays and allows editing of the attributes of signals, pins, symbolsand their elements. To open the Properties window, use the Edit > ... Properties command, the

button on the View Toolbar, or by right-clicking on the selected element and choosing ...Properties. Additionally, double-clicking the selected elements in the Symbol Window opensthe Properties Window. Note that the actual name of the menu command displaying theProperties window depends on the active window. For example, if the Signals List is active, thecommand is named Signal Properties.

The contents of the Properties Window depends on the active window and the current selection.If the Signals List is active, signal properties are displayed. If the Pins List is active, pinproperties are displayed. If the Symbol Window is active, selected elements properties aredisplayed, or the attributes of the whole symbol when nothing is selected.

Some attributes displayed in the Properties window are read-only, for example, Signal name forports. Other attributes may be modified by double clicking the attribute field on the right side ofthe Properties window. Some attributes are presented in groups, with a + sign on the left. Forinstance, all attributes associated with displaying the Signal Name besides the port are in theSignal Name group.

In the Properties window you change attributes for a group of selected items at once. Forexample, to change properties for several pins, select the pins, open the Properties window, andedit the desired attribute.

Any change made to an attribute will be carried through to all elements supporting this attribute.For example, if some ports are selected together with an arc, changing the Inverted attributewill set its new value for all selected ports, leaving the arc intact.

I/O Designer interprets most of the symbol attributes internally. However, it is possible to addcustom symbol attributes. To add a custom attribute, click on the right side of the Propertieswindow next to the text "New attribute", and type in the name of the new attribute. It will thenappear on the list, and can be edited as other attributes. Custom attributes are generated insymbol and schematic files in the form of properties.



The following tables list all the attributes available in the Properties Window for each type ofelement:

• Signal Properties

• Pin Properties

• Port Properties

• Symbol Properties



Signal Properties

Table 3-9. Signal Properties

Name Value

PCB Name The signal’s PCB name

HDL Name The signal’s HDL name

Dir Indicates the direction of the signal (In/Out)

Pin Shows the pin assigned to the signal

Type Shows the type of signal

I/O Standard Shows the I/O standard of the signal

Swap group Shows the signal swap group

Locked by Indicates whether the signal is locked

Symbol Shows the symbol name that the signal isplaced upon. If a signal is placed on more thanone symbol, their names are separated by ‘&’.

STRENGTH Shows the pin’s drive strength.

TERMINATIONSLEW_RATEDELAY

Additional signal properties for Xilinx devices

WEAK_PULL_UP_RESISTORTREAT_BIDIR_AS_OUTPUTSLOW_SLEW_RATEPOWER_UP_LEVELPCI_IOINCREASE_DELAY_TO_OUTPUT_PINFAST_OUTPUT_REGSITERFAST_OUTPUT_ENABLE_REGISTERFAST_INPUT_REGISTERENABLE_BUS_HOLD_CIRCUITRYDECREASE_INPUT_DELAY_TO_INTERNAL_CELLSSTRENGTH

Additional signal properties for Altera devices



Pin Properties

Table 3-10. Pin Properties

Name Value

Number Shows the pin number. This property is read-only.

Name Shows the pin name. This property is read-only.

Signal Shows the signal to which the pin is assigned.

Swap group Shows the pin swap group.

Type Indicates the pin type.

I/O Standard Shows the I/O Standard selected for the pin.

Function Shows the pin function. This property is read-only.

Bank Shows the power bank the pin belongs to. Thisproperty is read-only.

VCCIO Shows the I/O VCC supply level.

STRENGTH Shows the pin’s drive strength.

TERMINATIONSLEW_RATEDELAY

Additional pin properties for Xilinx devices.

SLOW_SLEW_RATEPOWER_UP_LEVELFAST_OUTPUT_REGISTERFAST_INPUT_REGISTERDECREASE_INPUT_DELAY_TO_INTERNAL_CELLS

Additional pin properties for Altera devices.

DQDQS X32X36 Region Shows the X32X36 region number the pin belongs to.This property is read-only.



DQDQS X4 Region Shows the X4 region number the pin belongs to. Thisproperty is read-only.

Vref Group Shows the vref group name/number the pin belongsto. This property is read-only

Lab Row Shows the row number of a Lab where the pin exists.This property is read-only.



Lab Column Shows the column number of a Lab where the pinexists. This property is read-only.

Local Pad Number Shows the pin position inside of a Lab. This propertyis read-only.

Global Pad Number Shows the global internal pin number. This propertyis read-only.

Table 3-10. Pin Properties (cont.)



Port Properties

Table 3-11. Port Properties

Name Value

Port Label Label VisibleIndicates whether the port label is visible or hidden. The default is True.

Label PositionIndicates the position of label relative to the port. The property is availableonly when Label Visible is set to True. This can be one of the following:Over, Under, Side, and Moved. Moved signifies that you have moved thelabel. The default is Side.

Label TypeOne of the following: Signal Name, Pin Name, and Pin Number. Indicateswhat is used as the port label. The default value of this property may be setunder Tools > Preferences, on the Symbol Editor page. The Label infunctional symbol option is used to set the default for functional symbols.The Label in PCB symbol option is used to set the default for PCB symbols.

Signal Name Displays the signal name as well as the main port label.

Label VisibleIndicates whether the signal name is visible or hidden. The default is False.

Label PositionIndicates the position of the signal name relative to the port. The property isonly available when Label Visible is set to True. This can be one of thefollowing: Over, Under, Side, and Moved. Moved signifies that you havemoved the signal name. The default is Side.

Pin Number Displays the pin number as well as the main port label.



Pin Name Label VisibleIndicates whether the pin number is visible or hidden. The default is False.

Label PositionIndicates the position of the pin number relative to the port. The property isonly available when Label Visible is set to True. This can be one of thefollowing: Over, Under, Side, and Moved. Moved signifies that you havemoved the pin number. The default is Over.Displays the pin name as well as the main port label.

Label VisibleIndicates whether the pin name is visible or hidden. The default is False.

Label PositionIndicates the position of the pin name relative to the port. The property isonly available when Label Visible is set to True. This can be one of thefollowing: Over, Under, Side, and Moved. Moved signifies that you havemoved the pin name. The default is Side.

Pin Function Displays the pin function as well as the main port label.

Label VisibleIndicates whether the pin function is visible or hidden. The default is False.

Label PositionIndicates the position of the pin function relative to the port. The property isonly available when Label Visible is set to True. This can be one of thefollowing: Over, Under, Side, and Moved. Moved signifies that you havemoved the pin function. The default is Over.

Signal Name Displays signal name.

Label VisibleIndicates whether signal name is visible or hidden. The default is False.

Label PositionIndicates the position of the label relative to the port. The property isavailable only when Label Visible property is set to True. Label Positionmay be one of the following: Over, Under, Side, and Moved. Movedindicates that you have moved the label. The default value is Over.

Pin Type Shows the pin type. This property is read-only.

Dir Shows the direction of the signal. This property is read-only.

Port Type Shows the port type. The available types are:default, IN, OUT, BI, ANALOG, OCL, OEM, TRI, POWER, GROUND,TERMINAL.

Table 3-11. Port Properties (cont.)



Symbol Properties

Graphic Properties• Outline Color - shows the color of the lines or border of the selected graphical elements.

• Fill Color - shows the fill color of the selected graphical elements. You can fill anygraphical element such as an arc.

Port Shape Shows the shape of the port. The available shapes are: default, ARROW, andCLK.

Inverted Indicates whether the port is inverted. The default value is False.

Length Specifies the port length.

Port Binding Specifies port binding behavior during signal reassignment. There are twopossibilities:

Signal: If a given port has the Signal binding type, it means that the port isbound to a signal. On reassignment the port’s pin properties changeaccording to the reassignment. Port’s signal properties remain unchanged.

Pin: If a given port has the Pin binding type, it means that the port is boundto a pin. On reassignment the port’s signal properties change according to thereassignment. Port’s pin properties remain unchanged.

Attributes Lists the attributes defined for the port.

Table 3-12. Symbol Properties

Symbol Name Indicates the name of the current symbol.

PCB Symbol Indicates whether the current symbol is a PCBor functional symbol. This property is read-only.

Background Shows the background of the current symbol.The default empty value is a standardrectangular background.

Attributes Lists attributes of a symbol. Symbol attributesmay be locked to make sure they are notoverwritten during the export/import process.To lock/unlock a given attribute, click thepadlock icon.

Instanceattributes

Lists instance specific attributes.

Table 3-11. Port Properties (cont.)


I/O Designer WorkspaceSynchronization Wizard

Text Properties• Text - shows the characters within the text.

• Font - shows the font in which the selected text is displayed.

• Font Size - shows the font height of the selected text.

• Text Color - shows the color of the selected text.

Synchronization WizardThe Synchronization Wizard is used to synchronize the database with all external filesassociated with it, such as input files specified to supply source data for the component, or theschematic to which the component is to be exported.

To access the Synchronization Wizard, select Export > Synchronize, or click the icon onthe main toolbar.

Use the and icons to switch between Logical view and Files view.

Logical view lists items that need to be synchronized in a logical manner. Files view lists allitems that may need to be synchronized. For each tracked item, the Status column reportswhether there is a conflict to solve.

Synchronizing FilesUse the following procedure to run the Synchronization Wizard and update some or all filesused in the database:

1. For each item in the list, if the checkbox in the Track Status column is checked, thenthe required action for that file is suggested in the Action column, for example, toimport data , export data or take no action (blank selection). If tracking isdisabled, you must select the required action from the Action column.

2. (Optional) Click Apply to save the Synchronization Wizard settings for the currentdatabase. These settings will be stored in the database file following a Save action.When I/O Designer checks for updated files, it will only look for those selected in theTrack Status column.

3. Click Next.

This starts the process of synchronizing items that have been marked for update in theTrack Status column.

4. When the progress indicator is at 100%, synchronization is complete. Click Next.

A summary of what has been updated is displayed.

I/O Designer WorkspaceGUI Startup Preferences


If there are conflicts in assignments, the Synchronization Wizard allows you to mergethe assignments manually, or select a file from which to read the assignments. Thefollowing files contain the assignment information:

• Synthesis Constraints Files

• P&R Constraints Files

• Pin Report Files

• FPGA Xchange Files

• PCB Design Files - (Design Architect/Board Architect/ DxDesigner/DesignCapture/DesignView project files)

5. Click Finish.

Synchronization CheckI/O Designer checks for updated files at a specified time interval, and prompts you to runSynchronization if it finds them. This check is performed every 3 seconds by default, but thistime interval can be changed on the Tools > Preferences + Synchronization Check page. Onlythe files selected in the Track Status column of the Synchronization Wizard are included inthis check. For each item in the list, select the checkbox in the Track Status column if yourequire that item to be checked using the Synchronization checker.

GUI Startup PreferencesI/O Designer GUI Startup preferences can be set under Tools > Preferences + Gui Startup.

You can choose one of the following three startup actions to be performed by default uponstarting the application:

• Load last project

• Create new project

• Show startup dialog

If you want to disable the display of the license dialog upon startup, uncheck this option here.

The use of database preference settings can be controlled such that they are always used, neverused, or you can be prompted to choose whether they are used or not in each case.

Database preference settings can be saved as global settings by selecting the Save also as globalsettings checkbox.

For more information on project and databases, see “Working with Projects and Databases” onpage 61.


I/O Designer WorkspaceErrors and Warnings

Errors and WarningsErrors and warnings are reported via the Console Window and are also displayed in dialogs.This behavior is customizable in the Tools > Preferences dialog. On the Advanced page youcan find the options Show warnings in dialogs and Show errors in dialogs. Separate optionsfor errors and warnings give more control over what should be presented in the dialog, and whatin the Console Window only.

Customizing Files and DirectoriesThe Tools > Preferences + Paths page allows you to specify paths to files and directoriesnecessary for tool and project integration.

To change a directory path, double-click on the path and select the icon. This allows youto browse and select a new location.

AppearanceThe appearance page allows you to change the appearance of some elements of I/O Designer.The settings are grouped by categories, and a number of subcategories are available for eachcategory. For each subcategory the color, font, and other attributes can be changed. Note thatthe default settings are read from the DxDesigner configuration file.

NoteFont size in the Symbol Window can be set either in standard points or relative to thesymbol port length. If the option Size relative to port length is selected, then font size isset in relation to Port Length. Port Length may be changed on the Symbol Editor page inthe Preferences dialog.

Source Control PreferencesThe Source Control page is the place where you can set the source control system of yourchoice. I/O Designer supports the following:

• Microsoft SourceSafe

• CVS

• RCS

• Clearcase

• Custom

I/O Designer WorkspaceCustomizing Files and Directories


Depending on your choice of source control system, there are various options available inSource Control page. Below is the list of possibilities:

Microsoft SourceSafe

To configure I/O Designer to work with Microsoft SourceSafe you need to provide thefollowing information:

• Database - path to SourceSafe initialization file

• Root - root node of the SourceSafe repository

CVS

To configure I/O Designer to work with CVS (Concurrent Versioning System) you need toenter a path to CVS repository.

Custom Source Control System

Custom page allows you to enter any number of variable-value pairs that may later be used bycustom Source Control System TCL commands.

Source Control page can be found at:

• Tools > Preferences + Source Control

Advanced SettingsYou can set the following options on the Tools > Preferences + Advanced page:

• Show warnings in dialog (default off)

• Show errors in dialog (default on)

• Open Console Window on warning (default off)

• Open Console Window on error (default off)

• Differential pins postfixes (defaults: _P and _N)

• Recognize differential signals: Turns on extracting differential structures info from HDLfiles. The option by signal postfixes tells I/O Designer to use the specified postfixesduring differential pairs search.

• Default bus direction: Specifies a default bus direction for scalar signal groups

• Separate bus pins: Does not create bus pins during update from constraints file

• Recognize differential signals by postfixes: Enables the extraction of differential signalsduring constraints file update, based on defined postfixes.


I/O Designer WorkspaceCustomizing Files and Directories

• Generate DIFF_PAIR attribute: Generates DIFF_PAIR attributes during schematicgeneration.

• Generate UNATTPHY pins in map file: Adds UNATTPHY pins to the map file duringschematic generation.

• Autodetect clocks: Turns on recognizing clock signals based on a regular expression.Autodetection applies to reading signals from files (HDL source files, constraint files)

Advanced page can be found at using Tools > Preferences > Advanced.


Chapter 4Typical Design Flows

FPGA FirstThe following steps describe how to create an FPGA component database in I/O Designer,create and export symbols to DxDesigner, perform I/O planning and layout optimization usingdata from Expedition PCB.

1. Create a new project containing a new FPGA database as described in “Creating a NewProject” on page 62 and “Adding Databases to a Design” on page 65.

2. Build the FPGA database either using the FPGA Database Wizard or by doing thefollowing:

a. Select File > Database Properties and click the FPGA Flow tab to specify anFPGA device. See “Selecting the Device” on page 68.

You can also specify FPGA vendor files such as Place and Route Constraints Filesor Pin Report Files at this time. See “Importing FPGA Vendor Files” on page 68.

b. Select the I/O Signals tab to import I/O signals for the FPGA from an HDL file orspreadsheet. See “Defining I/O Signals” on page 70.

c. Set the I/O Standard for signals in the Properties Window. See “Set the I/OStandard” on page 76.

3. Add user-defined rules (optional step). See “User-defined Rules” on page 79.

4. Select Assign > Assign Pins or use the shortcut key F4 to assign signals to pins asdefined in the HDL source specified. For information on other ways to assign pins, see“Making Pin Assignments” on page 83.

The pin assignments will follow device-specific rules as well as user-defined rules. See“Device-dependant Assignment Rules” on page 213 and “User-defined Rules” onpage 79.

The FPGA design is now ready to insert into the PCB schematic and go to Layout. Thenext step is to build a symbol set for the I/O signals and then export them to theschematic.

NoteAt this stage, the pin assignments are not optimized for the PCB layout.


Typical Design FlowsFPGA First

5. Create PCB symbols using the Symbol Wizard. See “Symbol Wizard” on page 95.

a. Create a PCB symbol for inputs. Select the inputs in the Signals List.

b. Invoke the Symbol Wizard by selecting Symbol > Symbol Wizard or by clickingthe icon on the toolbar or at the top of the Symbol Window.

c. Create a PCB symbol for outputs in the same way.

This flow makes use of Implicit Power Connections, so there is no need to createpower and ground symbols. I/O Designer will attach the necessary properties to thecomponent.

6. Select Export > Schematic and Symbols to export the symbols to the schematic. See“Exporting Symbols and Schematics” on page 110.

7. I/O Planning

a. Select Import > Schematic to load critical components into the Layout Database.

b. Change the positioning and orientation of parts. See “Adjusting ComponentOrientation” on page 123.

Components can be moved around freely inside the Layout Window. At this stage,clearances are not important; the orientation of the parts is what matters.

c. Unravel nets see “Unravel Nets” on page 123.

Next, optimization can be performed using Unravel Nets and different scenarios canbe created until the best solution is found and applied (see “Creating and Applying aLayout Scenario” on page 126).

d. Launch CES. Go to the FPGA database and add CES constraints to the FPGA nets.

When nets are selected in the I/O Designer FPGA database, that selection is alsomade in CES allowing constraints to be added to the specific nets quickly and easily.

8. Select Export > Schematic and Symbols to update the schematic with the optimizedpin assignments. See “Exporting Symbols and Schematics” on page 110.

If only the pin assignments have changed, the symbols are automatically updated. Thesymbol set will remain unchanged with the exception of the new pin assignments. Onlythe pin number will move. The pin label will be unchanged.

9. In DxDesigner, run Packager and open Expedition to view the optimized board results.

10. I/O Optimization (optional)

a. In the I/O Designer layout database, select Import > Layout to load the PCB layout.

The PCB layout and netlines are visible in the Layout Window.

b. Review the layout and create new layout scenarios if further optimization is needed.


PADS I/O Designer User Guide, 8.2 59

11. Select Export > Schematic and Symbols to update the schematic with the optimizedpin assignments. See “Exporting Symbols and Schematics” on page 110.

If you specified FPGA vendor files when you set up the database, you can use the FPGAdatabase’s Export menu to update them with the new pin outs. See “Place and RouteConstraints Files” on page 133 and “FPGA Xchange Files” on page 134. To create newfiles, select File > Database Properties and click the FPGA Flow tab to enter filelocations for these files.

With that step, the loop is completed and the FPGA design will be updated to reflect theoptimized I/O assignments.


Chapter 5Working with Projects and Databases

What is a Project?After I/O Designer launches, the first step is to open or create a project. A project is anenvironment in which you can work with multiple databases which form part of the samedesign.

The project file (.prj) should be created within the Mentor flow tool, for example DxDesigner,and this project file is then opened in I/O Designer (see “Opening a Project” on page 62). If youare using the EE flow, projects can be created within I/O Designer first (see “Creating a NewProject” on page 62), and then opened within DxDesigner and used as normal. For other flows,if you create the project in I/O Designer first, it will not be able to connect to the iCDB and youwill be unable to work interactively.

NoteFor BoardStation XE flows, projects that are created within I/O Designer do not createthe iCDB database. In order for the project to work online with the iCDB, the iCDBdatabase must be created within BoardStation XE.

An I/O Designer project can contain one or more “Designs” which correspond to the top-leveldesign or designs in the Mentor flow tool project. When working in I/O Designer, databases arecreated within the project, and are associated with a particular top-level design in DxDesigner.

Project WindowThe Project Window allows you to organize databases for a design into the project environment.All database files within a project are listed by design with their path and Reference Designator(if applicable). Each design in the project can be selected using the drop-down box. The ProjectWindow may be closed and opened at any time, either using the menu item View > Windows >Project list, or the button on the view toolbar.

Right-clicking in the Project Window gives access to a menu of commands allowing you tocreate a new project, open or close an existing project, add new designs to the project or addnew or existing databases to the current project.

Related Topics

• “What is a Project?” on page 61

• “Creating a New Project” on page 62.


Working with Projects and DatabasesWhat is a Project?

• “Adding a Design to a Project” on page 63.

• “Adding Databases to a Design” on page 65

Opening a Project1. Open the Project Window by selecting View > Windows > Project, or click the

button on the view toolbar.

2. Do one of the following:

• Select File > Open Project.

• Right-click in the Project Window and select Open Project.

3. Browse to the existing project file (.prj), select it and click Open.

The project will open in the Project Window. Top-level designs can be selected from thedropdown box, and any associated I/O Designer databases are listed in the window.Double-click on a database in the list to open it.

Creating a New ProjectIf you are using the EE flow, projects can be created within I/O Designer, and then openedwithin DxDesigner and used as normal.

1. Open the Project Window by selecting View > Windows > Project, or click thebutton on the view toolbar.


• Select File > New Project.

• Right-click in the Project Window and select New Project.

The New project dialog is displayed.

3. In the Project Path field, enter the path to the location to which the project should besaved (or click Browse to navigate there) and enter a name for the project.

A project file (.prj) will be saved in that location.

4. Enter the path to the central library (.lmc) in the Central Library Path field, or clickBrowse to navigate to it.

5. Click OK.

An empty project is created in the Project Window. You can now add designs to theproject, and then add I/O Designer databases to each design.

• See “Adding a Design to a Project” on page 63

Working with Projects and DatabasesWhat is a Project?


• See “Adding Databases to a Design” on page 65

Adding a Design to a ProjectIn DxDesigner, a project may contain a number of designs within it, which correspond to adifferent PCB design in the project. Figure 5-1 shows the DxDesigner Project Navigator whereDesigns are listed underneath the project name (in this case: DxBoardDesign).

Figure 5-1. DxDesigner Project Navigator

When opening a DxDesigner project in I/O Designer, you can select each top-level design usingthe drop-down box on the Project Window as shown in Figure 5-2. When a Design is selected,all the I/O Designer components residing within it are listed in the Project Window.


Working with Projects and DatabasesWhat is a Database?

Figure 5-2. Selecting a Design in the I/O Designer Project Window

New Designs can be added to the Project in I/O Designer using the following procedure:

1. Do one of the following to add a new Design to the project:

• Select File > Add New Design.

• Right-click in the Project Window and select Add New Design.

2. Enter a name for the Design and click OK.

What is a Database?In I/O Designer you create a database file for each FPGA device, and a Layout Database file inwhich to perform layout optimization:

• FPGA Database (.fpc)

See “FPGA Database Wizard” on page 67

• Layout Database (.lpc)

See “Optimizing the I/O Assignments” on page 119.

NoteLayout database functionality is not available in the WG flow.



When multiple databases are open, the workspace contains multiple tabs to display concurrentlyopened databases. The database icon on each tab indicates the database type (FPGA, or layout).

Adding Databases to a DesignDatabases are created by adding them to Designs that reside within a project. Once you haveadded a database to a design, you can begin building or modifying that component or layout.

1. To add a new database to your project, do one of the following:

• Select File > Add to Design > New FPGA, or Layout.

• Right-click on the Project Window and select Add to Design > New FPGA, orLayout.

2. The Save As dialog appears. Enter a name for the new database and save it to yourworking directory.

The new database opens and will be listed under the design in the Project Window. Anewly created database contains neither signals nor symbols, but a default FPGA (lastused) device is chosen.

You may also add existing databases to the project by doing one of the following:

• Select File > Add to Design > Existing Database.

• Right-click on the Project Window and select Add to Design > Existing Database.

You can also use the Database Wizard to add a new FPGA database to a design, by doing one ofthe following:

• Select File > Add to Design > New FPGA from Wizard.

• Right-click on the Project Window and select Add to Design > New FPGA fromWizard.

See “FPGA Database Wizard” on page 67.

Related Topics


• “Adding a Design to a Project” on page 63

FPGA database

Layout database



• “Optimizing the I/O Assignments” on page 119


Chapter 6Adding an FPGA to the Design

This chapter describes in detail the steps necessary for building an FPGA device database.

FPGA Database WizardThe Database Wizard guides you through the steps necessary in order to specify the informationrequired to build a new FPGA database in I/O Designer.

1. Do one of the following to invoke the FPGA database wizard:

• Select File > Add to Design > New FPGA from Wizard.

• Right-click in the project window and select Add to Design > New FPGA fromWizard.

Click Next to begin adding data.

2. Specify an HDL source file.

This is the file that is analyzed by I/O Designer and from which signals are read. If theHDL file contains multiple top-level units, you will be prompted to choose one of them.

If you have a Verilog file that references some external files (using include construct),you will also be prompted to enter the directory in which to search for those additionalfiles. See “Additional HDL Files” on page 71 for more information.

3. Define the database name and location.

The default name is the top-level unit name from the file provided in the previous step, ifany. Click Next and enter a location for the database.

4. Specify vendor, Place & Route tool and device for use in the new database.

You can select one of over 1000 devices from a library that is kept current with those ofthe FPGA vendors.

5. Specify the Place & Route constraints file and the Place & Route pin report file.

See “Place and Route Constraints Files” on page 133 and “Pin Report Files” onpage 134.

6. Specify Synthesis tool and select Synthesis constraints file. See “Synthesis ConstraintsFiles” on page 132.

7. Configure a Design Definition tool. This includes specifying some tool-specific options.


Adding an FPGA to the DesignFPGA Device Setup

The information entered here may be changed at a later date by selecting File > DatabaseSettings and making the changes using the Database Settings Dialog.

Related Topics

• “FPGA Device Library” on page 69

• “Place and Route Constraints Files” on page 133

• “Pin Report Files” on page 134

FPGA Device SetupCreate a new project containing a new FPGA database as described in “Creating a New Project”on page 62 and “Adding Databases to a Design” on page 65.

Once you have added a new FPGA database to a project, you can begin to build the FPGAeither using the FPGA Database Wizard or by doing the following:

• Selecting the Device

• Importing FPGA Vendor Files

Selecting the Device1. Select File > Database Properties and click the FPGA Flow Tab to specify an FPGA

device.

2. Specify the Vendor Actel, Altera, Lattice or Xilinx using the dropdown box.

3. The other fields in the Device section are populated with the options available, allowingyou to choose the device from a particular tool/library and family, and to specify apackage and speed.

Importing FPGA Vendor FilesFPGA vendor files can be imported directly into I/O Designer either during setup of a newFPGA database using the FPGA Database Wizard, or using the Database Settings Dialog.

1. Right-click on an FPGA database in the Project Window, select Database Propertiesand click the FPGA flow tab.

2. Specify FPGA vendor files such as Place and Route Constraints Files or Pin ReportFiles.

FPGA vendor files typically have a pin number assigned and the I/O Standard assigned. Thesetwo items do not exist in the HDL file. I/O Designer will re-assign the existing signals to thenew pins assignments in the vendor file as well as making the I/O Standard assignment.

Adding an FPGA to the DesignFPGA Device Library


Related Topics


• “Pin Report Files” on page 134

FPGA Device LibraryI/O Designer’s built-in library contains information about each FPGA device and the rules thatapply to it. Mentor Graphics receives this data from the FPGA vendors either directly or byusing an automated process which translates that data directly from the FPGA Vendor libraryformats.

In the case where these mechanisms fail to deliver the complete set of data a request for moredata will be discussed with the appropriate FPGA Vendor via the partnership channel thatMentor Graphics has with all supported FPGA Vendors. In some cases this data can bedelivered quickly, while in other cases it takes some time for the FPGA Vendors to make thisdata available.

Since the I/O Designer device library has a one-to-one relationship with the same version of theFPGA Vendor tool, any errors that were introduced in the FPGA Vendor library will also existin the I/O Designer library unless they were found during the translation process. As soon as theFPGA Vendor fixes their errors they will automatically make their way into the I/O Designerdevice libraries. This could be as soon as the FPGA Vendor releases their new software sinceMentor Graphics is planning to make separate library updates for the I/O Designer devicelibraries available via SupportNet more frequently than the major software releases.

I/O Designer cannot guarantee that after changes have been made to the pin assignment thedesign:

• is still routable due to the available FPGA surface given the new re-located signals. Forexample it could be difficult to route an FPGA for which 90% of the surface is used witha pin assignment that is not optimal for routability.

• meets their timing requirements since the pin assignment also influences the timingpaths and therefore the actual timing. So when a design is timing critical it could be thata new pin assignment will violate certain timing requirements.

• meets all the I/O Design rules. I/O Designer’s built-in library with device and ruleinformation is used on-the-fly to test the design. However, Mentor Graphics isdependent on the FPGA Vendors for these rules and in some cases it takes time beforethe data becomes available.


Adding an FPGA to the DesignDefining I/O Signals

Design Rule CheckIt is recommended that you check the I/O design against any of the violations mentioned aboveby running it through the FPGA Vendor tools before proceeding to the PCB process. I/ODesigner offers two ways to achieve these checks:

1. After generating the Place and Route constraints file the DRC utility from the chosenFPGA Vendor can be run from within I/O Designer through the Tools > Design RuleCheck menu. This ensures that the design is not violating any of the I/O Design rules.

2. When the Place and Route constraints file has been generated, continue the regularFPGA process by taking the design including the Place and Route constraints filethrough the FPGA Vendor tool flow to implement the device. This way the design canbe verified against any risks of not being able to implement the design.

NoteIn both steps, the chosen FPGA Vendor tools have to be installed in order to complete thechecks.

Related Topics

• “Preferred Devices List” on page 207

• “Vendor Support Information” on page 209

• “Device-dependant Assignment Rules” on page 213

• “Generic IO Standards” on page 217

Defining I/O SignalsI/O signals and signal assignments can be defined in an FPGA database in the following ways:

• “Importing I/O Signals Using HDL/Netlist Files” on page 70

• “Importing I/O Signals Using a Spreadsheet” on page 72

I/O signals can also be created manually within I/O Designer:

• “Creating a New Signal or Signal Bus” on page 73

Importing I/O Signals Using HDL/Netlist FilesI/O Designer includes integrated VHDL, Verilog, EDIF and XML parsers. The followingprocedure describes how to import I/O signals into a database from source files in those formatsusing the Database Settings Dialog:

1. Select File > Database Settings to display the Database Settings Dialog.



2. Select the I/O Signal List Tab.

3. Select VHDL, Verilog or Edif / XML as the HDL / Netlist file: Language.

4. Specify the path to the file in the Name field. You can enter the path manually, or clickBrowse to navigate to the file’s location.

5. Click Analyze.

The Unit field will be populated with the available entities (VHDL), modules (Verilog)or cells (EDIF /XML) found in the HDL/Netlist file.

6. Select the required entity, module or cell from the Unit field.

7. (Optional step) If appropriate, specify additional VHDL file(s) or Verilog search path(s)in the box below. Use the Open and Close icons to add and remove additional files, andthe arrow icons to change their ordering. See “Additional HDL Files” on page 71 formore information.

8. Click OK. I/O Designer will prompt you to run synchronization. Click RunSynchronization Dialog... to open the Synchronization Wizard.

9. Click Next and Finish on the Synchronization Wizard to import the data from thespecified file.

The Signals List will be populated with the signals read from the source file.

NoteIf the file contains errors that prevent the signals from being read, then the errors foundby the integrated parser are displayed. To continue reading in signals from the file, theerrors have to be corrected first.

Additional HDL FilesBefore the file containing the entity declaration is analyzed, it is sometimes necessary toanalyze additional files in advance. This may be the case if, for example, the selected HDL fileuses some constants declared in packages. I/O Designer allows parsing any number ofadditional HDL files before the main one.

The I/O Signal List Tab on the Database Settings Dialog contains the list of these additionalHDL files.

1. To add a file to the list, use the button located on the right side of the list.

2. To remove a file from the list, use the button.

3. Files are processed in the same order as presented on the list. To move a file up or downthe list, click on it, and use the arrow buttons.



Since I/O Designer installation already includes standard VHDL libraries (IEEE andSTANDARD), there is no need to manually add these files for analysis.

Note that the main VHDL file is analyzed at the very end, after all of the additional files havebeen analyzed. So for example, if you have multiple entity architectures in separate files, thearchitecture that you want to use in I/O Designer needs to be analyzed at the very end. To dothis, you need to set the architecture file as the main file.

HDL Names and PCB NamesIn the Signals List each signal has an HDL Name and PCB Name. Upon loading an HDL netlist,both names assume the HDL name. The PCB Name can be used as the pin name during symbolcreation by specifying Signal Name as the Port label for the PCB symbol in the SymbolWizard.

PCB names and HDL names can be changed by doing one of the following:

• Select the signal in the Signals List and edit the PCB Name or HDL Name fields in theProperties Window. DIFF children are also renamed.

• Right-click in the Signals List and select rename. A dialog appears into which the newPCB name and/or HDL name can be entered.

A checkbox can be used to select whether DIFF children are also renamed.

Changing the PCB name of a signal only affects the PCB names of its children. Similarly,changing the HDL name of a signal only affects the HDL names of its children.

Importing I/O Signals Using a SpreadsheetThe following procedure describes how to import I/O signals and signal assignments into adatabase from a spreadsheet using the Database Settings Dialog.

1. Select File > Database Settings to display the Database Settings Dialog.

2. Select the I/O Signal List tab.

3. Select Spreadsheet as the HDL / Netlist file: Language.

4. Specify the path to the spreadsheet file in the Name field. You can enter the pathmanually, or click Browse to navigate to the file’s location.

5. In the Delimiter field, enter the character which will define the start of each entry.

6. In the Column assignments window, the numbering should match the spreadsheetcolumn numbers where I/O Designer can locate information for items such as Signalname, Signal type, Signal direction, Cell template name, Cell instance name, Pad name,and so on. Use the arrows to move the assignments up or down in the list.



7. Click OK. I/O Designer will prompt you to run synchronization. Click RunSynchronization Dialog... to open the Synchronization Wizard.

8. Click Next and Finish on the Synchronization Wizard to import the data from thespecified file.

The Signals List will be populated with the signals listed in the spreadsheet.

Creating and Editing Signals in the Signals ListIn an FPGA database, signals can be added, removed and renamed in the Signals List using theAdd Signal Dialog.

• “Creating a New Signal or Signal Bus” on page 73

• “Removing Signals” on page 73

• “Renaming Signals” on page 74

• “Combining Signals into a Bus Signal” on page 74

Creating a New Signal or Signal BusUse the following procedure to create a new signal and add it to a database in the Signals List:

1. Do one of the following to display the Add Signal Dialog:

a. Right-click in the Signals List and select Add Signal...

b. Select the menu item Edit > Add Signal...

2. Enter a name for the signal in the Name field.

3. Select the signal’s direction (In, Out, Inout, Buffer or Linkage) in the Direction field.

4. Select the signal’s type in the Type field.

5. Enter an I/O standard (if applicable) for the signal in the I/O Standard field (optional).

6. Specify a range of values in order to create a signal bus (optional).

Removing SignalsUse the following procedure to remove a signal from a database:

1. From the Signals List, select the signal or signals to be removed and do one of thefollowing:

• Right-click on the signal or signal selection in the Signals List and select RemoveSignals.

• Select the menu item Edit > Remove Signals.



The signal(s) will be removed from the Signals List.

Renaming SignalsTo change the name of a signal in a database, use the following procedure:

1. From the Signals List, select the signal to be renamed and do one of the following:

• Right-click in the Signals List, select Rename and enter the new name for the signalin the dialog box.

• Select the menu item Edit > Rename and enter the new name for the signal in thedialog box.

• Enter the new name for the signal in the Properties Window.

Combining Signals into a Bus SignalIn the Signals List signals can be grouped into buses, known as bus signals. Bus signals arecreated automatically for vectors read from an HDL file. Additionally, user-defined bus signalsmay be created at any time. To create a bus, use the following procedure:

1. In the Signals List, select the signals which will form the bus.

2. Right-click on the selection and select Combine.

3. Enter a PCB name and an HDL name for the bus signal. Optionally, you can use thecontrols on this dialog to adjust the range of signals in your bus.

A bus signal is created and can be identified in the Signals List by the plus sign at theleft of the bus name.

Click the plus sign to expand or collapse the bus in the list, displaying or hiding itselements. Alternatively, select View > Expand, or View > Collapse to do the samething. To expand or collapse all buses together, select View > Expand All, or View >Collapse All.

NoteBuses cannot be nested - bus signals cannot be combined into another bus.

A bus may be split or replaced with the flat list of its elements. To split a bus right-click on itand select Split. To split all buses at once, right-click in the List Window and select Split All.

Bus signals can be renamed in the same way as other signals. See “Renaming Signals” onpage 74.



Related Topics

• “Combining Pins into a Bus Pin” on page 85

• “HDL Names and PCB Names” on page 72

Differential PairsTo create a differential signal pair from existing signals, select the required signals in theSignals List, right-click and choose Create Differential Pair.

To split a differential pair back into separate signals, right-click the selection and choose SplitDifferential Pair.

When adding signals to the Signals List manually, you can specify that they are a differentialsignal pair by selecting the signal type as DIFF in the Type field on the Add Signal Dialog.

In an FPGA database, differential signal assignments assign the whole DIFF signal, andmember assignment is done automatically.

It is possible to force assignment of differential signals to IO pins by holding down SHIFTwhilst assigning signals to pins. The pin type will be automatically changed to DIFF.

Differential signals are displayed as shown in Figure 6-1.

Figure 6-1. Differential Pairs Displayed in the Signals Window

PCB Signal AssignmentsI/O Designer supports PCB signal assignments. Special signals, for example ANALOG_GND,may be assigned to pins from the PCB page of the Pins List. I/O Designer allows you to add and



use PCB signals directly in the Signals List. You can distinguish HDL signals from PCB signalsby their icons.

Set the I/O StandardFPGAs are very flexible and I/O Designer fully supports the variety of I/O standards available.To change a signal’s I/O standard, select the signal in the Signals List, and then in the PropertiesWindow, you can select the I/O standard from the dropdown list.

The example in Figure 6-2 shows the bus PDATA[0:63] being assigned an I/O standard ofLVCMOS25. The"25" indicates this is a 2.5 Volt signal and will require that the Bank suppliesbe set to 2.5 Volts typically using the VCCO pins.

Figure 6-2. Setting the I/O Standard

When a signal is assigned a specific voltage, the entire bank is affected and unused pins arechanged to the same I/O standard. A conflicting voltage level or I/O standard cannot be appliedto that bank. As part of the I/O Standard assignment, I/O Designer will also manage the powerassignment for any affected banks. I/O Designer creates a new power signal for the voltage (inthis example, it would be named V_2_5) and assigns it to the VCCO pins on the affected banks.

Adding an FPGA to the DesignDesign for Multiple Devices in a Common Package


Signal LockingWhenever a signal is locked, it is immutable. I/O Designer does not allow changing its pinassignment, deleting it, or changing any other attribute of the locked signal. Locking signals canbe useful when multiple designers are sharing a database, or simply to apply security to a signal.The Signal locking feature does not depend on any source control system. The locked/unlockedstate of a signal is stored in the database.

To lock a signal or signal selection, right-click on it in the Signals List, and choose LockSignals.

To unlock a signal or signal selection, right-click on it in the Signals List, and choose UnlockSignals.

Design for Multiple Devices in a CommonPackage

I/O Designer supports designing for multiple devices, allowing you to switch to a larger orsmaller device without changing the pin assignment or PCB routing. This is accomplished byoverlaying multiple devices typically in a common package and enabling only those pins thatare common. Pin assignments are thus limited to only those common pins. This provides theflexibility to swap devices while maintaining I/O assignments and leaving the PCB unchanged.

I/O Designer provides a possibility to show only pins common to the current device and someother devices. To turn it on, select View > Pins from Other Devices. The displayed windowpresents the list of devices from the current vendor with the same package as the current device.The list can be easily modified by the use of the Add and Remove buttons.

If the option is turned on by the OK button, only pins which have the same functions in thecurrent device and all selected devices are displayed. For instance, if a pin is IO in the currentdevice, and the pin in the same position is not connected in one of the devices from the list, thepin is not displayed. In this way the option helps you to plan the design for different parts.

To access pins hidden by the Pins from Other Devices option select View > Show HiddenRows. If that setting is checked, all rows are displayed. The rows that are hidden will bedisplayed in a gray color.

PCB Design WizardUsed to import symbols with signals and pins into a an FPGA database directly from thedesign.

1. In an FPGA database, select Import > PCB Design Wizard. The Import DesignWizard Dialog is displayed.


Adding an FPGA to the DesignPCB Design Wizard

2. Enter the path to the project file containing the required design in the Project Path:field, or click Browse to navigate to the file’s location.

3. In the Design Name field, select the top-level design containing the requiredcomponent.

4. (Optional Step) Enter the Reference Designator for the required component in the RefDes: field and click Next.

5. Select the required symbol from the list.

You can use Regular Expression Filters to filter the list of symbols. Click the ... buttonfor a list of popular filters. Click Apply to apply the filter to the list.

6. (Optional Step) If you want to Import signals and assignments only, select thecheckbox for this option, located beneath the list of symbols. This will not import thesymbol. This option can be used with Schematic Update in order to preserve existingsymbols.

7. (Optional Step) If you want to Generate Functional Blocks for PCB Symbols, selectthe checkbox for this option, located beneath the list of symbols.

8. Click Next.

9. Specify information about the FPGA device by selecting the options from the drop-down boxes. Click Next.

10. Verify that the signal mapping from the imported PCB signals and any existing HDLsignals found in the database is correct and click Finish.


Chapter 7User-defined Rules

I/O Designer provides a mechanism for defining and managing user-specified rules for anFPGA device, which can supplement the vendor device rules. Every rule can contain a set ofsimple conditions or “primitives” concatenated by logical operators. Conditions can be set foreach primitive such that the rule is executed when the primitive is, is not, contains, does notcontain, matches or does not match the value(s) specified.

This section describes how to create rules see “Creating a New Rule” on page 79, and then referto the following example:

• “Setting a Rule for an FPGA Device” on page 80

Creating a New Rule1. Select Tools > Rule Editor.

The Rule Manager Dialog is displayed.

2. Click the New Rule icon. The Rules Wizard is displayed.

3. Enter a name for the new rule in the Name field.

4. Enter a description for the rule in the Description field.

5. In the Failure answer field, enter some text that will be returned if the attemptedassignment breaks this rule.

6. Click Next.

7. Set whether the rule will allow or forbid placements.

This information appears in the window at the bottom of the Rules Wizard.

8. Click Next.

The next pages allow primitives and conditions for signals and pin conditions to bedefined.

9. Double-click the required primitive or use the arrow controls to move it from theAvailable Primitives: list into the Rule Primitives: list.

The Edit Primitive Value(s) Dialog is displayed.

10. In the Operator: field, select the required operator for the primitive.


User-defined RulesCreating a New Rule

The rule is executed when the primitive is, is not, contains, does not contain, matches,or does not match the values defined in the Operand: field or selected from the list ofavailable values (present depending upon the type of operator).

11. Enter value(s) into the Operand: field or select them from the list of available values(present depending upon the type of operator). This field is case sensitive.

Regular Expression Filters may be used to specify values. Clicking the arrow next to theOperand: field gives suggestions of commonly used regular expression filters.

12. Click OK.

Primitive details are added to the window at the bottom of the Rules Wizard.

13. Click Add Term to make more rule assignments for a different set of signals (optional).

NoteWhen setting “Allow” rules, any signals or pins which do not qualify the rule will bedisallowed by default. If you want all signals and pins to be usable, ensure that you setadditional terms to allow those signals and pins to be assigned. This is demonstrated in“Setting a Rule for an FPGA Device” on page 80.

14. Repeat step 10 to add further primitives to the rule if required.

15. Click Next.

16. Click Finish.

The rule is created and will be present in the Rules: field in the Rule Manager Dialog.

Example 7-1. Setting a Rule for an FPGA Device

The following example creates locate rules for an FPGA device. The intent of the rule is tolocate the ALU busses and strobe to banks 6 and 10 in the top left quadrant of the Xilinx Virtex4 part.

1. In an FPGA database, select Tools > Rule Editor to open the Rule Manager dialog.

2. Click the New Rule icon to create a new rule.

The Set rule name and description page allows you to enter a name for the new rule inthe Name field, a description for the rule in the Description field, and in the Failureanswer field, you can enter some text that will be returned if the attempted assignmentbreaks this rule.

3. Click Next.

4. On the Rule scope page, set the following primitives by double-clicking them from thelist of Available Primitives:

• Vendor name is Xilinx



• Family name is Virtex 4

• Device name is 4vfx40

• Package name is ff1152

5. Click Next.

6. Select Allow assignments.

7. On the Pins condition page, set the following primitives by double-clicking them fromthe list of Available Primitives:

• Pin type is IO

• Pin bank is 6 or 10.

8. On the Signal conditions page, double-click Signal Name from the list of AvailablePrimitives. Set the primitive to:

• Signal Name is ^ALU.*

This sets the primitive to use all signals that start with "ALU".

9. The final step is to add an additional term that states “do nothing” for the remainingsignals. This in effect "releases" the remaining signals to be assigned as needed.

a. Click Add Term.

b. On the Signal conditions page, double-click Signal Name from the list ofAvailable Primitives.

c. Set the primitive to: Signal Name not matches ^ALU.*

This adds a term to the rule to allow use of signals that don’t start with "ALU".

Additional terms can also be set up to make more rule assignments for a different set ofsignals.


Chapter 8Making Pin Assignments

Assigning Signals to PinsUse the following procedure to assign all unassigned signals to available pins in one step:

1. Ensure that no signals are selected in the Signals List.

If no signal is selected, then I/O Designer will attempt to assign all signals in the list orthose which are marked to assign (see “Mark to Assign” on page 83).

2. To assign all signals to available pins, do one of the following:

• Select Assign > Assign Pins or click the icon on the toolbar.

Signals are assigned to available pins, preserving any existing assignments.

• Select Assign > Assign Pins with Overwrite or click the icon on the toolbar.

Signals are assigned to available pins, overwriting any existing assignments.

Signals are assigned in the same order that they are listed in the Signals List to the pinsin the order listed in the Pins List. If the number of signals differs from the number ofpins, the remaining signals or pins are ignored.

Mark to AssignThe Mark to Assign command is used to make a selection of signals or pins and assign justthose signals or pins when Assign > Assign Pins or Assign > Assign Pins with Overwrite ischosen. To mark signals or pins for assignment, use the following procedure:

1. Select the required signals or pins in the Signals List, the Pins List or the DeviceWindow .

2. Right-click on the selection and choose Mark to Assign.

Marked signals are displayed in the Signals List and Pins List with an animatedboundary. In the Device Window marked pins blink continuously. Marked signals orpins remain marked until the assignment is made.

Marked signals or pins can be unmarked by right-clicking on the selection and choosingRemove Marks.


Making Pin AssignmentsAssign Mode

Assigning Signals to Pins Using Drag and DropTo assign signals to pins with drag and drop, use the following procedure:

1. Select the signals that are to be assigned in the Signal List. Selecting a bus will assignpins to all bus elements.

2. Click the selected signals, and drag them to the Pins List or Device Window .

Pins that are to be assigned are highlighted in yellow. In the Pins List, the signal namesare displayed in the Signal column.

When more than one signal is being dragged onto the device, pins are highlighted inhorizontal rows. The horizontal row may be toggled to a vertical column by holdingdown the CTRL key while dragging.

To restrict the assignment to one power bank only, hold down the ALT key whiledragging.

Existing assignments are preserved, since signals that already have pins assigned tothem are not considered for assignment. To force changes in existing assignments, holddown the SHIFT key while dragging. New assignments are then given independently ofthe existing assignments. Conflicting assignments will be removed.

3. Drop the dragged signals to perform the assignments.

If too many signals are selected, as many signals as pins available will be assigned.

Assignments using drag and drop may also be performed in the opposite direction, by draggingpins in the Pins List or the Device Window to the Signals List. Signals that are to be assigned toare highlighted in yellow, and holding down the SHIFT key overwrites existing assignments.

Assign ModeI/O Designer allows you to assign pins visually in Assign Mode. This mode is especially usefulfor assigning bus signals. For a detailed description see “Device Window Modes” on page 38.

Changing Assignments in Lists

Drag & DropSelected rows in the Signal List and Pin List may also be dragged within the same list window.This operation changes pin assignments. To reassign pins select the signals in the Signal List,and drag the rows to a different position. During the drag and drop, the pin numbers aredisplayed in new positions. Dropping the pins assigns them. Similarly it is possible to select - inthe Pin List - pins that are assigned, and then drag the signals assigned to them to a new position

Making Pin AssignmentsChanging Assignments in Lists


in the Pin List. Note that this feature, as opposed to other pin assignment options, alwayschanges existing assignments.

Choosing Signals/Pins to Assign from a ListAnother way of changing assignments within List Windows is to double click on the Pincolumn in the Signal List, or on the Signal column in the Pin List. Then the list of all suitablepins or signals is displayed. Selecting an item from the list changes the assignment.

Assigning BusesWhile working with bus assignments, it is possible to assign bus members to pins one at a time.This is similar to the Assign Mode in the Device Window . To start assigning bus members dothe following:

• Select the bus in the Signal List window

• Click the pin in the Pin List window with one of the following key combinationspressed:

o Alt - to assign bus members MSB to LSB

o Shift+Alt - to assign bus members LSB to MSB

Combining Pins into a Bus PinThe Pins List allows pins to be grouped into buses, known as bus pins. To create a bus, use thefollowing procedure:

1. In the Pins List, select the pins which will form the bus.

2. Right-click on the selection and select Combine.

3. I/O Designer will ask you to enter a name for the bus pin, or you can accept the defaultname. Optionally, you can use the controls on this dialog to adjust the range of pins inyour bus.

A bus pin is created and can be identified in the Pins List by the + at the left of the busname.

Click + to expand or collapse the bus in the list, displaying or hiding its elements. Alternatively,select View > Expand, or View > Collapse to do the same thing. To expand or collapse allbuses together, select View > Expand All, or View > Collapse All.

NoteBuses cannot be nested - bus pins cannot be combined into another bus.


Making Pin AssignmentsPin and Signal Types

A bus may be split or replaced with the flat list of its elements. To split a bus right-click on itand select Split. To split all buses at once, right-click in the List Window and select Split All.

To change the name of a bus pin, right-click it in the Pins List and select Rename, or with thebus selected in the Pins List, select the menu item Edit > Rename.

You can also combine signals into bus signals, see “Combining Signals into a Bus Signal” onpage 74.

Pin SwappingI/O Designer offers you advanced swapping capabilities, available in Signal List and Pin Listcontext menus:

• Swap > Swap Two Pins: Swaps two selected signals/pins.

• Swap > Swap Entire Bus: Swaps two selected buses. The selected buses must have thesame width.

• Swap > Swap Entire Swap Group: If the selected pins/signals belong to two differentswap groups, this command swaps all assignments for these two swap groups.

• Swap > Swap Entire Bank: If the selected pins/signals belong to two different banks,this command swaps all assignments to pins from these two banks

Pin and Signal TypesThe Type column in the Pin List displays the pin type, such as IO, CLOCK, etc. Some typesmay be combined. For example, for differential clock pins DIFFCLOCK is displayed. Theavailable types are:

Table 8-1. Pin and Signal Types

Pin Type Description

Analog TRTN Unassignable temperature monitor return pin.

AnalogGND Unassignable ground for an analog circuitrypin.

AnalogIO Unassignable analog I/O pin.

AnalogPF Unassignable analog power filter pin.

AnalogVCC Unassignable power for an analog circuitrypin.

AnalogVREF Unassignable analog reference voltage pin.

CCLOCK Assignable Clock Capable pin.

CCLOCKDIFF Assignable differential Clock Capable pin.



CLOCK Assignable clock pin (see Clock Assignmentsbelow).

CONFIG Unassignable configuration pin.

DIFF Assignable differential pin (see ClockAssignments below).

DIFFCLOCK Assignable differential clock pin.

DQ Assignable Double Data Rate memoryinterface data pin.

DQS Assignable Double Data Rate memoryinterface data strobe pin.

DQSDIFF Assignable Double Date Rate memoryinterface differential data strobe pin.

GND Unassignable ground pin.

IO Normal assignable pin.

JTAG Unassignable JTAG pin.

MGT Multi-Gigabit Transceiver pin.

MGTCALRES Unasssignable MGT calibration resistor pin.

MGTCLK Assignable differential reference clock ofMGT pins.

MGTRX Assignable MGT receiver pin.

MgtTerminationReference Unassignable precision reference resistor pin.

MGTTX Assignable MGT transmitter pin.

MGTVCC Unassignable power-supply pin for transceivermixed signal circuitry of the MGT.

MGTVCCAUX Unassignable analog power supply pin forcircuitry of the MGT.

MGTVCCIO Unassignable power-supply pin for the MGToutput drivers.

MGTVCCPLL Unassignable power-supply pin for PLL MGT.

MGTVCCTRX Unassignable input/output buffer power supplypin for channel on left or right side of device.

MGTVREF Unassignable threshold voltage pin for MGT.

Table 8-1. Pin and Signal Types (cont.)




A pin type can be changed for some pins. After clicking inside the Type column, a listcontaining all types possible for the selected pin is presented. Changed pin types are stored inthe database. Changes made to pin types are always associated with appropriate changes of theI/O Standards. It works the other way around too. If a pin is switched to an I/O Standard thatdoes not support differential pins, the pin type is switched to non-differential.

MGTVTTRXC Unassignable power-supply pin for the resistorcalibration circuit of the MGT.

NC Unassignable not connected pin.

OTHER Unassignable pin of some other category.

PLL Assignable phase-locked loops pin.

PLLCAP Unassignable phase-locked loops capacitorpin.

PLLDIFF Assignable differential phase-locked loops pin.

PowerManagement Unassignable power management pin.

REFRES Unassignable reference resistor pin.

RESERVED Assignable pin with some additional features.

SystemMonitorADC Unassignable system monitor pin.

TemperatureDiode Unassignable temperate diode pin.

VBATT Unassignable decrypter key memory backupsupply pin.

VCC Unassignable power pin.

VCCAUX Unassignable power-supply pin for auxiliarycircuits.

VCCINT Unassignable dedicated internal core logicpower supply pin.

VccMgtTermination Unassignable power-supply pin for TX/RXcircuitry of a transceiver.

VCCO Unassignable power-supply pin for the outputdrivers.

VREF Unassignable threshold voltage pin.

VTT Unassignable dedicated terminating supplypin.

Table 8-1. Pin and Signal Types (cont.)




Clock AssignmentsYou can set I/O Designer to automatically detect clock signals. This behavior is enabled on thethe Advanced page of the Tools > Preferences dialog. In most cases, clock signals areuniformly named, with names such as CLK. While parsing an HDL file, I/O Designer looks forsignals with similar names, and marks them as clock signals.

Clock assignments can be modified later, using the Type column in the Signal List. To mark orunmark a signal as a clock, locate it in the Signal List, click in the Type column, and select theCLOCK or IO option from the list. The clock property of a signal is stored in the database.

I/O Designer helps to avoid error-prone situations, when a normal I/O signal is assigned to aclock pin or vice versa. If an assignment is done without explicitly choosing the signals andpins, then I/O Designer does not assign clock signals to non-clock signals. If the signals and thepins to be assigned are explicitly specified by the selection and the Mark to Assign command,then the clock attributes of signals and pins are automatically changed. The rules of thosechanges are as follows:

• If a clock signal is assigned to a non-clock pin, the signal is changed to non-clock. Theexception is when the pin is actual clock, switched to non-clock in the Type column.Then the pin is switched back to clock.

• If a non-clock signal, being the member of a bus, is assigned to a clock pin, the pin isswitched to non-clock.

• If a non-clock signal, not being the member of a bus, is assigned to a clock pin, thesignal is switched to clock.

Differential Pins SupportI/O Designer checks for assignments to differential pins, i.e., pairs of pins that should beassigned to one signal, representing its positive and negative part, respectively. Differential pinsare by default treated as normal. For any differential pin it is possible to turn on the differentialpins support built in I/O Designer. To do that, switch the type of such pin to DIFF. Then thetype of the second pin of the pair will be switched to DIFF too. Similarly as for clock signals, asignal may be marked as being differential. Such signals are to be assigned to differential pinpairs.

To mark a signal as differential, locate it in the Signals List, click in the Type column, and in thedisplayed list select the DIFF option.

To unmark a signal as differential, locate it in the Signals List, click in the Type column and, inthe displayed list, select the IO option. Then, whenever a signal is assigned to one pin of thepair, the other pin is assigned to the same signal automatically.

You can also choose as the type of a signal DIFFCLOCK, which means that such a signal isboth a clock and a differential signal.



To easily distinguish differential pins, right-click on the Pins List and select Combine AllDifferential Pins. Two-element bus pins are created from all differential pin pairs. If one of apair of differential pins is selected, right-click on the Pins List and select GotoComplementary Differential Pin to locate another one from the pair.

VREFsFor some I/O Standards, a VREF source with a specified value is required. If there’s a pinassigned with such an I/O Standard the VREF value is established for the entire bank.Therefore, I/O Designer will not allow you to make an assignment to a pin that requires adifferent VREF level.

Multi-Gigabit Transceiver PinsI/O Designer supports working with MGT (Multi-Gigabit Transceiver) pins by offering thefollowing features:

• Combining MGT pins

To combine the MGT pins in the Pin List, go to Edit > Buses > Combine All Multi-Gigabit Transceiver Pins or choose the Combine All Multi-Gigabit Transceiver Pinsfrom the Pin List popup menu.

• MGT channel reassignment

I/O Designer allows you to reassign an entire MGT channel within a single operation.To reassign an MGT channel:

a. Drag and drop a single MGT pin onto a pin from a different channel

A smart tag should appear.



Figure 8-1. MGT Channel Reassignment

b. Move the mouse pointer over the smart tag, and click the dropdown button

c. From the dropdown menu, choose the Swap Multi-Gigabit Transceiver channels

Figure 8-2. Swap Multi-Gigabit Transceiver Channels



• PCB Symbols

The Symbol Wizard allows you to generate symbols for MGT channels:

o One common symbol for all MGT channels

o Separate symbol for each MGT channel

o One common symbol for all MGT blocks

o Separate symbol for each MGT block

For more information, refer to “Symbol Wizard” on page 95.

Special Signal/Pin AssignmentsIt is possible to define compatibility between different pin and signal types such that specialassignments may be made.

• An association between signal and pin types is made by defining a signal type and a pintype using the Types Compatibilities dialog.

• Special assignments mode has to be entered while assigning by holding down CTRL +SHIFT while dragging signals to the pins list.

Setting Types Compatibilities1. Select Tools > Types Compatibility. The Types Compatibility dialog is displayed.

2. Right-click in the dialog and select Insert. An entry appears in the list.

3. Double-click in the Signal Type column and select the required signal using the dropdown box.

4. Double-click in the Pin Type column and select the required signal using the drop downbox.

5. Click OK.

The signal/pin association is now enabled and assignments between signals and pins ofthese types can now be made. See “Making Special Assignments” on page 93.



Figure 8-3. Setting Types Compatibility

Making Special AssignmentsOnce Types Compatibilities have been set (see “Setting Types Compatibilities” on page 92)assignments can be made between signals and pins of those types by holding down CTRL +SHIFT whilst dragging signals to pins.

Special FPGA assignments can only be made when assigning signals that have not beenpreviously assigned.

NoteWhen making special assignments in this way, any User-defined Rules which have beencreated are ignored.

Special assignments can be unassigned in the same way as ordinary assignments - it is notnecessary to hold down CTRL + SHIFT to remove assignments.

Tip: This operation could be used after the device is optimized, to allow connection ofunused IO pins to a PCB signal (i.e. GND) such that the pins will be automaticallyconnected to the appropriate net (i.e. GND) on the layout.


Chapter 9Creating, Editing and Updating Symbols and

Schematics

Symbol GenerationOnce a device has been built in a an FPGA database, I/O Designer can generate Functionalblock and PCB symbols to represent it. These symbols can then be exported to the schematic.

Functional Block Symbols (or simply Functional Symbols) are used on functional-levelschematics. Ports in functional blocks are equivalent to signals in an HDL unit (VHDL entity orVerilog module).

PCB symbols are used on board-level schematics, as the representation of a physicaldevice. Ports in PCB symbols are equivalent to pins in the physical device.

There are two methods which can be used to create new symbols in I/O Designer:

• Generate symbols using the Symbol Wizard.

• Build symbols in the Symbol Window using the symbol editing tools. See “Building aNew Symbol” on page 102.

I/O Designer supports heterogeneous symbols, that is, several symbols belonging to one logicalunit. All functional blocks share signals from the database, and the signals are not normallyduplicated on different functional blocks. Each PCB symbol in I/O Designer belongs to afunctional block and should only contain pins that are assigned to signals placed on thatfunctional block. There may be one or more functional blocks, and each of them may containone or more PCB symbols, forming a hierarchy, which is directly represented if symbols withschematics are generated. Each functional block is then generated as a symbol with attachedschematic. The schematic contains all PCB symbols belonging to the functional block, and thewires attached to the PCB symbols pins in the hierarchical schematic represent the pinassignments.

Only one symbol may be edited at a time. To switch between symbols, you can use the list at thetop of the Symbol Window. You could also browse through the available symbols by using thetwo arrow buttons in the bottom-right corner of the Symbol Window.

Symbol WizardThe Symbol Wizard is a full-featured tool provided to assist you in creating and updating bothfunctional block symbols and related PCB symbols.


Creating, Editing and Updating Symbols and SchematicsSymbol Generation

The default binding type for ports created by the Symbol Wizard is Signal. The only exceptionare ports on symbols created using the Split by power banks fracturing scheme, which have thePin binding type.

Creating a New Symbol Using the Symbol Wizard1. Invoke the Symbol Wizard by doing one of the following:

• From the main menu in I/O Designer, select Symbol > Symbol Wizard.

• Click the icon on the toolbar or at the top of the Symbol Window.

2. Select the Design Definition Tool that you want to use with I/O Designer and clickNext.

This step is only necessary the first time the Symbol Wizard is used - the selected toolmay be changed at a later time using Tools > Preferences + Symbol Editor + Export +Export type.

3. On the Basic information page enter information for:

• Symbol name

The naming convention for PCB symbols is <Symbol name>_pcb. Do not usenames with characters following _pcb, as this may cause problems when creatingfunctional symbols split by PCB afterwards. Functional symbols should always benamed differently to PCB symbols (for example, without the _pcb) to avoidoverwriting them.

• DEVICE (BoardStation)

• PCB cell name (DxD)

• PKG_TYPE (DxDesigner scheme)

• Symbol type: whether to create Functional symbols, PCB symbols, or Both

• Use signals: during symbol generation, whether to use All signals or Selected only

• Generate full PCB symbols: If this option is not selected, I/O Designer will createsymbols only for assigned pins. With the option selected I/O Designer creates allPCB symbols regardless of pin assignments

• Choose Create symbols (overwrites existing symbols).

4. Click Next.

5. On the Symbol fracturing page, select whether the symbol should be split. The optionsavailable here depend on whether you have chosen to create Functional Symbol, PCBSymbol, or both. Following is a list of symbol fracturing options with explanations.



NoteIf you are using the Symbol Wizard to update symbols in a database created in an olderversion of I/O Designer (7.4 or earlier) the fracturing scheme may be automaticallydetected, and the fracturing options here are populated with those settings. See “UpdatingSymbols in Databases Created Using Older Versions of I/O Designer” on page 100 formore information.

• For Functional symbols:

o Do not split: create a single functional symbol

o Split functional symbols: split functional symbols using the options from theFracturing scheme section

• For PCB symbols:

o Do not split: create a single PCB symbol

o Split by existing functional symbols only: create one PCB symbol for eachexisting functional symbol

o Split using fine-grained scheme: This option enables you to specify moredetailed split method, using the options described below

• For Both (Functional and PCB symbols):

o Do not split: create a single functional and a single PCB symbol

o Split only PCB symbols: This option enables you to specify more detailed splitmethod for PCB symbols, using the options described below

o Split functional and PCB symbols: This option enables you to specify moredetailed split method for both functional and PCB symbols, using the optionsdescribed below.

6. Select the Fracturing Scheme:

• Split by power banks: create separate symbols for groups of pins that belong todifferent power banks

• Separate data and control signals: create separate symbols for buses and scalarsignals

• Separate signals connected to different components: create separate symbol forgroups of signals that belong to different HDL units

7. Set Limits:

• Always split symbols larger than page size: This option applies to functional andPCB symbols



Buses are not split between symbols even if the resulting symbol is larger than thepage size.

• Always split symbols with more pins than <number>: This option applies tofunctional and PCB symbols

8. Click Next.

9. Set additional Symbol Fracturing options:

• CONFIG and JTAG Pins

o Do not use CONFIG and JTAG pins. Do not create separate symbols forCONFIG and JTAG pins. This option applies to PCB symbols only.

o Create separate symbol for CONFIG and JTAG pins. This option applies to PCBsymbols only.

o Add CONFIG and JTAG pins to symbols. This option applies to PCB symbolsonly.

• Multi-Gigabit Transceiver Pins

o Do not use Multi-Gigabit Transceiver channels or blocks

o Create separate symbols for each Multi-Gigabit Transceiver channel

o Create separate symbol for all Multi-Gigabit Transceiver channels

o Create separate symbols for each Multi-Gigabit Transceiver block

o Create separate symbol for all Multi-Gigabit Transceiver blocks

• Powers and Grounds

o Create Core power and ground symbol set

Split power and ground pins by PCB symbols: this option creates a separatesymbol for each group of power and ground pins that have the same PCB signalassigned. This will create symbols namedSymbolName_powerpins_bank_voltage.

o Create Bank power symbol set

a. Add Bank power pins to PCB symbols. This option applies to PCB symbolsonly.

b. Split power pins by PCB symbols: creates separate symbols for each groupof power and ground pins that belong to the same power bank.

• Add VREF pins if required by I/O Standard: For some I/O Standards, a VREFsource with a specified value is required. If the option is selected, I/O Designer willadd the VREF ports to the generated power symbols.



• Add VRP/VRN pins for DCI I/O Standard: Add VRP/VRN ports to the generatedpower symbols for pins with DCI I/O Standard.

10. Determine symbol appearance settings:

• Symbol name

• Symbol description

• Port length,

• Port spacing

• Functional symbol background

• PCB symbol background

• Pin positions for power pins, ground pins and clock pins

11. Port Labels page allows you to customize labels for ports in functional and PCBsymbols. Each port label’s caption can be one of the following:

• Signal Name

• Pin Name

• Pin Number

• Pin Function, or

• Custom Label

You can also specify one additional port label as well as its relative position. Labelsof the following symbols may be customized:

o Functional symbol

o PCB symbol

o Power and ground symbol,

o CONFIG and JTAG symbol

12. Divide Ports page allows you to add unplaced signals and pins to symbols (existing orcreated by the wizard). The page provides an easy way to handle signals and pins thathave not been assigned and therefore are not part of any symbol.

13. Click Finish.

The symbols are created and appear in the Symbol Window.



Updating Symbols Using the Symbol WizardOnce symbols have been created, the Symbol Wizard can be used to update them. In this case, itis not necessary to re-enter the information for symbol fracturing, appearance or port labels; I/ODesigner will use the settings entered upon symbol creation.

1. Invoke the Symbol Wizard by doing one of the following:

• From the main menu in I/O Designer, select Symbol > Symbol Wizard.

• Click the button at the top of the Symbol Window.

2. The wizard opens on the Basic information page. Select Update Symbols and clickNext and Finish.

Updating Symbols in Databases Created Using Older Versions of I/ODesigner

It is possible to work with databases that were created using older versions of I/O Designer (7.4or earlier), which may have generated symbols. In I/O Designer 8.0, the first time the SymbolWizard is used to update these symbols, I/O Designer attempts to recognize the existing symbolfracture scheme based on the symbol names that exist in the database. After the database issaved, the fracture scheme set is saved to file.

Power Symbol GenerationFPGA power can be managed as implicit connections in the PDB or explicitly in the generatedsymbols.

Alist of default power signal name assignments can be viewed under Tools > Preferences +Symbol Editor + Symbol generation.

If an I/O Standard is not selected with a specific voltage (e.g. 2.5, 3.3, 1.8 volts) the top windowon the dialog is ignored and the power signal names shown in the bottom window are used. If anI/O Standard is selected (e.g. LVCDI_33), I/O Designer will detect a 3.3 volt signal and applythe "Default PCB Signal" in the top window named "v_3_3". I/O Designer will automaticallyconfigure the Bank where this pin resides.

Implicit Power ConnectionsI/O Designer gives you the option to use implicit power connections. In this approach there isno need for power symbols. All power connections are made through the use of properties.

To use implicit power connections, during symbol creation, select the Do not use powers andgrounds option on the on the Symbol Wizard so that no power symbols are created. If there areno power symbols, I/O Designer will attach the necessary properties to the component. Powerconnections can be verified in Expedition using the Parts Editor.



Explicit Power Connection SymbolsExplicit power management requires the generation of power symbols. By selecting powersymbol creation in the Symbol Wizard, I/O Designer will automatically create new powersignals in the Signals List. Those new power signals will be automatically assigned to thecorrect power pins in the Pins List.

Power signals are NOT part of the functional block that is created as part of the Symbol Wizardprocess. But power symbols are exported as part of the Exporting Symbols and Schematics step.Power symbols must be placed and the proper power and ground signals must be manuallyattached.

I/O Designer will automatically create new power signals based on the I/O Standard assignmentand makes the appropriate assignments for the bank VCCO pins. In Figure 9-1, the P_DATAbus was assigned a LVCMOS25 standard which requires a 2.5V VCCO supply. I/O Designerautomatically creates the signal during symbol generation and makes the assignments.

Figure 9-1. Power Signal Generation Based on I/O Standard Assignment



Configuration Symbol GenerationThe Symbol Wizard may be used to create configuration symbols such as JTAG by selectingthe Create separate symbol for CONFIG and JTAG pins option. This will create symbolsfor all the pins with type CONFIG.

If more control is required, CONFIG signals can be added and the symbol created manually. Todo this, use the following steps:

1. After the JTAG signals are added to the FPGA database assign them to the JTAG pinsby dragging the JTAG pin to the JTAG signal.

2. Create a new empty symbol by selecting Symbol > New or by clicking the icon onthe toolbar or on the Symbol Window.

3. Manually create the symbol by dragging the signals from the Signals List to the newsymbol in the Symbol Window. The result is a symbol specifically for JTAG purposes.

Figure 9-2. Manually Created JTAG Symbol

The JTAG symbol is typically not part of the hierarchical block. Make sure the SymbolProperties do not list a functional block attribute.

This symbol can now be exported and placed in the schematic. See “Exporting Symbols andSchematics” on page 110.

Building a New SymbolI/O Designer incorporates an advanced built-in symbol editor which can be used to create andedit PCB-level symbols or functional-level block symbols.

To create a new symbol in I/O Designer:


• Select Symbol > New



• Click the button on the Zoom Toolbar.

2. Enter a name for the symbol in the Symbol name: field.

3. To create a PCB Symbol, check the PCB symbol option. To create a functional blocksymbol, uncheck this option.

If this option is checked, the list of all existing functional blocks in the Functionalblock: field is activated.

4. For PCB symbols, select the functional block to which the new PCB symbol will belong,in the Functional block: field.

5. Select a background for the symbol from the list of those available n the Symbolbackground: field.

6. Click OK.

The new symbol is displayed in the Symbol Window.

7. Add ports to the symbol by dragging and dropping signals and pins from the Signals Listand Pins List to the symbol in the Symbol Window.

You can create several ports by selecting a group of ports / signals and dragging thegroup to the symbol. Ports created by dragging signals have their binding type set toSignal. Ports created by dragging pins have their binding type set to Pin.

NoteIf you drag a bus to a PCB symbol, bus members are added as separate ports, since inmost cases you do not want buses on PCB symbols. It is possible to override this feature -just drag a bus to a PCB symbol with the CTRL key down. Then it will be added as onebus port.

Port Types and ShapesI/O Designer provides support for several port types. Besides the default port type, it is possibleto choose from ANALOG, BI, IN, OCL, OEM, OUT, TRI, TERMINAL, POWER andGROUND. You can change the type of a port in the Properties Window.

By default, port types are visualized by means of different port shapes. If you prefer straightlines without any decorations for ports of all types, uncheck the View > Symbol > Show PortType option.

Further customization of the appearance of ports is possible. All available port types are listedunder Tools > Preferences > Port types together with shapes assigned to them. There areseveral shapes to choose from. Additional, user-defined shapes may be created as well.

To create a new port shape, open an existing one, modify it, and save it under a new name. Toopen an existing shape, use File > Open. In the Files of type list, switch from Database File to



Port Shape File. Then select a shape file (shape files are stored in the shapes subdirectory of theI/O Designer installation directory). The shape graphics will be displayed in the SymbolWindow, where it may be modified. To save the shape under a different name, use the Save Asoption in the usual way. The new shape will then become available on the list of shapes on thePort Types page in the Preferences dialog.

Drawing ToolsUse the drawing tools to add Arcs, Bezier Curves, Circles, Lines, Rectangles or text to asymbol. The following sections describe all operations specific to these modes.

Arcs

To draw an arc, use the button on the toolbar. Then click the position where the arc shouldbegin, and drag to its desired end.

Additional features available while drawing an arc are:

• Orientation of the arc may be toggled with the Tab key.

• Its middle point may be anchored with the Space key.

• If the arcs middle point is anchored, it may be unanchored with the Backspace key.

Bezier Curves

To draw a Bezier curve, use the button on the toolbar. Then click the position where theBezier curve should begin, and drag to its desired endpoint.

Additional features available while drawing a Bezier curve are:

• Press the Spacebar while drawing to add a new segment to the line. Added segmentsmay be removed with the Backspace key.

• Press, the CTRL key while editing (dragging one of the handles) to add a new segment.

• Press SHIFT while dragging the middle handle to split the line into two parts.

• Press the CTRL key while editing a control handle to cause the opposite control handleto be moved too. If one of the control handles is being dragged (a control handle is ahandle at the end of the dotted lines). The SHIFT key presents the same feature, but inaddition, the opposite handle mirrors the movements of the dragged one.

Circles

To draw a circle, use the button on the toolbar. Then click on the position where one of thecorners of circles bounding rectangle should lie, and drag to the opposite corner.

Additional features available during circle drawing are:



• Hold down SHIFT while drawing to force an ellipse instead of an arbitrary circle.

Lines

To draw a line or polyline, use the button on the toolbar. Then click the position where theline should begin, and drag to its desired end.

Additional features available during line drawing are:

• Press the Spacebar while drawing to add a new segment to the line. Added segmentsmay be removed with the Backspace key.

• Press CTRL while editing (dragging one of the handles) to add a new segment.

• Press SHIFT while dragging the middle handle to split the line into two parts.

Rectangles

To draw a rectangle, use the button on the toolbar. Then click the position where one of thecorners of rectangle should lie, and drag to the opposite corner.

Additional features available during rectangle drawing are:

• Hold down SHIFT while drawing to force a square instead of an arbitrary rectangle.

Text

To add text to a symbol, use the button on the toolbar, then click the position where thetext should begin and start typing. The text cursor (caret) is displayed, and normal editingoperations, limited to a single line, may be performed. Editing is completed after the Enter keyhas been pressed. The Esc key may be used to cancel editing without adding the text to thesymbol.

Snap to Grid

While drawing and editing symbols, Snap to Grid is enabled/disabled under Tools >Preferences + Symbol Editor. If the Snap to Grid option is selected, all drawing operationsobey this setting. However, snapping to grid may be temporarily disabled with the ALT key.For instance, to start drawing a line outside grid, it is not necessary to disable snapping to grid inthe Preferences, but it is enough to hold the ALT key down while drawing.

Adding an Image to a SymbolIn the DxDesigner flows, you can add an image to each symbol by associating it with a graphicsfile. Graphics files are stored in the /OLE directory within the project. To do this, either:

• Select Symbol > Add Picture



or

• Right-click in the Symbol Window and select Add Picture from the pop-up menu.

You can then browse for a graphics file, which can be in the format .bmp or .jpg.

NoteAdding an image file to a symbol is available in the DxDesigner flow only.

Editing Symbol ElementsTo select elements in a symbol, enable Select Mode by clicking the icon in the toolbar.Select an element by clicking on it. To add an element to the existing selection, CTRL+click onthe element. More than one element may be selected together by dragging. While dragging, youwill see the selection rectangle displayed. All elements within the rectangle are selected.

To zoom in on an area, drag the mouse with the SHIFT key down. The rectangle is displayedwhen you drag. After dragging the selected rectangle will be zoomed to fill the entire window.See “Symbol Window Zoom Controls” on page 30 for more information on zoom controls.

The Symbol Window supports the usual clipboard operations: Cut, Copy, and Paste. Theoptions are available in the View menu, in the toolbar, and in the pop-up menu.

In Select Mode, the selected elements can be duplicated by dragging them with the CTRL keyheld down. The selected elements remain unmoved, and the copy of the selection may bedragged to the desired position.

To delete symbol elements, select them, right-click and select Delete. This command is alsoavailable in the Edit menu.

Moving and Changing ElementsTo move symbol elements, select them, and drag them to the desired position. To resize asymbol element, select it, and make sure that it is the only selected element. A resizable elementwill now display handles, that is, small squares. Dragging handles will resize or reshape thesymbol element.

To edit graphical text, use the Edit command located in the selected text pop-up menu. I/ODesigner will switch to text-editing mode. The text cursor is displayed, and usual operations forediting a single line of text are available. The Enter key completes editing, while Esc cancels allchanges.



Changing Symbol BackgroundsI/O Designer supports different symbol backgrounds. In addition to the default rectangle, youcan choose among several other backgrounds, such as mux. To change the background, open theProperties window for the symbol, and change the Background property there.

Backgrounds may be customized. To edit the background of the current symbol, check theSymbol > Edit Background option. All symbol elements, except for the background, arehidden. In this mode you can use any graphical elements to change the appearance of thebackground. To switch back to normal symbol editing, uncheck the Edit Background option.

You can save the changed background in order to use it in other symbols. Use the commandSymbol > Export Background. This option displays the standard Save dialog, in which youcan choose the background file name. Backgrounds should be saved to the shapes subdirectoryof the I/O Designer installation directory, since in theProperties Window only backgroundsfound in this subdirectory are accessible.

You can also edit a background in stand-alone mode. To open an existing background, use File> Open. In the Files of type list switch from Database File to Background File. Then select abackground file (background files are stored in the shapes subdirectory of the I/O Designerinstallation directory). The background graphics will be displayed in the Symbol Window,where it may be modified. To save the background, use the Save or Save As option in the usualway.

Printing SymbolsI/O Designer allows printing symbols created and edited in the program. To print the currentsymbol, use the File > Print > Symbol command. This displays your computer’s standard Printdialog.

Deleting SymbolsTo delete the symbol displayed in the Symbol Window, use the Symbol > Delete command. Ifyou want to delete all symbols, then use the Symbol > Delete All Symbols command.

Symbol Editor PreferencesSelect Tools > Preferences + Symbol Editor to define properties for symbols created in I/ODesigner as well as the page size and orientation for building schematics.

The Ports section defines pin length as a function of the units defined in the General section.Also it defines the spacing between pins as a function of grid steps. The default grid step is setin the lower part of the form. This should be set to the same grid spacing as the schematic tool.

The Symbol Editor page allows you to alter the following Symbol Window options:



• Show or hide rulers.

• Show or hide the crosshair cursor.

• Default unit of measurement. Possible values are: 0.01mm, 0.05mm, 0.1mm, 0.5mm,1.0mm or 0.005inch, 0.01inch, 0.05inch, 0.1inch.

• Page size. Available page sizes are: A0, A1, A2, A3, A4, A, B, C, D, E.

• Page orientation; portrait or landscape.

• Port length.

• Spacing between ports

• Label format for ports in functional symbols and pins in PCB symbols (Signal Name,Pin Name, Pin Number or Pin Function).

• Show or hide grid.

• Snap Symbol Window elements to grid.

• Grid Step.

Port Types

The Tools > Preferences + Symbol Editor + Port Types page allows you to alter thefollowing options:

• Show or hide port type on a symbol in the Symbol Window.

• Set port size of a symbol in the Symbol Window.

• Associate port type with a shape.

o Available built-in port types include: TERMINAL, GROUND, POWER, TRI,OEM, OCL, ANALOG, BI, OUT and IN.

o Available built-in shapes include: ANALOG, ARROW, BI, CLK, DIAMOND, IN,INV, OCL, OEM, OUT and TRI.

Symbol Generation Settings

The Tools > Preferences + Symbol Editor + Symbol generation page contains settings forpower and ground pins on exported symbols.

The PCB Signals for VREF/VCCIO Pins list contains default PCB signal mappings forVREF/VCCIO pins. The value for a given VREF/VCCIO pin from the list is used only if the pindoes not have a manually assigned PCB Signal.



The remaining power and ground pins list contains default PCB signal mappings for power andground pins other than VREF/VCCIO. The automatically connect remaining power and groundpins option allows you to control whether I/O Designer should generate nets for the selectedpins.

Symbol Export Settings

The Tools > Preferences + Symbol Editor + Export page contains settings for symbol export

• Run viewer after export: select whether to run a viewer after exporting a symbol.

• Export graphical attributes: This option allows you to export graphical attributes, suchas colors, fonts and graphics.

• Create multipage schematic: This option allows you to split generated schematics intomultiple pages. When this option is enabled, schematics that do not fit into the chosenpage size will be split.

• Add dangling nets: A generated schematic contains nets that connect PCB symbol portswith functional block ports. This option tells I/O Designer to generate nets for ports thatdo not exist in the functional block.

• Export port direction shape: This options adds graphical elements representing porttypes to the exported file.

• Export swap groups: Export swap group information. Option is enabled by default.

• (DxDesigner only) Automatically add page border to the generated schematic: Thispreference setting group allows you to add a page border to the DxDesigner schematic.

Creating Generic Symbols for Use With I/O DesignerGeneric symbols are symbols for devices that are stored in the Central Library whose pinnames, pin numbers, fracturing scheme and symbol name do not change from one design toanother. PCB based pin swapping is not used in this flow because FPGA pin swapping rules aredesign as well as device based. The generic symbols in the Central Library are placed directlyinto the schematic and are not touched by I/O Designer.

Part information for the device needs to be created. I/O Designer can produce the Part HKP filefor the device which may be imported into the Central Library. Right-click in the ProjectWindow and select Project Properties. Ensure that Export Part Data is selected and chooseExpedition Library Services ASCII format (HKP).

When using generic symbols, when pin assignment changes are made in I/O Designer they aremigrated to the schematic using Export > Schematic Update. This implements the pinassignments made in I/O Designer by adding net name stubs to the symbol on the schematic.The symbol itself is not modified using this process.


Creating, Editing and Updating Symbols and SchematicsExporting Symbols and Schematics

Generic Symbols are PCB symbols and not functional blocks. The reason for this is that I/ODesigner reads the FPGA vendor delivered libraries and interprets the number of pins, pinnumbers, and pin functions for each of the devices in the library. I/O Designer willautomatically create basic symbols with appropriate fractures and create the associated partsdatabase (PDB) library files for these symbols with all the appropriate pin mapping information.

The initial settings for the symbol editor may be configured by editing Symbol EditorPreferences under Tools > Preferences.

The label for functional and PCB signals should be set to "Pin Function" for creating genericsymbols.

Exporting Symbols and SchematicsI/O Designer allows you to generate symbol and schematics data for exchange with externaldesign definition tools, such as DxDesigner.

When exporting to DxDesigner and Design Architect, I/O Designer puts I/O Designer symbolson separate sheets called a reserved sheet that should not be modified. Reserved sheets containonly I/O Designer symbols and nets. Connection to the rest of the schematics is guaranteed bynet names. During schematics export, sheets with the IOD_RESERVED_SHEET attribute areautomatically overwritten. In the remaining sheets, symbols with the IOD_GENERATEDattribute are moved to a new Reserved Sheet.

All sheets are placed into separate blocks in the schematic tool. When you add a sheet inside ablock generated by I/O Designer, then the sheet will not have the IOD_RESERVED_SHEETattribute. I/O Designer protects against deleting of this additional sheet during the symbolupdate process.

Hierarchical Schematic GenerationA hierarchical schematic is generated using the following generation methods:

• Export > Schematic and Symbols

Generates a functional block along with the underlying schematics containing PCBsymbols for the current database.

• Export > Schematic and Symbols for all Components

Generates functional block along with the underlying schematics containing PCBsymbols for all component databases in the design.

I/O Designer will automatically export the symbol set along with the necessary number ofschematic pages. Upon export completion, the new schematic pages will appear in DxDesignerunder Blocks. The hierarchical block can be placed by selecting the local "Symbols" and then"local" for the exported functional block. Place the functional block with "Added Nets" and

Creating, Editing and Updating Symbols and SchematicsExporting Symbols and Schematics


"Net Names" so the functional block is fully wired. For more information see “Placing Symbolsin a DxDesigner Schematic” on page 112.

The underlying schematic contains the PCB symbols and the necessary wires and ports to makethe connection to the Functional block.

NoteWhen exporting schematics from I/O Designer, if the following message is reported:

“iCDB Error: Running server for the project has changed (Could not create new session- project GUID mismatch) I/O Designer is not connected to iCDB database”

This problem may be connected with copying a project while it is already opened inDxDesigner. Close DxDesigner to clear the problem.

Flat Schematic GenerationA flat schematic is created when only the symbols are exported from I/O Designer. Thefollowing generation methods are available:

• Export > All Symbols

Generates all symbols without an underlying schematic.

• Export > Current Symbol Only

Generates a single symbol without an underlying schematic.

This option can be used to export the current symbol to the central library, or to create afunctional block early in the PCB design process where a local parts database is not yetavailable.

The symbols can then be placed in the schematic where desired. Turn on the "Add Nets" and"Add Net Name" option so the placed symbols are fully wired. For this DxDesigner feature towork correctly, the symbol pin label must be the name of the wire. This is a "custom" symbolfor this implementation of the component.

After pin changes in I/O Designer, only the symbols need to be updated in DxDesigner.

NOTE: this assumes that the symbols are not changed (e.g. a signal is added or deleted fromsymbols).

Once symbols have been exported, they are available in the local symbols partition, ready to beplaced into the schematic. See “Placing Symbols in a DxDesigner Schematic” on page 112.


Creating, Editing and Updating Symbols and SchematicsPlacing Symbols in a DxDesigner Schematic

Schematic Scope SettingsI/O Designer generates schematics with the following scope settings.

For PCB nets, the scope is set to global.

For IO nets, the scope is set to local.

The scope is preserved by I/O Designer so that the scope of a net on the schematic can bechanged and the tool will not overwrite it.

Placing Symbols in a DxDesigner SchematicUse the following procedure to place symbols created in I/O Designer into a DxDesignerschematic, package the design and generate reference Designators for those symbols.

1. In DxDesigner, activate the Symbols Window and choose the Symbol View tab.Symbols can be selected from the local symbols partition. Symbols from the CentralLibrary can be selected from the Part View tab.

2. Click Place Symbol to add the selected symbol to the schematic.



Figure 9-3. Placing Symbols in DxDesigner

3. Once the symbol has been placed on the schematic it can be wired to the desired nets. Itis recommended that symbols are wired using the "Net Stub" technique. This techniqueis indicated by placing only a small wire segment from the pins with the appropriate NetLabel text property on the wire segment.



Figure 9-4. Wiring a Device in DxDesigner Using the “Net Stub” Technique

4. In DxDesigner, click the Packager icon on the toolbar to run the Packager on theschematic. This updates part information from the Central Library to the local dabdatabase and will assign a Reference Designator to the newly placed symbol(s).

Creating, Editing and Updating Symbols and SchematicsImporting Symbols and Schematics


Figure 9-5. Running Packager in DxDesigner

In DxDesigner, the Reference Designator allocated to the symbol by the packager can bedetermined by double-clicking on the symbol to bring up the Properties Window.

Importing Symbols and SchematicsI/O Designer can import symbols and schematics from external files. This allows you to modifysymbols and schematics outside I/O Designer using an external tool and then incorporate thesechanges into the symbol in I/O Designer. The process of updating I/O Designer symbols andschematics based on external tool information is called back annotation. When you make anychanges to the symbol and switch back to I/O Designer, the tool will inform you that the symbolneeds to be updated by showing a yellow update indicator in the bottom-right corner. If youdouble-click the indicator, the Synchronization Wizard will prompt you to update symbols.

Similarly, if you make changes in the tool that require running the export process, I/O Designerwill notify you using the yellow synchronization indicator.


Creating, Editing and Updating Symbols and SchematicsSchematic Update

Figure 9-6. Yellow Synchronization Indicator

Schematic UpdateSchematic update is used to update pin assignment changes made in I/O Designer to theDxDesigner schematic database by selecting Export > Schematic Update...

This can be used as an alternative to exporting symbols and/or schematics using Export >Schematic and Symbols (see “Exporting Symbols and Schematics” on page 110). Usingschematic update, any symbols which already exist on the schematic are preserved, they are notreplaced with I/O Designer-created symbols.

Using this flow, the pin numbers of the symbols are not swapped, as is done during typical backannotation from Expedition PCB. Instead, the net names and net stubs that have been placed onthe schematic are swapped.

This function may be used with symbols developed in I/O Designer as well as with symbols thatwere developed in the Central Library.

Prerequisites

To use this functionality I/O Designer must be initialized and the FPGA database must beloaded with the required HDL and/or pin report file for the specific device. Do the following toverify that these conditions exist:

• In the FPGA database, select File > Database Settings to display the Database SettingsDialog, and click the I/O Signal List tab. Ensure that the path to the requiredHDL/Netlist file is set correctly.

• On the Database Settings Dialog, click the FPGA Flow tab. Ensure that the path to therequired Pin report file is set correctly.

Procedure

Use the following steps to update pin assignment changes made in I/O Designer to theDxDesigner schematic, using schematic update:



1. Using the PCB Design Wizard, signals and assignments can be imported into I/ODesigner from the schematic with the option to Import signals and assignments only.This means that the symbol will not be imported.

2. Use I/O Designer to perform unraveling and update pin assignments.

3. Select Export > Schematic Update...

Symbols generated and exported from I/O Designer will be placed in the localDxDesigner database (iCDB) ready to be used. See “Placing Symbols in a DxDesignerSchematic” on page 112.

4. After placing and wiring the symbol(s), run Packager in DxDesigner to generateReference Designators for each symbol.

5. In the I/O Designer FPGA database for the device, select File > Database Settings todisplay the Database Settings Dialog, click the PCB Flow tab and enter the ReferenceDesignator value in the Ref Des: field.

6. If layout information is required to be presented in I/O Designer, run ForwardAnnotation and Back Annotation in Expedition PCB.

7. Synchronize the FPGA database in I/O Designer using the Synchronization Wizard, byselecting Import > Synchronize.

If layout information is required to be presented in I/O Designer, ensure that theLayoutDB.lyt file is selected for synchronization.

8. Once the data has been loaded, unraveling may be performed in I/O Designer. For moreinformation see “Unravel Nets” on page 123.

9. After optimization in I/O Designer, with the schematic still open in DxDesigner, runschematic update a second time to update the DxDesigner schematic with the newoptimized results. Select Export > Schematic Update... and click Update Schematic.

Example 9-1. Using Central Library Symbols with Schematic Update

You may want to use a device that exists in a Central Library and has a generic symbol set. Thismeans that the pin labels are from the FPGA vendors, and in the case of Xilinx have the form ofIOB_X0Y123. A custom symbol will use the design signal name as the symbol pin label (e.g.Data_Strobe).

Suppose a device database has the signals assigned for a component in the Central Library. InDxDesigner the symbol from the Central Library is placed and the design is packaged (see“Placing Symbols in a DxDesigner Schematic” on page 112).

1. In the device database in I/O Designer, select File > Database Settings and enter theReference Designator generated in DxDesigner into the Ref Des field on the PCB Flowtab.



2. Select Export > Schematic Update... and click Update Schematic.

The Central Library symbol / component is untouched and fully preserved. Only thewire stubs are added to the schematic.


Chapter 10Optimizing the I/O Assignments

Layout DatabaseThe layout database is an I/O optimization environment that allows you to optimize the I/Oassignments based on a component orientation. Data is imported into the layout database fromthe schematic and the PCB layout tool or simply created from a netlist and I/O Designercomponents. The editor within the database allows devices to be moved and new solutionscenarios to be created. The best results can then be selected and propagated to the FPGAdatabase.

NoteLayout database functionality is not available in the WG flow.

In order to work with a layout, add a layout database to a design within the project by selectingFile > Add to Design > New Layout. You can only have one layout database per design.

When working within a layout database, the Layout Window, Pins List, Connectivity ListWindow and Layout Scenarios Window are used to optimize I/O assignments betweencomponents.

Note how the terms I/O Planning and I/O Optimization are associated to pre and post layout,respectively.

I/O PlanningComponents and netlines can be loaded directly from the design entry tool for "I/O Planning",which allows you to define critical component orientation and assign I/O based on componentorientation. The components are extracted from the schematic and do not require a PCBplacement. I/O Planning will significantly shorten the design cycle and remove the need formultiple iterations.

The purpose of this activity is to orient critical components and optimize the I/O based on thecomponent orientation. You are NOT creating a PCB layout at this stage.


Optimizing the I/O AssignmentsI/O Planning

Synchronizing the Layout Database with a SchematicUse the following procedure to import a layout from a schematic:

Prerequisite

After exporting the FPGA from I/O Designer to the schematic; run the packager in DxDesignerso that reference designators are assigned. You can verify this in I/O Designer by selectingDatabase Settings > PCB Flow tab.

1. Select File > Database Settings and click the Netlist source tab.

2. Select Schematic as the Netlist source and click OK.

3. In I/O Designer, select Import > Schematic to populate the layout database from theschematic.

The Layout Window shows the netlines in the design and the Layout Scenarios Windowopens with an "Initial Scenario". When importing from the schematic, all thecomponents are stacked at the Layout Editor origin as shown in Figure 10-1.

Figure 10-1. Components Imported Into Layout

In I/O Designer, the layout database can be populated from the PCB tool using Import> Layout. If this option is used, then the correct component orientation will be shown inthe Layout Window. I/O Optimization is defined as utilizing the actual layout data tooptimize the I/O. The step requires a PCB layout and is described in “I/O Optimization”on page 128.

4. Select Tools > Layout Setup and click the IOD components tab. The devices availablefor I/O optimization are listed here.



Visibility of each component can be turned off and on using the Visibility control, ormirrored by checking the Mirror control.

5. (Optional Step) You can filter the components in the schematic, such that only those youwant to use in the I/O Designer optimization process are imported. Select File >Database Settings and click the Component Filter tab. Use regular expressions tospecify the reference designators of the unwanted components.

Components can now be moved around freely inside the Layout Window. At this stage,clearances are not important; the orientation of the parts is what matters. Next, optimization canbe performed using Unravel Nets and different scenarios can be created until the best solution isfound and applied (see “Creating and Applying a Layout Scenario” on page 126).

Layout WindowThe Layout Window provides a graphical representation of the package or board componentlayout. Connectivity between components is shown using a logical representation ofconnectivity known as “rubber bands”. Rubber bands only represent the I/O connectivitybetween the components on the layout, not their physical implementation.

Figure 10-2. Layout Window



Select Pin/Net ModeThis mode is used to select multiple pins and nets in the Layout Window in order to runappropriate actions on the whole selection. To activate this mode, click the icon in thetoolbar. Click the required component and then:

• Use the left mouse button to select individual pins and nets.

• CTRL + click to select multiple pins and nets.

• Drag a rectangle around the required pins and nets.

Show TracesThis mode allows you to show or hide physical traces between objects imported directly fromthe PCB layout. To activate this mode, click the icon in the toolbar.

Figure 10-3. Show/Hide Traces

Show NetlinesThis mode allows you to show or hide netlines. Netlines order is imported from PCB layout.MST and custom orders are indicated by different net colors. To activate this mode, click the

icon in the toolbar.

Connectivity List WindowDisplays connectivity between components in a board or package layout when working within aLayout Database.

The Connectivity List Window may be closed and opened at any time; to do this, either selectthe menu item View > Windows > Connectivity List, or click the button on the viewtoolbar.



The Connectivity List contains the following information for each net or pin on the device:

When a net is selected in the Connectivity List Window, it is automatically highlighted in theLayout Window.

Adjusting Component OrientationIn the Layout Window, you can move components around, rotate them and mirror them in orderto achieve the best orientation for the design.

To move a component, select it and drag it to a different position.

To rotate a component, select it, right-click and select Rotate 90, Rotate 180 or Rotate 270.

To mirror a component, select it, right-click and select Horizontal Mirror.

Once you begin moving components, a new layout scenario is created and the changes youmake are listed in the Layout Scenarios Window.

Unravel NetsThe Unravel Nets functionality in I/O Designer optimizes signal to pin assignments byshortening nets and eliminating crossovers on the PCB or layout. This allows much moreefficient routing of nets in the physical design tool. Use the following procedure to performunraveling:

1. In the Layout Window, select the component or nets, right-click and select UnravelNets.

2. On the Unravel Nets Dialog, set the Optimize slider to the required position. Movingthe slider to the left means that the Unravel algorithm will focus on finding the shortestpossible length of nets. Moving the slider to the right sets the algorithm to focus more onthe elimination of crossed over nets.

3. Check Unravel scalars and buses concurrently in order to use all signals selected forunravel as one package of nets and pins (optional).

Table 10-1. Connectivity List Window Contents

Column Description

Net/Signal Name Displays the net name and all pin names connectedto the net.

Component Displays the component Reference Designator towhich the pin belongs.

Pin Number Displays the number of the pin connected to the net.



When this option is checked, all selected for unravel signals will be used as one packageof nets and pins such that a scalar net can be swapped with one of the bits of a bus. Whenthis option is unchecked, then bus members are unraveled separately within the bus andscalar nets are unraveled with other scalar nets.

4. Check Use unused pins to include unoccupied pins in the unravelling process(optional).

When this option is unchecked then the unravel process uses only the currently occupiedpins. So its outcome is a set of swaps made on signals. When this option is checked thenthe algorithm will use not only currently used pins but also those unassigned, givingmuch more flexibility to find optimal results.

5. Click Unravel to begin the unraveling process with the current options.

Any user-defined rules set for the device will be taken into account during unraveling.All signals marked as Locked in the Signals List will not be moved during unravelprocess

The Cancel button can be selected at any time during the process to stop unraveling.

6. Click Close to save the current unravel settings and exit the dialog.

Figure 10-4 and Figure 10-5 show examples of nets before and after unraveling.



Figure 10-4. FPGA Nets Prior to Unraveling

Figure 10-5. FPGA Nets After Unraveling



Layout Scenarios WindowA scenario is a group of component placement commands and signal assignment commandswithin a layout database. A number of different scenarios can be created, and you can switchbetween them to explore different variants. Each scenario is independent and does not takeeffect to the design until it is applied.

Scenarios allow the exploration of different layout solutions which may consist of differentcomponent orientations (e.g. connector located on the left or right side of the device) anddifferent applications of unraveling. The I/O assignment can be optimized based on differentcomponent orientations and have the best solution propagated to the PCB layout process.

The first entry in the Layout Scenario window is the initial scenario - the initial layout of thedesign as it has been imported. When changes are made to component placement or signalassignment in a layout database, a new scenario is created, and will appear in the LayoutScenarios window. A green arrow next to the scenario name indicates the currently activescenario.

Creating and Applying a Layout ScenarioUse the following procedure to work with a layout, create and apply layout scenarios:

1. Manipulate the components in the layout. A new scenario will appear in the LayoutScenarios Window, named Scenario 1. The changes made are listed in the Changescolumn.

2. Select Initial Scenario in the Layout Scenarios Window, and create another scenario inthe same way. This scenario will be named Scenario 2.

You now have an initial scenario, which has the initial component placements and signalassignments, and 2 scenarios, each with different modifications.

3. To switch between scenarios in the Layout Window, right-click on a scenario and selectActivate.

This will not apply the scenario, it just allows you to view and manipulate it. You cancontinue to make changes to each scenario.

4. Upon creation of a suitable scenario, right-click on the scenario in the Layout ScenariosWindow and select Apply Scenario.

The changes recorded in the scenario are applied to the layout, and the FPGA databasefor the device is updated with the new pin assignments.

Multi-chip PCB OptimizationUse the following procedure to select devices for PCB layout optimization.



NoteIf you do not hold a multi-device license, then when applying optimization scenarios in alayout database, you can work with only one device at a time.

No Multi-chip License Held

1. In the layout database, select Tools > Layout Setup and click the IOD components tab.

2. Select the device you want to optimize and click OK.

3. Manipulate the components within the layout and perform unraveling on the selecteddevice.

The device selection cannot be changed until a scenario is applied.

4. Once you are satisfied with the component orientation and the I/O assignments on theselected device, apply the scenario. See “Creating and Applying a Layout Scenario” onpage 126 for more information.

The FPGA database will be updated with the new pin assignments. After the scenario isapplied, the layout editor is returned to the "Initial Scenario". The Initial Scenario doesNOT reflect the changes on the previously selected device. All other scenarios aredeleted.

5. Go to the FPGA database and create or update its symbols. See “Creating, Editing andUpdating Symbols and Schematics” on page 95 for more information.

6. Export symbols and schematics for the device by selecting Export > Schematic andSymbols, and forward annotate the changes to the PCB tool.

You can now import the PCB layout into the layout database in order to optimizeanother device with the results of the first device optimization.

Multi-chip License Held

1. In the layout database, select Tools > Layout Setup and click the IOD components tab.

2. Select one or more devices for optimization and click OK.

3. Manipulate the components within the layout and perform unraveling. See “UnravelNets” on page 123 for more information.

4. Once you are satisfied with the component orientation and the I/O assignments on theselected device(s), apply the scenario. See “Creating and Applying a Layout Scenario”on page 126 for more information.

The FPGA databases for the selected device(s) will be updated with the new pinassignments. After the scenario is applied, the layout editor is returned to the "InitialScenario". The Initial Scenario does NOT reflect the changes on the previously selecteddevice. All other scenarios are deleted.


Optimizing the I/O AssignmentsI/O Optimization

5. Go to the FPGA database and create or update its symbols. See “Creating, Editing andUpdating Symbols and Schematics” on page 95 for more information.

6. Export symbols and schematics for the device by selecting Export > Schematic andSymbols, and forward annotate the changes to the PCB tool.

You can now import the PCB layout into the layout database in order to optimizeanother device with the results of the first device optimization.

I/O OptimizationAfter completing the I/O Planning phase of the FPGA on Board process, I/O Optimization canbe performed. I/O Optimization is defined as utilizing the actual layout data to optimize the I/O.The step requires a PCB layout.

In I/O Designer, the layout database can be populated from the Expedition physical layout usingImport > Layout.

Now, the I/O can be further optimized, new layout scenarios can be created and applied.

When loading a design from Expedition, you can view the netlines from a pin-to-pin view or apin to partial route view. This can be valuable when considering I/O alignment with a large bus.A pin-to-pin view may leave unwanted cross-overs based on routes that are already in place.

Fan-out VisibilityIn the Layout Window, it is possible to view fan-outs imported from the design, such that theirpositions are taken into account when unravelling is performed.



Figure 10-6. Fan-out Visibility

PADS I/O Designer User Guide 8.2 131November 30, 2009

Chapter 11Data Exchange

I/O Designer allows you to exchange a wide variety of design data with external systems suchas HDL Entry tools, Synthesis tools, Place & Route tools and Design Definition tools. Thischapter describes this data exchange in detail.

• “HDL and EDIF/XML Files” on page 131

• “Synthesis Constraints Files” on page 132


• “FPGA Xchange Files” on page 134

• “Integration with DxDesigner” on page 136

•

• “Integration with Pads Layout” on page 146

•

NoteBefore generating a file, its name must be entered in the Database Settings dialog.

Whenever possible, I/O Designer does not overwrite the contents of an existing file. Forinstance, if a constraints file is generated, and the file already exists, the file is read, modified toreflect the current pin assignments, and then written back. In other words, I/O Designerpreserves constraints created by external tools.

HDL and EDIF/XML FilesI/O Designer allows you to work with HDL files in the following way:

• Read signals from an HDL/Netlist file, see “Importing I/O Signals Using HDL/NetlistFiles” on page 70.

• Create signals and let I/O Designer generate an HDL/Netlist file for you

• Update signals from an HDL/Netlist file

To generate an initial VHDL entity or Verilog module from I/O Designer, select Export >VHDL Entity or Export > Verilog Module. Only ports in entity/module declaration aregenerated, without any underlying architecture. This allows manual addition of signals within


Data ExchangeSynthesis Constraints Files

November 30, 2009

I/O Designer(see the section called Adding, removing, and renaming signals). Subsequently anHDL file is generated as a starting point for further design, that is, writing architecture/modulecontents.

I/O Designer monitors HDL files using the Synchronization Wizard. Whenever the HDL file ischanged and the ports of the unit displayed in the Signals List are modified, the Signal List isupdated to reflect the actual unit declaration.

Recognizing Differential SignalsI/O Designer recognizes differential signals in an HDL source file. To enable this, select Tools> Preferences + Advanced and under HDL source, select the Recognize differential signalsoption.

I/O Designer will recognize differential signals in an HDL design if the differential buffers areinstantiated in the top-level design unit. A successfully recognized differential signal isdisplayed as a single signal in the Signals List. The signal may then be assigned to a pair ofdifferential pins. If the by regular expressions option is selected I/O Designer will try torecognize differential signals using regular expressions set in Recognition of differentialsignal with regular expressions. Additionally I/O Designer will try to recognize differentialclock signals when Autodetect clocks is enabled in the Clock autodetection section. Ifdifferential clock signals are detected they will be allocated the type "DIFFCLOCK".

Synthesis Constraints FilesI/O Designer allows you to read and generate synthesis constraints files. To generate synthesisconstraints file from I/O Designer, choose Export > Synthesis Constraints File from the mainmenu. I/O Designer supports reading and writing constraints files for the following synthesistools:

• Leonardo Spectrum (.ctr)

• Precision (.sdc)

• Synopsys (.sdc)

• Synplify Pro (.sdc)

• Xilinx XST

Place and Route ToolsI/O Designer allows you to read in a Place & Route constraints file or Pin Report file, changepin assignments, and regenerate the constraints file to be read by the Place & Route software.I/O Designer supports reading and writing constraints files for the following Place & Routetools:

Data ExchangePlace and Route Tools


• Actel Designer 8.6 SPB / Actel Designer 8.5

• Altera Quartus II 9.0 SP2 / Altera Quartus 8.1

• Lattice ispLEVER 7.2 SP2 / ispLEVER 7.1

• Xilinx ISE 11.3 / Xilinx ISE 11.2 / Xilinx ISE 10.1

NoteI/O Designer supports older FPGA tool versions but these are not included in the standardinstallation:

Actel Designer 8.5 / 8.5 SP2 / 8.4 SP2 / 8.3 SP1 / 8.2 SP2 / 8.1 SP2 / 8.0 SP2 / 7.3 SP2 /7.2 SP2 / 7.1 / 7.0 SP1 / 6.3 /6.2 SP2 / 6.1 SP1 / 6.0 SP2 / 5.2 SP1 / 5.0 SP1

Altera Quartus II 9.0 / 9.0 SP1 / 8.0 / 7.2 SP3 / 7.1 SP1 / 6.2 / 6.1 / 6.0 SP1 / 5.1 SP2 / 5.0/ 4.2 SP1 / 4.1 SP2 / 4.0 SP1 / 3.0 SP2, MaxPlus II 10

Lattice ispLEVER 7.2 / 7.2 SP1 / 7.1 SP1 / 7.0 SP2 / 6.1 SP2 / 6.0 SP1 / 5.1 SP2 / 5.0 SP1

Xilinx ISE 11.1 / ISE 9.2 SP4 / 9.1 SP3 / ISE 8.2 SP3 / ISE 8.1 SP2 / 7.1 SP1 / 6.3 SP3/6.2 SP2 / 6.0

These libraries can be provided upon request.

Place and Route Constraints FilesConstraints files pass data such as pin assignments from I/O Designer to the Place & Route tool.To generate a Place & Route constraints file from I/O Designer, select Export > P&RConstraints File. Constraints files formats vary between vendors. Below is the list of Vendor -Constraints file formats.

• Actel (.pin, .gcf or .pdc)

• Altera (.csf or .qsf)

• Xilinx (.ucf)

• Lattice (.lpf)

I/O Designer monitors Place & Route constraints files using the Synchronization Wizard, butthey are not selected for update by default. During the constraints file generation process, I/ODesigner writes necessary information such as pin assignments, I/O Standards and the targetdevice, to the constraints file. It does not overwrite any other information present in the file.Therefore, it is safe to have a constraints file created in an external program, load the file into



November 30, 2009

I/O Designer, modify it, and then save your changes by selecting Export > P&R ConstraintsFile.

NoteIt is important to save the FPGA database following an import of constraints files (.lpf) orpin report files (.pad) from Lattice. This ensures that the correct bus syntax is applied toall bus members.

Pin Report FilesPin report files format is vendor-dependent:

• Actel (.rpt)

• Altera (.pin)

• Xilinx (.pad or .csv)

• Lattice (.pad)

These files are generated by Place & Route software. I/O Designer uses these files to update pinassignments, signal data and other settings based on the output of the Place & Route tool. I/ODesigner does not generate pin report files.

NoteIt is important to save the FPGA database following an import of constraints files (.lpf) orpin report files (.pad) from Lattice. This ensures that the correct bus syntax is applied toall bus members.

FPGA Xchange FilesFPGA Xchange files contain various design information that may be exchanged between FPGAand PCB tools including:

• Design name

• Device information (vendor, package, speed)

• Pin information (names, numbers, IO standards, assignments)

• Differential pins information

• Signal information (name, direction)

• Swap Groups information

To generate an FPGA Xchange File, go to Export > FPGA Xchange File.



FPGA Device Library PathYou can load a device library update outside the install tree. Update the FPGA location libraryvariable by using Tools > Preferences + Paths and double-clicking the FPGA library locationrow. You can browse to your path by clicking the ellipsis located just to the right-side of thePath column.

Timing Report FilesTiming report files contain timing information generated by Place & Route software. Theinformation read by I/O Designer from these files include timing constraints, timing actuals,signals, etc.

Timing report file format is vendor-dependent:

Altera: RPT

Actel: Not Available

Lattice: TWR

Xilinx: TWR

Design Rule CheckI/O Designer enables you to run the Design Rule Check for Altera devices. Go to Tools >Design Rule Check.

SSO CheckI/O Designer enables you to run the Xilinx SSO (Simultaneous Switching Output) Check. Thesettings for the SSO Check can be found in Database Properties, on the Advanced tab. Theseare:

• SSO Package Allowance

• SSO Bank Threshold

Additionally, the SSO Check is run automatically when an assignment has changed, and a statusmessage printed to the Console Window.

To run the SSO Check, go to Tools > Simultaneous Switching Output Check.


Data ExchangeIntegration with DxDesigner

November 30, 2009

Generating Device ListI/O Designer allows you to generate the full device list available by executing thegenerate_all_devices command in the Console Window.

Integration with DxDesignerBefore you start working with I/O Designer and DxDesigner, ensure that the followingconditions are satisfied:

• DxDesigner installed and path to its executables is set in I/O Designer under Tools >Preferences + Paths.

• In I/O Designer, the Export type is set to DxDesigner under Tools > Preferences +Symbol Editor + Export.

Importing an Existing DxDesigner Project1. Go to Tools > Preferences and make sure the scheme is set to DxDesigner.

2. Go to Import > PCB Design Wizard.

3. In the Project Path field, enter the path to the required DxDesigner project or clickBrowse to navigate to it.

4. Click Next.

5. Select the symbols that you want to import. If you want I/O Designer to generate afunctional symbol for each PCB symbol, select the Generate Functional Blocks forPCB Symbols option. If you want to change the symbol type, you can do it by double-clicking the Type column in a symbol entry.

NoteBy default, I/O Designer lists only symbols with the following attributes:

DEVICE and PKG_TYPE (for DxDesigner)

To browse all available symbols, set the Show All Symbols option.

6. Click Next.

7. Set the device that you want to use for the imported design. I/O Designer tries torecognize the correct device to use, but still gives you the ability to choose a differentone.

8. Click Finish to complete the import process.



Importing Symbols from DxDesignerI/O Designer imports symbols from DxDesigner using the information from symbol fileslocated in DxDesigner project subdirectory sym. When importing symbols that were notgenerated from I/O Designer, the symbol files are searched for the following ports’ attributes:

• Pin Label: sets the Port Label property in I/O Designer

• # attribute: sets the Pin Name property in I/O Designer if the value matches Pin Namein the selected device

• PINTYPE attribute: sets the Pin Type property in I/O Designer

If some of the pin names in the imported symbol do not match pins in the currently selecteddevice, I/O Designer displays a warning. If more than 50% of all pins do not match, I/ODesigner informs you that the device does not match the symbol. If the imported symbol hasbeen generated from I/O Designer, the following information is read from DxDesigner symbolfiles:

To import symbol from DxDesigner, follow these steps:

1. Choose Import > Symbol from the main menu.

2. Choose the .dproj or .ini file that points to the DxDesigner project that you want toimport symbols from.

3. Choose the desired symbols from the list, select whether they are PCB symbols and ifso, to which functional symbol each of them should belong. If you don’t want aparticular symbol to belong to any of the existing functional symbols, put the symbolunder the top-level entry.

4. To complete the import operation, click Import.

Importing Symbols from the Central LibraryI/O Designer allows you to import existing symbols from the Central Library into an FPGAdatabase.

1. Select Import > Symbol from Central Library and specify the path to the requiredCentral Library .lmc file in the Central Library field.

• Port Label • Pin Type

• Signal Name • Port Type

• Pin Number • Port Shape

• Pin Function • Length

• PCB Signal Name • Attributes



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2. In the Partition field, specify the required partition within the library from which thesymbols should be read and click Next.

3. Choose symbols from the partition by clicking the corresponding checkbox. You canalso choose to import the associated parts / associated cells.

Exporting Symbols/Schematics to DxDesignerBefore you start updating symbols/schematics from DxDesigner to I/O Designer, make sure thatyou have set your environment correctly.

The following files are created during symbols / schematics export from I/O Designer toDxDesigner:

• All symbols are saved to the sym directory.

I/O Designer creates one file with the symbol name per symbol. So for example if youhave a symbol named symbol1 then the filename of the generated symbol file will besymbol1.1 and it will be placed in the sym directory.

• The sch directory contains schematic files, which contain information regarding symbolinstantiations and connections between them.

• If you are exporting symbols for the second time, the previously generated symbols aresaved in the bac directory. Design project .prj is generated as well, along with theviewdraw.ini project initialization file.

What is Exported?• Hierarchy - In case of schematics export, all dependencies between symbols are

exported. Schematics information is put into sch directory.

NoteDuring symbol and schematics export, I/O Designer does not generate nets for CONFIGpins. If you want the connection to be created, you have to use the Assign PCB Signaloption.

• Symbol properties - During export, symbol properties information is saved to thesymbol files in the sym directory. Below is the list of symbol properties available in I/ODesigner and their corresponding properties in DxDesigner:

o Port Label: PIN

o Signal Name: SIGNALNAME

o Pin Number: PINNUMBER, PORTID

o Pin Function: PINFUNCTION



o PCB Signal Name: IMPLSIGNALNAME

o Pin Type: PINTYPE

o Dir: ignored

o Port Type: exported

o Port Shape: exported

o Inverted: exported

o Length: exported

o Attributes: exported

• Graphical attributes - Graphical attributes are saved to the symbol file. They include:

o Colors

o Fonts: font family, font color, and font size are all exported. However, since thereare differences in fonts between I/O Designer and DxDesigner, some fonts may bechanged during export. The tool provides special font for use with DxDesignercalled SCHEMATIC_DX. It is strongly recommended that you use this font whileworking with I/O Designer and DxDesigner symbols / schematics.

o Graphics: graphical items are all exported to DxDesigner.

Updating Symbols/Schematics from DxDesignerDuring the update, I/O Designer looks into the DxDesigner project directory specified in theDatabase Settings Dialog on the PCB Flow page. Symbols and schematics are then updatedaccording to changes done by DxDesigner in the sch and sym directories. PCB symbolsmappings are read from the symbol files.

What is Updated?• Hierarchy - Only those schematics / symbols that were generated by I/O Designer are

updated. If you have added a symbol to the DxDesigner project and want it to appear inI/O Designer, you have to import this symbol manually by using the Import Symbolcommand from the menu Import > Symbol.

• Symbol Properties - the following symbol properties are updated from DxDesigner:

o Port Label

o Signal Name

o Pin Number

o Pin Function



November 30, 2009

o PCB Signal Name

o Pin Type

o Port Type

o Port Shape

o Length

o Attributes

• Graphics Attributes - All graphical attributes like colors, fonts and graphical items areupdated from symbol files. For details, see the section on exporting graphical attributes.

DxDesigner Usage ScenariosThis section details the use of I/O Designer in a DxDesigner flow. The section covers threepossible usage models:

• I/O Designer normal mode

Full flexibility mode where I/O Designer is used to generate symbols/fractures,schematics and the PCB pin-swap data for layout. The advantage of using this flow isthe unconstrained PCB layout optimization ability.

• I/O Designer with existing symbols

This usage model imports existing schematic symbols but I/O Designer generatesschematics and the PCB pin-swap data for layout. The advantage of this flow is that youmay use the library symbols while still having the possibility to optimize the PCBlayout.

• I/O Designer with existing symbols and PDB data

This is the most restricted mode. It uses existing schematic symbols and the associatedPDB data from the Central Library. I/O Designer is used to generate the schematics butthere is no swap information exported to the symbols during the export process. In thiscase, the data must match the PDB data from the library. Using this method limits theability to optimize the PCB layout to I/O Designer capabilities. The only way to do it isby using I/O Designer’s Multi-Component View feature.

Scenario 1: I/O Designer Normal Mode - DxDesignerIn this mode of operation I/O Designer creates both the symbol data and the PCB mapping datafor the design. This allows the greatest level of flexibility when optimizing I/O and allows forfast iteration through the design process. The schematics and symbols are generated by I/ODesigner and are simply forward annotated to the PCB design. The process is shown in theflowchart below followed by the steps for this flow.



Figure 11-1. I/O Designer Normal Mode - DxDesigner

After mapping the signal names to the appropriate pins in the device, the Symbol Wizard can beused to quickly generate the PCB level symbols and PCB data ready for layout. To launch theSymbol Wizard, click the icon on the toolbar or choose Symbol > Symbol Wizard from

the menu. For a detailed description of the Symbol Wizard, see the section called “SymbolWizard” on page 95.

The symbol may be fractured according to one of the schemes supported by I/O Designer orcreated as a custom fracture set.

I/O Designer will then generate the required symbols and schematics during the export process,along with a design specific set of pinswap attributes. To export schematics and symbols, usethe Export > Schematic and Symbols menu entry. The design is now ready to forwardannotate to your PCB design tool.

Scenario 2: I/O Designer with Existing Symbols - DxDesignerIn this mode of operation I/O Designer uses a set of library symbols from a DxDesigner designor library. This still allows you to perform optimization during layout using the PCB tools as thePCB pin-swap data is generated from I/O Designer. The process is shown in the flowchartbelow followed by the steps for this flow.



November 30, 2009

Figure 11-2. IOD with Existing Symbols - DxDesigner

I/O Designer can import a set of existing symbols and use it to map the pin to signal assignmentof the device to the generated schematics. I/O Designer can import from a project file, .ini file,schematic file or library using the Import > Symbol menu item.

Once the symbols are available they can be imported into I/O Designer. In order to associate thesymbols with the correct schematic it is necessary to have the top-level functional symbolcreated in I/O Designer; if it does not exist then the imported symbols will not have anassociated functional block. The functional block can be generated as soon as the HDLdefinition has been loaded into I/O Designer.

The PCB Symbol checkbox should be set. Make sure that the Read-only symbol option is NOTchecked since this allows I/O Designerto map the design specific pinswap information to theimported symbols. Once the symbols are imported I/O Designer will map signal associations tothe symbols.

After the symbols have been imported to I/O Designer and the signal to pin assignmentcompleted the schematics must be generated using the Export > Schematic and Symbolsmenu. I/O Designer will generate the schematic for the device complete with the correctconnectivity and attach the design specific swap information to the symbols in the form ofattributes. See “Exporting Symbols/Schematics to DxDesigner” on page 138 for moreinformation.



The pin swap data can be used to complete optimization on the PCB if necessary. Afterbackannotation these swaps will be picked up by I/O Designer automatically through the pinnumber changes on the schematic.

Scenario 3: I/O Designer with Existing Symbols with PDB Data -DxDesigner

In this mode of operation I/O Designer uses a set of library data from the Central Libraryincluding the PDB data for the existing schematic set. This limits the capability to performoptimization during layout using the PCB tools as the PDB entry in the Central Library willprobably not contain any pin-swap information. The process is shown in the flowchart belowfollowed by the steps for this flow.

Figure 11-3. IOD with Existing Symbols and PDB Data

I/O Designer can import a set of existing symbols and use it to map the pin to signal assignmentof the device to the generated schematics. I/O Designer can import from a project file, .ini file,schematic file or library using the Import > Symbol menu item.

Once the symbols are available they can be imported into I/O Designer. In order to associate thesymbols with the correct schematic it is necessary to have the top-level functional symbolcreated in I/O Designer; If it does not exist, then the imported symbols will not have anassociated functional block. The functional block can be generated as soon as the HDLdefinition has been loaded into I/O Designer.

The PCB Symbol check box should be set. Make also sure that the Readonly symbol option ischecked this time since this will fix the swapping ability that is read from library symbols, andtherefore fix the swapping to the way it is defined in the Central Library. Setting the Read-only



November 30, 2009

symbol option also gives the DEVICE attribute a correct value that matches the part number inthe Central Library, which causes the pin numbers and mapping data to be taken from theCentral Library PDB during the packaging process. Once the symbols are imported, I/ODesigner will map signal associations to the symbols.

After the symbols have been imported and the assignment completed the schematics must begenerated using the Export > Schematic and Symbols menu. I/O Designer will generate theschematic for the device complete with the correct connectivity.

In order to enable the usage of PDB data during the packaging process make sure you have theLibrary Manager Central Library option selected in the Design Configurations in DxDesigner.Since the symbols where imported into I/O Designer in read-only symbol mode, the DEVICEattribute on these symbols matches a component in the PDB and therefore the packagingprocess (ViewPCB or PCBFWD in DxDesigner) will use the PDB data for pin mappingpurpose.

Figure 11-4. Design Configuration Dialog

The design will then forward annotate to layout using the entries in the Central Library. Pinswapping will not be available in the PCB design tool but optimization can be achieved by usingthe device window and layout view in I/O Designer.



Figure 11-5. Generation Example

Setting Part Data Export FormatPin mapping can be exported using the HKP format or PDB format. To set-up the export format,

1. Select File > Project Properties and select the Export Part Data checkbox.

2. Choose from the following two options:

• Expedition Library Services ASCII format (HKP)

• Write to Local PDB file.

NotePart Data Export is not available for DxDesigner 2007 for non-Expedition flows.

Exporting to the Central LibraryIf the symbols are imported from the Central Library into I/O Designer, then no action isrequired.

If the symbols are created in I/O Designer, then follow these steps once your changes arecomplete:

1. Export to the local symbol partition of your DxDesigner project.

2. Load the Symbol Editor from within DxDesigner.

3. Import into the Central Library.

To export the part database:


Data ExchangeIntegration with Pads Layout

November 30, 2009

1. Export to an HKP file.

2. Import into the Central Library using the library service.

NoteFor DxDesigner for non-Expedition flows, it is not possible to export symbols to theCentral Library from within I/O Designer.

Using the Interconnectivity Table EditorYou can use DxDesigner to create and manage a design from the Interconnect Table Editor. I/ODesigner can create an Interconnect Table (ICT) in addition to a schematic.

Within a DxD design, if the top level is a schematic, I/O Designer can create a functional blockwith either a schematic or ICT below. If the top level of the design is an ICT, I/O Designer canonly create a functional component (analogous to a functional block) and an ICT below.

To export to a connectivity table, choose Export > Interconnectivity Table.

NoteBefore running the ICT export, a DxDesigner project path should be set and a functionalblock must be created. All PCB fractures must be present.

Integration with Pads LayoutI/O Designer reads the PCB layout information contained in the Pads Layout layout file. Thisallows you to view the connections between the current device and the surrounding elements onthe PCB schematic.

Data ExchangeConstraints Bus Members Generation


Constraints Bus Members GenerationWith this functionality, you can choose a constraints delimiter format for a specified constraintstype. This is done by choosing a delimiter format for a specific constraint type. The ConstraintsBus dialog is located under the advanced preferences path (Tools > Preferences + Advanced +Constraints Bus Members Generation) as shown in Figure 11-6.

Figure 11-6. Constraints Bus Dialog: Default Values

The File Type column lists the type of constraints file. The Slice Format column shows thecurrent format associated with the file in the adjacent field. Slice format determines the type ofdelimiters to be used for presenting constraints (for example, writing them to a file).

Initially, default settings populate the dialog table. A row highlighted in bold, indicates that theformat in the Slice Format column has been changed. When changes are applied, only changedsettings are written to the local settings file (the user’s .ini file). Unchanged rows (that is, defaultrows) are always read from global settings.

To change a value, highlight the row, click the down arrow to display a drop-down list, andselect the appropriate value. Click Apply to apply the new value and leave the dialog open orOK to save the new value and close the dialog. Figure 11-7 shows a modified entry (Lattice -PRF).


Data ExchangeConstraints Bus Members Generation

November 30, 2009

Figure 11-7. Constraints Bus Dialog: Modified Defaults

The default values can be restored selectively by choosing the appropriate value for a specificrow. To restore all slice formats to their default values, click Default.

Some constraints delimiter formats can be set to Automatic. This option tells the system todetermine the slice format from the appropriate database settings (for example, for a specificvendor or language option).

Make sure the name of your


Chapter 12I/O Designer Tool Reference

The following sections give detailed information on the following:

• “Navigating List Windows” on page 150

• “Keyboard Shortcuts” on page 155

• “Toolbars” on page 159

Status BarA status bar at the bottom of the screen displays information related to the current selection. Inaddition, tips are continuously displayed here. These are short texts, presenting additionalfeatures available in the current context.

Pop-up MenusThe right mouse button is used exclusively to display pop-up menus, giving access tocommands specific to a given context. In this manual, the word click always refers to the leftmouse button click.

You may use operating system dependent ways to display pop-up menus. For details, pleaserefer to the operating system documentation.

Undo and RedoI/O Designer provides unlimited undo/redo possibilities. Any operation may be undone, and anyundone operation may be redone again. There is no limit to the amount of times an undo step isreversed. To undo an operation, use the Edit > Undo command, or the button on the MainToolbar. To redo an undone operation, use the Edit > Redo, or the button on the MainToolbar.

It is possible to perform more than one undo or redo action at a time. Click the down arrowto the right of the Undo and Redo buttons to display a list of operations that may be undone orredone. Moving the mouse pointer over the list highlights the operations, and displays the textbelow them, such as Undo 5 actions. Clicking on an operation executes the Undo or Redo forthat operation and all operations performed since.


I/O Designer Tool ReferenceNavigating List Windows

The Undo/Redo history will be cleared, as the result of operations that change the entiredatabase, such as File > New, File > Open, and those Source Control system interfacecommands that result in reloading the database.

Navigating List WindowsThe following sections describe how to navigate the Signals List, Pins Listand Connectivity ListWindow.

Operations on ColumnsColumns in the List Windows are resizable. To shrink or enlarge a column, click the linebetween the two columns on the header, and drag the separating line to the desired position.

Columns in the List Windows may be freely hidden and displayed again. Right-click on acolumn header to display the pop-up menu. Each column is listed on the pop-up menu with acheck mark to indicate that they are shown. Select the required column from the list to toggle itsshow/hide state.

Row SelectionClick on a row to select it. The row will be highlighted and any previously selected row will bedeselected. To select multiple rows, use CTRL+click, which toggles the selection state of arow.

To select a range of adjacent rows, click the first row in the range, and then SHIFT+click on thelast row in the range.

Whenever a list window is active, only one of the rows is current. The current row does not haveto be selected. The current row is outlined with a slightly wider frame. For some operations,especially while using the keyboard, it is important to know which row is current. Use the Spacekey to toggle the selection state of the current row.

Sorting RowsRows in the List Windows can be sorted alphabetically, based on any single column, and alsoon multiple columns.

To sort the rows by a single column, do one of the following:

• Click on the required column header. A second click on the same column headerreverses the sort order.

The triangle shown in the header acts as a sort column indicator.



• Right-click on the required column header and select Sort Ascending or SortDescending.

To sort rows based on multiple columns

1. Right-click on any column header and select Multicolumn Sort...

This displays the Multicolumn sort properties dialog, which contains one row namedsort by.

2. In the Column field, select the first column to start sorting by, using the drop down list.

A second row appears named then sort by.

3. Select a second column in the Column field for the then sort by row. The drop down listwill contain only the remaining columns.

4. Repeat this step to add further columns to define sorting properties.

5. In the Direction field, select Ascending, or Descending, to set the sort order for eachcolumn separately.

Filtering RowsIn order to view only relevant entries in a List Window, filters can be set for each column byentering a value in the filter field at the top of the window.

Filters are maintained for each column separately, and are equally taken into account.Therefore, it is possible to display results that match more than one column filter. For example,in the Signals List, setting a filter of A on the Name column, and a filter of ‘In’ on the Dircolumn will display signals with names beginning with the letter A and are of the direction ‘In’.

Procedure

Use the following procedure to set filters on one or more columns:

1. In the List Window, right-click on the required column header and ensure FilterColumn is selected. Or use the keyboard shortcut CTRL+click on the column header toset this column as the filter column.

The column header is marked with bold face.

2. Enter a value into the filter field and press Enter.

Only rows matching the value entered are displayed in the List Window. In addition tothe filter field for each column, the value of the filter appears in brackets after thecolumn header and in the status bar.

3. Repeat steps 1 and 2 on subsequent columns to filter the results further.



All filters are displayed in the header, after column names, and additionally in the statusbar.

To remove all column filters, right-click on any column header in the List Window and selectReset Filters.

Filtering to Selected Rows

Select the required rows in the List Window and select View > Show Only Selected Rows. Anappropriate filter is constructed in such a way that only the selected rows match it.

Filter RulesFilters operate only on the level of individual signals or pins. Bus signals or bus pins are nevertaken into account while filtering. For example: the Add Signal Dialog contains a bus namedABUS, with elements BIN and BIN1. If a filter A is set for signal names, the bus is not displayed.On the other hand, if a filter B is set, the bus is displayed.

Filters are not case sensitive by default, but case sensitivity may be selected in the Tools >Preferences dialog, by using the option Case Sensitive on the General page, in the Filter Settingsgroup.

Filters may contain special characters, which, for instance, allow construction of a filter fordisplaying only pins which Function contains the text VREF. The following sections describeWildcard Filters, and Regular Expression Filters in detail.

Wildcard FiltersWildcard filters use special characters such as * in a similar way to filename wildcards.Wildcard filters are treated as if they had * character appended at the end, for example, filter Ais the same as A*, and matches strings beginning with the letter A.

The following characters are treated special in wildcard filters:

Table 12-1. Wildcard Filters

? Matches any single character.

* Matches any number (including zero) of any characters.

[ ] Characters inside square brackets are called character classes.Character class matches any single character included in theclass.For example, [abc] matches any of the letters a, b, c.

- This character is treated specially in character classes. It isused to denote ranges. For example, [a-z] matches any letter.A character class may contain several ranges, so e.g., [a-z0-9]matches any letter or digit.



Regular Expression FiltersRegular expression filters use the popular regular expression syntax known in many programssuch as grep, Perl, etc. providing a more powerful filtering method than wildcards.

In order to use regular expressions in filters, they must be enabled. Select Tools > Preferences+ Filters and check the Regular expressions option.

The following characters are treated as special in regular expression filters:

^ This character used immediately after opening square bracketnegates the character classes, e.g., [^a-z] matches anycharacter except letters.

Table 12-2. Regular Expression Filters

. Matches any character.

^ Matches the beginning of the string.

$ Matches the end of the string.

\ The meaning depends on the character that follows \ . SeeTable below.

[ ] Characters inside square brackets are called character classes.Character class matches any single character included in theclass. For example, [abc] matches any of the letters a, b, c.

- The character - is treated specially in character classes. It isused to denote ranges. For example, [a-z] matches any letter.A character class may contain several ranges, so [a-z0-9]matches any letter or digit.

^ The character ^ used immediately after opening squarebracket negates the character class, so [^a-z] matches anycharacter except for letters.

( ) Parentheses are used to group elements. Grouping elements ofa regular expression is useful for using ? not for a single letter,but a longer expression instead.

? Matches zero or one occurrence of the preceding expression(i.e., single character, character class, or grouped elements).

+ Matches one or more occurrences of the preceding expression.

* Matches zero or more occurrences of the precedingexpression.

Table 12-1. Wildcard Filters



The backslash \ character is used to construct further special constructs, which are listed below.

Regular expression filters do not need to match the entire string to succeed. For instance, whilewildcard filter A* matches any string beginning with the letter A, the regular expression filterA.* matches any string containing the letter A. This feature does not limit expressiveness ofregular expression filters, since the two special characters ^ $ may be used to force matching ofthe whole string. In short, the regular expression equivalent to wildcard filter A* is ^A.*$.

Custom FiltersIn Tools > Preferences + Filters, you can alter default filter settings for named groups ofsignals or pins such as I/O, clock, differential, etc. You can also define new custom groups thatsuit your specific needs.

Changing the Pin Name Font SizeIf the font size on a pin name is too large in I/O Designer, you can change this setting in theProperties window.

1. Select the pin name to be changed by right-clicking on it.

2. Choose Label Properties to display the Properties window.

3. Check the Font Size. The default is 7. If your pin name is showing a larger font size,click the drop-down box and choose 7.

{ } Notation {n,m} matches at least n, and at most m occurrencesof the preceding expression. There are shortcut forms:{n} means {n,n};{n,} means {n,max};{,m} means {0,m}.

Table 12-3. Backslash Character Filters

\d Matches a single digit, so it is the same as [0-9]

\D Matches non-digits, so it is the same as [^0-9]

\s Matches whitespace.

\S Matches non-whitespace.

\w Matches a word character.

\W Matches a non-word character.

Table 12-2. Regular Expression Filters (cont.)

I/O Designer Tool ReferenceKeyboard Shortcuts


Figure 12-1. Change Pin Name Font Size

Keyboard ShortcutsMany operations available in I/O Designer can be performed by using shortcut keys. Mostshortcut keys are always available. However, the function of some keys depends on the activewindow.

• “Global Shortcuts” on page 156

• “Shortcuts in Signal and Pins Lists” on page 157

• “Shortcuts in the Symbol Window” on page 158



Global Shortcuts

Table 12-4. Global Keyboard Shortcuts

Shortcut Action Menu Item

CTRL + O Open Project File > Open Project

CTRL + S Saves current database File > Save Database

ALT + X Quit I/O Designer File > Quit

CTRL + Z,ALT + Backspace

Undo Edit > Undo

CTRL + Y,CTRL + R

Redo Edit > Redo

CTRL + W Close Database File > Close Database

F2 Edit text on symbol Symbol > Edit Selection >Edit Text

F4 Assign Pins Assign > Assign Pins

SHIFT + F4 Assign Pins with Overwrite Assign > Assign Pins withOverwrite

ALT + 1 Show/Hide Signals List View > Windows > SignalList

ALT + 2 Show/Hide Pins List View > Windows > PinsList

ALT + 3 Show/Hide Symbol Window View > Windows > Symbol

ALT + 4 Show/Hide Device Window View > Windows > Device

ALT + 5 Show/Hide Console Window View > Windows >Console

ALT + 6 Show/Hide Timings Window View > Windows >Timings List

ALT + 7 Show/Hide Project Window View > Windows > Project

ALT + 9 Show/Hide Layout Window View > Windows > Layout

ALT + Enter Show Properties Window Edit > ... Properties(depends on currentselection)

CTRL + ALT + 2 Show/Hide Connectivity List Window View > Windows >Connectivity List

CTRL + ALT + 3 Show/Hide Layout Scenarios Window View > Windows > LayoutScenarios List



Shortcuts in Signal and Pins ListsThe following keys are recognized in the Signals List and the Pins List:

All keys that move the current row may be used together with these modifier keys:

Additionally, the letter keys are used for incremental search. By typing letters contained in thefilter column, you turn the row that starts with those letters into the current row.

Table 12-5. Shortcuts in Signal and Pin Lists

Space Toggles the selection state of the current row.

Left Arrow If the current row is bus element, it turns the bus into thecurrent element. If the current row is a bus, and it is expanded,the key collapses the bus. Otherwise, it scrolls the entire list tothe left.

Right Arrow If the current row is a collapsed bus, the right arrow willexpand it. If the current row is an expanded bus, the key turnsits first element into the current one. Otherwise, it scrolls theentire list to the right.

Up Arrow Shifts the current row up.

Down Arrow Shifts the current row down.

Home Makes the first row current.

End Makes the last row current.

Page Up Makes the row above the first visible row current.

Page Down Makes the row below the last visible row current.

CTRL + Page Up Switches to the next tab.

CTRL + Page Down Switches to the previous tab.

CTRL + A Selects all rows.

Esc Removes marks, see Mark to Assign.

Table 12-6. Modifier Keys

None Makes the current row selected, and deselects all other rows.

CTRL Does not change the selection.

SHIFT Adds all rows between the selection and the current row to theexisting selection.

ALT Marks the selected rows for assigning.



Shortcuts in the Symbol WindowThe following keys are recognized in the Symbol Window:

Shortcuts in the Device WindowThe following keys are recognized in the Device Window :

Table 12-7. Symbol Window Shortcuts

Esc Select Mode.

+ Zoom In

- Zoom Out

Home Zoom to Fit

CTRL + X,SHIFT + DELETE

Cut.

CTRL + C,CTRL + Insert

Copy

CTRL + V,SHIFT + Insert

Paste

CTRL + A Select all elements.

F2 Edit the selected text.

Table 12-8. Device Window Shortcuts

+ Zoom In

- Zoom Out

Home Zoom to Fit

CTRL + A Selects all pins

Esc Remove marks, see Mark toAssign

I/O Designer Tool ReferenceToolbars


ToolbarsToolbars provide quick access to most frequently used menu options. Toolbars can be docked,undocked and switched on/off. This section provides detailed information on the functionsavailable on each toolbar:

• “Main Toolbar” on page 159

• “View Toolbar” on page 160

• “Mode Toolbar” on page 161

• “Layout View Toolbar” on page 161

• “Zoom Toolbar” on page 162

• “Symbol Toolbar” on page 163

• “Source Control Toolbar” on page 164

Main ToolbarThe main toolbar contains:

Table 12-9. Main Toolbar

New FPGA database

New layout database

Open existing project

Save current database file

Save all database files

Close current database file

Database settings

Synchronize databases

Cross Probing



View ToolbarThe View toolbar is used to display or hide different windows in the I/O Designer workspace.

Cut

Copy

Paste

Undo previous operation

Redo previous operation

Assign pins

Assign pins with overwrite

Table 12-10. View Toolbar

Show/Hide Signals List

Show/Hide Pins List

Show/Hide Symbol Window

Show/Hide Device Window

Show/Hide Timings Window

Show/Hide Connectivity List Window (Layout database only)

Show/Hide Layout Scenarios Window (Layout database only)

Show/Hide Layout Window (Layout database only)

Show/Hide Project Window

Table 12-9. Main Toolbar (cont.)



Mode ToolbarTable 12-11. Mode Toolbar

Related Topics

• “Symbol Window Modes” on page 31

• “Select Pin/Net Mode” on page 122

Layout View ToolbarWhen working within a layout database, the Layout View toolbar is available.

Table 12-12. Layout View Toolbar

Related Topics

• “Show Traces” on page 122

• “Show Netlines” on page 122

Show/Hide Console Window

Show/Hide Properties Window

Select Mode

Zoom Mode

Pan Mode

Assign Mode

Select Pin/Net Mode

Show/Hide Traces

Show/Hide Netlines

Table 12-10. View Toolbar



Zoom Toolbar

Related Topics

• “Scrolling and Zooming in the Device Window” on page 37

Table 12-13. Zoom Toolbar

Zoom In

Zoom Out

Zoom to Fit

Zoom to Selection

Undo Zoom Operation

Redo Zoom Operation



Symbol Toolbar

Related Topics

• “Symbol Window” on page 29

Table 12-14. Symbol Toolbar

Create New Symbol

Symbol Wizard

Draw Arc

Draw Bezier Curve

Draw Circle

Draw Line

Draw Rectangle

Insert Text



Source Control Toolbar

Related Topics

• “Source Control Preferences” on page 54

Table 12-15. Source Control Toolbar

Get Project from Source Control System (GetProject)

Create New Project(Create Project)

Add New File(Add New)

Get Latest Version(Get Latest Version)

Check Out File(Check Out)

Check In File(Check In)

Undo Checkout(Undo Checkout)

Set Label(Set Label)

Revision History(Show History)

Show Differences(Show Diff)

Refresh Files Status(Refresh Status)


Chapter 13TCL Interface

The following sections are included in this chapter:

“Creating and Running TCL Scripts” on page 165

“I/O Designer TCL Commands” on page 165

“I/O Designer Defined Scalar TCL Variables” on page 188

“I/O Designer Defined TCL Array Variables” on page 190

Creating and Running TCL ScriptsIn I/O Designer the built-in TCL interpreter is the base for all commands and operations. I/ODesigner performs the following steps to execute an operation:

• Constructs a TCL command line

• Displays the command line in the Console Window

• Executes the command

NoteCommands may be executed directly in GUI mode by entering the command into the Console

Window. I/O Designer includes a TCL interpreter with I/O Designer-specificextensions. All standard TCL commands are available. All TCL scripts to be executed byI/O Designer have to be written using the standard TCL syntax. This manual does notcontain any introduction to the TCL language.

What follows is the list of all TCL extensions specific to I/O Designer. Each of listed commandscan be invoked with the -help parameter and information about the command’s parameters willbe displayed. Parameter ? has the same meaning as -help.

I/O Designer TCL Commands

addandedittext

addandedittext [-parentId <value>] [-string | -signalname |-pinnumber | -pinname | -pinfunction | -implsignalname | -custom][-text <value>] [-left | -center | -right] [-top | -vcenter |-bottom] [-angle <0|90|180|270>] [-font <value>] [-color <value>]


TCL InterfaceI/O Designer TCL Commands

-pos <value> -symbol <value> -view <value>

Adds a graphical text to a symbol and starts-up its edition.

addarc

addarc -symbol <value> [-pencolor <value>] [-penwidth <value>][-penstyle <value>] [-factor <value>] start middle end

Adds an arc to a symbol.

addbezier

addbezier -symbol <value> [-pencolor <value>] [-penwidth <value>][-penstyle <value>] bezierpoints

Adds a Bezier curve to a symbol.

addbitmap

addbitmap -symbol <value> [-rect <coordinates relative to left top symbolcorner>] [-file <path to the image file>]

Adds an image file to a symbol. This is available for DxDesigner 2007 for Expedition andDxDesigner for non-Expedition flows only.

addcircle

addcircle -symbol <value> [-pencolor <value>] [-penwidth <value>][-penstyle <value>] [-fillstyle <value>] [-fillcolor <value>] rect

Adds an circle to a symbol.

addexternalfile

addexternalfile [-filepath <path to the external file>] [-filetype<value>]

Adds information about an external file of any type to a database. This information is used bysynchronization commands. The -filetype value is a text identifying the type of the file. Thistext should be exactly the same as the one supported by synchronization command.

addignorelengthnet

addignorelengthnet

Defines the name of the net whose length will not be minimized by automatic unraveling. Thisis useful for power and ground nets. Command has only one parameter specifying the name ofthe net.



addiocell

addiocellAdds an instance of the specified I/O cell template to a die.

addiocelltemplatepad

addiocelltemplatepadAdds a new pin to an I/O cell template.

addiolibrarypadopeningname

addiolibrarypadopeningnameAdds a new name to the list of pin names to be treated as pad openings in a library.

addline

addline -symbol <value> [-pencolor <value>] [-penwidth <value>][-penstyle <value>] points

Adds a line to a symbol.

addportwithlabel

addportwithlabel -symbol <value> [-signal | -standalonesignal | -pin| -standalonepin | -buspin | -signalpn | -signalpcb | -busslice |-unknown] [-exttype <value>] [-shape <value>] [-rangeText <value>][-range <value>] [-angle <0|90|180|270>] [-len <value>] <-signalname| -pinname | -pinnumber | -pinfunction | -implsignalname |-custom> -pos <value> [-slot <value>] [-diff <value>] [-customtext<value>] [-inverted <value>] [-noupdate <value>] [-nocheck <value>][-loaddefaultattr <value>] identifier

Adds a port to a symbol.

addportwithlabelandedit

addportwithlabelandedit -symbol <value> [-signal | -standalonesignal| -pin | -standalonepin | -buspin | -signalpn | -signalpcb| -busslice | -unknown] [-exttype <value>] [-shape <value>][-rangeText <value>] [-range <value>] [-angle <0|90|180|270>][-len <value>] <-signalname | -pinname | -pinnumber | -pinfunction| -implsignalname | -custom> -pos <value> -view <value> [-slot<value>] [-diff <value>] [-customtext <value>] [-noupdate <value>]identifier

Adds a port to a symbol and enters label editing mode.

addrect

addrect -symbol <value> [-pencolor <value>] [-penwidth <value>][-penstyle <value>] [-fillstyle <value>] [-fillcolor <value>] rect



Adds a rectangle to a symbol.

addscenario

addscenario

Adds new layout scenario. The new scenario becomes active. Command has only one parameterspecifying the name of new scenario.

addtext

addtext [-parentId <value>] [-string | -signalname | -pinnumber |-pinname | -pinfunction | -portlabel | -implsignalname | -custom][-text <value>] [-left | -center | -right] [-top | -vcenter |-bottom] [-angle <0|90|180|270>] [-font <value>] [-deffont] [-color<value>] -pos <value> -symbol <value>

Adds a graphical text to a symbol.

bottomalign

bottomalign symbol items

Aligns items for a given symbol.

ces_set_db

ces_set_db database_file

Command sets the CES database file.

changeattribvisibility

changeattribvisibility [-port <value>] [-index <value>] [-owner<value>] [-none | -name | -value | -both] symbol attrib

Command changes symbol attributes’ visibility.

changebuspinrange

changebuspinrange name from to

Command changes bus pin range. from and to are integer values representing bounds for therange. The width of the bus must remain unchanged for the command to succeed.

changebusrange

changebusrange name from to

Command changes bus signal range. from and to are integer values representing bounds for therange. The width of the bus must remain unchanged for the command to succeed.



changecoresize

changecoresizeChanges the size of a die’s core outline.

changediename

changedienameChanges the name of a die.

changediesize

changediesizeChanges the size of a die outline. The status of the size is fixed, therefore no automatic resizingwill take place. To enable automatic die outline resizing using this command, set the width andheight to 0.

changeexttype

changeexttype <symbol> <port> <type>

Command changes the port type.

changeiocellorientation

changeiocellorientationChanges the orientation of an I/O cell.

changeiocellstatus

changeiocellstatusChanges the status of an I/O cell.

changeiocelltemplate

changeiocelltemplateChanges the attributes of an I/O cell template.

changeiocelltemplatepad

changeiocelltemplatepadChanges the I/O cell template pin.

changelabelvisibility

changelabelvisibility symbol label visible

Command changes the symbol label’s visibility.



changeshape

changeshape <symbol> <port> <shape>

Command changes the shape of a port.

copy

copy symbol items

Command copies symbol items.

creatediffpair

creatediffpair diffpair_name pos_name neg_name

Command creates a differential pair out of pos_name and neg_name signals.

createsymbol

createsymbol [-pcb] [-background <value>] [-parent <value>] [-rect<value>] [-noupdate <value>] name

Command creates a new symbol.

delattrib

delattrib [-port <value>] [-index <value>] [-owner <value>] symbolattrib

Command removes attributes from symbols.

delete

delete symbolname items

Command performs the Delete operation in a symbol.

deletesymbol

deletesymbol <symbol>

Command removes the specified symbol.

delinstanceattrib

delinstanceattrib [-index <value>] [-owner <value>] symbol attrib

Command deletes the specified symbol’s attribute.



editbackground

editbackground [-on | -off] symbol

Command starts/stops the edition of the background in the specified symbol.

eval

eval scriptfile

Command invokes a script file in the I/O Designer environment.(Same command as source scriptfile.)

executeextool

executeextool [-blocking] [-recvstdout] [-recvstderr] [-initdir <value>]

Command invokes an external tool.

exportbackground

exportbackground fileName symbolName

Command exports the symbol’s background.

exportschematic

exportschematic <-dc | -da | -dx> [-lmc <value>] [-partition<value>] [-pdb <value ...>] [-notimestamp] [-noviewer] [-nounattphy][-warningsaserrors] [-overwrite] [-skipcolors] [-portdirection][-multipages] [-danglingnets] [-swapgroups] [-locallmssymbols][-hkp] [-diffpairattr] fileName

Command exports schematics.

exportsymbol

exportsymbol <-dc | -da | -dx> [-lmc <value>] [-partition <value>][-pdb <value ...>] [-notimestamp] [-noviewer] [-skipcolors][-portdirection] [-swapgroups] [-locallmssymbols] [-hkp] fileNamesymbolName [symbolName]

Command exports the specified symbol to the specified file.

generate_constraints_file

Command generates Place & Route constraints file according to the constraints_ file read-onlyvariable set by the set_constraints_file command.

generate_fpga_xchange_file

generate_fpga_xchange_file



Command generates FPGA Xchange file according to fpga_xchange_file read-only variablewhich is set by set_fpga_xchange_file command.

generate_synthesis_constraints_file

Command generates constraints file according to read-only constraints_ file variable, which isset by set_synthesis_constraints_file command.

help

help [<command>]

Command displays the list of all I/O Designer-specific commands. If used with argument,displays the usage of the specified command.

hide

hide symbolname items

Command hides symbol items.

horzmirror

horzmirror <symbol> <item1> [<item2> [...]]

Command performs the Horizontal Mirror operation. See also vertmirror command.

hsrename

hsrename oldName newName

Command changes the signal’s HDL Name to newName.

importdesign

importdesign [-dc | -dx | -da | -edif] [-mapfile <value>] [-viewpoint<value>] [-oatfile <value>] [-cddbfile <value>] [-vendor <value>][-tool <value>] [-family <value>] [-device <value>] [-package<value>] [-signalsmapping <value ...>] [-create_functional_symbols][-wizard] [-showpartpage] fileName symbols

Command imports design information from external design files. See also the Import PCBDesign Wizard.

importlmcsymbol

importlmcsymbol [-all] [-pcb] [-pcbonly] [-readonly] [-wizard][-nogui] [-parent <value>] [-lmc <value>] [-partition <value>] [-dc| -dx | -da | -edif] [-vendor <value>] [-tool <value>] [-family<value>] [-device <value>] [-package <value>] [-properties <value



...>] symbols

Command imports symbols from the Central Library.

importsymbol

importsymbol [-all] [-pcb] [-pcbonly] [-readonly] [-nogui][-checkportexttype] [-parent <value>] [-mapfile <value>] [-lmc<value>] [-partition <value>] [-dc | -dx | -da | -edif] [-mapfonts][-properties <value ...>] [-mgc_comps <value ...>] fileName symbols

Command imports specified symbols from the specified file. The switch -all imports allsymbols, while the -pcb switch imports PCB symbols only, adding them to the specifiedfunctional block.

invertbuspins

invertbuspins pin_name [pin_name ...]

Command inverts bus pins.

invertbussignals

invertbussignals signal_name [signal_name ...]

Command inverts bus signals.

leftalign

leftalign symbol items

Command aligns items for a given symbol.

mergepins

mergepins bus_name {pin_name ...}

Command combines the specified pins to a bus pin.

mergesignals

mergesignals bus_name {signal_name ...}

Command combines the specified signals to a bus.

paste

paste symbol data

Command pastes the data into the symbol.



pasteat

pasteat symbol posx posy items portspos

Command pastes the data into the symbol at the specified position.

prjaddexistingdb

prjaddnewdb <filename>

Adds an existing FPGA or layout database to the current design (same as File > Add to design> Existing Database).

prjaddnewdb

prjaddnewdb [-layout]

Adds a new FPGA or layout database to the current design (same as File > Add to design >New FPGA or Layout). Use the argument layout to add a layout database to the design.

prjopen

prjopen <filename>

Opens an existing project (same as File > Open Project).

prjclose

prjclose [-savealldb][-saveprj]

Closes the currently open project (same as File > Close Project).

prjopendb

prjopendb name -loaddbprefs <Untitled> <my_fpga>

Opens the database.

redo

redo [ count ]

Loads a list of databases specified by the argument.

removefill

removefill symbol items

Command switches the fill of elements of a symbol to Transparent.



renameattrib

renameattrib [-port <value>] symbol old_name new_name owner

Command renames symbol’s attribute.

renamebuspin

renamebuspin <oldname> <newname>

Command renames a bus pin.

renamesymbol

renamesymbol <oldname> <newname>

Command renames a symbol.

reshapearc

reshapearc -symbol <value> -id <value> [-factor <value>] startmiddle end

Command changes the shape of an arc.

reshapebezier

reshapebezier -symbol <value> -id <value> bezierpoints

Command changes the shape of a Bezier curve.

reshapecircle

reshapecircle -symbol <value> -id <value> newrect

Command changes the shape of an circle.

reshapeline

reshapeline -symbol <value> -id <value> points

Command changes the shape of a line.

reshapeoutline

reshapeoutline symbol rect

Command changes the shape of the outline of a symbol.

reshaperect

reshaperect -symbol <value> -id <value> newrect



Command changes the shape of a rectangle.

rightalign

rightalign symbol items

Command aligns items for a given symbol.

rotate

rotate symbol angle items

Command rotates elements of a symbol.

rundrc

rundrc [-cf <value>] [-src <value>] [-log <value>]

Command runs the Design Rule Check for Xilinx and Altera devices. The command can beinvoked with the following command line arguments:

-cf <value>: allows you to specify a constraint file-src <value>: allows you to specify an hdl source file

sadd

sadd name(s) dir type [iostd]

Command adds signals with the name and direction specified to the database. If the nameparameter is a string, the scalar signal will be added. If the name parameter is a list, the bussignal will be added. The first element of the list will be the bus’ name. The remaining elementsof the list will be the names of the elements of the bus. The directions available are: in, out,inout, buffer, and linkage.

savedb

savedb <filename>

Command saves the current database to the specified file.

scaddnew

scaddnew [-binary] [-description <description>] [-comment <comment>]<filename>

Command performs the Add New File operation.

scalebackground

scalebackground symbolName



Command scales the symbol’s background so that it fits the outline.

sccheckin

sccheckin [-keepcheckedout] [-label <label>] [-comment <comment>]

Command performs the Check-In operation.

sccheckout

sccheckout [-force]

Command performs the Check-Out operation. The switch -force executes the operationunconditionally, without this switch the confirmation dialog is displayed, whenever somechanges are about to be lost.

sccreateproject

sccreateproject [-comment comment] <name>

Command performs the Create Project operation.

scdiff

scdiff [-short] [-rev <revision>] [-rev2 <revision2>] [-log<filename>]

Command performs the Diff operation. If the filename argument is given, the differences reportis saved to the file, instead of being displayed in the dialog. The -short lists only categories ofdifferences, without details. With arguments -rev, and -rev2 you can display diff between anyversions of the database.

scgetlatestversion

scgetlatestversion [-force]

Command performs the Get Latest Version operation. The switch -force executes the operationunconditionally, without this switch the confirmation dialog is displayed, whenever somechanges are about to be lost.

scgetproject

scgetproject <name> <directory>

Command performs the Get Project operation.

scgetrev

scgetrev [-force] [-rev <revision>] <filename>



Command performs the Get operation. The selected revision is stored to the given filename. Theswitch -force executes the operation unconditionally. Without this switch the confirmationdialog is displayed, whenever some changes are about to be lost, and for read-only files.

schistory

schistory [-log <filename> [-notime]]Command performs the Show History operation. If the filename argument is given, the historyof versions is saved to the file, instead of being displayed in the dialog. The switch -notimedisables saving of date/time information.

sclabel

sclabel [-comment <comment>] [-rev <revision>] <label>

Command performs the Label operation.

screfreshstatus

Command performs the Refresh Status operation.

scundocheckout

scundocheckout [-force]

Command performs the Undo Check-Out operation. The switch -force executes the operationunconditionally, without this switch the confirmation dialog is displayed, whenever somechanges are about to be lost.

set_cdb_flow

set_cdb_flow [-hkp] [-cdbflow <value>] [-lmc <value>] [-partition<value>] [-pdb <value ...>]

Command sets the Central Library export options.

set_constraints_file

set_constraints_file [-maxplus_acf | -quartus_csf | -ise_ucf |-designer_pdc | -designer_pin | -designer_gcf | -quartus_qsf |-lattice_prf | -lattice_lpf] constraints_file_name

Command changes constraints file.

set_design_architect_project

set_design_architect_project [-path <value>] [-viewpoint <value>][-mapfile <value>] [-catalog <value>]

Command sets the Design Architect project path and viewport file path.



set_dx_designer_project

set_dx_designer_project [-path <value>] [-top <value>] [-oat <value>]

Command sets the DxDesigner project path and OAT file path.

set_expedition_layout

set_expedition_layout [-refdes <value>] layout_file

Commands sets the Expedition PCB or Pads Layout layout file.

set_fpga_xchange_file

set_fpga_xchange_file <filename>

Command changes FPGA Xchange file.

set_pin_report_file

set_pin_report_file [-ise_pad | -ise_csv | -quartus_pin | -maxplus_fit| -designer_rpt | -isp_pad] pin report file name

Command changes the pin report file.

set_synthesis_constraints_file

set_synthesis_constraints_file [-synplicity_sdc | -synopsys_sdc |-leonardo_ctr | -precision_sdc | -xst_xcf] <filename>

Command changes synthesis constraints file.

set_timing_report_file

set_timing_report_file [-ise_twr | -ise_rpt] timing report file name

Command changes the timing report file.

setalign

setalign [-left | -center | -right] [-top | -vcenter | -bottom]symbol item

Command changes the alignment of texts in a symbol.

setattrib

setattrib [-port <value>] [-index <value>] [-owner <value>] [-locked<value>] symbol attrib [values]

Command changes the symbol attributes.



setbackground

setbackground <symbol> <background>

Command changes the background in the specified symbol.

setbackgroundproperty

setbackgroundproperty symbol background items

Sets the background properties for particular items.

setdefaultlinestyle

setdefaultlinestyle symbol items

The command sets default line style for items in a symbol.

setdefaultoutline

Command changes the outline color of the symbol elements to default.

setdesignator

setdesignator symbol designator

Command sets the symbol designator.

setfillcolor

setfillcolor symbol color items

Command changes the fill color of the symbol elements.

setfont

setfont -symbol <value> [-font <value>] [-deffont] items

Command changes the font of texts in a symbol.

setfontsize

setfontsize symbol size items

Command changes the font size of texts in a symbol.

setgeom

setgeom geomCommand sets the symbol property: PCB Geometry (Design Architect) or PKG_TYPE(DxDesigner).



setfunctionalblock

setfunctionalblock <pcbsymbol> <functionalblock>

Command changes functional block to which the specified PCB symbol belongs.

setinstanceattrib

setinstanceattrib [-index <value>] [-locked <value>] [-owner<value>] symbol attrib value

Command sets the specified symbol’s attribute.

setinvert

setinvert [-on | -off] symbol port

Command changes the Inverted attribute of a port.

setlabeltype

setlabeltype -symbol <value> -port <value> <-signalname | -pinname |-pinnumber | -pinfunction | -implsignalname | -custom>

Command changes the text which is used as port label.

setlinestyle

setlinestyle symbol style items

Command sets the line style for symbol’s items.

setoutlinecolor

setoutlinecolor symbol color items

Command changes the outline color of elements of a symbol.

setpart

setpart -vendor <vendor> -tool <tool> -family <family> -device<device> -package <package>

Command changes the selected physical device.

setpartno

setpartno partno

Command sets the part number.



setpinlabel

setpinlabel -symbol <value> -port <value> -recreate <value>-labeltype <value> label

Command changes the port label properties.

setportlength

setportlength symbol port len

Command changes the port length.

setreadonly

setreadonly symbol readonly

Command makes the symbol read-only.

setsigprop

setsigprop signal prop_name prop_value

Command sets the additional signal properties.

setsimilardevices

setsimilardevices part

Command performs the View > Pins from Other Devices operation.

setsourcefile

setsourcefile [-vhdl | -verilog | -edif_xml] [-unit <value>][-include <value>] [-noload] file [additional_files ...]

Command changes the selected HDL file. The language of the file may be also selected, as wellas the name of an entity/module to be used. Additional HDL files may be appended as nextarguments.

setstyle

setstyle [-color <value>] [-automaticcolor] [-linestyle <value>][-linewidth <value>] [-fillstyle <value>] [-automaticstyle][-items <value ...>] [-symbol <value>]

Command sets the color, line style, fill style, and line width.

settext

settext symbol text items



Command changes the text in a symbol.

settextcolor

settextcolor symbol color items

Command changes the color of a text in a symbol.

setvendor

setvendor vendor

Sets the current vendor.

show

show symbolname items

Command shows symbol items.

source

source scriptfile

Command invokes a script file in the I/O Designer environment.(Same command as eval scriptfile.)

splitdiffpair

splitdiffpair diffpair_name

Command splits a differential pair created through creatediffpair command.

splitpins

splitpins <buspin> ...

Command splits the specified bus pins.

splitsignals

splitsignals <bus> ...

Command splits the specified bus signals.

sremove

sremove [-norec] name ...

Command removes specified signals from the database.



taddclockcon

taddclockcon -clock <value> -reqTime <value ...> -dutyCycle <value...> [-actTime <value ...>] [-hl <value>]

The command adds a Clock timing constraint.

taddtcocon

taddtcocon -signal <value> -clock <value> -reqTime <value ...>[-actTime <value ...>] [-min <value ...>] [-ba <value>] [-hl<value>]

The command adds a Clock to Pad timing constraint.

taddtpdcon

taddtpdcon -signalIn <value> -signalOut <value> -reqTime <value ...>[-actTime <value ...>]

The command adds a Pad to Pad timing constraint.

taddtsucon

taddtsucon -signal <value> -clock <value> -reqTime <value ...>[-actTime <value ...>] [-hold <value ...>] [-ba <value>] [-hl<value>]

The command adds a Pad to Setup timing constraint.

tdelclockcon

tdelclockcon -clock <value>

The commands removes a Clock timing constraint.

tdeltcocon

tdeltcocon -signal <value> -clock <value>

The command removes a Clock to Pad timing constraint.

tdeltpdcon

tdeltpdcon -signalIn <value> -signalOut <value>

The command removes a Pad to Pad timing constraint.

tdeltsucon

tdeltsucon -signal <value> -clock <value>



The command removes a Pad to Setup timing constraint.

topalign

topalign symbol items

Aligns items for a given symbol.

typescompatibility

typescompatibility (-set|-rem) signal_type pin_type

Makes or removes an association between the specified signal and pin types such thatassignments between signals and pins of those types can be made. By default, this commandsets types compatibility using the -set switch. When removing types compatibility it isnecessary to add the switch -rem. It's obligatory to specify signal and pin types.

unassign

unassign signals ...

Used to unassign signals.

unassignall

unassignall

Removes all assignments.

unassignpins

unassignpins pins ...

The command unassigns pins.

undo

undo [<levels>]

Command performs an Undo operation.

unravelnets

unravelnets [-p] item1 [item2 [...]]

Command unravels connections between components. item1, item2, ... are the names of signalsor buses that you want to unravel.



updatehdl

Command performs the update operation from the HDL file.

update_from_constraints_file

Command performs the update operation from the constraints file defined by constraints_filevariable. If the constraints_file variable has not been set, no update is performed.

update_from_fpga_xchange_file

Command performs the update operation from the FPGA Xchange file defined byfpga_xchange_file variable. If the fpga_xchange_file variable has not been set, no update isperformed.

update_from_pin_report_file

Command performs the update operation from the pin report file defined by pin_report_filevariable. If the pin_report_file variable has not been set, no update is performed.

update_from_synthesis_constraints_file

Command performs the update operation from the synthesis constraints file defined bysynthesis_constraints_file variable. If the synthesis_ constraints_file variable has not been set,no update is performed.

update_symbols_attributes

update_symbols_attributes

The command updates symbol’s attributes.

updatesymbols

updatesymbols <-dc | -da | -dx> [-graphics] [-attributes] [-assignments][-designator] [-verifyIODattribs] [-skip_signals <value ...>][fileName]

Command performs the update operation from the file containing symbols.

Arguments:

-assignmentsUpdate pin assignments

-graphicsUpdate graphical data

-attributesUpdate attributes


TCL InterfaceI/O Designer Defined Scalar TCL Variables

<filename>Use the file <filename> to perform the update instead of current file.

vertmirror

vertmirror <symbol> <item1> [<item2> [...]]

Command performs the Vertical Mirror operation. See also horzmirror command.

I/O Designer Defined Scalar TCL Variables

constraints_file

TCL read-only variable containing the name of the constraints file.

constraints_file_format

TCL read-only variable containing the name of the constraints file format.

database_file

TCL variable containing the file name of the current database.

ddp_project_path

TCL variable containing the directory name of the selected Design Architect project.

device

TCL variable containing the name of the selected device. This variable is read-only; to changedevice use the setpart command.

dx_project_path

TCL variable containing the directory name of the selected DxDesigner project.

family

TCL variable containing the name of the selected family. This variable is read-only; to changefamily use the setpart command.

fpga_xchange_file

TCL read-only variable containing the name of the FPGA Xchange file.

TCL InterfaceI/O Designer Defined Scalar TCL Variables


hdl_file

TCL variable containing the name of the selected HDL file. This variable is read-only; tochange an HDL file name use the setsourcefile command.

package

TCL variable containing the name of the selected package. This variable is read-only; to changethe package use the setpart command.

pin_report_file

TCL read-only variable containing the name of the pin report file.

pin_report_file_format

TCL read-only variable containing the name of the pin report file format.

speed

TCL variable containing the selected speed.

sso_bank_threshold

TCL variable containing the SSO Bank Threshold.

sso_package_allowance

TCL variable containing the SSO Package Allowance.

synthesis_constraints_file

TCL read-only variable containing the name of the synthesis constraints file.

synthesis_constraints_file_format

TCL read-only variable containing the name of the synthesis constraints file format.

synthesis_tool

TCL variable containing the synthesis tool name.

timing_report_file

TCL variable containing path to the timing report file.

timing_report_file_format

TCL variable containing the timing report file format string.


TCL InterfaceI/O Designer Defined TCL Array Variables

vendor

TCL variable containing the name of the selected vendor. This variable is read-only; to changethe vendor name use the setpart command.

verilog_search_path

TCL variable containing the Verilog search path.

I/O Designer Defined TCL Array Variables

hdlsigname

TCL array containing HDL names of signals.

sdiffnames

TCL array mapping signal names to differential pairs.

sdir

TCL array mapping signal names to signal directions.

slock

TCL array containing the Locked By strings. All signals from the current database are stored inthe slock array. The values of the slock array are the Locked By strings displayed in the SignalList.

sswapgroup

TCL array mapping signals to swap groups.

stypes

TCL array mapping signals to types.

pinbank

TCL array mapping pin numbers to power banks. This array is read-only.

pinfunction

TCL array mapping pin numbers to pin functions. This array is read-only.

pinname

TCL array mapping pin numbers to pin names. This array is read-only.



pinnumber

TCL array containing the pin assignments. All signals from the current database are stored inthe pinnumber array. The values of the pinnumber array are the assigned pin numbers. Signalswithout assigned pins have an empty value in the array.

pinsignal

TCL array mapping pin numbers to signals. The values of the pinsignal array are the signals towhich pins are assigned. Pins not assigned to signals have an empty value in the array.

pinswapgroup

TCL array mapping pins to swap groups.

pintypes

TCL array mapping pin numbers to pin types such as clock, diff, etc.


Chapter 14Design Versioning

Source Control ConfigurationI/O Designer supports several source control systems, such as:

• CVS

• RCS

• Source Safe

To choose a source control system, open the Tools > Preferences dialog. On the SourceControl page a system may be chosen. Additional configuration settings are available there,depending on the chosen system.

The source control interface is implemented in I/O Designer using TCL interface. It is possibleto add the support for another source control system by editing a TCL script. The list in thePreferences dialog contains the custom item. Selecting this item turns on the interface describedin the scc_custom.tcl file, located in the tcl subdirectory of the I/O Designer installationdirectory. The comments on the scc_custom.tcl file contain the details on customizing.

The main advantage of using source control is to have a repository, which stores the baseversion of the database. Designers do not modify the database directly in the repository, butrather work on the local copy. The usual way to utilize Source Control is to get the databasefrom the repository, and store it in the local directory. The database will be read-only and maybe reviewed. If a designer wants to make some changes in the database, the database should bechecked-out, which means that the database is marked in the repository as being modified bythe designer. Only one designer may modify the database at a time. After completing changes,the database may be checked in to the repository, creating new version of the stored database.I/O Designer integrates support to check-in and -out databases, review database history, andso on.

Source Control UsageAll Source Control options can be found in two places: in the File > Source Control menu, andin the Source Control toolbar.

Getting Existing DatabasesTo start using a database that is already stored in the repository (e.g., added there by some otherdesigner) use the File > Source Control > Get Project command button. This button


Design VersioningSource Control Usage

November 30, 2009

displays a dialog for entering the Source Control project name, and the local directory, wherethe database is to be stored.

Adding Databases to the RepositoryTo add a database to the repository:

1. Select File > Source Control > Create Project.

2. Enter the Source Control project name

3. Enter a comment which will be stored in the repository with the first version of thedatabase.

Additional Files in the RepositoryTo add an additional file, such as an HDL file, to the repository:

1. Select File > Source Control > Add New.

2. Specify the path to the required file.

3. Enter a comment which will be stored in the repository.

Since binary files may in some circumstances be explicitly stated as such in the repository, theAdd New command contains the Binary option.

Getting Latest Database VersionTo get the latest version of the database from the repository, and store it in the local directory,select File > Source Control > Get Latest Version.

Checking Out the DatabaseTo check out the database, select File > Source Control > Check Out. If the database is notchecked out, each time you try to modify it the software asks you whether or not the databaseshould be checked out.

Checking In the DatabaseTo check-in the database:

1. Select File > Source Control > Check In.

2. Enter a comment which will be stored in the repository to summarize all changes madeto the database since it was checked out.



Undo Check OutTo cancel all the changes made after the database was checked out, and resign from checkingout, select File > Source Control > Undo Check Out.

Setting LabelsTo set the label (or tag) to the last version of the database, select File > Source Control > SetLabel. Labels are displayed in the Browse Changes History dialog and may be used whensource control software is used not within I/O Designer. For instance, many source controlsystems contain commands to go to a version with a given label.

Browse Changes HistoryTo review the history of changes made to the database, select File > Source Control > ShowHistory. The dialog displays all database versions, with labels, including the user that createdthe version, the time of creation, and comments. All this information may be displayed in moreconvenient way after clicking on the Details button.

The Diff button in the History dialog allows comparing two version of the database. In case twoversions are selected, the button will display the differences between the selected versions. If asingle version is selected, the differences between the selected version and local version will bedisplayed. The dialog displayed after clicking Diff is described in details below, in the sectionabout the Show Diff command.

The Get button in the History dialog allows retrieval of any version from the repository, andsave it in the local directory.

Showing DifferencesTo demonstrate the differences between the local version, and the latest version stored in therepository, select File > Source Control > Show Diff. This button displays a dialog presentinginformation in two panes. The left one summarizes the differences, and the right one presentsdetails about the category selected on the left side.

Refreshing Source Control StatusIt is possible that the state of the database file is changed outside of I/O Designer. Tosynchronize Source Control, select File > Source Control > Refresh Status.



November 30, 2009


Chapter 15Dialog and Field Reference

This chapter describes in detail each dialog available in I/O Designer.

• “Add Signal Dialog” on page 197

• “Database Settings Dialog” on page 198

• “Edit Primitive Value(s) Dialog” on page 200

• “Import Design Wizard Dialog” on page 200

• “Layout Setup Dialog” on page 201

• “Project Properties Dialog” on page 203

• “Rule Manager Dialog” on page 203

• “Rules Wizard” on page 204

• “Unravel Nets Dialog” on page 206

Add Signal DialogUsed to create a new signal and add it to the database. The new signal will appear in the AddSignal Dialog.

To access this dialog, do one of the following:

• Right-click in the Signals List and select Add Signal...

• Select the menu item Edit > Add Signal...

Table 15-1. Add Signal Dialog Contents

Field Description Allowed Values

Name Specifies a name for the signal --

Direction Specifies the signal’s direction In, Out, Inout, Buffer,Linkage

Type Specifies the signal’s type --

I/O Standard Specifies an I/O Standard for thesignal

--


Dialog and Field ReferenceDatabase Settings Dialog

Related Topics

• “Signals List” on page 24

• “Assigning Signals to Pins” on page 83

Database Settings DialogAllows information for the database to be set. The tabs available will differ depending on thetype of database: FPGA (.fpc) or layout (.lpc).

Range Specifies a range of values for thesignal

Table 15-2. Database Properties Dialog

Field Description

I/O Signal List

Language Specifies the format of the source data for the HDL/Netlistfile: VHDL, Verilog, Edif/XML, Spreadsheet or Schematic.

Name Specifies the path to the source data file.

Browse Opens a Browse window to navigate to the required sourcefile.

Analyze Analyzes the source data and populates the Unit list with theentities, modules or cells found. This field is not applicablewhen Spreadsheet is selected as the source data language.

Unit Specifies the entity, module or cell from the source data touse.

Specify the additionalVHDL file(s):

Allows additional VHDL files to be selected.

FPGA Flow

Vendor Specifies the device Vendor:• Actel• Altera• Lattice• Xilinx

Tool/Library Specifies the tool or library from which the device originates

Table 15-1. Add Signal Dialog Contents

Field Description Allowed Values

Dialog and Field ReferenceDatabase Settings Dialog


Related Topics

• “FPGA Device Setup” on page 68

• “Importing FPGA Vendor Files” on page 68

• “FPGA Xchange Files” on page 134


• “Synthesis Constraints Files” on page 132

Family Specifies the family of devices

Device Specifies the device itself

Package Specifies the package for the device

Speed Specifies the speed at which the device runs

FPGA Xchange Allows an FPGA Xchange file to be specified

Place and Route

Constraints file Allows a Place and Route constraints file to be specified

Pin report file Allows a Place and Route pin report file to be specified

Timing report file Allows a Place and Route timing report file to be specified

Synthesis

Tool Specifies the Synthesis tool used:• Leonardo Spectrum• Precision• Synopsys• Simplify Pro• Xilinx Synthesis

Constraints file Allows a Synthesis constraints file to be specified

PCB Flow

Ref Des Allows a Reference Designator for the device to be entered

Symbol Properties

PCB Part Number Allows a PCB Part Number to be entered

PCB cell name Allows a PCB cell name to be entered

Table 15-2. Database Properties Dialog

Field Description


Dialog and Field ReferenceEdit Primitive Value(s) Dialog

Edit Primitive Value(s) DialogUsed to specify the values of the selected rule primitive when creating or editing rules using theRules Wizard.

Accessed by moving a rule primitive from the Available Primitives: list to the RulePrimitives: list on the I/O cell selection page of the Rules Wizard.

Related Topics

• “User-defined Rules” on page 79


Import Design Wizard DialogUsed to import symbols with signals and pins into an FPGA database directly from the design.

Table 15-3. Edit Primitive Value(s) Dialog Contents

Field Description

Operator Specifies an operator for the primitive such that when theprimitive is, is not, contains, does not contain, matches or doesnot match the value(s) specified, the rule is executed.

Operand Specifies the value(s) or range of values for the condition.

List of available values Allows selection of values from those available. The presenceof this field is dependent upon the type of operator selected.

Table 15-4. Import Design Wizard Dialog Contents

Field Description

Pcb Flow

Project Path Specifies the path to the project containing the requireddesign.

Design Name Selects the top-level design within the specified project,containing the required component.

Ref Des Specifies the Reference Designator of the requiredcomponent.

Choose Symbols

Filter Allows the list of available symbols to be filtered usingregular expressions.

Dialog and Field ReferenceLayout Setup Dialog


Related Topics

• “PCB Design Wizard” on page 77

Layout Setup DialogUsed within a layout database to specify components to import into the layout either from adesign or added manually. This dialog contains the following tabs:

• IOD Components

• Library Components

... Accesses a list of popular filter options.

Apply Applies the filter to the list of symbols in the design.

Import signals andassignments only

The wizard will import only the signals and assignmentdata from the selected symbol in the list, the symbolitself will not be imported.

Generate Functional Blocksfor PCB Symbols

Functional block symbols will be generated in I/ODesigner for the imported PCB symbol.

FPGA Flow

Vendor Specifies the device Vendor:• Actel• Altera• Lattice• Xilinx

Tool/Library Specifies the tool or library from which the deviceoriginates

Family Specifies the family of devices

Device Specifies the device itself

Package Specifies the package for the device

Speed Specifies the speed at which the device runs

Choose signal mapping

Imported PCB signal Lists the signals found in the PCB symbol specified forimport.

Existing HDL signal Lists the HDL signals currently held in the FPGAdatabase.

Table 15-4. Import Design Wizard Dialog Contents

Field Description


Dialog and Field ReferenceLayout Setup Dialog

IOD ComponentsTo access this dialog, select Tools > Layout Setup and select the IOD Components tab.

Related Topics

• “I/O Planning” on page 119

Library ComponentsTo access this dialog, select Tools > Layout Setup and select the Library Components tab.

Table 15-5. Layout Setup Dialog Contents - IOD Components Tab

Field Description

Instance name Allows a name to be entered for the component instance.

Database File Allows selection of loaded database files from opened I/ODesigner projects.

Component Name Specifies the name of the component instance.

Position X X coordinate of the component’s position

Position Y Y coordinate of the component’s position

Angle Specifies the component’s rotational position

Mirror Mirrors the component

(Right-click) Insert Adds a new component to the list

(Right-click) Delete Removes the currently selected component from the list

Table 15-6. Layout Setup Dialog Contents - Library Components Tab

Field Description

Instance name The name of the component instance.

Partition The library component’s partition name

Cell The library component’s cell name

Database File Allows selection of loaded database files from opened I/ODesigner projects.

Position X X coordinate of the component’s position

Position Y Y coordinate of the component’s position

Angle Specifies the component’s rotational position

Mirror Mirrors the component

(Right-click) Delete Removes the currently selected component from the list

Dialog and Field ReferenceProject Properties Dialog


Project Properties DialogUsed to verify path information and specify part data export for the project.

To access this dialog, do one of the following:

• Select File > Project Properties

• Right-click in the Project Window and select Project Properties.

Related Topics


• “Setting Part Data Export Format” on page 145

Rule Manager DialogUsed to manage user-defined rules for an FPGA database and gives access to the Rules Wizardin order to create new rules. Allows rules databases to be imported and exported from/to otherprojects.

To access this dialog, select Tools > Rule Editor.

Table 15-7. Project Properties Dialog

Field Description

Project Path The path to the project file

Central Library Path the path to the central library associated with the project

Export Part Data Allows pin mapping to be exported in either HKP or PDB format

Table 15-8. Rule Manager Dialog Contents

Field Description

Import Allows a previously created rules engine database file tobe imported.

Export Allows the currently selected rules engine database file tobe exported for use in another die database.

Rules: Lists the name and description of all the rules applied tothe current database.

Opens the Rules Wizard to begin creation of a new rule.

Deleted the rule currently selected in the Rules: list.


Dialog and Field ReferenceRules Wizard

Related Topics




Rules WizardProvides a mechanism for defining I/O placement rules for a die. To access this wizard, selectTools > Rule Editor and click the New Rule icon.

Moves the selected rule up one place in the list.

Moves the selected rule down one place in the list.

Object Description Gives details on the rule currently selected in the Rules:list. Underlined values in this window can be selected forediting; this opens the Edit Primitive Value(s) Dialog.

Table 15-9. Rules Wizard

Field Description

Set rule name and description

Name: Specifies a name for the rule

Description: Allows description for the rule to be entered

Failure answer: Allows a failure answer to be entered. This text will bereturned if the attempted assignment breaks this rule.

Next Moves the wizard to the next page

Rule Scope

Available Primitives Lists the device primitives available for the rule.

Rule Primitives Lists the device primitives selected for this rule.

Moves the selected primitive from the AvailablePrimitives: list to the Rule Primitives: list, adding it tothe rule definition. Opens the Edit Primitive Value(s)Dialog to allow conditions to be set.

Table 15-8. Rule Manager Dialog Contents

Field Description

Dialog and Field ReferenceRules Wizard


Related Topics


• “Rule Manager Dialog” on page 203


Moves the selected primitive from the Rule Primitives:list back to the Available Primitives list, removing itfrom the rule definition.

Back Moves the wizard to the previous page.

Next Moves the wizard to the next page.

Set allowance for rule

Allow assignments Specifies that the rule conditions will allowassignments when met.

Forbid assignments Specifies that the rule conditions will forbidassignments when met.

Pins Conditions /Signal Conditions

Available Primitives Lists the available primitives for the rule.

Rule Primitives Lists the primitives selected for this rule.

Moves the selected primitive from the AvailablePrimitives: list to the Rule Primitives: list, adding it tothe rule definition. Opens the Edit Primitive Value(s)Dialog to allow conditions to be set.

Moves the selected primitive from the Rule Primitives:list back to the Available Primitives list, removing itfrom the rule definition.

Add Term Allows another term to be added to the rule.

Back Moves the wizard to the previous page.

Next Moves the wizard to the next page.

Finish Completes the rule definition and exits the dialog.

Table 15-9. Rules Wizard

Field Description


Dialog and Field ReferenceUnravel Nets Dialog

Unravel Nets DialogUsed to specify settings for unraveling nets.

Related Topics

• “Unravel Nets” on page 123

Table 15-10. Unravel Nets Dialog

Field Description

Optimize Adjusts the unravelling algorithm such that it focuses on:• Shortest possible net length• Least number of crossovers

Unravel scalars and busesconcurrently

All signals selected for unravel are used as one package ofnets and pins

Use unused pins The unravel process will use unoccupied pins in addition toswapping those already assigned


Appendix APreferred Devices List

I/O Designer allows you to limit the range of devices available for selection by using thepreferred devices list. This enables only the selected devices to be displayed in the DatabaseProperties.

The preferred devices list is stored in the file named componentlist.ini. The algorithm forlocating this file is the same as the one for locating the configuration file with the exception thatthe COMPONENTLIST_INI_DIR variable is used instead of MGC_IO_DESIGNER_HOME.See “Configuration File” on page 20. The preferred devices list is an ASCII file, which can beedited with any text editor.

The preferred devices list consists of sections of the following syntax:

[section]subsectionsubsection...

Here is the sample componentlist.ini file:

[Vendors]xilinx

[xilinx]virtexvirtex2xbrxc4000e

[virtex2]2v10002v20002v8000

Start from the section Vendors, where all available vendors should be listed. All availablefamilies are then listed in the section named after the vendor (Xilinx in the example). We canfurther limit devices and packages available within a family. The idea is that if a section existsin the preferred devices list, then only listed subsections are available. In the example, fourXilinx families: virtex virtex2 xbr xc4000e are available, and in the family virtex2 only threelisted devices are available. In the remaining families all devices are available.


Preferred Devices List

November 30, 2009


Appendix BVendor Support Information

Following is a list of vendor-dependent features in I/O Designer:

Table B-1. Vendor Features

Description Xilinx Altera Lattice Actel

Pin numbers, pin names, pin functiondescription for all device pins

Yes Yes Yes Yes

Pin I/O bank number for assignable I/Opins and for Vcco, Vref, and other I/O bankdedicated power or ground pins

Yes Yes Yes Yes

IO Banking Rules: Output standards withthe same output VCCO requirement can becombined in the same bank

Yes Yes Yes Yes

IO Banking Rules: Input standards with thesame input VCCO and input VREFrequirements can be combined in the samebank

Yes Yes Yes Yes

IO Banking Rules: Input standards andoutput standards with the same inputVCCO requirements can be combined inthe same bank

Yes Yes Yes Yes

IO Banking Rules: When combining bi-directional I/O with other standards, makesure the bi-directional standard can meetrules 1 through 3 above

Yes Yes Yes Yes

IO Banking Rules: No more than onesingle termination type (input or output) isallowed in the same bank.

Yes N/A N/A N/A

IO Banking Rules: No more than one splittermination type (input or output) isallowed in the same bank.

Yes N/A N/A N/A


Vendor Support Information

November 30, 2009

IO Banking Rules: The placement ofsingle-ended I/O pins with respect toLVDS I/O pins is restricted as detailed in“Design for Multiple Devices in aCommon Package” on page 77.

N/A Yes N/A N/A

Check swap group names. It is not allowedto assign signal to a pin if swap groups aredifferent.

Yes Yes Yes Yes

Check if type of signal and pin are thesame. It is possible to force assignment inthis case.

Yes Yes Yes Yes

Recognize differential pin pairs;differential pins that belong together

Yes Yes Yes Yes

Recognize differential signals, set a difftype for them and assign to diff pin pairs

Yes Yes Yes Yes

Pin properties: available sink/sourcecurrent levels for each I/O pin based uponselected I/O standard

Yes Yes Yes Yes

SSO (WASSO) check for some families -based on vendor specific data and rules forSSO (WASSO)

Yes No No No

Multiple sets of IO standards per family. Ifsome pins have a smaller set of IOstandards available, we are not able toprevent users from choosing a wrong IOstandard for that pin. Therefore, we do notcover Low Capacitance (LC) check forpins.

Yes Yes Yes No

Check direction when signal is assigned. Yes Yes Yes Yes

Special or additional types for Local Clockpins.

Yes N/A N/A N/A

Ability to parse HDL code to recognizeMGT channel pins. MGT types must be setfor signals manually, before automaticassignment.

No No N/A N/A

Interior cell information. Position of padsinternally to a device.

No Yes No No

VREF regions. No No No No

Table B-1. Vendor Features (cont.)




Checks that open drain is turned off for allpins with a differential I/O standard

? No ? ?

Checks to see if the drive strengthassignments are within the specificationsof the I/O standard

Yes Yes Yes Yes

Checks to see if the pin location supportsthe assigned drive path

N/A No N/A N/A

Checks if the pin location supportsBUSHOLD (dedicated clock pins do notsupport BUSHOLD)

N/A Yes N/A N/A

Checks if the pin location supportsWEAK_PULLUP (dedicated clock pins donot support WEAK_PULLUP)

N/A Yes N/A N/A

Checks if the combined drive strength ofconsecutive pads does not exceed a certainlimit

N/A No N/A N/A

Checks if the pin location along with theI/O standard assigned support PCI_IOclamp dIODe

N/A No N/A N/A

Checks if pins connected to PLL areassigned to the dedicated PLL pin locations

N/A No N/A N/A

Checks that no single-ended I/O pin existsin the same bank as a DPA

N/A No N/A N/A

Checks if single-ended output pins are acertain distance away from a differentialI/O pin

N/A Yes N/A N/A

Checks if single-ended output pins are acertain distance away from a VREF pad

N/A Yes N/A N/A

Checks if single-ended input pins are acertain distance away from a differentialI/O pin.

N/A Yes N/A N/A

Checks that there are no more than acertain number of outputs or bidirectionalpins in a VREFGROUP when a VREF isused

N/A Yes N/A N/A

Checks if too many outputs are in aVREFGROUP

N/A Yes N/A N/A





November 30, 2009

Set any IO pin as a VREF for > 128macrocells Coolrunner II devices

No N/A N/A N/A

Support for PROHIBIT constraint No N/A N/A N/A

Timing closure support (see the next 4points)

No Yes Yes Yes

a) Supported sources of actual times *.twr *.rpt *.twr N/A

b) Support constraint files as asource/destination

*.ucf *.qsf *.lcf,*.prf

N/A

c) Support for CES No No No N/A

d) Support for synthesis constraint files No No No N/A




Appendix CDevice-dependant Assignment Rules

The following assignment rules are implemented in I/O Designer beginning with releaseIOD7.4.

Actel Assignment Rules• Banking rules: I/O banking restrictions based on VCCIO VREF for I/O standards.

• Check if the type of signal and pin are the same.

• Check to see if the drive strength assignment is within the specifications of the I/Ostandard.

• Multiple sets of I/O standards per family. Some pins have a smaller set of I/O standardsavailable.

Altera Assignment Rules• Banking rules: I/O banking restrictions based on VCCIO VREF for I/O standards.

• I/O bank capacity. Checks the number of pins assigned to a bank against the number ofpins allowed in the bank.

• I/O bank VCCIO voltage compatibility. Checks that no more than one VCCIO isrequired from the pins assigned to the I/O bank.

• I/O bank VREF voltage compatibility. Checks that no more than one VREF is requiredfrom the pins assigned to the I/O bank.

• I/O standard and location conflicts. Checks if the pin location supports the assigned I/Ostandard.

• I/O standard and signal direction conflicts. Checks if the pin location supports the I/Ostandard assigned and the direction. For example, certain I/O standards on a particularpin location can only support output pins.

• I/O standard and drive strength conflicts. Checks to see if the drive strength assignmentsare within the specifications of the I/O standard.

• BUSHOLD and location conflicts. Checks if the pin location supports BUSHOLD(dedicated clock pins do not support BUSHOLD).

• WEAK_PULLUP and location conflicts. Checks if the pin location supportsWEAK_PULLUP (dedicated clock pins do not support WEAK_PULLUP).


Device-dependant Assignment RulesAltera Assignment Rules

November 30, 2009

• A PLL IO bank does not support both a single-ended I/O and a differential signalsimultaneously. Checks that there are no single-ended I/O pins present in the PLL I/Obank when a differential signal exists.

• Single-ended output is required to be a certain distance away from a differential I/O pin.Checks if single-ended output pins are a certain distance away from a differential I/Opin.

• Single-ended output has to be a certain distance away from a VREF pad. Checks ifsingle-ended output pins are a certain distance away from a VREF pad.

• Single-ended input is required to be a certain distance away from a differential I/O pin.Checks if single-ended input pins are a certain distance away from a differential I/O pin.

• Too many outputs in a VREFGROUP. Checks if too many outputs are in aVREFGROUP.

• Too many inputs in a VREFGROUP. Checks if too many inputs are in a VREFGROUP.

• Check if the type of signal and pin are the same.

• Interior cell information. Position of pads internally in a device - used internally.

• VREF regions - used internally.

• Give a warning if WEAK_PULLUP and BUSHOLD are used at the same time.

• Some double function pins (RX, TX, etc.) can be used only as differential inputs ordifferential outputs

I/O Pin Placement with Respect to LVDS I/O PinsFor the Altera Stratix III family, the placement of single-ended I/O pins with respect to LVDSI/O pins is restricted. As shown in Figure C-1, row I/O single-ended outputs with drivingstrength equal to or greater than 8 mA must be placed at least one row away from the LVDSI/O. The same restriction applies to single-ended inputs with OCT RT. You can place single-ended outputs with driving strength less than 8 mA in the rows adjacent to the LVDS I/O. Therestriction does not apply when you use the LVDS input buffer for differential HSTL/SSTLinput. Single-ended inputs without OCT RT have no placement restriction. When DPA isenabled, the constraint on single-ended I/O is the same as that on regular LVDS I/O.

Device-dependant Assignment RulesAltera Assignment Rules


Figure C-1. Single-Ended Row I/O Pin Placement for LVDS I/O Pins

The restriction on placing single-ended column I/O is similar to that on row I/O. Single-endedoutputs with drive strength equal to or greater than 8 mA must be placed at least four I/Os awayfrom the LVDS I/O. The same rule applies to single-ended input with OCT RT. The restrictiondoes not apply when the LVDS input buffer is used for differential HSTL/SSTL inputs. Single-ended outputs with a driving strength less than 8 mA and single-ended inputs without OCT RThave no restriction. The single-ended I/O placement rules for column I/O are shown inFigure C-2.

Figure C-2. Single-Ended Column I/O Pin Placement for LVDS I/O Pins


Device-dependant Assignment RulesXilinx Assignment Rules

November 30, 2009

Xilinx Assignment Rules• Banking rules: I/O banking restrictions based on VCCIO VREF for I/O standards.

• Check if type of signal and pin are the same.


• Multiple sets of I/O standards per family. Some pins have a smaller set of I/O standardsavailable.

Example C-1. Xilinx Assignment Rule

1. The following packages do not support DC1 in Banks 1 and 2: SF363, FF668, FF676,FF672, and FF1152.

2. The following devices do not support DC1 in Banks 1 and 2: XC4VLX15, XC4VLX25,XC4VSX25, XC4VSX35, XC4VFX12, XC4VFX20, XC4VFX40, AND XC4VFX60

• When the clock-capable I/Os are driven by single-ended clocks, then the clock must beconnected to the positive (P) side of the differential “clock capable” pin pair. Thenegative (N) side can be used as a general purpose I/O or left unconnected (Virtex4Virtex5).

• Virtex-4 has I/Os which cannot support differential output IO standards (identified inpackage files - *_LC_*).

• Some pins of devices can be used only as inputs (e.g., pin name:”IP_x”) - Spartan3A.

• An IOB cannot be configured to be both an input and an output if BIDIR ALLOWED isFALSE. The BIDIR_ALLOWED attribute is already available for IO standards andshould be used in this case to block assignments of bidirections signals, if needed.

Lattice Assignment Rules• Banking rules: I/O banking restrictions.

• Check if type of signal and pin are the same.


• Multiple sets of I?O standards per family. Some pins have a smaller set of I/O standardsavailable.


Appendix DGeneric IO Standards

Table D-1. Generic IO Standards

I/O Standards Actel Altera Lattice Xilinx

TTL TTL TTL NA TTL

AGP NA AGP 2X AGP2X33 AGP

CTT NA CTT NA CTT

GTL GTL33 GTL NA GTL

GTL25 GTL25 NA NA NA

GTL_DCI NA NA NA GTL_DCI

GTLP GTLP33 GTL+ NA GTLP

GTLP25 GTLP25 NA NA NA

GTLP_DCI NA NA NA GTLP_DCI

GTL12 NA NA GTL12 NA

GTLPLUS15 NA NA GTLPLUS15 NA

HSLVDCI_15 NA NA NA HSLVDCI_15




HSTL_I HSTLI HSTL CLASS I HSTL15_I HSTL_I

HSTL_I_DCI NA NA NA HSTL_I_DCI

HSTL_I_DCI_18

NA NA NA HSTL_I_DCI_18

HSTL_II HSTLII HSTL CLASS II HSTL15_II HSTL_II

HSTL_II_DCI NA NA NA HSTL_II_DCI

HSTL_II_T_DCI

NA NA NA HSTL_II_T_DCI


Generic IO Standards

November 30, 2009

HSTL_II_DCI_18

NA NA NA HSTL_II_DCI_18

HSTL_II_T_DCI_18

NA NA NA HSTL_II_T_DCI_18

HSTL_III NA HSTL CLASSIII

HSTL15_III HSTL_III

HSTL_III_DCI NA NA NA HSTL_III_DCI

HSTL_III_DCI_18

NA NA NA HSTL_III_DCI_18

HSTL_IV NA HSTL CLASSIV

HSTL15_IV HSTL_IV

HSTL_IV_18 NA NA HSTL18_IV HSTL_IV_18

HSTL_IV_DCI NA NA NA HSTL_IV_DCI

HSTL_IV_DCI_18

NA NA NA HSTL_IV_DCI_18

HSTL_I_18 NA 1.8-V HSTLCLASS I

HSTL18_I HSTL_I_18

HSTL_II_18 NA 1.8-V HSTLCLASS II

HSTL18_II HSTL_II_18

HSTL_III_18 NA NA HSTL18_III HSTL_III_18

CMOS CMOS NA NA NA

LVCMOS2 NA NA NA LVCMOS2

LVCMOS12 LVCMOS12 1.2 V LVCMOS12 LVCMOS12




LVCMOS_30 NA 3.0-V LVCMOS NA NA

LVCMOS33 LVCMOS33 LVCMOS LVCMOS33 LVCMOS33

LVCMOS50 LVCMOS25_50 NA NA NA

LVTTL33D NA NA LVTTL33D NA

LVCMOS33D NA NA LVCMOS33D NA


Table D-1. Generic IO Standards (cont.)







LVDCI_15 NA NA NA LVDCI_15




LVDCI_DV2_15

NA NA NA LVDCI_DV2_15

LVDCI_DV2_18


LVDCI_DV2_25


LVDCI_DV2_33


LVDS LVDS LVDS LVDS LVDS

LVDS_25 NA NA LVDS25 LVDS_25

LVDS25E NA NA LVDS25E NA

LVDS_1R NA LVDS_1R NA NA

LVDS_3R NA LVDS_3R NA NA

MLVDS NA NA MLVDS NA

MLVDS25 NA NA MLVDS25 NA

MINI_LVDS NA mini-LVDS MINILVDS MINI_LVDS_25

mini-LVDS_E_1R

NA mini-LVDS_E_1R

NA NA

mini-LVDS_E_3R

NA mini-LVDS_E_3R

NA NA

mini-LVDS_1R NA mini-LVDS_1R NA NA

mini-LVDS_3R NA mini-LVDS_3R NA NA

LVDS_25_DCI NA NA NA LVDS_25_DCI

LVDS_25_DT NA NA NA LVDS_25_DT





November 30, 2009

LVDS_33 NA NA NA LVDS_33

LVDS_33_DCI NA NA NA LVDS_33_DCI

LVDS_E_1R NA LVDS_E_1R NA NA

LVDS_E_3R NA LVDS_E_3R NA NA

LVPECL LVPECL NA NA LVPECL

LVPECL_33 NA NA LVPECL33 LVPECL_33

LVPECL_25 NA DIFFERENTIAL LVPECL

NA LVPECL_25

BLVDS_25 NA BLVDS BLVDS25 BLVDS_25

LDT_25 NA NA NA LDT_25

LDT_25_DT NA NA NA LDT_25_DT

LVDSEXT_25 NA NA NA LVDSEXT_25

LVDSEXT_25_DCI

NA NA NA LVDSEXT_25_DCI

LVDSEXT_25_DT

NA NA NA LVDSEXT_25_DT

LVDSEXT_33 NA NA NA LVDSEXT_33

LVDSEXT_33_DCI

NA NA NA LVDSEXT_33_DCI

ULVDS_25 NA NA NA ULVDS_25

ULVDS_25_DT NA NA NA ULVDS_25_DT

LVTTL LVTTL LVTTL LVTTL33 LVTTL

LVTTL NA 3.3-V LVTTL NA NA

LVTTL_30 NA 3.0-V LVTTL NA NA

PCI30 NA 3.0-V PCI NA NA

PCI33_3 NA NA PCI33 PCI33_3

PCI33_5 NA NA NA PCI33_5

PCI PCI 3.3-V PCI NA PCI66_3

PCIX30 NA 3.0-V PCI-X NA NA

PCIX PCIX 3.3-V PCI-X PCIX33 PCIX

PCIX66_3 NA NA NA PCIX66_3





PCIX15 NA NA PCIX15 NA

SSTL15_I NA SSTL-15CLASS I

SSTL15 NA

SSTL15_II NA SSTL-15CLASS II

NA NA

SSTL18_I NA SSTL-18CLASS I

SSTL18_I SSTL18_I

SSTL18_II NA SSTL-18CLASS II

SSTL18_II SSTL18_II

SSTL18_II_DCI NA NA NA SSTL18_II_DCI

SSTL18_II_T_DCI

NA NA NA SSTL18_II_T_DCI

SSTL18_I_DCI NA NA NA SSTL18_I_DCI

SSTL2_I SSTL2I SSTL-2 CLASSI

SSTL25_I SSTL2_I


SSTL2_II SSTL2II SSTL-2 CLASSII

SSTL25_II SSTL2_II


SSTL2_II_T_DCI

NA NA NA SSTL2_II_T_DCI

SSTL3_I SSTL3I SSTL-3 CLASSI

SSTL33_I SSTL3_I


SSTL3_II SSTL3II SSTL-3 CLASSII

SSTL33_II SSTL3_II


RSDS NA RSDS RSDS RSDS_25

DIFF_HSTL_I NA DIFFERENTIAL HSTL

HSTL15D_I DIFF_HSTL_I

DIFF_HSTL_II NA DIFFERENTIAL HSTL CLASSII

HSTL15D_II DIFF_HSTL_II

DIFF_HSTL_III NA NA HSTL15D_III DIFF_HSTL_III





November 30, 2009

DIFF_HSTL_I_18

NA DIFFERENTIAL 1.8-V HSTLCLASS I

HSTL18D_I DIFF_HSTL_I_18

DIFF_HSTL_II_18

NA DIFFERENTIAL 1.8-V HSTLCLASS II

HSTL18D_II DIFF_HSTL_II_18

DIFF_HSTL_III_18

NA NA HSTL18D_III DIFF_HSTL_III_18

DIFF_HSTL_I_DCI

NA NA NA DIFF_HSTL_I_DCI

DIFF_HSTL_II_DCI

NA NA NA DIFF_HSTL_II_DCI

DIFF_HSTL_I_DCI_18

NA NA NA DIFF_HSTL_I_DCI_18

DIFF_HSTL_II_DCI_18

NA NA NA DIFF_HSTL_II_DCI_18

DIFF_SSTL15_I NA DIFFERENTIAL 1.5-V SSTLCLASS I

NA NA

DIFF_SSTL15_II

NA DIFFERENTIAL 1.5-V SSTLCLASS II

NA NA


SSTL18D_I DIFF_SSTL18_I

DIFF_SSTL18_II

NA DIFFERENTIAL 1.8-V SSTLCLASS II

SSTL18D_II DIFF_SSTL18_II

DIFF_SSTL18_I_DCI

NA NA NA DIFF_SSTL18_I_DCI

DIFF_SSTL18_II_DCI

NA NA NA DIFF_SSTL18_II_DCI

DIFF_SSTL2_I NA DIFFERENTIAL SSTL-2CLASS I

SSTL25D_I DIFF_SSTL2_I

DIFF_SSTL2_II NA DIFFERENTIAL SSTL-2CLASS II

SSTL25D_II DIFF_SSTL2_II






NA NA

DIFF_SSTL2_II NA DIFFERENTIAL 2.5-V SSTLCLASS II

NA NA

DIFF_SSTL2_I_DCI

NA NA NA DIFF_SSTL2_I_DCI

DIFF_SSTL2_II_DCI

NA NA NA DIFF_SSTL2_II_DCI

DIFF_SSTL3_I NA NA SSTL33D_I DIFF_SSTL3_I

DIFF_SSTL3_II NA NA SSTL33D_II DIFF_SSTL3_II

HSTL_I_12 NA 1.2-V HSTL NA HSTL_I_12

HSTL_II_12 NA 1.2-V HSTLCLASS II

NA NA

CML NA CML NA NA

COMPACT_PCI

NA COMPACT PCI NA NA

AGP_1X NA AGP 1X AGP1X33 NA

STI33V NA 3.3-VSCHMITTTRIGGERINPUT

NA NA

STI25V NA 2.5-VSCHMITTTRIGGERINPUT

NA NA

PCML33 NA 3.3-V PCML NA NA





HYPERTRANSPORT

NA HYPERTRANSPORT

HYPT HT_25

SIMPLE_RSDS NA SIMPLE RSDS NA NA





November 30, 2009

DIFF_HSTL_12 NA DIFFERENTIAL 1.2-V HSTL

NA NA

DIFF_HSTL_12_II

NA DIFFERENTIAL 1.2-V HSTLCLASS II

NA NA

HCSL NA HCSL NA NA

X25TO18 NA NA NA X25TO18

TMDS_33 NA NA NA TMDS_33

MINI_LVDS_33

NA NA NA MINI_LVDS_33

RSDS_33 NA NA NA RSDS_33

RSDS_E_1R NA RSDS_E_1R NA NA

RSDS_E_3R NA RSDS_E_3R NA NA

RSDS_1R NA RSDS_1R NA NA

RSDS_3R NA RSDS_3R NA NA

PPDS_33 NA NA NA PPDS_33

PPDS_25 NA PPDS NA PPDS_25

PPDS_E_3R NA PPDS_E_3R NA NA

TRLVDS NA NA TRLVDS NA

SSTL15D NA NA SSTL15D NA

RSDSE NA NA RSDSE NA

PPLVDS NA NA PPLVDS NA

BUS_LVDS NA BUS LVDS NA NA



Third-Party Information

This section provides information on open source and third-party software that may be included in the I/O Designer product.

• This software application may include Pthreads-w32 version 2.8.0 third-party software. Pthreads-w32 v2.8.0 is distributedunder the terms of the GNU Lesser General Public License v2.1 and is distributed on an "AS IS" basis, WITHOUTWARRANTY OF ANY KIND, either expressed or implied. See the license for the specific language governing rights andl imi ta t ions under the l i cense . You can v iew a copy of the l i cense a t : <pa th to IOD ins ta l l a t iondirectory>/docs/legal/gnu_lgpl_2.1.pdf. To obtain a copy of the Pthreads-w32 v2.8.0 source code, send a request [email protected]. This offer shall only be available for three years from the date Mentor GraphicsCorporation first distributed Pthreads-w32 v2.8.0.

227

A B F GDC E H I J K L M N O P Q R S T U V XW Y Z


Index

— A —addandedittext, 165addarc, 166addbezier, 166addellipse, 166Adding Graphics, 104addline, 167addportwithlabel, 167addportwithlabelandedit, 167addrect, 167addtext, 168Arcs, 104Assign Buses, 85Assign Commands, 84Assign Mode, 84Assign Pins, 84Assignment rules

Actel, 213Altera, 213Lattice, 216Xilinx, 216

AttributeIOD_GENERATED, 110IOD_RESERVEDSHEET, 110

— B —Bank Display, 34Bezier Curves, 104bottomalign, 168Bus Pin

Definition, 85Bus Signal

Definition, 74

— C —Central Library Import Symbols, 137ces_set_db, 168Change pin name font size, 154changeattribvisibility, 168changebuspinrange, 168

changebusrange, 168changeexttype, 169changelabelvisibility, 169changeshape, 170Circles, 104Clock Assignments, 89Clock Display, 35Commands

Redo, 24Undo, 24

componentlist.ini, 207CONFIG Pins, 98Console Window

Overview, 39Console Window Shortcuts, 40Constraints Bus

dialog, 147constraints_file, 188constraints_file_format, 188copy, 170creatediffpair, 170createsymbol, 170

— D —Database

Wizard, 67Database Repository, 193database_file, 188ddp_project_path, 188delatrrib, 170delete, 170Delete Elements, 106deletesymbol, 170delimiter,constraints bus, 147delinstanceattrib, 170device, 188Device Window

Bank Display, 34Clock Display, 35Modes, 38

Index

228November 30, 2009



PCB Layout View, 39Pin Display, 33

Device window, 32Device Window Shortcuts, 158dx_project_path, 188DxDesigner

Setting Up Environment, 136

— E —Edit Symbol Elements, 106editbackground, 171Ellipses

See Circles, 104Environment

DxDesigner, 136Environment Variables, 19

IOD_PATH_DIR_DEF_DB, 20IOD_PATH_DIR_WORKING, 20IOD_PATH_FILE_PDF_VIEWER, 20IOD_PATH_FILE_VD_DX, 20IOD_PATH_FILE_VD_IDX, 20MGC_IO_DESIGNER_HOME, 19

export to Central Library, symbolsexport to CL, export symbols, 145

exportbackground, 171exportschematic, 171exportsymbol, 171

— F —family, 188Filtering, 151Filters

regular expression, 153wildcard, 152

flows, 19Font size

change, 154fpga_xchange_file, 188

— G —generate_constraints_file, 171generate_fpga_xchange_file, 171generate_synthesis_constraints_file, 172Get Existing Database

Existing DatabasesGet, 193

GraphcisRectangles, 105

GraphicsAdding, 104Arcs, 104Bezier Curves, 104Circles, 104Lines, 105Text, 105

Graphics Properties, 51

— H —hdl_file, 189hdlsigname, 190help, 172hide, 172horzmirror, 172hsrename, 172

— I —ICE, 146importdesign, 172importlmcsymbol, 172importsymbol, 173Installation Directory, 19interconnect table editor, 146invertbuspins, 173invertbussignals, 173IOD_GENERATED, 110IOD_PATH_DIR_DEF_DB, 20IOD_PATH_DIR_WORKING, 20IOD_PATH_FILE_PDF_VIEWER, 20IOD_PATH_FILE_VD_DX, 20IOD_PATH_FILE_VD_IDX, 20IOD_RESERVEDSHEET, 110

— J —JTAG Pins, 98

— L —leftalign, 173Lines, 105

— M —mergepins, 173mergesignals, 173MGT Pins, 90, 98

229PADS I/O Designer User Guide, 8.2November 30, 2009


— O —OrCAD font size

change, 154

— P —package, 189Pads Layout, 146paste, 173pasteat, 174PCB Layout View, 39Pin Display, 33Pin List

Definition, 150, 197Pin List Shortcuts, 157Pin name font size, 154Pin Properties, 47Pin Report Formats, 134Pin Types, 86pin_report_file, 189pin_report_file_format, 189pinbank, 190pinfunction, 190pinname, 190pinnumber, 191Pins

printing, 29pinsignal, 191pinswapgroup, 191pintypes, 191Place & Route Constraint Formats, 133platforms, 19Port Properties, 49Preferred Devices, 207Printing

signals and pinsSignals

printing, 29Properties

Graphic, 51Pin, 47Port, 49Symbol, 51Text, 52

Properties WindowOverview, 44

— R —Rectangels, 105Redo, 24redo, 174removefill, 174renameattrib, 175renamebuspin, 175renamesymbol, 175reshapearc, 175reshapebezier, 175reshapeellipse, 175reshapeline, 175reshapeoutline, 175reshaperect, 175rightalign, 176rotate, 176Rows

Filtering, 151Selecting, 150

rundrc, 176

— S —sadd, 176savedb, 176scaddnew, 176scalebackground, 176sccheckin, 177sccheckout, 177sccreateproject, 177scdiff, 177scgetlatestversion, 177scgetproject, 177scgetrev, 177schistory, 178sclabel, 178Scope, 112screfreshstatus, 178scundocheckout, 178sdiffnames, 190sdir, 190Selecting rows, 150Set Part Data Export, 145set_cdb_flow, 178set_constraints_file, 178set_design_architect_project, 178




set_dx_designer_project, 179set_expedition_layout, 179set_fpga_xchange, 179set_pin_report_file, 179set_synthesis_constraints_file, 179set_timing_report_file, 179setalign, 179setattrib, 179setbackground, 180setbackgroundproperty, 180setdefaultlinestyle, 180setdefaultoutline, 180setdesignator, 180setfillcolor, 180setfont, 180setfontsize, 180setfunctionalblock, 181setgeom, 180setinstanceattrib, 181setinvert, 181setlabletype, 181setlinestyle, 181setoutlinecolor, 181setpart, 181setpartno, 181setportlabel, 182setportlength, 182setreadonly, 182setsigprop, 182setsimilardevices, 182setstyle, 182settext, 182settextcolor, 183setvendor, 183show, 183Signal List

Definition, 150, 197Signal List Shortcuts, 157Signal Types, 86Slice Format, constraints bus, 147slock, 190Sorting Rows, 150Source Control Systems, 193speed, 189splitdiffpair, 183

splitpins, 183splitsignals, 183sremove, 183srename, 184SSO Check, 135sso_bank_threshold, 189sso_package_allowance, 189sswapgroup, 190Starting IOD

GUI Mode, 21stypes, 190Supported Platforms

Windows, 19Swap, 86swappins, 184Symbol Properties, 51Symbol Window

Modes, 31Overview, 154

Symbol window, 29Symbol Window Shortcuts, 158Symbol Windows

Settings, 31Symbol Wizard, 95Symbols

Backgrounds, 107Edit Elements, 106Functional, 95Import from Central Library, 137Import from DxDesigner, 137PCB, 95

symbolwizard, 184Synchronization Wizard, 52synthesis_constraints_file, 189synthesis_constraints_file_format, 189synthesis_tool, 189

— T —taddclockcon, 185taddtcocon, 185taddtpdcon, 185taddtsucon, 185TCL Command

addandedittext, 165addarc, 166addbezier, 166



addellipse, 166addline, 167addportwithlabel, 167addportwithlabelandedit, 167addrect, 167addtext, 168bottomalign, 168ces_set_db, 168changeattribvisibility, 168changebuspinrange, 168changebusrange, 168changeexttype, 169changelabelvisibility, 169changeshape, 170copy, 170creatediffpair, 170createsymbol, 170delatrrib, 170delete, 170deletesymbol, 170delinstanceattrib, 170editbackground, 171exportbackground, 171exportschematic, 171exportsymbol, 171generate_constraints_file, 171generate_fpga_xchange_file, 171generate_synthesis_contraints_file, 172help, 172hide, 172horzmirror, 172hsrename, 172importdesign, 172importlmcsymbol, 172importsymbol, 173invertbuspins, 173invertbussignals, 173leftalign, 173mergepins, 173mergesignals, 173paste, 173pasteat, 174redo, 174removefill, 174renameattrib, 175

renamebuspin, 175renamesymbol, 175reshapearc, 175reshapebezier, 175reshapeellipse, 175reshapeline, 175reshapeoutline, 175reshaperect, 175rightalign, 176rotate, 176rundrc, 176sadd, 176savedb, 176scaddnew, 176scalebackground, 176sccheckin, 177sccheckout, 177sccreateproject, 177scdiff, 177scgetlatestversion, 177scgetproject, 177scgetrev, 177schistory, 178sclabel, 178screfreshstatus, 178scundocheckout, 178set_cdb_flow, 178set_constraints_file, 178set_design_architect_project, 178set_dx_designer_project, 179set_expedition_layout, 179set_fpga_xchange_file, 179set_pin_report_file, 179set_synthesis_contraints_file, 179set_timing_report_file, 179setalign, 179setattrib, 179setbackground, 180setbackgroundproperty, 180setdefaultlinestyle, 180setdefaultoutline, 180setdesignator, 180setfillcolor, 180setfont, 180setfontsize, 180




setfunctionalblock, 181setgeom, 180setinstanceattrib, 181setinvert, 181setlabeltype, 181setlinestyle, 181setoutlinecolor, 181setpart, 181setpartno, 181setportlabel, 182setportlength, 182setreadonly, 182setsigprop, 182setsimilardevices, 182settext, 182settextcolor, 183setvendor, 183show, 183splitdiffpair, 183splitpins, 183splitsignals, 183sremove, 183srename, 184swappins, 184symbolwizard, 184taddclockcon, 185taddtcocon, 185taddtpdcon, 185taddtsucon, 185tdelclockcon, 185tdeltcocon, 185tdeltpdcon, 185tdeltsucon, 185topalign, 186unassign, 186unassignall, 186unassignpins, 186undo, 186unravelnets, 186update_from_constraints_file, 187update_from_fpga_xchange_file, 187update_from_pin_report_file, 187update_from_synthesis_constraints_file,

187update_symbol_attributes, 187

updatehdl, 187updatesymbols, 187vertmirror, 188

TCL commandsetstyle, 182

TCL Variableconstraints_file, 188constraints_file_format, 188database_file, 188ddp_project_path, 188device, 188dx_project_path, 188family, 188fpga_xchange_file, 188hdl_file, 189hdlsigname, 190package, 189pin_report_file, 189pin_report_file_format, 189pinbank, 190pinfunction, 190pinname, 190pinnumber, 191pinsignal, 191pinswapgroup, 191pintypes, 191sdiffnames, 190sdir, 190slock, 190speed, 189sso_bank_threshold, 189sso_package_allowance, 189sswapgroup, 190stypes, 190synthesis_constraints_file, 189synthesis_constraints_file_format, 189synthesis_tool, 189timing_report_file, 189timing_report_file_format, 189vendor, 190verilog_search_path, 190

tdelclockcon, 185tdeltcocon, 185tdeltpdcon, 185tdeltsucon, 185



Text, 105Text Properties, 52timing_report_file, 189timing_report_file_format, 189Timings Window

Overview, 40Toolbars

Main, 159Overview, 159Source Control, 164View, 160

topalign, 186

— U —unassign, 186unassignall, 186unassignpins, 186Undo, 24undo, 186unravelnets, 186update_from_constraints_file, 187update_from_fpga_xchange_file, 187update_from_pin_report_file, 187update_from_synthesis_constraints_file, 187update_symbol_attributes, 187updatehdl, 187updatesymbols, 187

— V —vendor, 190verilog_search_path, 190vertmirror, 188VREFs, 90

— W —Wildcard filters, 152

End-User License AgreementThe latest version of the End-User License Agreement is available on-line at:

www.mentor.com/eula

END-USER LICENSE AGREEMENT (“Agreement”)

This is a legal agreement concerning the use of Software (as defined in Section 2) between the company acquiringthe license (“Customer”), and the Mentor Graphics entity that issued the corresponding quotation or, if noquotation was issued, the applicable local Mentor Graphics entity (“Mentor Graphics”). Except for licenseagreements related to the subject matter of this license agreement which are physically signed by Customer and anauthorized representative of Mentor Graphics, this Agreement and the applicable quotation contain the parties'entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements. IfCustomer does not agree to these terms and conditions, promptly return or, if received electronically, certifydestruction of Software and all accompanying items within five days after receipt of Software and receive a fullrefund of any license fee paid.

1. ORDERS, FEES AND PAYMENT.

1.1. To the extent Customer (or if and as agreed by Mentor Graphics, Customer’s appointed third party buying agent) places andMentor Graphics accepts purchase orders pursuant to this Agreement (“Order(s)”), each Order will constitute a contractbetween Customer and Mentor Graphics, which shall be governed solely and exclusively by the terms and conditions of thisAgreement, any applicable addenda and the applicable quotation, whether or not these documents are referenced on theOrder. Any additional or conflicting terms and conditions appearing on an Order will not be effective unless agreed inwriting by an authorized representative of Customer and Mentor Graphics.

1.2. Amounts invoiced will be paid, in the currency specified on the applicable invoice, within 30 days from the date of suchinvoice. Any past due invoices will be subject to the imposition of interest charges in the amount of one and one-halfpercent per month or the applicable legal rate currently in effect, whichever is lower. Prices do not include freight,insurance, customs duties, taxes or other similar charges, which Mentor Graphics will invoice separately. Unless providedwith a certificate of exemption, Mentor Graphics will invoice Customer for all applicable taxes. Customer will make allpayments free and clear of, and without reduction for, any withholding or other taxes; any such taxes imposed on paymentsby Customer hereunder will be Customer’s sole responsibility. Notwithstanding anything to the contrary, if Customerappoints a third party to place purchase orders and/or make payments on Customer’s behalf, Customer shall be liable forpayment under such orders in the event of default by the third party.

1.3. All products are delivered FCA factory (Incoterms 2000) except Software delivered electronically, which shall be deemeddelivered when made available to Customer for download. Mentor Graphics retains a security interest in all productsdelivered under this Agreement, to secure payment of the purchase price of such products, and Customer agrees to sign anydocuments that Mentor Graphics determines to be necessary or convenient for use in filing or perfecting such securityinterest. Mentor Graphics’ delivery of Software by electronic means is subject to Customer’s provision of both a primaryand an alternate e-mail address.

2. GRANT OF LICENSE. The software installed, downloaded, or otherwise acquired by Customer under this Agreement,including any updates, modifications, revisions, copies, documentation and design data (“Software”) are copyrighted, tradesecret and confidential information of Mentor Graphics or its licensors, who maintain exclusive title to all Software and retainall rights not expressly granted by this Agreement. Mentor Graphics grants to Customer, subject to payment of applicablelicense fees, a nontransferable, nonexclusive license to use Software solely: (a) in machine-readable, object-code form; (b) forCustomer’s internal business purposes; (c) for the term; and (d) on the computer hardware and at the site authorized by MentorGraphics. A site is restricted to a one-half mile (800 meter) radius. Customer may have Software temporarily used by anemployee for telecommuting purposes from locations other than a Customer office, such as the employee's residence, an airportor hotel, provided that such employee's primary place of employment is the site where the Software is authorized for use.Mentor Graphics’ standard policies and programs, which vary depending on Software, license fees paid or services purchased,apply to the following: (a) relocation of Software; (b) use of Software, which may be limited, for example, to execution of asingle session by a single user on the authorized hardware or for a restricted period of time (such limitations may be technicallyimplemented through the use of authorization codes or similar devices); and (c) support services provided, including eligibilityto receive telephone support, updates, modifications, and revisions. For the avoidance of doubt, if Customer requests any changeor enhancement to Software, whether in the course of receiving support or consulting services, evaluating Software or

IMPORTANT INFORMATION

USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THISLICENSE AGREEMENT BEFORE USING THE SOFTWARE. USE OF SOFTWARE INDICATES YOURCOMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH

IN THIS AGREEMENT. ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS ANDCONDITIONS SHALL NOT APPLY.

http://www.mentor.com/eula

otherwise, any inventions, product improvements, modifications or developments made by Mentor Graphics (at MentorGraphics’ sole discretion) will be the exclusive property of Mentor Graphics.

3. ESC SOFTWARE. If Customer purchases a license to use development or prototyping tools of Mentor Graphics’ EmbeddedSoftware Channel (“ESC”), Mentor Graphics grants to Customer a nontransferable, nonexclusive license to reproduce anddistribute executable files created using ESC compilers, including the ESC run-time libraries distributed with ESC C and C++compiler Software that are linked into a composite program as an integral part of Customer’s compiled computer program,provided that Customer distributes these files only in conjunction with Customer’s compiled computer program. MentorGraphics does NOT grant Customer any right to duplicate, incorporate or embed copies of Mentor Graphics’ real-time operatingsystems or other embedded software products into Customer’s products or applications without first signing or otherwiseagreeing to a separate agreement with Mentor Graphics for such purpose.

4. BETA CODE.

4.1. Portions or all of certain Software may contain code for experimental testing and evaluation (“Beta Code”), which may notbe used without Mentor Graphics’ explicit authorization. Upon Mentor Graphics’ authorization, Mentor Graphics grants toCustomer a temporary, nontransferable, nonexclusive license for experimental use to test and evaluate the Beta Codewithout charge for a limited period of time specified by Mentor Graphics. This grant and Customer’s use of the Beta Codeshall not be construed as marketing or offering to sell a license to the Beta Code, which Mentor Graphics may choose not torelease commercially in any form.

4.2. If Mentor Graphics authorizes Customer to use the Beta Code, Customer agrees to evaluate and test the Beta Code undernormal conditions as directed by Mentor Graphics. Customer will contact Mentor Graphics periodically during Customer’suse of the Beta Code to discuss any malfunctions or suggested improvements. Upon completion of Customer’s evaluationand testing, Customer will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths,weaknesses and recommended improvements.

4.3. Customer agrees that any written evaluations and all inventions, product improvements, modifications or developments thatMentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly onCustomer’s feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, titleand interest in all such property. The provisions of this Subsection 4.3 shall survive termination of this Agreement.

5. RESTRICTIONS ON USE.

5.1. Customer may copy Software only as reasonably necessary to support the authorized use. Each copy must include allnotices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. Allcopies shall remain the property of Mentor Graphics or its licensors. Customer shall maintain a record of the number andprimary location of all copies of Software, including copies merged with other software, and shall make those recordsavailable to Mentor Graphics upon request. Customer shall not make Software available in any form to any person otherthan Customer’s employees and on-site contractors, excluding Mentor Graphics competitors, whose job performancerequires access and who are under obligations of confidentiality. Customer shall take appropriate action to protect theconfidentiality of Software and ensure that any person permitted access does not disclose or use it except as permitted bythis Agreement. Log files, data files, rule files and script files generated by or for the Software (collectively “Files”)constitute and/or include confidential information of Mentor Graphics. Customer may share Files with third partiesexcluding Mentor Graphics competitors provided that the confidentiality of such Files is protected by written agreement atleast as well as Customer protects other information of a similar nature or importance, but in any case with at leastreasonable care. Standard Verification Rule Format (“SVRF”) and Tcl Verification Format (“TVF”) mean MentorGraphics’ proprietary syntaxes for expressing process rules. Customer may use Files containing SVRF or TVF only withMentor Graphics products. Under no circumstances shall Customer use Software or allow its use for the purpose ofdeveloping, enhancing or marketing any product that is in any way competitive with Software, or disclose to any third partythe results of, or information pertaining to, any benchmark. Except as otherwise permitted for purposes of interoperabilityas specified by applicable and mandatory local law, Customer shall not reverse-assemble, reverse-compile, reverse-engineer or in any way derive from Software any source code.

5.2. Customer may not sublicense, assign or otherwise transfer Software, this Agreement or the rights under it, whether byoperation of law or otherwise (“attempted transfer”), without Mentor Graphics’ prior written consent and payment ofMentor Graphics’ then-current applicable transfer charges. Any attempted transfer without Mentor Graphics’ prior writtenconsent shall be a material breach of this Agreement and may, at Mentor Graphics’ option, result in the immediatetermination of the Agreement and licenses granted under this Agreement. The terms of this Agreement, including withoutlimitation the licensing and assignment provisions, shall be binding upon Customer’s permitted successors in interest andassigns.

5.3. The provisions of this Section 5 shall survive the termination of this Agreement.

6. SUPPORT SERVICES. To the extent Customer purchases support services for Software, Mentor Graphics will provideCustomer with available updates and technical support for the Software which are made generally available by Mentor Graphicsas part of such services in accordance with Mentor Graphics’ then current End-User Software Support Terms located athttp://supportnet.mentor.com/about/legal/.

http://supportnet.mentor.com/about/legal/

7. LIMITED WARRANTY.

7.1. Mentor Graphics warrants that during the warranty period its standard, generally supported Software, when properlyinstalled, will substantially conform to the functional specifications set forth in the applicable user manual. MentorGraphics does not warrant that Software will meet Customer’s requirements or that operation of Software will beuninterrupted or error free. The warranty period is 90 days starting on the 15th day after delivery or upon installation,whichever first occurs. Customer must notify Mentor Graphics in writing of any nonconformity within the warranty period.For the avoidance of doubt, this warranty applies only to the initial shipment of Software under the applicable Order anddoes not renew or reset, by way of example, with the delivery of (a) Software updates or (b) authorization codes or alternateSoftware under a transaction involving Software re-mix. This warranty shall not be valid if Software has been subject tomisuse, unauthorized modification or improper installation. MENTOR GRAPHICS’ ENTIRE LIABILITY ANDCUSTOMER’S EXCLUSIVE REMEDY SHALL BE, AT MENTOR GRAPHICS’ OPTION, EITHER (A) REFUND OFTHE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR (B) MODIFICATION ORREPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY, PROVIDEDCUSTOMER HAS OTHERWISE COMPLIED WITH THIS AGREEMENT. MENTOR GRAPHICS MAKES NOWARRANTIES WITH RESPECT TO: (A) SERVICES; (B) SOFTWARE WHICH IS LICENSED AT NO COST; OR (C)BETA CODE; ALL OF WHICH ARE PROVIDED “AS IS.”

7.2. THE WARRANTIES SET FORTH IN THIS SECTION 7 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NORITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TOSOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITSLICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FORA PARTICULAR PURPOSE AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.

8. LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BEVOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS OR ITSLICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDINGLOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVENIF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. INNO EVENT SHALL MENTOR GRAPHICS’ OR ITS LICENSORS’ LIABILITY UNDER THIS AGREEMENT EXCEEDTHE AMOUNT PAID BY CUSTOMER FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM. IN THECASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITYFOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 8 SHALL SURVIVE THETERMINATION OF THIS AGREEMENT.

9. LIFE ENDANGERING APPLICATIONS. NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLEFOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANYAPPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH ORPERSONAL INJURY. THE PROVISIONS OF THIS SECTION 9 SHALL SURVIVE THE TERMINATION OF THISAGREEMENT.

10. INDEMNIFICATION. CUSTOMER AGREES TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS ANDITS LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE OR LIABILITY, INCLUDINGATTORNEYS’ FEES, ARISING OUT OF OR IN CONNECTION WITH CUSTOMER’S USE OF SOFTWARE ASDESCRIBED IN SECTION 9. THE PROVISIONS OF THIS SECTION 10 SHALL SURVIVE THE TERMINATION OFTHIS AGREEMENT.

11. INFRINGEMENT.

11.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against Customer in the United States,Canada, Japan, or member state of the European Union which alleges that any standard, generally supported Softwareproduct infringes a patent or copyright or misappropriates a trade secret in such jurisdiction. Mentor Graphics will pay anycosts and damages finally awarded against Customer that are attributable to the action. Customer understands and agreesthat as conditions to Mentor Graphics’ obligations under this section Customer must: (a) notify Mentor Graphics promptlyin writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to settle or defend theaction; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action.

11.2. If a claim is made under Subsection 11.1 Mentor Graphics may, at its option and expense, (a) replace or modify Software sothat it becomes noninfringing, or (b) procure for Customer the right to continue using Software, or (c) require the return ofSoftware and refund to Customer any license fee paid, less a reasonable allowance for use.

11.3. Mentor Graphics has no liability to Customer if the claim is based upon: (a) the combination of Software with any productnot furnished by Mentor Graphics; (b) the modification of Software other than by Mentor Graphics; (c) the use of other thana current unaltered release of Software; (d) the use of Software as part of an infringing process; (e) a product that Customermakes, uses, or sells; (f) any Beta Code; (g) any Software provided by Mentor Graphics’ licensors who do not provide suchindemnification to Mentor Graphics’ customers; or (h) infringement by Customer that is deemed willful. In the case of (h),Customer shall reimburse Mentor Graphics for its reasonable attorney fees and other costs related to the action.

11.4. THIS SECTION IS SUBJECT TO SECTION 8 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTORGRAPHICS AND ITS LICENSORS AND CUSTOMER’S SOLE AND EXCLUSIVE REMEDY WITH RESPECT TOANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BYANY SOFTWARE LICENSED UNDER THIS AGREEMENT.

12. TERM.

12.1. This Agreement remains effective until expiration or termination. This Agreement will immediately terminate upon noticeif you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 2, 3, or 5. For anyother material breach under this Agreement, Mentor Graphics may terminate this Agreement upon 30 days written notice ifyou are in material breach and fail to cure such breach within the 30 day notice period. If a Software license was providedfor limited term use, such license will automatically terminate at the end of the authorized term.

12.2. Mentor Graphics may terminate this Agreement immediately upon notice in the event Customer is insolvent or subject to apetition for (a) the appointment of an administrator, receiver or similar appointee; or (b) winding up, dissolution orbankruptcy.

12.3. Upon termination of this Agreement or any Software license under this Agreement, Customer shall ensure that all use of theaffected Software ceases, and shall return it to Mentor Graphics or certify its deletion and destruction, including all copies,to Mentor Graphics’ reasonable satisfaction.

12.4. Termination of this Agreement or any Software license granted hereunder will not affect Customer’s obligation to pay forproducts shipped or licenses granted prior to the termination, which amounts shall immediately be payable at the date oftermination.

13. EXPORT. Software is subject to regulation by local laws and United States government agencies, which prohibit export ordiversion of certain products, information about the products, and direct products of the products to certain countries and certainpersons. Customer agrees that it will not export Software or a direct product of Software in any manner without first obtainingall necessary approval from appropriate local and United States government agencies.

14. U.S. GOVERNMENT LICENSE RIGHTS. Software was developed entirely at private expense. All Software is commercialcomputer software within the meaning of the applicable acquisition regulations. Accordingly, pursuant to US FAR 48 CFR12.212 and DFAR 48 CFR 227.7202, use, duplication and disclosure of the Software by or for the U.S. Government or a U.S.Government subcontractor is subject solely to the terms and conditions set forth in this Agreement, except for provisions whichare contrary to applicable mandatory federal laws.

15. THIRD PARTY BENEFICIARY. Mentor Graphics Corporation, Mentor Graphics (Ireland) Limited, Microsoft Corporationand other licensors may be third party beneficiaries of this Agreement with the right to enforce the obligations set forth herein.

16. REVIEW OF LICENSE USAGE. Customer will monitor the access to and use of Software. With prior written notice andduring Customer’s normal business hours, Mentor Graphics may engage an internationally recognized accounting firm toreview Customer’s software monitoring system and records deemed relevant by the internationally recognized accounting firmto confirm Customer’s compliance with the terms of this Agreement or U.S. or other local export laws. Such review may includeFLEXlm or FLEXnet (or successor product) report log files that Customer shall capture and provide at Mentor Graphics’request. Customer shall make records available in electronic format and shall fully cooperate with data gathering to support thelicense review. Mentor Graphics shall bear the expense of any such review unless a material non-compliance is revealed. MentorGraphics shall treat as confidential information all information gained as a result of any request or review and shall only use ordisclose such information as required by law or to enforce its rights under this Agreement. The provisions of this section shallsurvive the termination of this Agreement.

17. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. The owners of the Mentor Graphics intellectualproperty rights licensed under this Agreement are located in Ireland and the United States. To promote consistency around theworld, disputes shall be resolved as follows: This Agreement shall be governed by and construed under the laws of the State ofOregon, USA, if Customer is located in North or South America, and the laws of Ireland if Customer is located outside of Northor South America. All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction ofPortland, Oregon when the laws of Oregon apply, or Dublin, Ireland when the laws of Ireland apply. Notwithstanding theforegoing, all disputes in Asia (except for Japan) arising out of or in relation to this Agreement shall be resolved by arbitration inSingapore before a single arbitrator to be appointed by the Chairman of the Singapore International Arbitration Centre (“SIAC”)to be conducted in the English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of thedispute, which rules are deemed to be incorporated by reference in this section. This section shall not restrict Mentor Graphics’right to bring an action against Customer in the jurisdiction where Customer’s place of business is located. The United NationsConvention on Contracts for the International Sale of Goods does not apply to this Agreement.

18. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid,unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in fullforce and effect.

19. MISCELLANEOUS. This Agreement contains the parties’ entire understanding relating to its subject matter and supersedes allprior or contemporaneous agreements, including but not limited to any purchase order terms and conditions. Some Softwaremay contain code distributed under a third party license agreement that may provide additional rights to Customer. Please seethe applicable Software documentation for details. This Agreement may only be modified in writing by authorizedrepresentatives of the parties. All notices required or authorized under this Agreement must be in writing and shall be sent to theperson who signs this Agreement, at the address specified below. Waiver of terms or excuse of breach must be in writing andshall not constitute subsequent consent, waiver or excuse.

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