page - 1 the leading provider of eda software & technologies for the physical implementation of...
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Page - 1
The Leading Provider of EDA Software & Technologies for
the Physical Implementation of Structured ASICs
Page - 211/21/2000www.ViASIC.com
ViASIC, Inc.
• Early-stage EDA software company• Located in Research Triangle Park, NC • Founded 1999
• Growing, profitable, debt-free, low burn rate• ViaPath/ViaMask products first announced in May
2003• Four customers since announcement • Two patents on ViaPath/ViaMask granted
– 6,693,454 & 6,580,289– more on the way
• Experienced management team• Closed investment round in late 2003
Page - 311/21/2000www.ViASIC.com
Why Use A Structured ASIC Fabric
0
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Cumulative PhotoMask Costs
($ millions)
1 2 3 4 5 6 7 8# Of Designs/Versions/Respins
Standard-Cell
Metal Prog.Structured ASICs
One MaskStructured ASIC
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interconnect
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Logic Cell Schematic
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memory architecture
WLdrv …WLdrv …
WLdrv …SA …
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SA SA
WLdrv
WLdrv
WLdrv
SA
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SA
bit
bit bit
bit
bit
bit
bit bit bit bit bit
bit bit
bit bit
WLdrv … WLdrvbit bit bit bit bit
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LOGIC
CELL
LOGIC
CELL
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SA
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SA
bit bit
bit bit
bit bit
bit bit
LOGIC
CELL
LOGIC
CELL
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………
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SA
bit
bit
bit
bit
•Stretch custom RAM along word lines:•Increase size of word line driver•Keeps bit lines and therefore SA size the same
•Patent 6,693,454
Traditional Ram vs. Distributed RAM
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ViaMask Nomenclaturefor TSMC/ST 0.13 Micron 6ML
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Available Libraries Include:• TSMC 0.13 6ML• ST 0.13 6ML• TSMC 0.13 8ML• AMS 0.35 4ML• IBM 0.13 6ML in development• Customization of fabric is available
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Features
Simultaneously available embedded RAM Typically routes 100% utilized designs Available via configurable ROM Programmable partition power-down Unlimited clock domains Fits traditional design flows
Standard test flow Generates files for LVS/LEC
Diodes for antenna repair
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ViaMaskOther One
Mask FabricsMetal ProgrammedStructured ASICs
Simultaneously available logic & embedded RAM Yes No NoAvailability of easy to use physical design tools Yes No NoReal world density Excellent Fair Good-ExcellentRisk/cost should respin be needed Good Good PoorNRE Cost (based on number of masks) Good Good PoorUnit Cost Excellent Fair Good-ExcellentArchitecture Sea of Gates LUT varies
The Best Structured ASIC• Single mask• SOC or full-chip• RAM & logic• Excellent density &
performance
Page - 1111/21/2000www.ViASIC.com
ViASICViaMask eASIC
LeopardLogic
NECISSP ChipX
AMIXpressArray
Virage/LSIRapidChip
Number of Masks 1 1 1 3 3-5 6 4-12
Logic Architecture Sea ofGates
LUT LUT MetalProg
MetalProg
MetalProg
MetalProg
Simultaneously Available Logic& Embedded RAM
Yes No No No No Yes No
Equivalent Density vs. Standard Cell
70% 35% 20% 25% 35% 50% 25-75%
Typical Utilization 100% 50% 30% 70% 30% 70% 20-100%
Relative clock speeds 400 mhz 200 mhz 150 mhz 400 mhz 300 mhz na 300-500mhz
Manufacturing Time (weeks) 3 3 3 5 6 7 5-8
Physical Design Software available to end user
Yes No No No No No Yes
Available for use as embedded SOC block
Yes No No No No No Yes
Vs. Other SA Architectures
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DFM Issues
• Phase-shift coloring compatible• Repetitive structures can lead to yield
improvements• Redundant vias between in-line routing
segments• Uniform metal• Very wide power busses• Via-configured power-down of unused logic
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Synthesis
RTLNetlist
Tech MapperMemory Generation
Scan Chain ReorderingClock & Power Insertion
PlacementOptimization
RoutingDelay Calculation
SDF Annotation
Reordered Scan
Library
GateLevelNetlist
GDSOut
Verilogor VHDL
Pin Assignments
Page - 1411/21/2000www.ViASIC.com
Features
Timing driven placement Capacitance driven global routing Signal Integrity driven detailed routing Tie off of unused inputs Built in RAM generator Support traditional test flow with scan-chain interface to Tetramax Antenna violation detection and repair Buffer insertion for timing resolution Integrated clock routing Routing turn minimization Fast run times Efficient runtime memory usage Automatic selection of target footprint Integrates easily into existing tool flows Accurate delay simulation TCL interface for low level control Place & route an embedded block of an SoC or a full chip
Page - 1511/21/2000www.ViASIC.com
ViaPath Treatment of SI
• Simpler problem, since post-detailed routing changes are easily done
• Cross-talk fixed post 3-D extraction• Effective speedup of critical signals:
– Buffering, duplication, and gate sizing– During global route– During detailed route– Incrementally, after 3-D extraction
• True 3-D extraction of parasitics• White paper available
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Sample Design A
Process: AMS 0.35 4ML
Application: Fabric for Triad Semi (fabless structured ASIC manufacturer)
Footprint: 3x8 tiles
Die Size: 2.37mm x 2.98mm 7.06 mm2
• Sample design in this footprint was 35K gates & 3 memories
• ViaPath runtime of 45 seconds with memory usage of 152MB (on 1.8 GHz Opteron)
Page - 1711/21/2000www.ViASIC.com
Sample Design B
Process: TSMC 0.13 6ML
Application: Configurable Embedded Block of SOC
Footprint: 10x13 tiles
Die Size: 2.76mm x 3.71mm 10.24 mm2 w/power ring
• Initial Design for this footprint was 600K gates & 20 memories
• ViaPath runtime of 2.5 hrs with memory usage of 2.035 GB (on 1.8 GHz Opteron)
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For Microcontroller
• Two ViaMask fabrics– 0.25 4 ML in 5-50k gate footprints– 0.13 6 ML in 50-200k gate footprints
• Embedded Area could be– Single port SRAM– cache– Eprom
• Pick a single-footprint launch to cover ViASIC’s cost, Freescale can upgrade once proven.
Page - 2011/21/2000www.ViASIC.com
Contact Info
William Westhead
France +33 5 55 09 60 49
*
Max Lloyd, CEO
919-767-6941
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The Time Is Now
0100200300400500600700800900
2003
2005
2007
Dataquest: Structured ASIC Market Size
In $Millions
Sample Roll-out Plan
Page - 2211/21/2000www.ViASIC.com
Virage ASAP Metal Programmed Library• Each respin requires standard-cell like routing to be
rerun with corresponding closures of timing, signal integrity, and power.
• To approach ViaMask density Virage needs at least 6 masks (Via1 thru Metal 4). ViaMask uses only one mask, Via3.
• Memory in the Virage architecture is not reconfigurable.
• Customer should benchmark two netlists (designs) into same footprint for real world understanding of Virage density.
Page - 2311/21/2000www.ViASIC.com
Semiconductor’s Fastest Growing Segment
“Worldwide merchant market dollar shipments of
structured ASIC products are forecast to grow from the $5.2 million reached
[in 2002], to $460.3 million by 2007. This will
translate to a forecast Compound Annual
Growth Rate (CAGR), over the 2002 to 2007
forecast period, of 145%.”
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ViaMask FPGA Standard-cellTime to market Good Excellent PoorPerformance -Speed -Power Consumption
ExcellentExcellent
FairPoor
ExcellentExcellent
Size Good Poor ExcellentRisk (cost/schedule) should respin be needed Good Good PoorEDA cost Good Excellent PoorNRE cost Excellent Excellent PoorUnit part cost Excellent Poor Excellent
Structured ASICs - Solution– mask costs
– time to market
– yields
– advanced rules
– risk
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ST 0.13 6ML cell
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Increasing mask costs are limiting electronic innovation
One respin pays for a copy of ViaPath
ViASIC solutions enable new markets
Page - 2711/21/2000www.ViASIC.com
Details
Inputs
• Synthesized netlist in Verilog or VHDL
• Physical design data in .lib, LEF/DEF
• Timing constraints in SDC
Outputs
• Via photomask in GDSII
• Path delay data in SDF
• Auto pin assignment in TCL Scan chain reordering interface to Tetramax
• Print and plot data in Postscript
• Verilog for LVS & formal verification
Supported Platforms
• RedHat 32-bit Linux on AMD & Intel processors
• 64 bit Linux and Solaris also available
Page - 2811/21/2000www.ViASIC.com
ViaPath Features, Release Plan
2004.4• Spice Translation/Synthesis for Analog P&R• Skew of MUX balancing for additional timing resources• Configurable power, power estimation• Signal integrity driven routing (wire swapping/avoidance, shielding)• Path highlighting display• Complete timing driven (additional SDC support)• Timing modeling, reporting (include clock skew report)• Enable File/Print of Postscript Image
2005.2 • Fly line connectivity display• Scan chain link to Tetramax• Non-rectangular footprint support• Hierarchical design support, nested footprint support• LEF macro input
Page - 2911/21/2000www.ViASIC.com
Current Products
ViaMask– One-mask structured ASIC libraries– Announced May 2003
ViaPath– Physical design tool for one-mask structured ASICs
and VPGA– Announced May 2003
VRoute– Routing engine for standard-cell and metal
programmed structured ASICs– First tape-out March 2004, demo’d at DAC 2004– To be released