Diapositiva 1

COMBINED PAGING AND SEGMENTATION

CONTENTS A small review of Paging SegmentationCombined Segmentation and Paging Examples

PAGING

PAGINGPTBR and PTLRPageTable(One for each Process) allows the physical address space of a process to be non-contiguous

CPU generated Logical Address

Page# Offset

Pages Page FramesFrameTable(One of the Main Memory) Extends to any levels

PAGING HARDWARE

EXAMPLE-LOGICAL TO PHYSICAL ADDRESS TRANSLATION IN PAGING000001011101110

6-bit page #10-bit offset #16-bit logical address

00001011000110

0001100111011110

Page Table16-bit Physical address

ADVANTAGESNo external FragmentationSimple memory management algorithmSwapping is easy (Equal sized Pages and Page Frames)

DISADVANTAGESInternal fragmentationPage tables may consume more memory.Multi level paging leads to memory reference overhead.

HOW DOES USER VIEW MEMORY??An important part of the memory management is that become unavoidable with paging is the separation of the users view of the memory and the actual physical memoryThe users view is mapped to the physical memoryThus the differentiation comes between the logical and physical memory.

Do users view memory as linear array of bytes some containing instruction and other containing data??? NoRather they would see it as collection of segments.

SEGMENTATION

SO HOW IS IT FOR C COMPILER???C COMPILER

LOGICAL ADDRESSING IN SEGMENTATIONThe mapping of the logical address to the physical address is done with the help of the segment table.Segment LimitSegment BaseOther bits

SEGMENT TABLEA bit is needed to determine if the segment is already in main memory (P)Another bit is needed to determine if the segment has been modified since it was loaded in main memory (M)starting address of the corresponding segment in main memthe length of the segment

The segments of a program can be placed anywhere in the main memory.For each process in each execution, there is one segment address table.Segment-table base register (STBR) points to the segment tables location in memorySegment-table length register (STLR) indicates number of segments used by a program

EXAMPLE OF SEGMENTATION

EXAMPLE-LOGICAL TO PHYSICAL ADDRESS TRANSLATION IN SEGMENTATION000100011101110

12-bit offset #12-bit offset #16-bit logical address

0010001100010000

Segment Table16-bit Physical address00010111011100000010000000001011110011110001000000100000

LengthBase

16-bit seg base

SEGMENTATION HARDWARE

MMUSTBRSTLR

BaseLimitOtherSegment table

Seg 1(code)Seg 2(data)Seg 3(stack)

Logical MemorySegment #OffsetLogical addressmemoryaccess faultno

PhysicalmemorySeg 2(data)

Seg 1(code)Seg 3(stack)0x00

as in paging:valid, modified,protection, etc.offset