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Practical Considerations for the Design of Fully

Differential OTAs with SC-CMFB

Carlos D. Bula and Manuel JimenezElectrical and Computer Engineering Department

University of Puerto Rico, Mayaguez Campus

Mayaguez, PR 00681

e-mail:{carlos.bula, mjimenez}@ece.uprm.edu

Abstract—Practical considerations for the design of fully differ-ential OTAs and their switched-capacitor common mode feedback(SC-CMFB) network are presented. Different factors affectingthe system performance such as OTA gain, bandwidth, commonmode open loop gain and bandwidth, and CMFB parametersare discussed. The impact of varying CMFB capacitances andswitch sizes are analyzed by means of transistor level simulations.The results showed that larger capacitance ratios produce slowersettling times per cycle. However it is better to keep switch

widths and capacitances small since clock feedthrough and chargeinjection can cause significant errors in the steady state CMVoltage.

I. INTRODUCTION

Fully differential (FD) operational amplifiers are core el-

ements for the design of analog high performance systems.

These elements are used in a wide variety of applications, such

as audio amplifiers, analog filters, data converters (D/A and

A/D), modulators, instrumentation, etc. The fully differential

operation provides many advantages over its single ended

counterpart, such as, rejection to input common mode signals

(i.e. noise), much lower power supply sensitivity (PSS), higher

output dynamic range, and second order harmonics reduction.However high gain FD circuits require common mode feed-

back (CMFB).

A CMFB loop is used to stabilize the output common mode

(CM) voltage in differential circuits. The output CM level is

very sensitive to device properties and mismatches, and cannot

be precisely defined in the presence of differential feedback.

Thus a CMFB loop must sense the CM output level, compare

it to the reference CM value and accordingly adjust one of the

bias voltages of the amplifier to correct the output CM voltage

and force it towards the reference value [1].

There are two different types of CMFB networks: continu-

ous (C-CMFB) and switched-capacitor (SC-CMFB). C-CMFB

circuits are more suitable for continuous-time applicationswhere the output is valid at all times. SC-CMFBs are mostly

used in discrete type applications where the output is valid in

one phase of the clock and the effect of feedthrough can be

tolerated. Using a continuous CMFB network presents several

disadvantages over a switched-capacitor implementation. A

continuous network makes use of additional differential pairs

for detection and comparison of the output common mode

signal. This limits the linearity of the feedback when the

output is near to the power supply rails. In such situation

the transistors could go into cutoff or triode regions causing

detection errors and distortion. Another disadvantage of this

kind of CMFB network is the introduction of additional poles

affecting the differential frequency response. A SC-CMFB

network does not have these problems since it uses capacitors

to sense the CM voltage. The added capacitance increases the

amplifier’s loading, but does not introduce additional poles

that could affect stability. The most important advantage of the discrete network is the reduced power consumption. A

continuous implementation needs a permanent bias currents

since it uses active elements (differential pairs and current

sources). A SC-CMFB network uses elements that do not need

bias currents such as capacitors and switches, allowing for a

considerable lower power consumption.

Many analog circuit applications found in literature base

their designs on fully differential amplifiers but do not provide

details about the CMFB design [2], [3], [4], [5]. Only a few au-

thors address the design issues for SC-CMFB, providing some

design hints. However, they do not analyze the effect of such

considerations using a complete transistor-level OTA imple-

mentation [6], [7]. This paper presents practical considerationsin the design of fully differential Operational transconductance

amplifiers (OTAs) and their SC-CMFB networks based on the

results obtained from transistor-level simulations.

The rest of this paper is organized as follows. Sections II

and III describe the design’s OTA and SC-CMFB circuits,

respectively. Section IV discusses practical design consider-

ations for the SC-CMFB loop. Section V presents the results

of transistor-level simulations, emphasizing the effect of the

practical SC-CMFB design considerations on the OTA perfor-

mance. Lastly, concluding remarks are drawn in Section VI.

I I . FULLY DIFFERENTIAL OTA

This section describes the design of a fully differential OTAfor an oversampled data converter application. Specifications

for DC gain (AV 0), unit gain frequency (F 0−dB), phase margin

(PM ) , and current consumption (I suply) for the amplifier are

shown in Table I. A folded cascade (FC) topology (Figure

1) was chosen because it provides a high gain (≥60dB) and

large bandwidth at the same time. The folded cascode topology

behaves basically as a single stage configuration with high

impedance nodes located at the outputs. This characteristic is

desirable for high bandwidth (BW), fully differential OTAs,



because the dominant pole is given by the load capacitance

(C L). The remaining poles are located at much higher fre-

quencies where they do not affect the OTA’s AC gain response.

Attention must be paid to the load capacitance increase pro-

duced when the SC-CMFB network is added. The increase

of C L affects the OTA frequency response by shifting the

dominant pole to lower frequencies and thus reducing the unit-

gain frequency.

TABLE IFULLY DIFFERENTIAL OTA SPECIFICATIONS

AV 0 F0−dB PM Isuply

≥60dB 125MHz 60deg ≤ 500µA

Fig. 1. Fully Differential Folded Cascode OTA

Transistor sizes were calculated using the design equations

for a folded cascode topology [8]. The input differential pair

of the OTA was biased with a 250µA current (MB transistor),while each output branch holds a 125µA current (M5-M10).

It is important to mention that to achieve the unitary gain

frequency specification (125MHz), the load capacitance intro-

duced by the CMFB network was taken into account during

design and simulation. The next stage capacitance was 400fF

and another 300fF were considered to simulate the additional

load introduced by the CMFB network.

III. THE SC-CMFB NETWORK

The objective of the CMFB network is to sense the output

common mode signal (V cm = (V +cmo + V −cmo)/2), compare it

to the reference CM voltage (V cmref ) and control the output

CM voltage by manipulating the bias voltage applied to theamplifier (V cmfb). V bias is the reference biasing voltage which

is frequently generated by using a diode connected transistor

conducting the bias reference current of the output branch. In

this case the CMFB controls the bias voltages of transistors M9

and M10. The switched capacitor circuit used for the CMFB

is shown in Figure 2.

This SC-CMFB circuit works using non-overlapping clock

phases φ1 and φ2. During clock phase φ1 each of the C 1capacitors are charged to V cmref − V bias, and the V cmfb

Fig. 2. Switched Capacitor CMFB network

voltage is defined by C 2 capacitors which sense the output

CM level. In phase φ2 the corresponding C 1 and C 2 capacitors

are connected in parallel, causing the sensed output common

mode voltage (V cm) to be shifted by V cmref − V bias. This

makes the value of the control voltage to be defined as

V cmfb = V cm − V cmref + V bias. The SC-CMFB network and

the amplifier form a negative feedback control system where

the controlled variable is the output common mode voltage. If

V cm is higher than V cmref , the CMFB network will apply

a bias voltage higher than V bias. If V bias is increased the

current of M9 and M10 will increase, causing a decrease inV cm. The opposite occurs in the case when V cm is lower than

V cmref . The action of the control loop will make V cm reach a

steady value equal to V cmref . The CM voltage value will be

maintained at the reference value as long as the gain and the

bandwidth of the CM loop are high enough to stabilize the

variations [6].

IV. SC-CMFB PRACTICAL DESIGN CONSIDERATIONS

Practical considerations need to be taken into account when

designing Fully Differential OTAs that use SC-CMFB. The

most critical parameters for a good design are the open loop

CMFB gain (Acm) and BW. Acm needs to be as high as

possible for a better accuracy when V cm reaches the steadystate. As seen in equation (1), the steady state value of the

output CM voltage (V o[∞]) approaches the desired theoretical

value when the common mode gain (Acm) grows. In the

expression C p1 and C p2 are the parasitic capacitances of

switches S1 and S2, respectively; ∆Qtot and I Jeq represent

the charge injection and lekage errors, and T is the sampling

clock period. On the other hand, the CMFB BW should be as

large as the differential mode BW in order to track fast CM

variations [9]. As occurs with the Differential Mode (DM)

gain and BW, there is a relation between CMFB gain and

BW. The challenge is to obtain the highest CMFB gain while

having the required BW and still maintain the OTA required

specifications.

V o[∞] =

V cmref +

1 +C p1C 1

(V cmfb[∞] − V bias)

1 +

1

Acm

·

1 +C p1C 1

−

∆Qtot

C 1+

I Jeq ·T

2C 1

1 +

1

Acm

·

1 +C p1C 1

(1)



Equation (1) also allows to conclude that the steady state

CM output value is affected by the charge injection and leak-

age errors. The parasitic capacitances introduced by switches

S1 and S2 also have an impact on the final CM output

value. The analytical expression suggests that increasing C1

could reduce the steady state errors. However by increasing

this value alone the CMFB bandwidth gets reduced affecting

circuit performance.

To obtain the highest Acm two issues must be addressed.

The first is to determine which OTA bias point offers the

largest Acm while having the required CMFB BW. This de-

cision is also topology dependant. For a multi-stage topology,

a bias point of the first stage is frequently selected since this

option offers the highest gain. For a single stage configuration

such as folded cascode a current source from the output

branch is frequently selected due to the high sensitivity of

CM voltage to changes in that current. The second issue is to

maximize the Acm gain from the selected CMFB point without

compromising the the OTA specifications. An approach to

increase Acm for a folded cascode topology is to increase

gm9,10. To increase this parameter, the effective gate voltage(vgs10,11 − V tn) or the transistor size must be increased. This

could reduce the output swing significantly thus care must be

taken in order to keep the specification for this parameter.

As mentioned before, a fast enough CMFB loop is desirable

because it allows faster settling of the CM voltage and causes

less distortion in the output signal. Phase and gain margins

(PM and GM) of the common mode loop also need to be

verified to ensure stability. It is recommended to have PM of

60 degrees and a gain margin of 10dB. Poor margins would

cause slow settling and ringing of the CM signal. It is not

an easy task to make the CMFB BW comparable to the DM

BW, specially for multi-stage OTA configurations where the

DM and CMFB signal paths are different. In this last casethe CM signal path could include additional poles affecting

the frequency response and making the CMFB path slower

than the DM path. This could cause potential instability. To

overcome this problem there are two solutions. The first is

to use separate CMFB networks for each stage, in case of

having a multi-stage OTA. The other is to use a single stage,

high GBW OTA topology such as a folded cascode [10]. For

this last configuration the open loop CM BW is the same

as the differential mode (DM) bandwidth, as the dominant

pole affecting the DM response is the same affecting the CM

response. The remaining high frequency poles have no effect

over BW or stability.

ts =

ln(D)

lnβ

· T, (0 ≤ β ≤ 1) (2)

When designing the SC-CMFB network in Figure 2 the

parameters under control in the circuit are the sizes of capac-

itances C1 and C2, and the size of the switching transistors.

Changing these parameters affects the performance and spec-

ifications of the complete OTA. More specifically, the CM

voltage settling time, CM voltage accuracy, OTA bandwidth,

and chip area. The capacitance ratio C2/C1 (α) has an effect

over the V cm settling time (ts), which is defined by equation

(2). Where β is a variable that decreases as α decreases, and D

is the required normalized DC settling-time error tolerance [6].

For higher values of α the DC CM voltage settles faster after

startup. This suggests that C2 should be as small as possible

and C1 as large as possible. In the case of C2 this affirmation

is correct because a lower value will cause less loading to

the amplifier. On the other hand, C1 can not be too large

because it would require larger switches to keep the CMFB

network RC constant low. The use of larger switches increases

the charge injection error and requires more chip area. The

charge injection can be reduced by using the dummy switches

scheme shown in Figure 3.

Fig. 3. Dummy switches scheme to reduce clock feedthrough and chargeinjection

V. SIMULATIONS AND RESULTS

Transistor level simulations were performed using Spectre

simulator. The technology process used for the design was

AMI C5 (0.6u). The supply voltage was 3.3 V and the

reference common mode voltage (V cmref ) was 1.65V.

The parameters of the CMFB network were changed to

observe what the effect in the performance was. Figure 4

shows output CM and CFMB voltages. In this case thesimulation was performed without using dummy switches.

The effect of clock feedthrough and charge injection can not

eliminated, but can be reduced by adding dummy switches as

shown Figure 5. This is not a major issue in discrete time

applications since the output is only valid during phase φ2when the V cm voltage settles to the correct value.

Fig. 4. V cm and V cmfb settling with no dummy switches. C 1 = 200 pF ,C 2 = 100 pF , (W/L)Switch = 6/0.6

The results in Figure 6 were obtained by doubling the

capacitance ratio α (increased C1 from 200fF to 400fF).

When comparing the results with those in Figure 4 it can



Fig. 5. V cm and V cmfb settling with dummy switches and α = 2. C 1 =200 pF , C 2 = 100 pF , (W/L)Switch = 6/0.6

be seen how the DC V cm settles faster. It should be noted

that with α = 2, V cm settled to 1.6386V and for α = 4V cm settled to 1.6442V. This last value of V cm is nearer

to V cmref , suggesting that increasing α also improves the

accuracy. The increase in the value of C1 also increases the

time constant of the CMFB network producing higher settling

time per cycle. The strategy for solving this problem could be

increasing the switches width. However, as shown in Figure7 this causes a significant deviation (-0.1333V) in the CM

voltage when compared to V cmref . This is a consequence

of the higher clock feedthrough and charge injection errors

introduced by using larger switches. These results suggest to

keep transistors sizes and capacitances low.

Fig. 6. V cm and V cmfb settling with dummy switches and increased α.α = 4 , C 1 = 400 pF , C 2 = 100 pF , (W/L)Switch = 6/0.6

Fig. 7. V cm and V cmfb settling with dummy switches and increased(W/L)Switch . α = 2, C 1 = 400 pF , C 2 = 100 pF , (W/L)Switch =24/0.6

Table II summarizes how changing the mentioned parame-

ters (Acm, BW CM , C 1, C 2 and W switch) improved the OTA

and CMFB performance.

TABLE IIEFFECT OF PARAMETERS VARIATION IN CMFB NETWORK

Effect Acm BWCM C1 C2 WSwitch

DC Vcm Settling time ↓ - ↑ ↑ ↓ ↑

Vcm Accuracy ↑ ↑ - ↑ - ↓OTA BW ↑ - ↑ - ↓ -

Charge injection error ↓ - - ↓ - ↓

VI . CONCLUSION

Important practical considerations for the design of a fully

differential folded cascode OTA using SC-CMFB were pre-

sented. The principal factors influencing the performance of

the FD OTA and the common mode feedback include the OTA

open loop gain and bandwidth, CMFB open loop gain, and SC-

CMFB network component values such as capacitances and

switch sizes. The parameters of the SC-CMFB were modified

during transistor level simulations and the effect on the OTAperformance was observed. According to the results, it can

be concluded that the capacitance ratio in the CMFB network

needs to be as large as possible for faster DC settling of the

common mode voltage and better accuracy. However having

a larger C1 will produce slower settling times per cycle. It

is better to keep switch widths and capacitances small since

clock feedthrough and charge injection cause significant errors

in the steady state CM Voltage.

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