Name :- Smit Shah -140410109096

S.Y electrical 2 Sem 4

Subject:-Digital Electronics

Topic :- Parallel Adder and Subtractor….

The n-Bit Parallel Adder:The full adder is capable of adding only two

single digit binary numbers along with a carry input.

But in practice we need to add binary numbers which are much larger in size than just one bit. The Two binary numbers to be added could be 4 bit, 8 bit, 16 bit long. In general we assume that both the numbers are n bit long.

It uses a number of full adders which are connected in cascade.

The carry output of the previous full adder is connected to the carry input of the next full adder.

A Four Bit Parallel Adder Using Full Adder..The block diagram of a four bit parallel adder

using full adders is show in fig. Lets the two four bit word that are to be added be A and B.

A=A3 A2 A1 A0 B=B3 B2 B1 B0

Hence Full Adder -0 is the lowest stage. Hence its cin has been connected to 0 permanenty.

The rest of connection are exactly same as those done for the n-bit parallel adder.

The 4-bit parallel adder is a very common logic circuit. It is normally shown by a block diagram as shown in fig.

An n-bit parallel adder requires n full-adders It can be constructed from 4-bit, 2-bit and 1-bit

full-adders ICs by cascading several packages.

The 4-bit binary parallel adder is a typical example of an MSI function.

It can be used in many applications involving arithmetic operations.

The application of this MSI function to the design of a combinational circuit is demonstrated in the example of BCD to excess-1 code converter.

CARRY PROPAGATION The addition of two binary numbers in parallel

implies that all the bits of the augend and the addend are available for computation at the same time.

As in any combinational circuit, the signal must propagate through gates before the correct output sum is available in output terminals.

The total propagation time is equal to the propagation delay of typical gate times the number of gate levels in the circuit.

The longest propagation delay time in a parallel adder is the time it takes the carry to propagate through the full-adders

N-Bit Parallel subtractorThe subtractor can be carried out by taking

1s or 2s complement of the number to be subtracted.

For example we can perform the subtraction (A-B) by adding either 1s complement or 2s complement of B to A. that means we can use a binary adder to perform the binary subtraction..

4 bit parallel subtractor using 2s complementA 4-bit parallel subtractor using 4 bit parallel

adder is shown in fig.

The number to be subtracted B is first passed through inverters to obtain its 1s complement. One inverter per bit of word B is used so that all bits of B get inverted.

Then 1 is added to 1s complement of B, by making cin=1. Thus we obtain the 2s complement of B.

The 4-bit adder then add a and 2s complement of B to produce the subtraction at its sum output .

If A>B then c out =0 and the result is in true binary form but if A < B then c out=1 and the result is negative and in the 2s complement form…