parallel i/o
DESCRIPTION
Parallel I/O. Introduction. This section focuses on performing parallel input and output operations on the 68HC11 3 operation types – Simple, blind data transfers – Strobed transfers – Transfers with handshaking Contd. - PowerPoint PPT PresentationTRANSCRIPT
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Parallel I/OParallel I/O
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Introduction
This section focuses on performing parallelinput and output operations on the 68HC11 3 operation types– Simple, blind data transfers– Strobed transfers– Transfers with handshaking
Contd
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SEGMENT code
Look at examples of each transfer
operation
Reading:
– Text, Chap 9:
» Read: 9.1, 9.4-9.8.1
» Scan: 9.2, 9.3
– E9: Section 6
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Recall the block diagram of the 68HC11
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Simple I/O operations
These I/O operations take place under the direction
of the processor
Operations are performed without regard to the
status of the I/O port –
the port is always assumed to be "ready“
contd
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Since the current status of the port is not known, it
is possible to
– Read the same value in more than once on input
operations
– Overwrite the current value in an output port that is
waiting to be transferred
"Good" examples of use:
– Input initialization values from a port -- port is in
known state as a result of system reset
– I/O when overwrites or multiple reads don't matter --
writing to the hex display’s port in the labs, for
example
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Simple I/O example -- keypad interface
– Consider the simple 12-key keypad shown
below
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High-level procedure to detect key closures
» Drive Row 1 input low
» Read Columns -- any =0?
» Repeat this process for all remaining rows until
“see” a column=0
» If no column=0, then no key has been depressed
CONTD
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Knowing which row and column were low permits
you to calculate the key number that was pressed
» Can use a simple equation (similar to the
approach of Listing 9.5)
– Key# = col# + (3*row#) -3
– Assumes row and col numbers start with 1
– Listing 9.5 is for 2-of-7 keyboard!
» Or use a lookup table (similar to the approach in
Listing 9.10)
– Assumes row and col use same port (port C
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– Key debounce
» Need to avoid the multiple make/break closures
associated with key bounce
» “Simple” approach is ID the key closed and then
wait for a period of time to see if the key is still
closed (therefore not bouncing)
» Then and only then, return the key value
» The waiting period will vary from switch to
switch -- 10s to 100s of ms
CONTD
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– How will the system react if you hold a key down for
a long time?
» Should an action (in response to a key closure) be
repeated over and over despite there being only 1
switch closure “action”
» Should the action take place only once and then
wait for the key “break” before recognizing
another closure?
» Consider routines to recognize key makes and
breaks
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Strobed I/O
This method of performing I/O operations uses a
control line, the strobe, to notify the receiving unit
of the availability of data at its (input) port
CONTD
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Strobed I/O
Contd…
The process:
– Device performing the write places data onto data
bus (its output port)
– Strobe signal is asserted (for 2 cycles in 68HC11)
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– Strobe signal causes an I/O interrupt to occur or a
flag to be set -- in either case the receiving device is
signaled that new data has arrived
– It is up to the receiving device to read the new data at
its input port in a "timely" fashion
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Problem
– If a second data item arrives at the input port and is
strobed in (latched) before the input device has read
the first item, the first item will be overwritten and
lost
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68HC11 register support for strobed I/O
– DDRC -- data direction register for port C
– PORTCL -- port C input latch -- data is latched
on STRA edge
– PORTC -- input pins for port C -- not latched
– PORTB -- latched output data port B -- outputs
data using STRB
– PIOC -- parallel I/O control register
– PORTD -- bits 6 and 7 are STRA and STRB
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Strobed input operations using port C– Data is placed at the input pins of port C
– STRA is asserted by peripheral device, causing
» Data to be latched into PORTCL
» STAF flag to be asserted
» Interrupt initiated, if interrupts are enabled
– Data is read into to processor from PORTCL
– To clear STAF, read PIOC first then PORTCL
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Strobed Output– Peripheral device is connected to Port B
– When the MCU writes to Port B, . . .
» Data is placed on Port B pins
» STRB is asserted for 2 clock cycles
– Peripheral device should use STRB to latch the
data
– STRB can be configured as active-high or
active-low
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Handshaking I/O
In this mode, the sending and receivingdevices exchange positive sent/receivedsignals to one another
– Insures that each transmitted word is receivedbefore the next word is transmitted
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SHR
Transfers can occur in either the pulsed or
the interlocked method
– Pulsed input operations
» Peripheral pulses STRA to indicate that data
is present
» When 68HC11 reads the data (from
PORTCL), it automatically generates an
acknowledgment strobe on STRB for 2
Cycles
CONTD
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SAR
» This mode is selected by initializing the PLS
bit (bit 2 of the PIOC) to 1
– Interlocked input operations
» Here, STRB acts as a READY signal
» Asserted = 68HC11 ready to receive data
» Negated = 68HC11 is not ready -- do not
send data now
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Output operations with handshaking
– Port C is used for output handshake operations, along
with STRB and STRA
– STRB is the output "data available" strobe
– STRA is the acknowledgment / input ready strobe
line
– PIOC bit 3, OIN, set to 1 for output operations
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– Pulsed operations
» 68HC11 writes data to PORTCL and
automatically asserts STRB for 2 cycles
» Peripheral device reads data upon receipt of the
STRB strobe
» Peripheral asserts its READY line (68HC11's
input STRA line) to signal receipt of data
» PIOC bit 2, PLS set to 1 for pulsed mode
– Interlocked mode
» Upon writing data to PORTCL, STRB is asserted
» STRB negated only upon ACK
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Handshaking example:
Centronics parallel printer interface
– The "Centronics" definition of a printer port
interface has become the standard parallel
printer interface
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– Using the 68HC11 as the output device (to the
printer) requires a software interface
(note the errors in the text!)
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; I/O service routines to control "Centronics" interface
; part of printer control system. Also demonstrates
; software handshaking because port C configured
; for simple input strobe. Main program would call
; service routines to store input data in a RAM print
; buffer for later output to print mechanism.
CONTD
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;;;
CONNECTIONS
; Computer Printer Port MCU as Printer Controller
; DATA -----------------> Port C
; STB -----------------> STRA
; ACK <----------------- PD2
; BUSY <----------------- PD
CONTD
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PIOC CONFIGURATION DETAILS
; INVB=x STRB not used
; EGA=0 STRA/ACK active on falling edge
; PLS=x Pulsed/Interlocked not used
; OIN=x Output/input handshake not used
; HNDS=0 Simple strobe mode
; CWOM=0 Normal CMOS outputs
; STAI=0 Disable interrupt
; STAF=x Sets on falling STRA line
; To clear STAF, read PIOC, then read PORTCL
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ORG $100
; Subroutine INIT_INTRF
; Initializes parallel interface part
; of printer upon power-up reset.
; Calling Registers:
; IX = Address of register block
; No Return Registers except CCR affected
CONTD
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INIT_INTRF:
psha ; preserve registers
ldaa PIOC,X ; clear STAF if set
ldaa PORTCL,X
bset PORTD,X $0C ; PD2, 3 output and
bset DDRD,X $0C ; BUSY, ACK high
ldaa #00 ; configure PIOC
staa PIOC,X
pula ; restore registers
rts ; and return
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; Subroutine INPUT
; Reads parallel port to get byte sent
; by an external device
; Calling registers
; IX = Address of register block
; Return registers
; ACCA = input data byte
; CCR affected
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INPUT:
bclr PORTD,X $0C ; BUSY low and pulse ACK
nop ; for approx 5 us (E=2MHz)
bset PORTD,X $04 ; set ACK high again
CIN:
brclr PIOC,X $80 CIN ; wait for STB pulse
ldaa PORTCL,X ; get input and clear STAF
bset PORTD,X $08 ; set BUSY high
rts ; return
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Parallel subsystem summary Ports B and C are available for I/O only in the
single chip mode -- can be replaced by the PRU
when in expanded mode
Port A
– 3 input, 3 output, 2 bi-directional pins
– Bits DDRA7 and DDRA3 in PACTL set direction
for A7 and A3
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Port C
– Data register is PORTC
– Latched register is PORTCL
– Each bit is bi-directional
» Direction set using register DDRC
Port D
– 6 bi-directional pins, directions set by DDRD
– Pin 6 = STRA, Pin 7 = STRB
» These pins become AS and R/W* in expanded multiplexed
mode
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Port E
– 8-bit input only
Conditions on reset
– All data direction bits set to 0 (input)
– Output port bits set to 0
– Input port bits high impedance
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Strobed I/O
– Strobed output via Port B, strobed input via Port C
– Detected edge on STRA causes input data to be
latched in PORTCL and flag set (and interrupt, if
enabled)
– Writing data to Port B also pulses STRB
Handshake I/O
– Port C used for either input or output operation
– Input: read data from PORTCL
– Output: write data to PORTCL