Parametric Fault Isolation TesterCapstone 2014Sponsored by IntelAdvisor: Dr. Robert

Daasch

Team Members:Phuong Ho, Ben Schwarz, Padmashree Patil, Gary Davis,Nicholas Klein

Department of Electrical and Computer Engineering

Fault isolation methodologies at Intel Corporation currently rely on using more than one testing with varying degrees of success and associated costs. These solutions have various components attached to Intel microprocessor pins which can cause moving the Unit Under Test (UUT) to other test equipment difficult. Moving the UUT between equipment has the potential to introduce error into the fault isolation. A low cost, all encompassing tester is needed.

Develop Tester Interface Unit: Universal Backplane PCB Product Specific Family PCB Interconnection Cables

Develop Automated National Instruments LabView Tests: Board ID Boot Up Standard Test Pins

Curve Tracing Shorts and Opens Latch Up

FLIR Image Capture Automated Report Generation

Design Universal Backplane PCB: Enables connectivity to test equipment. Allows for JTAG support of the part. Design for useful life of > 6 years. Smallest possible footprint

Design a set of automated LabView Tests User friendly GUI Automated tests as well as user controlled

options. All test performed from one test station Large main program is composed of smaller

blocks

Design Product specific family PCB: Specific to each family of Intel Silicon Sandy Bridge, Broadwell, etc. Breaks out small pitch pins of microprocessor to

common interface. Socket able such that you can test multiple

products with one board.

[LabView pic of GUI]

A total system solution that not only decreases required test time but reduces cost of testing.

[Pic of how overall system set up]

Some paragraph about why this solution is so great.

Some paragraph about Intel and PSUs collaboration.

Some paragraph about where our capstone will go after we’ve all left.

Problem Statement

Proposed Solution

Strategy Results