pcb

Ericsson Internal REQUIREMENTS SPEC.

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Prepared (also subject responsible if other) No.

ERABENY 105 82-110 Uen Approved Checked Date Rev Reference

EAB/FST/Z (Jordanis Caracolias) 2011-12-21 Y

Printed boards for hole- and surface-mounted components. Mechanical product requirements

Abstract

This standard contains product requirements for single-sided, double-sided and multilayer printed boards in its finished form for hole- and surface-mounted components.

Application

The standard is to be applied within Ericsson for printed boards in accordance with the abstract.

Requirements other than those stipulated in this standard shall apply if it is specified in the product documentation.

If printed boards are to be used for experimental purposes, etc., deviations are permitted to the extent decided by the office responsible for the product.

Supplementary documents

124 42-103 Uen Handling and storing of printed boards.

UL 94 Underwriters Laboratories Test for Flammability of plastic materials for parts in devices and appliance.

UL 796 Printing-wirings boards.

IPC-4101 Specification for base materials for rigid and multilayer printed boards.

IPC-4562 Metal foil for printed wiring applications.

IPC-TM-650 Test method 2.1.1, 2.4.1, 2.5.5.3, 2.5.5.9 and 2.3.41.

IPC-SM-840 Qualification and performance of permanent polymer coating (solder mask) for printed boards.


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IPC/EIA J-STD-003 Solderability test for printed boards.

ANSI/J-STD-004 Requirements for soldering fluxes.

IPC/EIA J-STD-006 Requirements for electronic grade solder alloys and fluxed and non-fluxed solid solder for electronic soldering applications.

PC/JEDEC J-STD-020 Moisture/Reflow sensitivity classification for nonhermetic solid state surface mount devices.

Contents 1 Terminology ............................................................................................. 8 2 Standard atmospheric conditions for referee tests ............................ 8 3 General requirements/workmanship..................................................... 8 4 Examination ............................................................................................. 9 5 Reference system.................................................................................... 9 6 Base material ........................................................................................... 9

6.1 Requirements .............................................................................. 9 6.2 Board thickness ......................................................................... 10

7 Survey of dimensions ........................................................................... 11 8 Conductive pattern (plating included) ................................................ 12

8.1 Conductor width ........................................................................ 12 8.2 Annular ring for mechanically drilled holes ............................... 13 8.3 Soldering surface ...................................................................... 14 8.3.1 Size............................................................................................ 14 8.3.2 Position ...................................................................................... 14 8.4 Conductor spacing .................................................................... 14 8.5 Edge spacing to conductive pattern.......................................... 15 8.6 Defects ...................................................................................... 15 8.6.1 Nicks in conductors ................................................................... 15 8.6.2 Protuberances ........................................................................... 16 8.6.3 Surplus foil................................................................................. 16 8.6.4 Scratch ...................................................................................... 16 8.6.5 Nicks in soldering surfaces or contact fingers .......................... 17 8.6.6 Separation of conductive pattern .............................................. 17 8.7 Supplementary pattern .............................................................. 18

9 Holes ....................................................................................................... 18 9.1 Mechanically drilled holes ......................................................... 18 9.1.1 Dimensions................................................................................ 18 9.1.2 Hole position.............................................................................. 19 9.1.3 Burr height ................................................................................. 20 9.1.4 Resin smear .............................................................................. 20 9.1.5 Resin recession ......................................................................... 20


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9.1.6 Residues on hole walls. ............................................................ 21 9.1.6.1 Not plated holes ........................................................................ 21 9.1.6.2 Plated-through via holes ........................................................... 21 9.1.7 Resin fill in viaholes................................................................... 21 9.1.7.1 Buried via................................................................................... 21 9.1.7.2 Vias in pad with lid .................................................................... 21 9.1.8 Partially filled via (Plugged via) in pad ...................................... 21 9.2 Specific requirements for microvia holes .................................. 22 9.2.1 Holes ......................................................................................... 22 9.2.2 Minimum annular ring................................................................ 22

10 Design ..................................................................................................... 22 10.1 Outline position.......................................................................... 22 10.2 Outline dimension...................................................................... 23 10.3 Corners ...................................................................................... 23 10.4 Bow and twist ............................................................................ 24

11 Defects on base material ...................................................................... 25 11.1 General ...................................................................................... 25 11.2 Edge damage ............................................................................ 25

12 Surface treatment .................................................................................. 25 12.1 Copper electroplating ................................................................ 25 12.1.1 Appearance ............................................................................... 25 12.1.2 Thickness .................................................................................. 26 12.1.2.1 Hole walls .................................................................................. 26 12.1.2.2 Conductors ................................................................................ 26 12.1.3 Ductility and adhesion ............................................................... 27 12.2 Electroless nickel/gold plating ................................................... 27 12.2.1 Appearance and surface defects .............................................. 27 12.2.2 Adhesion.................................................................................... 27 12.2.3 Thickness .................................................................................. 27 12.2.4 Gold content .............................................................................. 27 12.3 Organic preserved solderability (OSP) ..................................... 27 12.3.1 Appearance and surface defects .............................................. 27 12.4 Gold for edge printed board connectors/ hard gold.................. 27 12.5 Mechanical defects ................................................................... 28

13 Solder mask ........................................................................................... 28 13.1 Requirements ............................................................................ 28 13.1.1 Requirements according to IPC-SM-840 .................................. 28 13.1.2 Requirements that differ from IPC-SM-840 .............................. 28 13.1.2.1 General requirements ............................................................... 28 13.1.2.2 Thickness of the solder mask ................................................... 29 13.1.2.3 Breakdown voltage.................................................................... 29 13.2 Design of the solder mask for conductive pattern .................... 29 13.2.1 Lands for plated-through via holes ........................................... 30 13.2.2 Solder mask between soldering surface and land.................... 30 13.2.3 Solder mask between soldering surfaces ................................. 30 13.2.4 Distance between solder mask and not plated holes or outline31 13.3 Mechanical defects ................................................................... 31


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14 Solderability ........................................................................................... 31 14.1 Test............................................................................................ 31 14.2 Shelf life ..................................................................................... 32

15 Legend .................................................................................................... 32 15.1 Identity ....................................................................................... 32 15.2 Printing material and other printing placement ......................... 33

16 Purity....................................................................................................... 33 17 Test.......................................................................................................... 33

17.1 Environmental test .................................................................... 33 17.1.1 Boards for lead-free soldering, thermal test ............................. 33 17.1.2 Thermal shock test, continutity and microsection..................... 33 17.1.3 Moisture and insulation resistance test (SIR) ........................... 34 17.2 Electrical test ............................................................................. 34

18 Flammability........................................................................................... 34 19 Handling and packing ........................................................................... 34

19.1 X-Out ......................................................................................... 34 20 Repair...................................................................................................... 35

20.1 Excision of short circuit ............................................................. 35 20.1.1 General ...................................................................................... 35 20.1.2 Requirements ............................................................................ 35 20.2 Repairs of solder mask ............................................................. 35 20.2.1 General ...................................................................................... 35 20.2.2 Requirements ............................................................................ 35

21 Impedance requirements...................................................................... 36 22 Requirements for specific boards ....................................................... 36

22.1 Boards designed with a shielding layer of printed carbon inc. . 36 22.1.1 General requirements ............................................................... 36 22.1.2 Requirements on the printed carbon pattern ............................ 37

23 Requirements that may occur in older product documents. ........... 37 23.1 Related to section 6.1. Layer drawing ...................................... 37 23.2 Related to section 8.1. Conductor width pattern class 1--8 ..... 37 23.3 Related to section 8.4. Conductor spacing pattern class 1--8 . 37 23.4 Related to section 9.1.1. Hole tolerances for boards with HASL38 23.5 Related to section 9.1.8, 3rd bullet and 17.1.1 .......................... 38 23.6 Related to section 12. Hot air solder leveling (HASL) .............. 38 23.7 Related to section 12.2 ............................................................. 39 23.8 Related to section 13.1 ............................................................. 39 23.9 Related to section 13.1.2.2 ....................................................... 39 23.10 Related to section 13.2.1 .......................................................... 39 23.11 Related to section 17.1 ............................................................. 40

24 References ............................................................................................. 40 25 Change Information .............................................................................. 41


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Survey

This survey presents the performance of 105 82-110 in n abbreviated form. See the reference paragraph for the full description of the requirements.

Characteristic Requirements Paragraph Reference conditions Temperature 23 +/- 1 Cel.

Relative humidity 50 +/- 5% Rh. Air pressure 86 -- 106 kPa.

2

Base material According to IPC-4101, IPC-4562 or product documentation. 6.1 Board thickness According to product specification 1301-/130 40-. 6.2 Conductor width According to product specification 1301-/130 40-. Etch compensation, recommended. 8.1 Minimum annular ring PTH. Maximum 90 degrees breakout, to conductors minimum 0.05mm 8.2 Tolerance on pad size Pad size. Tolerance at the top. Maximum dimension at the bottom.

> 0.55 mm +/- 0.05 mm Not specified. ≤ 0.55 mm +/- 0.03 mm Maximum, top dimension plus 0.05 mm.

8.3.1

Pad position According to the table. 8.3.2 Conductor spacing According to product specification 1301-/130 40-. 8.4 Minimum edge spacing to conductive pattern

Requirements see All layers: Pattern -- board edge ≤ 0.2 mm in CAD then requirement = 0 mm.

8.5

Nicks in conductors Maximum 20% reduction of the width at 5 mm in length. Ground/voltage layer, void size max 1 mm.

8.6.1

Protuberances and surplus foil

Must not reduce minimum conductor spacing. 8.6.2 &8.6.3

Scratch Maximum 20% reduction of the cross section area. 8.6.4 Nicks in pad Maximum 2 nicks/pad, 20% of length and 10% of width. 8.6.5 Separation of conductive pattern

Not permitted 8.6.6

Hole tolerances (mechanically drilled) if tolerance is not stated in 1301-/130 40

Not plated holes + 0.10/-0 mm ---"--- H > 6.2 mm See table 10.2 Plated holes +0.15/-0 mm Via holes No tolerance req. only annular ring Perforation holes (boards in panel) No tolerance requirements.

9.1.1

Hole position Tolerance class 4 according to the table. Second drilled holes, tolerance class 3 according to the table.

9.1.2

Burr height Not plated holes. Maximum 100 µm Plated holes or pattern to the board edge. ---”--- 25 µm

9.1.3

Resin smear Maximum 25% of the circumference of the hole. 9.1.4 Resin recession Maximum 40% of the cumulative base material thickness. 9.1.5

Residues on hole wall (not plated hole) PT - via holes

Tenting holes: (I.e. holes with lands) Residues of foil must not be more than 20% of the length or circumference of the hole Without lands: Some residues of Ni/Au plating on the hole walls are allowed if there are no loose residues. Some residues of solder mask is allowed in the via holes

9.1.6

Resin fill in viaholes Buried via, blind via and filled PT-via shall be totally filled with resin. Via in pad/test point shall have a lid and maximum dimple of 25 µm.

9.1.7

Partially filled via in pad. Must be plugged from the board’s side as stated in 1301-/130 40. The hole must be completely blocked and the plug must not extend above the Cu surface.

9.1.8

Microvia Minimum hole size at the bottom, 50 µm Maximum 90 degrees breakout, no breakout on stop layers.

9.2.1 9.2.2

Microvia in pad Maximum hole size at the top (holes through one dielectric layer), 130 µm Bare copper in the via hole is not permitted

9.2.1


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Maximum dimple for Cu-filled microvia is 25 µm Outline position Tolerance of the outline position is +/- 0.20 10.1 Tolerance on outline dimension

Distance. Class 1 & class 2. 0 -- 30 mm +/- 0.10 mm (30) -- 120 mm +/- 0.15 mm (120) -- 367 mm +/- 0.20 mm (367) – 1000 mm +/- 0.30 mm

10.2

Bow and twist Maximµm 0.7% or 0.5% for some boards. Board thickness 0.8 --(2.4) mm. 10.4 Defects on base material Cracks, blisters, delamination or exposed fibres is not permitted. Other defects

according to IPC-A-600 product class 2. 11.1

Edge damage Minimµm edge spacing to pattern must not be reduced. The maximµm length, 5 mm or 10% of the board’s edge.

11.2

Copper plating

Pits, cracks, burnt plating, nodules or particles are not permitted. Voids, maximµm 1/hole in no more than 5% of holes and maximµm 5% of the depth or circµmference of the hole.

Board thickness/hole depth. Cu-thickness in the hole walls > 2.5 mm 25/20 µm 2.5 -- 1.3 mm 20/18 µm < 1.3 mm 15/13 µm Microvia hole 10 µm Pressfitt According to 1301-/130 40-.

Thickness of the conductors. According to the product specification 1301-/130 40-.

12.1

Electroless nickel/gold plating

Maximum 2 voids (defects) /pad in no more than 5% of pads and not exceeding 5% of each individual area. No adherence of gold on tape after test is permitted.

Thickness: Nickel 3 -- 8 µm Gold 0.05 -- 0.15 µm.

12.2

OSP An even surface without crystals and foreign particles and withstand 3 reflow (LFS) cycles.

12.3

Edge board connectors/hard gold

Nickel min 2.5 µm. Gold min 0.8 µm.

12.4

Mechanical defect on surface treatment

Scratches on pads or contact areas is not permitted if Cu is exposed. A maximum of 4 indentation ≤ 15 µm on each individual area are perm itted.

12.5

Solder mask, general requirements and performance

IPC-SM-840. Flammability Class H, Electrochemical migration Class T No mask on the tape after tape test.

Thickness: Maximum 12 µm higher than the pad Minimum, shall withstand the breakdown voltage (250V or 500V ) according to the prod. spec. 1301-/130 40-.

PT - via holes lands partially covered by mask. The mask opening must not go outside the land’s edge. Solder dam must exist if the dimension in CAD data is ≥0,08 mm or 0.07 mm No mask on pads. Adjacent pattern to pads/lands must be covered by mask. Scratches must not expose Cu.

13.1.1 13.1.2.2 13.1.2.3 13.2.1 13.2.2--3 13.2.3 13.3

Solderability Test method and requirements according to IPC/EIA J-STD-003. Test E or E1 for boards with SMD components. Shelf life min 6 months. Boards having OSP see 14.1

14.1

Legend Boards must be marked with product number, R-state, manufacture’s code, time of manufacturer and HF (halogen free) if stated in 1301-/130 40-. Flammability rating and UL recognized marking according to product specification 1301-/130 40-. Marks added by the manufacturer see 15.1

15.1

Printing material and other printing placement

The material must not interfere with pads/ connectors. No print marking is allowed within the area marked with corner markings in copper or solder mask

15.2

Purity The cleanliness from ionizable surface contaminants (max. 1.0 µg NaCl/cm2) and minimum insulation resistance must be fulfilled

16

Boards for lead-free soldering, thermal test

The PB must withstand 4 soldering process with a reflow profile within the limits stated in IPC/JEDEC J-STD-020. The time must be minimum 20 seconds with the required peak temperature of 260 /-5° C.

17.1.1


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Thermal shock test, continutity and microsection

A maximum of 10% resistance increase. Test method: IPC 2.6.7.2 17.1.2

Moisture and insulation resistance test

Resistance must not be below 100 Mohm after exposure to moisture. Test method: IPC 2.6.3

17.1.3

Electrical test All boards shall be 100% continuity and insulating electricial tested. 17.2 Flammability 94 V-0 is normally required. Test according to UL 94 and UL 796. 18 Handling and packing See 124 42-103. If ESD approved plastic is NOT required by the customer, it has to be

stated in the purchase documentations 19

X-out Only permitted if stated in the product documentation 19.1 Repair by welding Only permitted on external layer with some limitations 20 Excision of short circuit A maximum of 6 excisions per board. No damages of the base material.

The requirements on conductor width/space must be met. 20.1

Repairs of solder mask After repairs, the same requirements as for the solder mask on the board must be fulfilled.

20.2

Impedence requirements

If (Zdiff) or/and (Z0) are stated in 1301--/130 40-, the verification of the requirements shall be done

21

Additional requirements for PB with layer of printed carbon inc.

General requirement See ==>

Requirement on carbon pattern see See ==>

22.1.1 22.1.2

Requirements that may occur in older product documents.

Requirements see 23.1—23.11


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1 Terminology CAD-data is defined in this standard as the information interface between design and production.

Partially filled via (Plugged via) is a via hole that is not completely filled by e.g. solder mask.

Filled via is a via hole that is completely filled with resin and with or without a Cu-lid (cap).

Cu-filled microvia (solid microvia) is a microvia-hole that is filled up with copper.

Advance/special design is a board that is design according to special rules decided by the office responsible for the product. Since this is not stated in 1301-/13040- at present (will be when the rules is updated) the dimensions in the CAD-data determine the requirements.

2 Standard atmospheric conditions for referee tests Temperature 23 +/- 1 Cel Relative humidity 50 +/- 5% Rh Air pressure 86 -- 106 kPa

3 General requirements/workmanship Printed boards manufactured according to this standard must meet or exceed stated requirements. The printed boards shall also be of professional quality and must meet such requirements that can be considered as being standard, although not explicitly stated.

In the event of conflict the following order of precedence shall apply:

1 Product documentation. 2 This document. 3 IPC-A-600 (Class 2)

PBs fabricated to the requirements of this document shall be processed in such a manner as to be uniform in quality and to preclude the introduction of dirt, foreign matter, oil, fingerprints, flux residues, or other contaminants that may affect the life or serviceability of the product. PBs shall be free of defects in excess of those allowed by this document. Acceptance of imperfections not specifically covered by this document shall be agreed upon by the user and supplier of the product.


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The manufacturer must have a system for process control and upon request during verifications or new product introduction the manufacturer shall be able to present product related simulation or test data to Ericsson.

If "Lead-free soldering" is stated in 1301-/130 40- the PB will be soldered in a Pb-free soldering process with a reflow profile within the limits stated in IPC/JEDEC J-STD-020. Requirements see 17.1.1.

4 Examination The measuring tools and equipment for visual examination shall have an accuracy and readability suitable for the dimension and tolerance to be measured. The magnification must also be adapted to the need, if nothing else is stated.

5 Reference system The primus datum point (normally as one of the fiducial marks, see fig 7) shall be physically discernible on the printed board.

6 Base material

6.1 Requirements

The base material must meet the requirements specified in the product specification (1301-/130 40-) or in the layer drawing and must also be RoHS compliant. If nothing is stated in 1301-/130 40- the base requirements is according to IPC-4101 and Cu foil according to IPC-4562.

If the dielectric constant Dk (may also be denoted as permittivity) is stated it is normally only used for the calculation of the impedance. The frequency stated in 1301-/130 40- is given in MHz in the following way.

• 1 =>1 MHz. • 1000 =>1 GHz. • 10000 =>10 GHz.

Test methods that can be used are IPC-TM-650 number 2.5.5.3, 2.5.5.5 or 2.5.5.9.

If halogen free base material is specified in the product specification 1301-/130 40-, (i.e. HFFR4) the maximum contents, by weight, is as follow:

Cl 0.09%. Br 0.09%. And in total 0.15% (same as IPC 4101/xx).

Test method, IPC-TM-650 number 2.3.41.


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6.2 Board thickness

The board thickness must fulfill the requirements stated in the product specification (1301-/130 40-) or in the layer drawing. The thickness is measured without solder mask and surface treatment. If the information is stated in more than one document, the 1301-/130 40- applies.


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7 Survey of dimensions The table indicates where in this standard the dimensions and tolerances of the features illustrated in fig. 7 are specified.

FEATURE FIG 7 SECTION Size of sold. Surface A, A1 8.3.1 Conductor width B 8.1 Conductor spacing C 8.4 Edge spacing D 8.5 Registration E, P 13.2.1, 13.2.4 Hole position F1, F2 9.1.2 Position of sold. Surface F3, F4 8.3.2 Diameter of holes H 9.1.1 Microvia Hp, Hb 9.2 Outline position J, J1 10.1 Outline dimension K 10.2 Minimum annular ring L1--L5 8.2

Fiducial mark (primus datum point)

Concuctive pattern

Solder maskLands/conductors covered by solder mask or on internal layers

Reference hole

Fig 7


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8 Conductive pattern (plating included) It is permitted to remove areas of copper foil or fill in areas surrounded by copper foil if its size is less than 0.015 mm2, as long it isn’t a part of the functional pattern.

8.1 Conductor width

The dimension and tolerances of the conductor width must be as stated in the product specification (1301-/130 40-). The dimension in CAD-data for conductor width should be adapted (etch compensated) to reach the nominal value.

The conductor width is defined (with one exception) as the average value of the conductor width (top/bottom) at the point of measuring. The tolerance for all conductors (irrespective of its width) on one layer is as stated in 1301-/130 40 for that layer. The exception is conductors having a width of ≤ 74 µm that are to be measured at the bottom only.

Conductors with impedance requirements must fulfill the value indicated in the product documentation. Requirements on conductor width are not valid for these conductors. See section 21 regarding impedance requirements. If there is a deviation between stated impedance requirements and the manufacturer's calculation, the ordered must be contacted.


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8.2 Annular ring for mechanically drilled holes

Requirements on minimum annular ring, see fig 8.2.1 and table 8.2.1.

Not plated holes Plated holes Plated pattern

Not plated patternNote 2)

Max 90 °

Max 90 °

Max

90

°

L5L3

L2

B

L1

Fig 8.2.1 a Fig 8.2.1 b

Table 8.2.1 NOT PLATED HOLES,

DIMENSION ACC. TO FIG 8.2.1 a PLATED HOLES, DIMENSION ACCORDING TO FIG 8.2.1 b

For external layers and for blind- or buried via in internal layer where the via starts/ends

L1 min 0.10 mm

L2 + L3 min B 1)

Maximum 90 degrees breakout of the holes periphery from land or soldering surface. L4 minimum 0.05 mm

For other lands in internal layers

------------ Maximum 90 degrees breakout of the holes periphery from land L5 minimum 0.05 mm

1) B= minimum conductor width according to 1301-/130 40-.

2) The minimum lateral insulating spacing to other foil areas must be maintained.


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8.3 Soldering surface

8.3.1 Size

In relation to the CAD-data the soldering surface must fulfill the requirements stated in table 8.3.1. Etch compensation is recommended to reach the nominal value.

Table 8.3.1 The smallest dimension of the soldering surface (mm)

Tolerances at the top At (mm) (1)

Maximum dimension at the bottom, Ab (mm)

The profile (mm)

> 0.55 +/- 0.05 ----- ----- ≤ 0.55 +/- 0.03 (2) At max + 0.05 (surface

protection include) Max 0.025 See fig 8.3.1

(1) HASL excluded (2) At max = CAD dimension + 0.03 mm.

Ab

At

Max 0.025 mm

Surface protection

Fig 8.3.1 Cross section of a soldering surface

8.3.2 Position

The true position of a soldering surface (F3/F4 according to fig 7) in relation to a fiducial mark or a reference pattern must be according to table 8.3.2.

Table 8.3.2

Distance, F3/F4 according to fig 7 (mm)

≤50 (50)--150 (150)--300 (300)--450 (450)--600

True position (mm) +/- 0.04 +/- 0.05 +/- 0.07 +/- 0.09 +/- 0.11

8.4 Conductor spacing

The spacing and tolerances of the conductor spacing must be as stated in the product specification (1301-/130 40-).


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8.5 Edge spacing to conductive pattern

The minimum edge spacing to conductive pattern (dimension acc. to fig 8.5) is to be as stated in table 8.5 under “Req. min”. The CAD-data is according to the design rules and is stated here for the following reason: As long as the “Advance/special design” is not stated in 1301-/130 40- then the value in the CAD data determining the requirement of “Req min.”

Class 1 & 2 is stated in 1301-/130 40- but “Advance/special design” may not be stated until the rules has been updated.

Table 8.5 Applies for class 1 and 2 Advance/special design

Dimension (fig 8.5) (CAD-data mm) Req. min CAD-data Req. min D1 (mm) Class 1 0.70 / Class 2 0.50 0.20 0.30 0.10 D2 (mm) Class 1 1.15 / Class 2 0.63) 0.25 0.40 0.10

D4 and D5 (mm) ---- 0.10 ---- 0.10

D1

D2 D4

D5

Drilled hole

Boa

rd e

dge

or

mill

ed h

ole

Fig 8.5

If the spacing D1 or D2 is 0.2 mm or less in the CAD-data then it may be 0 on the board, i.e. bare Cu at the board edge is permitted. This applies for class 1 and 2 as well as for advance/special design boards.

8.6 Defects

8.6.1 Nicks in conductors

The A-measure according to fig 8.6.1 must not be less than 0.8 x B. The B-measure is the minimum permitted dimension for the conductor in question. The d-measure must not exceed 10% of the conductor length, however, 5 mm is the maximum. A maximum of one defect per 50 mm of conductor length is permitted. In ground and voltage layers the maximum allowable size of a void is 1 mm.


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A

A B

d

Fig. 8.6.1

8.6.2 Protuberances

Protuberances on conductors, lands, soldering surfaces etc. must not reduce the minimum permitted conductor spacing. However, the protuberance must not be more than 0.50 mm.

8.6.3 Surplus foil

Surplus foil that may effect the function, such as minimum conductor spacing or minimum edge distance, is not allowed. See fig. 8.6.3.

S1 + S2 >= minimum conductor spacingS1

S2

Fig. 8.6.3 Surplus foil

8.6.4 Scratch

A scratch across the conductor shall not reduce the minimum cross section area by more than 20%.


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8.6.5 Nicks in soldering surfaces or contact fingers

The soldering surfaces, contact fingers or other contact areas may have a maximum of 2 nicks with d < 0.2 x A1 and c < 0.1 x A or d < 0.2 x D and c < 0.1 x D. See fig. 8.6.5.

dA1

cA

c

Fig. 8.6.5

8.6.6 Separation of conductive pattern

Separation of conductive pattern from the base material is not permitted. Nor is it permitted to glue a foil that has come loosened from the carrier.


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8.7 Supplementary pattern

When addition of a supplementary pattern to the board is allowed (see 1301-/130 40-), it shall be designed according to fig 8.7.

When the supplementary pattern is included in the CAD-data as very short conductors, it must be adapted at the manufacturing site and inscribed squares turned 45 degrees hall be used. See fig 8.7

R = 0.12

Fig 8.7

9 Holes

9.1 Mechanically drilled holes

9.1.1 Dimensions

If no tolerances are stated in 1301-/130 40- the table below applies:

Table 9.1.1 Diameter tolerances, including surface protection Diameter (mm) H according to fig 7

Not plated holes

Not plated holes Plated holes

H ≤ 6.2 + 0.10 - 0

+ 0.15 - 0

H > 6.2 According to table 10.2

------

Note: Tolerances are normally not applied for via holes, the size of via holes is limited to the requirements for annular ring.

Holes for perforation in tabs (boards in panel), use the same drill size as stated in the product documentation. There are no tolerance requirements or these holes.


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9.1.2 Hole position

The true position is the deviation of a hole from the theoretical position in relation to a reference hole. If noting is stated in the product documentation (1301-/130 40-) the true position must fulfill the requirements according to tolerance class 4 of table 9.1.2. If reference hole/holes are not given in the product documentation it is freely to select the reference hole.

Holes that are drilled separately after etching of the pattern, tolerance class 3 applies.

Tolerance zone for hole centre

Theoretical position

Reference hole

Fig. 9.1.2 Hole position

Table 9.1.2 Tolerance of a hole position.

Distance F1/F2, see fig. 9.1.2

Type of tolerance fig. 9.1.2 True position as

Tolerance class of hole position

3 4 F1 and F2 <= 150 mm

Circle diam. V mm 0.30 mm 0.20 mm square +/- U/2 mm +/- 0.11 mm +/- 0.07 mm

F1 or F2 (150)--300 mm


F1 or F2 (300)--600 mm



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9.1.3 Burr height

The maximum permissible burr height f for not plated holes is 0.1 mm in accordance with fig. 9.1.3. This is also applied for plated slot.

For plated holes and foil that ends at board edge the maximum permissible burr height is 25 µm.

f

Fig 9.1.3 Burr height

9.1.4 Resin smear

In sections parallel to the board surface, resin smear between the hole plating and the land must not exceed 25 % of the circumference of the hole. See fig. 9.1.4.

Fig. 9.1.4 Example of permitted resin smear

9.1.5 Resin recession

Resin recession between hole-plating and hole wall, see fig 9.1.5, must not on any side of the plated-through hole exceed 40% of the cumulative base material thickness. For product evaluation the same requirement is valid before and after thermal test.

Fig 9.1.5


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9.1.6 Residues on hole walls.

9.1.6.1 Not plated holes

• Tenting holes (not plated holes with lands). Residue of foil on the hole wall must not be greater than 20% of the length or circumference of the hole.

• Some residues of chemical Ni/Au plating on the hole walls are allowed if there are no loose residues.

9.1.6.2 Plated-through via holes

• Residues of solder mask on the hole wall is allowed in via holes

9.1.7 Resin fill in viaholes

All viaholes stated below shall be totally filled with resin but voids are permitted as long as the thermal test according to 17.1.1 is fulfilled.

9.1.7.1 Buried via

Buried vias shall be filled.

9.1.7.2 Vias in pad with lid

Blind via (not mechanically drilled vias are excluded) placed in a soldering surface or test point shall have a copper lid and meet the requirements according to 17.1.1. The dimple must be ≤ 25 µm. The same also applies for filled plated-through vias that are required and stated in 1301-/130 40-.

9.1.8 Partially filled via (Plugged via) in pad

If partially filled vias are stated in 1301-/130 40- the following applies for these holes:

• Plugging can be done with solder mask, epoxy or other suitable material and shall be done from the board side stated in 1301-/130 40-. If the board side isn't specified, then it is a free choice.

• The plug must not extend above the Cu surface on primary as well as secondary side.

• The plug must meet the requirements according to 17.1.1 and the hole must be completely blocked i.e. prevent passage of solder and/or flux. Small voids inside the plug are permitted.

• No residues from the plugging material is permitted on surfaces connected to the plugged via.


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9.2 Specific requirements for microvia holes

9.2.1 Holes

The bottom diameter (Hb) must not be less than 50 µm, see fig 9.2.1.

Hp

Hb

Hp

Base Cu

Point of measuring

Fig 9.2.1

Copper thickness in the hole wall, see 12.1.2.1. It is permitted with areas in the viahole not filled with solder mask or resin.

The following requirement applies for via in pad (soldering surface):

• bare copper in the via holes are not permitted.

• for vias through one dielectric layer, the maximum hole diameter Hp according to fig 9.2.1 is 130 µm

• for Cu-filled microvias (solid microvias) the dimple must be ≤ 25 µm. Voids inside the Cu-fill are permitted as long it isn’t on the surface and affecting the dimple requirements.

9.2.2 Minimum annular ring

For pads and lands on start layers (also internal layers where the via start) 90 degrees break-out all around its periphery are allowed, i.e. no requirements of the dimensions L4 or L5 according to 8.2. On stop layers (the end of the via) no break-out are allowed.

10 Design

10.1 Outline position

Tolerance of the outline position in relation to the fiducial mark, J according to fig. 7, is +/- 0.20 mm.


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10.2 Outline dimension

Tolerances for outline dimension, K in accordance with fig. 7, are specified in the table 10.2. If the tolerance class is not stated, then the same class as specified for edge spacing applies, see 8.5.

The centre line in the Gerber/CAD-data represents the finished board’s contour.

Table 10.2 SIZE TOLERANCE CLASS Over up to 1 and 2 0 -- 30 mm +/- 0.10 mm (30) -- 120 mm +/- 0.15 mm (120) -- 367 mm +/- 0.20 mm (367) -- 1000 mm +/- 0.30 mm

Boards produced on panel with V-score the dimension of V and K will be stated in the drawing but also the following applies:

• The scoring deviation between the primary- and secondary side should not exceed +/- 0.1 mm (F).

• If it is not stated in the drawing, the tolerance of web thickness (K) must be within +/- 0.1 mm.

K

Fig 10.2

10.3 Corners

The tolerance on bevel and radius according to fig. 10.3, see table 10.2

K

KR

Fig. 10.3 Bevel and radius


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10.4 Bow and twist

The values shown in table 10.4 apply for bow and twist of individual boards. A correcting action, in order to reduce the bow and twist of a finished board, is only allowed if the method to be used is agreed upon.

D1

Fig. 10.4 Bow and twist

W = Width L = Length

Bow H < d x W or d x L. Is to be measured at the highest point (at the edge or at the centre of the board).

Twist S < d x D1. The other three corners must be tangential with the reference plane.

The value of the d-factor is specified in table 10.4 for double sided and multilayer printed boards.

Table 10.4 Board thickness (mm) d-factor

< 2.4 ≥ 2.4

0.007 (1) 0.005

(1) Some board may have the requirements of 0.5% (0.005) stated in the product

documentation (1301-/130 40-).

For boards in panel, the value of the d-factor shall be applied for the whole panel.


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11 Defects on base material

11.1 General

Cracks, blisters and delaminations are not accepted in the base material. For product evaluation the same requirement is valid before and after thermal test.

Scratches, dents and tool marks are acceptable provided they do not expose fibres. For voids and foreign particles the requirement is the same as stated in the material specification.

IPC-A-600, product class 2 can be used as a basis when assessing specific cases.

11.2 Edge damage

Generally, the edges of the printed board shall be intact. However, edge indentations and chips, as shown in fig. 11.2, are acceptable if the length of the damage does not exceed 5 mm or, alternatively, a maximum of 10 % of the length of the board's edge and that the D-measure must not be less than the minimum edge distance according to section 8.5.

D D

Fig. 11.2 Edge damage

12 Surface treatment

12.1 Copper electroplating

12.1.1 Appearance

Surface defects, like pits, cracks, burnt plating, nodules, embedded or loose solid particles, are not permitted. Such defects may cause impaired soldering properties or risk the function.


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Voids in the hole walls clearly visible in good illumination by the naked eye or with a magnification of 2--3x are not permitted. However, voids may be permitted occasionally in maximum 1 void/hole, but a maximum of 5% of all holes, the void must not occupy more than 5% of the depth or the circumference of the hole. No voids must be found at the junction between the hole wall and the land on the external as well as in the internal layers.

12.1.2 Thickness

The copper thickness is measured by the use of a microscope after encapsulation of the sample and polishing according to Test method IPC-TM-650 number 2.1.1.

12.1.2.1 Hole walls

The copper thickness is measured on three spots, A, B, and C as per fig 12.1.2.1. The average value of these three measurements and any of the individual measurements (minimum) must be as follow:

Board thickness/hole depth Minimum Cu thickness

> 2.50 mm 25µm, average value 20 µm, individual measure

2.50 -- 1.30 mm 20 µm, average value 18 µm, individual measure

< 1.30 mm 15 µm, average value 13 µm individual measure

Microvia 10 µm minimum

Pressfit According to stated thickness in1301-/130 40-

T/4

T/2

T/ 3

/4

T

E

A

C

B

Fig. 12.1.2.1 Measuring spots

12.1.2.2 Conductors

The total thickness of the conductors (E in the figure) shall fulfil the requirements according to the product documentation.


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12.1.3 Ductility and adhesion

The copper plating shall be ductile and free from stress. The requirements after thermal test is stated in section 17.1.

12.2 Electroless nickel/gold plating

12.2.1 Appearance and surface defects

The layer of nickel and gold must be smooth. A maximum of 2 voids or defects/soldering surface are permitted but it must not exceed 5% of each individual area and a maximum of 5% of all soldering surfaces.

12.2.2 Adhesion No adherence of gold on the tape is permitted when tested according to IPC-TM- 650 test method 2.4.1.

12.2.3 Thickness

Nickel 3--8 µm Gold 0.05--0.15 µm

12.2.4 Gold content

The gold layer must have a gold content of at least 99%.

12.3 Organic preserved solderability (OSP)

If the type of OSP is not defined in the product specification (1301-/130 40-) it shall withstand at least 3 reflow cycles (LFS) with preserve solder-ability as well as 24 hours (with open package) in a normal assembly environment.

12.3.1 Appearance and surface defects

The treatment must have an even surface without crystals and foreign particles. Discoloration of the metallic surface under the treatment is accepted.

12.4 Gold for edge printed board connectors/ hard gold

If nothing is defined in the product specification (1301-/130 40- ) the following applies:

Nickel Minimum 2.5 µm Gold Minimum 0.8 µm and gold content of at least 99%. No adherence of gold on the tape is permitted when tested according to IPC-TM-650 test method 2.4.1.


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12.5 Mechanical defects

Scratches or other defects on soldering surfaces or contact areas are not permitted if they expose copper more than 5% of the actual surface. A maximum of 4 indentations in the copper with a maximum depth of 15 µm on each individual area (e.g. from test probe) are permitted.

13 Solder mask

13.1 Requirements

13.1.1 Requirements according to IPC-SM-840

The requirements of solder mask must conform to IPC-SM-840 with the exception of section 13.1.2 and the following remarks:

Properties Section Remarks Appearance 3.3.1 Pits and voids are allowed in non-conductive

areas provided they have adherent edges and do not lift. On large foil area, pinholes < 1 mm are allowed

Adhesion to rigid printed board Tape test

3.5.2.1 Production board with a represantive pattern (both conductive and non-conductive area within the tested area) can be used as an alternative. Boards with OSP must be tested before the OSP coating. Requirement. No mask on the tape after the tape test

Flammability. 3.6.3.1 Shall be class H Insulation resistance 3.9.1 Shall be class T Electrochemical migration. 3.9.2 Shall be class T

13.1.2 Requirements that differ from IPC-SM-840

13.1.2.1 General requirements

The coating must not impair the solderability of the printed board (see 14), and act as a solder stop.


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13.1.2.2 Thickness of the solder mask

On boards intended for surface mount assembly the solder mask should be kept as thin as possible, however it must fulfill the required breakdown voltage (minimum thickness) stated in 1301-/130 40-. This test is to be done according to 13.1.2.3.

The maximum thickness of the solder mask over the base material must not be higher than the pad (soldering surface) + 12 µm. The thickness of the mask can be measured on the solder dam between two pads as in fig 13.1.2.2.

Max 12 µm

Solder mask

Pad

Base material

Fig 13.1.2.2

13.1.2.3 Breakdown voltage

The measurement is carried out with a 6 mm diameter electrode with the mass of 50+-2 g. The electrode shall be plane and have a round edge with a 1 mm radius in order to avoid the point effect. The electrode is placed over covered parallel conductors. The voltage (DC) is raised to the specified value and held for a period of 1 second. The breakdown is assumed to have occurred when the current exceeds 1 mA. The voltage source should have a maximum short-circuit current of 10 mA. Safety must be exercised because of the potential danger of electrical shock.

13.2 Design of the solder mask for conductive pattern

The size of the openings in the solder mask may require adaption at the manufacturing phase (e.g. if the size of the mask opening in the CAD-data have the relation 1:1 to the soldering surfaces or to the lands for components holes). However, the requirements stated in 13.2.2 – 13.2.4 must be fulfilled.


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13.2.1 Lands for plated-through via holes

If the size of the mask opening for plated-through via holes, in the CAD-data, is less than the land size an adaption of the mask opening may be required at the manufacturing phase to fulfill the requirement according to fig 13.2.1.

Solder

Conductivepattern

mask

> 0

Fig. 13.2.1

13.2.2 Solder mask between soldering surface and land

There must be a solder dam between the soldering surface and the land, if they are connected to each other and if the design is such that the width of the dam in the CAD-data is ≥ 0.08 mm. This requirement also applies for advance/special design boards (small size) if the design is such that the width of the dam in the CAD-data is ≥ 0.07 mm.

13.2.3 Solder mask between soldering surfaces

If the width of the solder dam in the CAD-data is ≥ 0.08 mm, then it must be a solder dam on the board between the soldering surfaces.

This requirement also applies for advance/special design boards if the design is such that the width of the dam in the CAD-data is ≥ 0.07 mm.


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The maximum allowed miss registration for the solder mask is seen in fig. and table 3.2.3. For plated-through via holes, see 13.2.1.

P

E

Solder mask

Conductivepattern

Fig. 13.2.3 Registration Table 13.2.3

Maximum miss registration Fig 13.2.4 Not plated component hole: To the inner edge of the hole E ≥0.1 mm Plated-through component hole: To the inner edge of the hole E > 0 To soldering surface No solder mask on

the top surface To conudctor P > 0

13.2.4 Distance between solder mask and not plated holes or outline

The solder mask may go edge to edge with holes and outline. However, it is permitted to draw back the mask from edges, as long as the pattern is covered.

13.3 Mechanical defects

Scratches in the solder mask that expose copper are not permitted. However, some scratches are permitted over ground or supplementary pattern.

14 Solderability

14.1 Test

The test methods and the requirements shall be in accordance with IPC/EIA JSTD-003B category 2 for "Durability of Coating Rating". Test E or E1 shall be used for boards with SMD components depending on if the board will be lead or lead-free soldered.


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Note: Printed boards with organic solderability preservation (OSP) may exhibit solder wetting only to specific areas where solder is printed. Exposed base metal in these areas should be considered normal under these circumstances, provided the achieved wetting characteristics of the intended solder connection areas are acceptable.

14.2 Shelf life

The solderability must last for a minimum of 6 months during normal storage condition, counted from the time of manufacturing.

15 Legend

15.1 Identity

The printed board is marked with product number and R-state in the CAD data (on some boards also flammability rating may be included). The manufacturer must add manufacture's code and time of manufacture (minimum, last digit of year and calendar week). The flammability rating must also be indicated, see section 18, either as UL recognized marking, flammability rating or both. The UL recognized marking must be done if stated in 1301-/130 40-. Additional rules are found in UL 796 under “Markings” The indication of flammability rating is not needed on boards for consumer products.

In addition, the manufacturer must also mark the boards with the letter HF in the solder mask if HF (halogen free) is stated in 1301-/130 40-. All marks should be brought together as much as possible and the marking added by the manufacturer is to be done in the following way: • If the placement of the marking is not indicated in the product documentation or if

“NO” is stated in 1301-/130 40- for supplementary pattern the marking must be done in the solder mask on Cu-free area or by screen printing.

• If the placement is indicated with a frame in the solder mask (CAD-data) the marking must be done in the solder mask within the frame. The HF marking may be placed outside the frame.

• If “YES” is stated for supplementary pattern or if the placement is indicated with a Cu frame (CAD-data) then the marking can be done by a Cu-pattern.

• If the board have the following text in the solder mask (CAD-data) it must be changed in the following manner:

o Text area --XXX-- is to be changed to manufacture’s code or logo. o Text area --YWW—or –YYWW is to be changed to last digit(s) of year and

calendar week.


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15.2 Printing material and other printing placement

The printing material used for marking must not interfere with the soldering and contact surfaces.

No print marking is allowed within the area marked with corner markings in copper or solder mask. (This area will be used for PBA marking).

16 Purity

Besides what is stated in section 3 the cleanliness of the boards from ionizable surface contaminants is to be within the limits of maximum 1,0 ug NaCl/cm2 equivalent. Test method 2.3.25.1 of IPC-TM-650 or equivalent methods. Verification is to be assured by system process control.

The minimum moisture insulation resistance (17.1.3) must also be fulfilled.

17 Test

17.1 Environmental test

Tests are to be performed according to the manufacturer’s quality system. Microsection shall be done when testing delamination, blistering etc. Beside the requirements stated in this document the copper in hole walls must not show any indication of having cracks or cavities.

17.1.1 Boards for lead-free soldering, thermal test

The PB must withstand 4 soldering processes with a reflow profile within the limits stated in IPC/JEDEC J-STD-020. The time must be minimum 20 seconds with the required peak temperature of 260 /-5°C i.e minimum 255 °C.

17.1.2 Thermal shock test, continutity and microsection

Test specimen: Coupon D from IPC-2221 Test method: IPC 650 Number 2.6.7.2. Test condition: condition D according to table 1.

The increase of the total resistance of the series-connected holes must, after temperature change test, not exceed 10%.


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17.1.3 Moisture and insulation resistance test (SIR)

Test specimens: Comb pattern D (IPC-B-25A) with conductor spacing of 0.318 mm and without solder mask.

Test method: IPC 650 Number 2.6.3 for class 2.

The insulation resistance must not be below 100 Mohm after exposure to moisture.

17.2 Electrical test

All PB shall be 100% continuity and insulating electrical tested. Only the original netlist files are to be used.

18 Flammability If not otherwise noted (normally in 1301-/130 40-) the flammability rating must obtain class 94 V-0. The flammability test for the printed board (containing the solder mask) is to be done according to UL 94 and the test specimens are to be prepared according to UL 796. The flammability rating must be marked according to 15.1.

19 Handling and packing The printed boards shall be protected against harmful environmental and mechanical influence during storage, transport and handling so as to enable the specified requirements on printed boards to be met prior to subsequent processing. Requirements on handling, packing material (including ESD approved plastic) and marking of the package are stated in 124 42-103 Uen.

Note: If ESD approved plastic is NOT required, as agreed upon between customer and supplier, it has to be stated in the purchase documentations.

19.1 X-Out

X-Out is permitted (method of identifying a defective board within a panel) if it is stated in 107 73- and the boards shall be marked according to that document.

If nothing is stated in 107 73- then X-Out is not permitted.


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20 Repair Repair by welding of conductor is only permitted on external layers and if the distance to the next layer is more than 0.08 mm. After welding the general requirements for conductor width/spacing applies. This repair is only to be done by the manufacturer of the printed boards.

The following repairs of printed boards are permitted provided that the delivery quality is verified.

20.1 Excision of short circuit

20.1.1 General

Excision of short circuit refers to removing of protuberances on conductive pattern, short circuits and metallic residues between conductive patterns. See fig 20.1.1.

Fig 20.1.1

20.1.2 Requirements

• A maximum of 6 excisions per board is permissible. • No damage of the base material of the printed board is permissible after excision. • The requirements on conductor width and conductor space shall be met.

20.2 Repairs of solder mask

20.2.1 General

Repairs of solder mask refer to repair of defects such as blisters or impurities in the insulation coating and the adding of additional insulation on such areas where the conductive pattern has not been covered.

20.2.2 Requirements

After repairing, the same requirements as for the solder mask on board applies.


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21 Impedance requirements If the differential (Zdiff) or/and singel ended (Z0) impedance are stated in 1301-/130 40- the verification of the requirements shall be done.

Zodd = 0.5 x Zdiff

Pitch

Zdiff = Vdif f / Idiff

Idiff

Vdiff

I0

V0

Z0 = V0 / I0

Fig 21

Definitions of impedance related terms:

Single ended (Z0): The impedance seen when testing a single line that is not coupled to an adjacent line.

Differential (Zdiff): The impedance testing between a pair of lines when driven by equal and opposite polarity signals. (Zdiff is twice the value of the odd mode impedance).

Odd Mode (Zodd): The impedance seen when testing the impedance of one side of a pair of lines when the other is drive in equal and opposite polarity (half the value of the differential impedance).

22 Requirements for specific boards

22.1 Boards designed with a shielding layer of printed carbon inc.

22.1.1 General requirements

The conductive carbon ink can be fine-grained or course-grained depending on the process used.

The surfaces of the printed carbon inc shall be smooth with a uniform appearance and with no scratches.

Unintentional carbon ink shall not be found on the soldering surfaces.

The printed carbon inc shall withstand the surfaces treatment used (HASL, Ni/Au etc.).

No blisters or delaminations between the printed carbon inc and the copper surface are allowed.


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22.1.2 Requirements on the printed carbon pattern

The maximum thickness is 100 µm and the minimum must not be less than the thickness of the solder mask.

The insulation spacing between two printed areas must not be less than 0.5 mm.

The unevenness of the carbon pattern edges shall be less than 0.15 mm.

Voids < 1 mm are allowed in the printed carbon pattern.

Adhesion shall be tested according IPC-TM-650 test method 2.4.1 No cracking, delaminations or flaking is accepted.

23 Requirements that may occur in older product documents.

In old product documents there might be references to documents that are withdrawn or that some unique requirements are stated. Here follows a list of those requirements and also the requirements that are to be applied in those cases.

23.1 Related to section 6.1. Layer drawing

In older 1301-or layer drawing (105 83-) there may be references to 105 49-231, 105 49-235, 105 49-MPP 214 and 105 49-MEA 120. Instead the requirements for laminate and prepreg are according to IPC-4101/21 and for Cu foil according to IPC-4562.

23.2 Related to section 8.1. Conductor width pattern class 1--8

If 1301- refers to a pattern class 1--8 for conductor width (B according to fig 7), then the requirements are as stated in the following table.

PATTERN CLASS 1 2 3 4 5 6 7 8 Minimum conductor width, (mm) 0.70 0.50 0.40 0.25 0.15 0.10 0.08 0.06 Tolerance in relation to the CADdata, (mm)

+0.02 -0.08

+0.02 -0.05

+0.01 -0.05

+0.01 -0.045

+0.01 -0.042

23.3 Related to section 8.4. Conductor spacing pattern class 1--8

If 1301- refers to a pattern class 1--8 for conductor spacing (C according to fig 7), then the requirements are as stated below.

PATTERN CLASS 1 2 3 4 5 6 7 8 Minimum conductor spacing C (mm) (1) 0.70 0.50 0.40 0.23 0.15 0.10 0.10 0.10


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23.4 Related to section 9.1.1. Hole tolerances for boards with HASL

Hole diameter < 1 mm + 0.15 mm / -0 mm Hole diameter 1 ≤ H ≤ 6.2 + 0,15 mm / -0.05 mm Using HASL the via holes may be filled up.

23.5 Related to section 9.1.8, 3rd bullet and 17.1.1

Boards for Sn/Pb soldering the peak temperature is to be 240° C

23.6 Related to section 12. Hot air solder leveling (HASL)

In older 1301-/130 40- a reference to MZY 372 50 may be stated, but the following requirements apply also for these boards.

Appearance and surface defects

The color and the gloss of the tin-lead coating shall be characteristic of the coating method. Variations of gloss from bright to semi-bright are characteristic and shall be permitted.

The coating shall completely cover hole walls and the surfaces of the pattern that are not permanently masked or temporarily masked during the coating operation. For voids on hole walls the same requirements apply as for plated through holes. Furthermore, a certain degree of dewetting is permitted around the outer edges of lands and soldering surfaces. The dewetting is permitted in the form of small voids but it must not exceed 5% of each individual area.

Embedded or loose solid slag particles or flux residues must not be found. Craters or blisters visible to the naked eye, or 3 times magnification, are not allowed either. Solder splashes (at a magnification of 3x) shall be considered as a process indicator (*), and must neither be loose nor violate minimum electrical spacing.

(*) May require corrective action to reduce their occurrence.

Coating thickness

Boards for hole mounting

On lands there is allowed a variation of thickness of between 1 and 50 µm. On hole walls the coating thickness is limited to the requirements on hole tolerances. A thinner coating is allowed in the junction between hole and land on condition that there is a complete covering. Likewise a thinner coating is allowed on large pattern areas of boards without solder mask.

Boards for surface mounting

On soldering surfaces the coating thickness must be 10 +15/-9 µm.


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Porosity

Maximum 2 pinholes with diameter ≤ 0.1 mm are allowed per square decimetre of board area. Such holes are visible to the naked eye or at a moderate magnification (3x).

Solder

The solder composition shall meet the requirements according to J-STD-006 (Sn63Pb37).

Flux

The flux must conform to the flux type L0 or L1 according to ANSI/J-STD-004.

23.7 Related to section 12.2

If 1301- refers to MZY 411 01 then the requirements according to 12.2 applies.


If 1301- refers to MZY 364 30 then the requirements according to 13.1 applies.

23.9 Related to section 13.1.2.2

If 1301- state the breakdown requirements expressed as an "Insulation coating class" (a three digits code e.g. 003, 004, 013, 014 etc.), then a break down voltage of 500 V applies. Also the maximum thickness may be stated in older 1301- such as a maximum thickness of 45 µm, 20---40 µm or expressed as an insulation coating class (a three digits code). In all these cases the requirement stated in 13.1.2.2 applies.

23.10 Related to section 13.2.1

Boards having HASL as surfaces treatment an air-passage opening must be provided according to fig 23 a. Also with a max miss-registration of the mask the requirements according to fig 23 b must be fulfilled. If the requirements of air-passage are not possible to achieve, then the vias must be plugged or other suitable solution according to an agreement between customer and supplier.

Solder

Conductivepattern

mask

> 0> 0

Fig 23 a Fig 23 b


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This test method is to be used for boards intended for a Sn/Pb soldering process to evaluate the delaminating properties. Heat the bath (solder, oil or sand) to 260 +5/-0 °C and maintain this temperature throughout the test. Immerse the specimen part and hold it in the bath for 20 +1/-0 seconds. The specimen shall cool down to at least 35 °C between immerses. Test specimen: Coupon, printed board or part of it. The number of immersions: 6 times. Before the evaluation clean the specimen if needed.

24 References IPC-6012 Qualification and performance

specification for rigid printed boards (Class 2 products)

IPC-T-50 Terms and definitions for interconnecting and packaging electronic circuits

IPC-A-600 Acceptability of printed boards (Class 2 products)


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25 Change Information Changes from rev X

In general: Rev for IPC doc. deleted, latest revision applies.

Section 1: “Advance/special design” added

Section 8.5: Text and table is changed.

---“--- 9.2.1 Max Hp is changed from 120 µm to 130 µm.

---“--- 10.4 Table regarding board thickness is changed.

---“--- 12.4 “Hard gold” is added

---“--- 13.2.3 One figure is deleted.

---“--- 16 The maximum NaCl/cm2 is changed from 0.5 to 1.0.

pcb

Documents

multilayer printed boards

y printed boards

ericsson internal requirements

printed wiring applications

printingwirings boards

soldering surface

y ipceia jstd

pcjedec jstd