pcie 2 0 system board test agilent dso81xxxx
TRANSCRIPT
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PCI Express 2.0 CEM Signal Quality and Reference Clock Jitter Test Methodology for Motherboard (System) Testing using Agilent
DSO81304B (13GHz) Real-Time Oscilloscopes
Version .9
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The PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI-SIG make a commitment to update the information contained
herein.
Contact the PCI-SIG office to obtain the latest revision of this document
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All product names are trademarks, registered trademarks, or servicemarks of their respective owners.
Copyright © 1999, 2000, 2003, 2005, 2006 PCI-SIG
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Index
1. Overview..................................................................................................................... 5 2. Hardware Requirements.............................................................................................. 6
2.1. Oscilloscope:....................................................................................................... 6 2.2. Probes/Cables:..................................................................................................... 6 2.3. Termination Load: .............................................................................................. 7 2.4. Adapters: ............................................................................................................. 8 2.5. Revision 2.0 Compliance Load Board (CLB): ................................................... 9 2.6. Test PC Computer:.............................................................................................. 9
3. Software Tool Requirements .................................................................................... 10 3.1 SIGTEST: ......................................................................................................... 10 SIGTEST post processing Analysis tool version 3.1.1 available for download at: ...... 10 3.2 Clock Jitter Tool: .............................................................................................. 10 Clock Jitter Tool version 1.3.0 available for download at:........................................... 10
4. Setup Example .......................................................................................................... 11 5. CEM 2.0 measurements using DSO81304B:............................................................ 12 6. Using data post processing tools:.............................................................................. 24
6.1 Clock Jitter Tool: (Required for testing 2.5 GT/s requirements)...................... 24 6.2 SIGTEST 3.1.1 for Gen-1 testing: .................................................................... 25 6.3 SIGTEST 3.1.1 for Gen-2 Jitter Testing:.......................................................... 27 6.4 SIGTEST 3.1.1 for Gen-2 Voltage Margin Testing: ........................................ 30
7. Appendix A: Scope/Probe/Cable Calibration ........................................................... 36 N5380A SMA Probe Head Calibration and Skew........................................................ 36
Setup for Attenuation, Offset, and Skew Calibration ............................................... 36 8. Appendix B: Abbreviations ...................................................................................... 38 9. Appendix C: List of Figures ..................................................................................... 38
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Revision History
Version Date Summary of Change(s) Contributors
1 4/10/2007 Initial Document Dan Froelich, Manisha Nilange, Marc Wells
.3 5/9/2007 updates for Agilent Scope Jim Choate
.9 8/2/2007 Updated for Sigtest 3.1.1,
Legal disclaimer, PCIe logo, procedure updates
Rick Eads
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1. Overview This document contains the procedure for testing Generation-2 PCI Express motherboards that support 5.0 GT/s using Agilent real time oscilloscopes DSO81304B (13GHz). This document provides the details on
1. Using revision 2.0 Compliance Load Board (CLB) test fixtures to gather mother board waveforms for the reference clock and data lanes at 2.5 GT/s and 5.0 GT/s.
2. Analyzing the data to test the motherboard against the 2.0 PCI-SIG Card
Electro-mechanical (CEM) specification electrical requirements using SIGTEST 3.1.1.
Note: The tests described in this document are intended to provide information about the tests that will be used in PCI-SIG compliance program. This testing is not a replacement for an exhaustive test validation plan.
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2. Hardware Requirements
2.1. Oscilloscope: This document is developed using Agilent digital storage oscilloscope, Model# DSO81304, 13 GHz / 40GS/s. This scope gives a sampling rate of 40GS/s on all four channels.
2.2. Probes/Cables:
Two of SMA-SMP differential probes: 1169A 12GHz InfiniiMax II series probe amplifier N5380A 12 GHz InfiniiMax II differential SMA adapter Two sets of Matched 50 Ohm Coaxial cables with SMA male connector on one end and SMP female connector on the other end to capture differential data. Cables pictured are Rosenberger cable assembly #101747. These cables are light weight and stay connected more easily to smooth bore SMP’s than some other options.
Figure 1: InfiniiMax II probing system with N5380A SMA Probe Head Assembly
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Figure 2: Agilent N5380A SMA probe head Assembly
Figure 3: Rosenburger Matched Pair of SMA-SMP cables
2.3. Termination Load: SMP, Female, Straight, 50 Ohms.
Figure 4: 50 Ohm Termination Load
When data signal lanes are terminated using 50 Ohm loads, it drives the particular lane into compliance mode. Note: All lanes except the lane under test must be terminated with 50 Ohm terminations for all testing described in this document.
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2.4. Adapters: 2 SMA (Male) - SMA (Male) Adapters, 2 SMA (Female)-SMP (Male) Adapters, and SMA Power splitter for cable de-skewing.
Figure 5: Miscellaneous components required for cable de-skew etc
Figure 6: Agilent 54855-67604 Precision SMA (3.5mm) Adapter
SMA(M)-SMP(M) Adapter
SMA Power Splitter
SMA(M)-SMA(M) Barrel connector
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2.5. Revision 2.0 Compliance Load Board (CLB): There are two different versions of CLB:
• x1/x16 which has x1 and x16 card edges for testing x1 and x16 motherboard slots.
• x4/x8 which has x4 and x8 card edges for testing x4 and x8 motherboard slots.
The CLB version(s) needed for testing a motherboard depend on the slot widths on the motherboard. All slots on the motherboard must be tested. Compliance fixtures can be ordered from PCISIG at: http://www.pcisig.com/specifications/order_form
2.6. Test PC Computer: 1.5 GHz or faster processor with 1GB or more memory, loaded with Microsoft Windows XP Professional operating system.
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3. Software Tool Requirements
3.1 SIGTEST:
SIGTEST post processing Analysis tool version 3.1.1 available for download at: http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library
3.2 Clock Jitter Tool:
Clock Jitter Tool version 1.3.0 available for download at: http://www.pcisig.com/specifications/pciexpress/compliance/compliance_library
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4. Setup Example
Figure 7: Connection Example
Note-1: Post-processing tools Sigtest and Clock Jitter Tool can also be run on the scope. Note-2: As shown in the Figure 7: Connection Example above, reference clock and data lane under test must both be sampled simultaneously to carry out measurements as described in the PCI-SIG 2.0 CEM specification.
N5480A Head
N5480A Head
Clock Data
Two Agilent N5380A 12 GHz Differential Probe Head + two 1169A 12GHz differential active probes
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5. CEM 2.0 measurements using DSO81304B: Note: The procedure described in this document assumes the motherboard under test changes compliance mode in the following order: Default: Motherboard system transmits compliance pattern at 2.5GT/s, First toggle: 5GT/s (-3.5dB) mode Second toggle: 5GT/s (-6dB) mode. If this is not the order for the system under test, then the procedure should be modified accordingly. 1. Perform scope calibration and cable de-skew as described in Appendix A. 2. Connect the SMA ends of two SMA-SMP cables to N5380A SMA Probe Head.
Connect SMA probe head to 1169A 12 GHz InfiniiMax II series probe amplifier and connect to Scope Channel 1. This channel will be used for capturing the data signal.
3. Connect the SMA ends of two SMA-SMP cables to N5380A SMA Probe Head. Connect SMA probe head to 1169A 12 GHz InfiniiMax II series probe amplifier and connect to Scope Channel 3. This channel will be used for capturing signaling from the reference clock. Note: The DSO81304 scope provides the sampling rate of 40GS/s on both channels 1 and 3 with this probing setup. The use of channels one and three is arbitrary; you could just as easily use channels 2 and 4, 1 and 4 or channels 2 and 3.
4. Make the SMA connections tight using a torque-wrench. (5.0 in lbs is recommended)
Figure 8: Setup for Dual Port Measurement using Agilent DSO81304B
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5. Turn off motherboard system power for the motherboard to be tested. Select
the appropriate revision 2.0 CLB based on the width of the motherboard slot to be tested:
X16 Motherboard Slot Under Test: • Put the jumpers: J91 (2, 3) and J92 (2, 3) on the x1/x16 CLB as
shown in Figure 9. • Change the slide switch SW3 to position “x16 REF CLK” i.e. slide it
towards x1 card edge as shown in Figure 10. • Connect SMP ends of cables from Ch1 and Ch2 to edge mounted
SMP’s J16 and J17, which are located on x1 card edge side of the CLB.
X1 Motherboard Slot Under Test:
• Put the jumpers: J88 (2, 3) and J89 (2, 3) on the x1/x16 CLB as shown in Figure 11.
• Change the slide switch SW3 to position “x1 REF CLK” i.e. slide it towards x16 card edge as shown in as shown in Figure 12.
• Connect SMP ends of cables from Ch1 and Ch2 to edge mounted SMP’s J6 and J9, which are located on x16 card edge side of the CLB.
X8 Motherboard Slot Under Test:
• Put the jumpers: J69 (2, 3) and J71 (2, 3) on the x4/x8 CLB. • Change the slide switch SW3 to position “x8 REF CLK” i.e. slide it
towards x4 card edge. • Connect SMP ends of cables from Ch1 and Ch2 to edge mounted
SMP’s J67 and J68, which are located on x4 card edge side of the CLB.
X4 Motherboard Slot Under Test:
• Put the jumpers: J64 (2, 3) and J66 (2, 3) on the x4/x8 CLB. • Change the slide switch SW3 to position “x4 REF CLK” i.e. slide it
towards x8 card edge. • Connect SMP ends of cables from Ch1 and Ch2 to edge mounted
SMP’s J57 and J63, which are located on x8 card edge side of the CLB.
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Figure 9: Jumpers for Compliance Mode Toggle (x16)
Figure 10: Switch showing x16 card edge selected
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Figure 11: Jumpers for Compliance Mode Toggle (x1)
Figure 12: x1 card edge selected
6. Make sure that all the data lanes except the lane being probed are terminated
with 50 Ohm terminations shown in Figure 4. 7. Insert the CLB into the slot on the motherboard to be tested. 8. Insert the SMP ends of cables from Ch3 into the data TX lane zero pair on the
CLB. 9. Turn On the system power 10. Configure the scope as follows to observe whether the slot has entered
compliance mode: • Ensure scope is in Real time mode • Set mode for Max memory depth • Set sample rate to 40GS/s
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• Optimize the vertical range of the signals on CH1 and CH3 to avoid clipping and to maximize vertical resolution.
11. Click Run/Stop button to stop the acquisition. 12. Make sure that the pattern on the scope is Compliance pattern as specified
by PCIE Base Specification 2.0. By default the compliance pattern is sent at 2.5GT/s. Use the cursors button (Shown in Figure 13 to place cursors on a pair of adjacent crossover locations that are closest together to make sure that the unit-interval (UI) is around 400ps (for 2.5 GT/s). Note: If the UI is not around 400ps then press the toggle button on CLB till the UI is around 400ps.
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Figure 13: CMM at 2.5GT/s
13. Click on Run/Stop button to start the acquisition. 14. Press the compliance mode change push button (As shown in Figure 14) to
change the compliance mode to: Gen-2 /-3.5db.
Note: 400ps indicates 2.5GT/s
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Figure 14: Push Buttons for Compliance Mode Toggle
15. Click Run/Stop to stop the acquisition. 16. Use cursors make sure that the UI (distance between the closest spaced
adjacent crossover locations) is around 200ps. (5GT/s). Note: If the UI is not around 200ps then press the toggle button on CLB till the UI is around 200ps.
• If the motherboard under test will be configured to use 3.5 dB of de-emphasis during normal operation at 5.0 GT/s advance to step 21, otherwise continue on to step 17.
Use this Push-button when using x1 card edge
Use this Push-button when using x16 card
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Figure 15: CMM at 5GT/s (-6dB TX De-emphasis)
17. Click Run/Stop to start the acquisition. 18. Press the “Toggle Switch” on the CLB one more time to change mode to
Gen-2/ -6 dB. 19. Click Run/Stop button to stop the acquisition. 20. Use the cursors to measure the UI (distance between the closest spaced
adjacent crossover locations). Make sure that it is approximately 200ps (5GT/s). Note: If the UI is not around 200ps then press the toggle button on CLB till the UI is around 200ps.
Note: 200ps indicates 5GT/s
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Dual port measurement 21. Click Run/Stop button to start the acquisition. 22. After the compliance mode has been selected: X16 Motherboard Slot Under Test:
• Change the jumpers J91,J92 from position (2,3 ) to position (1,2) X1 Motherboard Slot Under Test:
• Change the jumpers J88,J89 from position (2,3 ) to position (1,2), X8 Motherboard Slot Under Test:
• Change the jumpers J69,J71 from position (2,3 ) to position (1,2) X4 Motherboard Slot Under Test:
• Change the jumpers J64,J66 from position (2,3 ) to position (1,2)
Note: The system clock is either routed to circuitry used to change the compliance mode or to edge mounted SMP’s on the CLB. After a particular compliance mode is selected, the jumper settings need to be changed so that clock signal can be captured.
Figure 16: Clock and data probing options
Clock Probing
Data Probing
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23. For best accuracy, the amplitude of Ch1 and Ch3 should be adjusted so that both waveforms are around full scale. This takes advantage of full range of A/D converters in the oscilloscope. If the vertical scale is too high where amplitude is greater than 8 divisions, clipping will occur and measurement results will not be valid.
Figure 17: Reference Clock and data vertical adjustment
24. Adjust Sampling Rate to 40GS/s which is equivalent to a 25ps sampling interval (for measuring 5GT/s). Adjust the sample rate to 50ps sampling interval (for measuring at 2.5GT/s). Adjust memory depth to max.
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Figure 18: Oscilloscope Sampling Rate
25. Press “Run” to capture data and clock. Press Stop. 26. Save Ch1 as LaneN_data_runN_CaptureNN.BIN. The Agilent .BIN format
is a compressed binary format approximately 85% smaller in size compared to the standard .CSV ASCII format.
27. To achieve a 1 million UI sample size, capture and save 4 acquisitions (1 clock and 1 data) per lane tested.
Use 40GSa/s for 5GT/s. Use 20GSa/s for 2.5GT/x
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Figure 19: Save Data File in .BIN format
28. Save Ch3 as LaneN_clock_runN_CaptureNN.CSV. 29. Repeat steps 21-27 above on all data lanes to be tested. 30. Repeat steps 21-29 after selecting the 2.5 GT/s compliance mode with the
following exceptions. • Change the sample rate from 40GSa/s to 20GSa/s • Save only one clock file per slot tested (1.1 testing). • Refer to the Gen 1.1 test document entitled “PCI Express (Rev 1.1)
Signal Quality and Reference Clock Test Methodology”, Chapter 5.3 “Measuring the Clock Period Trend” for an alternative method of performing reference clock phase jitter measurements.
31. Repeat steps 1-29 on all slots on the motherboard.
Select .BIN format for Gen2 testing here
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6. Using data post processing tools:
6.1 Clock Jitter Tool: (Required for testing 2.5 GT/s requirements) 1. Refer to the Gen 1.1 test document entitled “PCI Express (Rev 1.1)
Signal Quality and Reference Clock Test Methodology”, Chapter 5.3 “Measuring the Clock Period Trend”.
2. Using the above procedure, capture and save an interval record of the motherboard reference clock period trend into a .CSV format file.
3. Open the Clock Jitter Tool application (Version1.3.0) installed on Computer
4. Select the “File Type” as “Interval”. 5. Use the browse button to open the saved interval
“Motherboard_Ref_Clk.CSV” period trend file. 6. Select appropriate template file:
• Select the template file: “PCIE_1_1” 7. Click on “Test File”
Figure 20: Clock Jitter Tool for Gen-1 testing
8. Window showing the jitter numbers pops-up, record the jitter
numbers. Refer Figure 21. 9. A spectral graph of the filtered clock period trend information is also
provided. Refer to Figure 22. 10. Repeat above steps for all the captured clock files.
Select Interval File Type
Skip 40 lines of header information
Select PCIe 1.1 template file
Click “Test File” to run tests
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Figure 21: Clock Jitter Test Results
Figure 22: Filtered Clock Period trend (frequency domain view of phase jitter)
6.2 SIGTEST 3.1.1 for Gen-1 testing: 1. Open the SIGTEST application (Version 3.1.1) installed on your Computer 2. Select “Differential” as data type 3. Use the browse button to open the saved
LaneN_clock_runN_AcquisitionNN.BIN differential data file. 4. Click on “Verify Valid Data File”
Pre-filtered reference clock jitter Filtered
reference clock jitter
Note that SSC is enabled on this clock.
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Figure 23: SIGTEST main window
5. After the data has been verified, the sample interval will be updated to 50
ps. If not, manually change it. 6. Under the “Technology” drop-down select “PCIE_CEM_SYS_1_1” and
under the “Template File” drop-down select “TX_SYS_CON” 7. Click on “Test” 8. Window showing test results will pop-up. Refer Figure 24. 9. To achieve a 1 million UI sample size it is necessary to run Sigtest 4 times
on 4 data sets per lane tested and record the worst case. 10. Repeat above steps for all the data files captured at 2.5 GT/s.
Load Agilent .BIN file.
Select PCIe 1.1 Techology File. Select PCIe
1.1 Template File.
Click on “Test” to begin Analysis.
Select “Differential” data file type.
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Figure 24: Results window
6.3 SIGTEST 3.1.1 for Gen-2 Jitter Testing:
1. Open the SIGTEST application (Version 3.1.1) installed on Computer 2. Select “Dual Port” as data type 3. Use the browse button to open the saved *.BIN data and clock files. 4. Click on “Verify Valid Data File”
Key Jitter measurements under the Gen1 spec are Max Median Peak Jitter and Max Peak to Peak Jitter.
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Figure 25: SIGTEST main window
5. After the data has been verified, change the sample interval to 25 ps.
Under the “Technology” drop-down select “PCIE_2_0_SYS” and under the “Template File” drop-down select “DUAL_PORT_SYS_CON”
6. Click on “Test” 7. Window showing test results will pop-up. Refer Figure 26. 8. To achieve a 1 million UI sample size it is necessary to run Sigtest 4
times on 4 data sets per lane tested and record the worst case. 9. Repeat above steps for all the data captured at 5.0 GT/s
Load .BIN data file here
Load .BIN clock file here
Select Data Type “Differential”
Select Technology File “PCIE_2_0_SYS”
Select Technology dual port template file
Click “test” to run tests
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Figure 26: SIGTEST Jitter Results
This part shows Jitter results for the waveforms. Other sections are not relevant for Jitter testing
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6.4 SIGTEST 3.1.1 for Gen-2 Voltage Margin Testing:
1. Refer to Section 6.3 and follow those procedures to perform jitter testing. This section simply describes additional features of Sigtest 3.1.1 you can perform once you have completed jitter testing.
2. Click on “App Settings and Debug Mode”. Check the boxes “Check Eye Voltage Info”, “Check Individual Point Pass/Fail”, “Check Voltage Margins” and “Create HTML Results File” as shown in Figure 27.
Figure 27: Test Settings
3. Click on “Return To Main”
Figure 28: Sigtest main window
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4. Click on “Test” 5. Window showing test results will pop-up. Refer Figure 29. 6. To test 1 million unit intervals it is necessary to run Sigtest 4 times on 4
data sets per lane tested and record the worst case. 7. Repeat above steps for all the data captured at 5.0 GT/s
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Figure 29: Voltage Margin test results
The eye violations field indicates the number of data points that fall the minimum allowable voltage levels. The other fields are direct calculations of parameters obtained from the test data. The radio buttons next to the results field will be green if the item is within the limits set in the template file. The button will be red if the item fails.
If closed, the results window can be recalled by clicking on the Results button. Selecting the View HTML Report button in the results screen will open the report that is generated by the SIGTEST tool. This report includes an eye diagram plot of the worst non transition signal eye, worst transition signal eye, the signal data plot and the following test summary:
These are the only sections that are relevant for voltage margin testing. Neglect the middle section.
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Figure 30: HTML Summary Report
Selecting the Worst Non Transition Eyes button will allows viewing the eye diagrams for de-emphasized bits.
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Figure 31: Worst Non Transition Signal Eye
Selecting the Worst Transition Eyes button will allow you to view the eye diagrams for the bits following a transition in the differential signal.
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Figure 32: Worst Transition Signal Eye
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7. Appendix A: Scope/Probe/Cable Calibration Before beginning any test or data acquisition, the oscilloscope must be warmed, calibrated, and cables de-skewed. This section will include the procedure for calibrating the scope and de-skewing the cables. The DSO81304B Oscilloscope must be calibrated manually and this is recommended after a 20-minute warm-up period.
N5380A SMA Probe Head Calibration and Skew
The N5380A SMA Probe Head attenuation and offset calibration requires the following equipment.
• SMA to BNC (M) Adapter • E2655A Deskew Fixture or SMA (f) to SMA (f) adapter • N5380A SMA Probe Head • Shorting Cap • InfiniiMax Probe Amp
Setup for Attenuation, Offset, and Skew Calibration
1. Connect the SMA to BNC adaptor to one of the SMA connectors of the deskew fixture or the SMA (f) to SMA (f) adapter.
2. Connect the shorting cap to the center SMA connector of the SMA probe head. 3. Connect the other end of the deskew fixture or SMA (f) to SMA (f) adapter to one
of the SMA connectors of the N5380A SMA probe head. 4. Connect the BNC connector of the SMA to BNC adaptor to the Aux Out on the
front panel of the Infiniium scope. 5. Connect the InfiniiMax probe amp to the GPO (SMP) connector of the N5380A
SMA probe head. Be sure to connect the plus (+) side to the side connected to the Aux Out of the scope.
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6. Start the calibration by selecting the Calibrate Probe button in the Probe Setup dialog box. The Probe Setup dialog box is launched from the Channel Setup dialog box.
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8. Appendix B: Abbreviations
9. Appendix C: List of Figures Figure 1: InfiniiMax II probing system with N5380A SMA Probe Head Assembly ......... 6 Figure 2: Agilent N5380A SMA probe head Assembly..................................................... 7 Figure 3: Rosenburger Matched Pair of SMA-SMP cables................................................ 7 Figure 4: 50 Ohm Termination Load.................................................................................. 7 Figure 5: Miscellaneous components required for cable de-skew etc ................................ 8 Figure 6: Agilent 54855-67604 Precision SMA (3.5mm) Adapter .................................... 8 Figure 7: Connection Example ......................................................................................... 11 Figure 8: Setup for Dual Port Measurement using Agilent DSO81304B......................... 12 Figure 9: Jumpers for Compliance Mode Toggle (x16) ................................................... 14 Figure 10: Switch showing x16 card edge selected .......................................................... 14 Figure 11: Jumpers for Compliance Mode Toggle (x1) ................................................... 15 Figure 12: x1 card edge selected....................................................................................... 15 Figure 13: CMM at 2.5GT/s ............................................................................................. 17 Figure 14: Push Buttons for Compliance Mode Toggle ................................................... 18 Figure 15: CMM at 5GT/s (-6dB TX De-emphasis) ........................................................ 19 Figure 16: Clock and data probing options....................................................................... 20 Figure 17: Reference Clock and data vertical adjustment ................................................ 21 Figure 18: Oscilloscope Sampling Rate............................................................................ 22 Figure 19: Save Data File in .BIN format......................................................................... 23 Figure 20: Clock Jitter Tool for Gen-1 testing.................................................................. 24 Figure 21: Clock Jitter Test Results.................................................................................. 25 Figure 22: Filtered Clock Period trend (frequency domain view of phase jitter) ............. 25 Figure 23: SIGTEST main window .................................................................................. 26 Figure 24: Results window ............................................................................................... 27 Figure 25: SIGTEST main window .................................................................................. 28 Figure 26: SIGTEST Jitter Results ................................................................................... 29 Figure 27: Test Settings .................................................................................................... 30 Figure 28: Sigtest main window ....................................................................................... 30 Figure 29: Voltage Margin test results.............................................................................. 32 Figure 30: HTML Summary Report ................................................................................. 33 Figure 31: Worst Non Transition Signal Eye ................................................................... 34 Figure 32: Worst Transition Signal Eye ........................................................................... 35
PCIE Peripheral Component Interconnect Express Gen-2 Generation-2 PCI Express CLB Compliance Load Board SMP Sub-miniature Type P connector SMA Sub-miniature Type A connector
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