pcn: pcn182406 date: to: pcn alerts mouser · o 24-channel direct memory access (dma) with...

Document No. 001-11767 Rev. *I Page 1 of 2

Cypress Semiconductor Corporation, 198 Champion Court, San Jose, CA 95134. Tel: (408) 943-2600

PCN: PCN182406 Date: June 17, 2018 Subject: Qualification of Fab 25 as an Additional Wafer Fab Site, Test 25 as an Additional Wafer Sort Site and ASE-Kaohsiung as a Transfer Site for Assembly for the Automotive PSoC 3 Product Family To: PCN ALERTS MOUSER [email protected] Change Type: Major Description of Change: Cypress announces the qualification of Fab 25 in Austin, Texas as an additional wafer fab site and Test 25 in Austin, Texas as an additional wafer sort site for the Automotive PSoC 3 product family. In addition, Cypress also announces its qualification of assembly site for 100-Lead TQFP package at ASE-Kaohsiung, Taiwan (ASE-KH) for the Automotive PSoC 3 product family. The 100-Lead TQFP Pb-Free automotive packages (14x14 mm) is assembled at ASE-KH using the following Bill of Materials:

Material ASE-KH Bill of Materials JCET Bill of Materials

Mold Compound Sumitomo G631SH Kyocera KE-G6000

LeadFrame Finish Matte Sn NiPdAu

Die Attach Epoxy Sumitomo CRM-1076WA Henkel QMI-509

Bond Wire 0.8mil Au 1.0mil Au

Benefit of Change: Qualification of alternate manufacturing sites is part of the ongoing flexible manufacturing initiative announced by Cypress. The goal of the flexible manufacturing initiative is to provide the means for Cypress to continue to meet delivery commitments through dynamic, changing market conditions. Part Numbers Affected: 56 See the attached Affected Parts List file for a list of all part numbers affected by this change. Note that any new parts that are introduced after the publication of this PCN will include all changes outlined in this PCN.

Document No. 001-11767 Rev. *I Page 2 of 2

Qualification Status: These products have been qualified through a series of tests documented in the Qualification Test Plans summarized in the table below. The qualification reports can be found as attachments to this PCN or by visiting www.cypress.com and typing the QTP number in the keyword search window.

QTP Number Qualification

164004 Fab 25 PSoC 3 Device

171610 Test 25 Additional Sort Site

174308 ASE-KH as Additional Assembly Site

Sample Status: Qualification samples may not be built ahead of time for all part numbers affected by this change. Please review the attached Affected Parts List file for a list of affected part numbers with their associated sample ordering part numbers. Samples are available now unless there is an indication that the sample ordering part numbers are subject to lead times. If you require qualification samples, please contact your local Cypress sales representative as soon as possible, preferably within 30 days of the date of this PCN, to place any sample orders. Approximate Implementation Date: Effective 90 days from the date of this notification or upon customer approval, whichever comes first, all shipments of Commercial, Industrial and Automotive non-PPAP part numbers in the attached file will be supplied from Fab 25 and ASE-KH or other approved wafer fabrication sites. For Automotive PPAP part numbers this change will be effective upon customer approval. Cypress requests that qualifications are completed no later than October 1, 2018. Anticipated Impact: Products assembled at the new site are completely compatible with existing products from form, fit, functional, parametric and quality performance perspectives. Cypress also recommends that customers take this opportunity to review these changes against current application notes, system design considerations and customer environment conditions to assess impact (if any) to their application. Method of Identification: Cypress maintains traceability of product to wafer level, including wafer fabrication location, through the lot number marked on the package. Response Required: No response is required. For additional information regarding this change, contact your local sales representative or contact the PCN Administrator at [email protected]. Sincerely, Cypress PCN Administration
http://www.cypress.com/mailto:[email protected]

Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.

Page 1 of 13

Cypress Semiconductor Corporation CY8C3xxx PSoC 3 FAB25 Characterization Report

Design Engineering Director Galen Stansell

[email protected]

Product Engineering Director Toan Ong

[email protected]

Product Engineer Dan Weinkauf

[email protected]

Applications Engineer Balasubramanian L [email protected]

Marketing Engineer

Anesh Kadudose [email protected]

www.cypress.com

198 Champion Ct.

San Jose, CA 95134 USA

Tel: (408) 943 2600 Fax: (408) 943 4730
mailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]://www.cypress.com/


Page 2 of 13

Table of Contents

Table of Contents .................................................................................................................................................. 2

Introduction 1.1 General Description ................................................................................................................................................ 3 1.2 Datasheet ................................................................................................................................................................ 5 1.3 Reference Documents and Application Notes ........................................................................................................ 5 1.4 Qualification Report ................................................................................................................................................ 6 1.5 Pin List .................................................................................................................................................................... 6

Characterization Hardware and Setup 2.1 DC Measurement System and Hardware ............................................................................................................... 7 2.2 Test Conditions ....................................................................................................................................................... 7

Electrical Specification 3.1 Absolute Maximum Ratings .................................................................................................................................... 8 3.2 Device Level Specification: N/A .............................................................................................................................. 8 3.3 Power Regulators: N/A ........................................................................................................................................... 8 3.4 GPIO DC Specifications.......................................................................................................................................... 9 3.5 GPIO AC Specification............................................................................................................................................ 9 3.6 SIO DC Specification .............................................................................................................................................. 9 3.7 SIO AC Specification ............................................................................................................................................ 10 3.8 XRES DC Specification......................................................................................................................................... 10 3.9 XRES AC Specification ......................................................................................................................................... 10 3.10 Analog Peripherals: N/A........................................................................................................................................ 10 3.11 Digital Peripherals: N/A ......................................................................................................................................... 10 3.12 Memory: N/A ......................................................................................................................................................... 10 3.13 PSoC System Resources: N/A ............................................................................................................................. 10 3.14 Clocking: N/A ........................................................................................................................................................ 10

Package 4.1 Package Characteristics ....................................................................................................................................... 11 4.2 Solder Reflow Peak Temperature ......................................................................................................................... 11 4.3 48 pin SSOP O483 Package Outline, 51-85061 ............................................................................................... 11 4.4 100 pin TQFP (14 x 14 x 1.4 mm) A100SA Package Outline, 51-85048 .......................................................... 12

Document History

CY8C3xxxx Fab 25 Characterization Report


Page 3 of 13

Introduction

1 General Description With its unique array of configurable blocks, PSoC 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C3xxx family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C38 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C38 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In addition to communication interfaces, the CY8C38 family has an easy to configure logic array, lexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C38 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Features:

Single cycle 8051 CPU o DC to 67 MHz operation o Multiply and divide instructions o Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple

security features o 512-byte flash cache o Up to 8-KB flash error correcting code (ECC) or configuration storage o Up to 8 KB SRAM o Up to 2 KB electrically erasable programmable read-only memory (EEPROM), 1 M cycles,

and 20 years retention o 24-channel direct memory access (DMA) with multilayer AHB bus access o Programmable chained descriptors and priorities o High bandwidth 32-bit transfer support

Low voltage, ultra-low-power

o Wide operating voltage range: 1.71 V to 5.5 V o 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 48 MHz o Low-power modes including: o 1-A sleep mode with real time clock and low-voltage detect (LVD) interrupt o 200-nA hibernate mode with RAM retention

Versatile I/O system

o 29 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two USBIOs o Any GPIO to any digital or analog peripheral routability o LCD direct drive from any GPIO, up to 46 16 segments o CapSense support from any GPIO o 1.2-V to 5.5-V I/O interface voltages, up to four domains



Page 4 of 13

o Maskable, independent IRQ on any pin or port o Schmitt-trigger transistor-transistor logic (TTL) inputs o All GPIO configurable as open drain high/low, pull-up/ pull-down, High Z, or strong output o Configurable GPIO pin state at power-on reset (POR) o 25 mA sink on SIO

Digital peripherals

o 20 to 24 programmable logic device (PLD) based universal digital blocks (UDB) o Full CAN 2.0b 16 Rx, 8 Tx buffers o Full-speed (FS) USB 2.0 12 Mbps using internal oscillator o Up to four 16-bit configurable timer, counter, and PWM blocks o 67 MHz, 24-bit fixed point digital filter block (DFB) to implement FIR and IIR filters

Library of standard peripherals

o 8-, 16-, 24-, and 32-bit timers, counters, and PWMs o Serial peripheral interface (SPI), universal asynchronous transmitter receiver (UART), and

I2C o Many others available in catalog

Library of advanced peripherals

o Cyclic redundancy check (CRC) o Pseudo random sequence (PRS) generator o Local interconnect network (LIN) bus 2.0 o Quadrature decoder

Analog peripherals (1.71 V VDDA 5.5 V)

o 1.024 V 0.1% internal voltage reference across 40 C to +85 C o Configurable delta-sigma ADC with 8- to 20-bit resolution o Sample rates up to 192 ksps o Programmable gain stage: 0.25 to 16 o 12-bit mode, 192 ksps, 66-dB signal to noise and distortion ratio (SINAD), 1-bit INL/DNL o 16-bit mode, 48 ksps, 84-dB SINAD, 2-bit INL, 1-bit DNL o Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs o Four comparators with 95-ns response time o Up to four uncommitted opamps with 25-mA drive capability o Up to four configurable multifunction analog blocks. Example configurations are

programmable gain amplifier (PGA), transimpedance amplifier (TIA), mixer, and sample and hold (S/H)

o CapSense support.

Programming, debug, and trace o JTAG (4-wire), serial wire debug (SWD) (2-wire), and single wire viewer (SWV) interfaces o Eight address and one data breakpoint o 4-KB instruction trace buffer o Bootloader programming supportable through I2C, SPI, UART, USB, and other interfaces

Precision, programmable clocking o 3- to 62-MHz internal oscillator over full temperature and voltage range o 4- to 25-MHz crystal oscillator for crystal PPM accuracy o Internal PLL clock generation up to 67 MHz



Page 5 of 13

o 32.768-kHz watch crystal oscillator o Low-power internal oscillator at 1, 33, and 100 kHz

Temperature and packaging o 40C to +85 C degrees automotive temperature o 48-pin SSOP and 100-pin TQFP package options

Digital

Filter

Block

ANALOG SYSTEMLCD Direct

Drive

CapSense

Temperature

Sensor

4 x

Opamp

+

-

SPC ADC

ADCs

4 x DAC 1 x

Del Sig

ADC

4 x SC/CT Blocks

(TIA, PGA, Mixer etc)

4 x

CMP

+

-

CAN

2.0

I2CMaster/

Slave

Universal Digital Block Array (24 x UDB)

4 x

Timer

Counter

PWM

FS USB

2.0

SYSTEM WIDE

RESOURCES

DIGITAL SYSTEM

Program

Debug &

Trace

Boundary

Scan

Program &

Debug8051 or

Cortex M3 CPUInterrupt

Controller

PHUB

DMA

SRAM

FLASH

EEPROM

EMIF

CPU SYSTEMMEMORY SYSTEM

SYSTEM BUS

Digital Interconnect

Analog Interconnect

1.7

1 t

o

5.5

V

0.5 to 5.5V

(Optional)

4-33 MHz

(Optional)

Xtal

Osc

32.768 KHz

(Optional)

RTC

Timer

IMO

Clo

ck

Tre

e

WDT

and

Wake

ILO

Clocking System

1.8V LDO

SMP

POR and

LVD

Sleep

Power

Power Management

System

USB

PHY

D+

D-

3 per

Opamp

GP

IOs

GP

IOs

GP

IOs

GP

IOs

GP

IOs

GP

IOs

SIO

GP

IOs

SIO

s

UDB

UDB

UDB

UDB

UDB

UDB

UDB UDB UDB

UDB

UDB

UDBUDBUDB UDB

UART

Logic

12-Bit PWM

I2C Slave8-Bit SPI

12-Bit SPILogic

8-Bit

Timer

16-Bit PRS

UDB

8-Bit

TimerQuadrature Decoder 16-Bit

PWM

Se

qu

en

cer

Us

ag

e E

xam

ple

fo

r U

DB UDBUDB

UDBUDB

UDBUDB

UDBUDB

Figure5: Simplified Block Diagram

Datasheet The CY8C3XXXX meets all datasheet specifications. The datasheet 001-54683 Rev ** is available under NDA through your local Cypress sales representative.

Reference Documents and Application Notes Cypress reference documents are available under NDA through your local Cypress sales representative. The CY8C38 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit psoc.cypress.com/getting-started to find out more. The Technical Reference Manual (TRM) contains all the technical detail you need to use a PSoC device, including a complete description of all PSoC registers



Page 6 of 13

Qualification Report The CY8C3XXXX is qualified under QTP# 164004

Pin List The Pinout diagram of the available package is shown below.

48 - Pin SSOP and 100 Pin TQFP part pinout.



Page 7 of 13

1.0 Characterization Hardware and Setup

DC Measurement System and Hardware

Temperature Forcing System The Temptronics Thermostream Advanced Temperature Source is used to force ambient/industrial operating temperature -45C, 130C and 25C. Power Supply Agilent E3631A used to supply operating voltage to multiple DUT as well as to measure drawn current. Digital Multi Meter HP 34410A was used to measure voltages at 10 NPLC configuration. Clock Input Tektronix AFG3102 Arbitrary Function Generator or Stanford Research Systems DS360 was used to provide clock signal Oscilloscope Tektronix DPO7104 Digital Phosphor Oscilloscope was used for all frequency, duty cycle, rise/fall and delay measurements using Tektronix TAP2500 active probes. Probes All AC signals were measured using Tektronix TAP-1500 FET Probe Automatic Tester Equipment The HP93000 was used to for measurements of production compatible parameters.

Test Conditions Characterization was done on following devices across voltage specified in Table-1 and Temperature conditions.

Power supply Min Nominal Max Units

VDDD (Core Regulator Enabled) 1.8 - 3.3 V

VCCD 1.71 1.80 1.89 V

VDDD (Core Regulator Disabled) 1.71 1.80 1.89 V

VDDA (Core Regulator Enabled) 1.8 3.30 5.5 V

VCCA 1.71 1.80 1.89 V

VDDA (Core Regulator Disabled) 1.71 1.80 1.89 V

VDDIO 1.71 - 3.3 V

Temperature -45 25 130 C

Table 1: Test Condition



Page 8 of 13

2.0 Characterization Data

Absolute Maximum Ratings

Specifications are valid for -40C Ta 125C and Tj 150C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator components, see the component data sheets for full AC/DC specifications of individual functions.

Device Level Specification: N/A

Power Regulators: N/A



Page 9 of 13

GPIO DC Specifications Block CHAR ID Parameter Description Conditions Units Min Typical Max Min Average Max Min Average Max

I2C CHAR.183 IDD Block current consumption Enabled, configured for 100kbps mA - - 0.250 0.04 0.07 0.12

I2C CHAR.184 IDD Block current consumption Enabled, configured for 400kbps mA - - 0.260 0.06 0.09 0.12

GPIO CHAR.20 Vih_5p5V Input Voltage high threshold CMOS Input, PRT[x]CTL = 0 V 0.7*Vddio - - 0.411*Vddio 0.411*Vddio 0.4112*Vddio

GPIO CHAR.21 Vih_1p7V Input Voltage high threshold CMOS Input, PRT[x]CTL = 0 V 0.7*Vddio - - 0.498*VDDIO 0.507*VDDIO 0.517*VDDIO 0.531*Vddio 0.547*Vddio 0.589*Vddio

GPIO CHAR.22 Vil_5p5V Input voltage low threshold CMOS Input, PRT[x]CTL = 0 V - - 0.3*Vddio 0.395*Vddio 0.405*Vddio 0.414*Vddio

GPIO CHAR.23 Vil_1p7V Input voltage low threshold CMOS Input, PRT[x]CTL = 0 V - - 0.3*Vddio 0.480*VDDIO 0.489*VDDIO 0.500*VDDIO 0.484*Vddio 0.486*Vddio 0.492*Vddio

GPIO CHAR.24 Vih Input Voltage high threshold LVTTL Input, PRT[x]CTL = 1, Vddio < 2.7V V 0.7*Vddio - - 0.448*VDDIO 0.459*VDDIO 0.469*VDDIO 0.409*Vddio 0.465*Vddio 0.572*Vddio

GPIO CHAR.25 Vih Input Voltage high threshold LVTTL Input, PRT[x]CTL = 1, Vddio > =2.7V V 2 - - 1.237*VDDIO 1.252*VDDIO 1.273*VDDIO 1.11 1.40 1.81

GPIO CHAR.26 Vil Input Voltage low threshold LVTTL Input, PRT[x]CTL = 1, Vddio < 2.7V V - - 0.3*Vddio 0.427*VDDIO 0.440*VDDIO 0.452*VDDIO 0.401*Vddio 0.439*Vddio 0.466*Vddio

GPIO CHAR.27 Vil Input Voltage low threshold LVTTL Input, PRT[x]CTL = 1, Vddio >=2.7V V - - 0.8 1.188*VDDIO 1.203*VDDIO 1.221*VDDIO 1.08 1.35 1.74

GPIO CHAR.28 Voh Output Voltage high Ioh = 4mA at 3.3Vddio V Vddio - 0.6 - - 2.95 3.03 3.04 Vddio-0.278 Vddio-0.217 Vddio-0.152

GPIO CHAR.29 Voh Output Voltage high Ioh = 1mA at 1.8Vddio V Vddio - 0.5 - - 1.60 1.66 1.67 Vddio-0.125 Vddio-0.091 Vddio-0.046

GPIO CHAR.30 Vol Output Voltage low Iol = 8mA at 3.3Vddio V - - 0.6 0.19 0.19 0.19 0.15 0.20 0.25

GPIO CHAR.32 Vol Output Voltage low Iol = 4mA at 1.8Vddio V - - 0.6 0.17 0.18 0.19 0.08 0.14 0.20

GPIO CHAR.33 Rpullup Pull-up Resistor kOhm 3.5 5.6 8.5 5.30 5.55 5.85 5.79 6.17 6.55

GPIO CHAR.34 Rpulldown Pull-down Resistor kOhm 3.5 5.6 8.5 5.35 5.91 5.59 4.73 5.12 5.51

GPIO CHAR.35 Iil input leakage current (Absolute value) [1] 25'C, Vddio = 3.0V nA - - 2 - - 1.2

GPIO CHAR.36 Cin Input capacitance GPIOs not shared with opamp outputs, MHz ECO or kHzECO pF - 4.0 7 2.60 7.63 4.16

GPIO CHAR.37 Cin Input capacitance GPIOs shared with MHz ECO or kHzECO pF - 5.0 7 4.56 5.48 4.76

GPIO CHAR.38 Cin Input capacitance GPIOs shared with opamp outputs pF - - 18 16.54 16.69 17.00 16.45 16.73 16.98

GPIO CHAR.40 Vh LVTTL - Input Voltage Hysterisis (Schmitt-Trigger) [1] mV - 40.0 - 4.00 36.83 110.00 60.00 75.00 80.00

GPIO CHAR.41 Idiode Current through protection diode to Vddio and Vssio uA - - 100

GPIO CHAR.42 Rglobal Resistance pin to analog global bus 25 C, VDDIO = 3.0 V Ohm - 320.0 - 404.16 436.10 458.22 423.73 520.51 672.04

GPIO CHAR.43 Rmux Resistance pin to analog mux bus 25 C, VDDIO = 3.0 V Ohm - 220.0 - 304.46 323.38 342.59 295.86 375.08 495.05

Covered in ESD

Measured value is less than 1 nA

Data Sheet CY8C3xxxx FAB 25 Characterization DataSkywater FAB 4 Characterization Data

No Data

No Data

Covered in ESD

No Data

No Data

No Data

No Data

GPIO AC Specification Block CHAR ID Parameter Description Conditions Units Min Typical Max Min Average Max Min Average Max

GPIO CHAR.44 TriseF Rise time in Fast Strong Mode [1] 3.3V Vddio Cload = 25 pF ns - - 12 2.34 6.15 7.14 1.62 2.62 3.49

GPIO CHAR.45 TfallF Fall time in Fast Strong Mode[1] 3.3V Vddio Cload = 25 pF ns - - 12 2.91 6.59 7.37 1.96 3.21 4.26

GPIO CHAR.46 TriseS Rise time in Slow Strong Mode [1] 3.3V Vddio Cload = 25 pF ns - - 60 17.3 33.6 36.4 14.41 16.71 18.31

GPIO CHAR.47 TfallS Rise time in Slow Strong Mode [1] 3.3V Vddio Cload = 25 pF ns - - 60 17.1 33.9 37.2 14.91 16.50 18.31

GPIO CHAR.48 Fgpioout GPIO output operating frequency 2.7V < Vddio < 5.5V, Fast strong drive mode 90/10% Vddio into 25 pF, -40C Ta 85C and Tj 100C MHz - - 33

GPIO CHAR.50 Fgpioout GPIO output operating frequency 1.71V < Vddio < 2.7V, Fast strong drive mode 90/10% Vddio into 25 pF, -40C Ta 85C and Tj 100C MHz - - 20

GPIO CHAR.52 Fgpioout GPIO output operating frequency 3.3V < Vddio < 5.5V, Slow strong drive mode 90/10% Vddio into 25 pF, -40C Ta 85C and Tj 100C MHz - - 7

GPIO CHAR.54 Fgpioout GPIO output operating frequency 1.71V < Vddio < 3.3V, Slow strong drive mode 90/10% Vddio into 25 pF, -40C Ta 85C and Tj 100C MHz - - 3.5

GPIO CHAR.56 Fgpioin GPIO input operating frequency 90/10% VDDIO, -40C Ta 85C and Tj 100C MHz - - 66

Functionally tested with 10% margin








Data Sheet CY8C3xxxx FAB 25 Characterization DataSkywater FAB 4 Characterization Data



SIO DC Specification

Block CHAR ID Parameter Description Conditions Units Min Typical Max Min Average Max Min Average Max

SIO CHAR.65 Vinmax Maximum Input Voltage All allowed values of Vddio and Vdd (see section 11.2.1) V - - 5.5

SIO CHAR.66 Vinref Input voltage reference (Set by internal DAC) V 0.5 - 0.52*Vddio

SIO CHAR.67 Voutref Output voltage reference (set internally for adjustable output levels) Vddio > 3.7 V 1 - Vddio-1

SIO CHAR.68 Voutref Output voltage reference (set internally for adjustable output levels) Vddio < 3.7 V 1 - Vddio - 0.5

SIO CHAR.69 Vih Input voltage high threshold GPIO mode CMOS input V 0.7 * Vddio - - 0.496*VDDIO 0.507*VDDIO 0.520*VDDIO 0.41*Vddio 0.47*Vddio 0.59*Vddio

SIO CHAR.70 Vih Input voltage high threshold Differential input mode Hysteresis disabled V SIO_ref+0.2 - - 0.57 0.59 0.62 0.01 0.089 0.231

SIO CHAR.71 Vil Input voltage low threshold GPIO mode CMOS input V - - 0.3*Vddio 0.474*VDDIO 0.486*VDDIO 0.497*VDDIO 0.4*Vddio 0.44*Vddio 0.49*Vddio

SIO CHAR.72 Vil Input voltage low threshold Differential input mode Hysteresis disabled V - - SIO_ref -0.2 0.545*VDDIO 0.565*VDDIO 0.586*VDDIO 0.002 0.013 0.025

SIO CHAR.73 Voh Output voltage high Unregulated mode Ioh = 4mA, Vddio = 3.3V V Vddio - 0.4 - - 2.91 3.03 3.04 0.111 0.155 0.191

SIO CHAR.74 Voh Output voltage high Regulated mode Ioh = 1mA, Vddio = 3.3V V SIO_ref-0.65 - SIO_ref + 0.2 3.28 3.29 3.29SIO_ref + 0.015 SIO_ref + 0.104 SIO_ref + 0.161

SIO CHAR.75 Voh Output voltage high Regulated mode Ioh = 0.1mA V SIO_ref-0.3 - SIO_ref + 0.2 3.04 3.23 3.25SIO_ref - 0.224 SIO_ref - 0.235 SIO_ref - 0.256

SIO CHAR.77 Vol Output voltage low Vddio = 3.3V, lol = 25mA V - - 0.8 0.19 0.19 0.19 0.327 0.459 0.583

SIO CHAR.78 Vol Output voltage low Vddio = 3.3V, lol = 20mA V - - 0.4 0.260 0.352 0.430

SIO CHAR.79 Vol Output voltage low Vddio = 1.80V, lol = 4mA V - - 0.4 0.170 0.190 0.190 0.071 0.105 0.136

SIO CHAR.80 Rpullup Pull-up Resistor kOhm 3.5 5.6 8.5 5.26 5.57 5.84 5.03 5.45 5.84

SIO CHAR.81 Rpulldown Pull-down Resistor kOhm 3.5 5.6 8.5 5.31 5.61 5.89 5.17 5.57 5.96

SIO CHAR.82 Iil Input leakage current (absolute value) [1] Vih



Page 10 of 13

SIO AC Specification Block CHAR ID Parameter Description Conditions Units Min Typical Max Min Average Max Min Average Max

SIO CHAR.88 TriseF Rise time in fast strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V ns - - 12 2.59 3.5 4.49 2.77 3.56 4.53

SIO CHAR.89 TfallF Fall time in fast strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V ns - - 12 2.71 3.28 3.81 2.39 3.21 4.07

SIO CHAR.90 TriseS Rise time in slow strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V ns - - 75 4.37 4.75 5.18 23.15 37.05 46.75

SIO CHAR.91 TfallS Fall time in slow strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V ns - - 60 3.78 4.06 4.33 19.96 36.12 47.50

SIO CHAR.92 FsiooutSIO output operating frequency

2.7 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, fast strong drive mode

90/10% VDDIO into 25 pF, -40C

Ta 85C and Tj 100CMHz - - 33


1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast strong drive mode90/10% VDDIO into 25 pF MHz - - 16


3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow strong drive mode90/10% VDDIO into 25 pF MHz - - 5


1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow strong drive mode90/10% VDDIO into 25 pF MHz - - 4


2.7V < VDDIO < 5.5 V, Regulated output mode, fast strong drive modeOutput continuously switching into 25 pF MHz - - 20


1.71 V < VDDIO < 2.7 V, Regulated output mode, fast strong drive modeOutput continuously switching into 25 pF MHz - - 10


1.71 V < VDDIO



Page 11 of 13

3.0 Packaging

Package Characteristics

Solder Reflow Peak Temperature

48 pin SSOP O483 Package Outline, 51-85061



Page 12 of 13

100 pin TQFP (14 x 14 x 1.4 mm) A100SA Package Outline, 51-85048



Page 13 of 13

4.0 Document History Page

Rev. ECN No. Orig. of Change

Description of Change

** CY8C3XXX PSoC 3 FAB25 Characterization Report

Document No. 002-19700 Rev. *A ECN #: 5874099


Page 1 of 7

Cypress Semiconductor Sort Site Qualification Report

QTP# 171610 VERSION *A

September 2017

Cypress Test 25, Austin, Texas

Sort Site for S8 Technology

MPD / MCD Devices

FOR ANY QUESTIONS ON THIS REPORT, PLEASE CONTACT [email protected] or via a CYLINK CRM CASE

Prepared By: Honesto Sintos

Reviewed By: Lorena Zapanta

Reliability Engineer Reliability Manager

Approved By:

David Hoffman

Reliability Director
mailto:[email protected]



Page 2 of 7

PACKAGE/PRODUCT QUALIFICATION HISTORY

QTP Number

Description of Qualification Purpose Date

151907 Cypress Test 25, Austin, Texas Sort Site Qualification for S4 Technology

June 2015

171610 Cypress Test 25, Austin, Texas Sort Site Qualification for S8 Technology

April 2017



Page 3 of 7

QUALIFICATION COVERAGE RANGE

MARKETING PART NUMBER DEVICE DESCRIPTION

CY8C4013 / CY8C4014 / CY8CMBR3002 / CY8CMBR3102 / CY8CMBR3110

CapSense MBR3

CY8CMBR31 / CY8C4013 / CY8C4014 PSoC 4000

CY8C4014 Automotive PSoC 4000

CY8C4124 / CY8C4125 / CY8C4244 / CY8C4245 PSoC 4100 & PSoC 4200

CY8C4124 / CY8C4125 / CY8C4244 / CY8C4245 Automotive PSoC 4100 & PSoC 4200

CY8CEBIKE PSoC 4100 & PSoC 4200

CY8C4125 /CY8C4126 / CY8C4127 PSoC 4100M & PSoC 4200M M Series

CY8C4245 / CY8C4246 / CY8C4247 PSoC 4100M & PSoC 4200M M Series

CY8C4246 / CY8C4247 / CY8C4248 PSoC 4200L L-Series

CY8C4127 / CY8C4247 PSoC 4 BLE 128K

CYBL1016 / CYBL10162 / CYBL10163 PRoCTM-BLE 128K



CYBL10999 PRoCTM-BLE 128K

CY8C4128 / CY8C4248 PSoC 4 BLE 256K

CYBL10573 PRoCTM-BLE 256K

CY8C3244 / CY8C3245 / CY8C3246 / CY8C3444 Automotive PSoC 3

CY8C3445 / CY8C3446 / CY8C3645 / CY8C3646 CY8C3665 / CY8C3666 / CY8C3846 /

CY8C3866 / Automotive PSoC 3

CY8C3244 / CY8C3245 / CY8C3246 / CY8C3444 PSoC 3

CY8C3445 / CY8C3446 / CY8C3665 / CY8C3666 / CY8C3846 / CY8C3865 /

CY8C3866 / CY8C3MFIDOCK / CY8C3USBAUDIO PSoC 3

CY8C5267 / CY8C5268 / CY8C5287 / CY8C5288/ CY8C5467 / CY8C5468 / CY8C5488 / CY8C5666

CY8C5667 / CY8C5668 / CY8C5688 / CY8C5866 / CY8C5867 / CY8C5868 / CY8C5888

PSoC 5LP

CY8CTMA1036 / CY8CTMA460 / CY8CTMA461/ CY8CTMA768

Automotive True Touch Gen4 Touchscreen Controller



Page 4 of 7

QUALIFICATION COVERAGE RANGE

MARKETING PART NUMBER DEVICE DESCRIPTION

CYTMA445A / CYTMA525A / CYTT21100 CYTT21401 / CYTT21402 /CYTT21403

True Touch Gen6M Touchscreen Controller

CYTT21100 / CYTT21401/ CYTT21402 CYTT21403 / CYTT31401/ CYTT31702

CYTT31802 / CYTT32302

True Touch Gen6L Touchscreen Controller

CYAT81682 / CYAT81685 / CYAT81688 Automotive True Touch Gen6XL

Touchscreen Controller

CYFPA1I True Touch Fingerprint

CYPD1103 / CYPD1104 / CYPD1105 CYPD1120 / CYPD1121 / CYPD1122

CYPD1134

EZ-PDTM CCG1 USB Type-C PD Controller

CYPD2103 / CYPD2104 / CYPD2105 CYPD2119 / CYPD2120 / CYPD2134

EZ-PDTM CCG2 USB Type-C PD Controller

CY7C65210 / CY7C65211 / CY7C65213 CY7C65215 / CY7C65217 / CY7C65221

USB-Serial Bridge Controller

CY14B064 / CY14E064 / CY14MB064 / CY14ME064 64Kb Serial nvSRAM

CY14B256 / CY14E256 256Kb Serial nvSRAM

CY14B512 512Kb Serial nvSRAM

CY14B101 / CY14E101 1Mb Serial nvSRAM

CY14V101 1Mb Quad SPI nvSRAM

CY14B256 / CY14E256 / CY14U256 / CY14V256 256Kb Parallel nvSRAM

CY14101V / CY14B101 / CY14V101 1Mb Parallel nvSRAM

CY14B102NS 2Mb Parallel nvSRAM

CY14104V / CY14B104 / CY14V104 4Mb Parallel nvSRAM

CY14B108 / CYATB108 8Mb Parallel nvSRAM

CY14B116 / CY14V116 / CY14E116 16Mb Parallel nvSRAM

CY27410F / CY27410L 4-PLL Spread-Spectrum Clock Generator



Page 5 of 7

Reliability Test Data

QTP #: 151907

Device Fab Lot # Assembly Lot# Test Loc Yield

SORT TEST: CORRELATION

Sort Yield:

8C24094AC 4446219 w2, w4, w5 N/A CMI-FAB25 Correlated

8A24094AC 4510997 w5, w6, w7 N/A CMI-FAB25 Correlated

8A24094AC 4506339 w6, w7, w8 N/A CMI-FAB25 Correlated

Bin Movement:

8C24094AC 4446219 w2 N/A CMI-FAB25 Correlated

8A24094AC 4510997 w5 N/A CMI-FAB25 Correlated

8A24094AC 4506339 w6 N/A CMI-FAB25 Correlated

Fishers Exact:

8C24094AC 4446219 w2, w4, w5 N/A CMI-FAB25 >0.05

8A24094AC 4510997 w5, w6, w7 N/A CMI-FAB25 >0.05

8A24094AC 4506339 w6, w7, w8 N/A CMI-FAB25 >0.05



Page 6 of 7


QTP #: 171610

Device Fab Lot # Assembly Lot# Test Loc Yield

SORT TEST: CORRELATION

Sort Yield:

8A20680BB 3639013 w21 N/A FAB25 Correlated

Bin Movement:

8A20680BB 3639013 w21 N/A FAB25


Document History Page

Document Title: QTP#171610: Cypress Test 25, Austin, Texas Sort Site for S8 Technology Document Number: 002-19700


Page 7 of 7

Rev. ECN No.

Orig. of Change


** 5747717 HSTO Initial Spec Release

*A 5874099 GKUS 1. Rearranged the nvSRAM parts as per the density & interface. 2. Included CY14B101 in the 1Mb Serial nvSRAM row which was

missed in the last revision.

Document No. 002-23499 Rev. *B ECN #: 6168197


Page 1 of 11

Cypress Semiconductor Automotive Product Qualification Report

QTP# 164004 VERSION **

June 2018

Automotive PSoC3 Device Family S8P-5PT Technology, Fab25

CY8CTMA616A CY8CTMA884A

Automotive Programmable System-On-Chip (PSoC) Application

FOR ANY QUESTIONS ON THIS REPORT, PLEASE CONTACT [email protected] or via a CYLINK CRM CASE

Prepared By: Honesto Sintos

Reviewed By: Sandhya Chandrashekhar


Approved By:

David Hoffman




Page 2 of 11

PRODUCT QUALIFICATION HISTORY

Qual Report


Comp

164004 Qualification of Automotive PSoC3 T05 Device, S8P-5P Technology, Fab25 June 2018



Page 3 of 11

PRODUCT DESCRIPTION

Qualification of Automotive PSoC3 T05 Device, S8P-5P Technology, Fab25

Marketing Part #: CY8CTMA616A / CY8CTMA884A

Device Description: Automotive Programmable System on a Chip

Cypress Division: Cypress Semiconductor Corporation MCU and Connectivity Division (MCD)

TECHNOLOGY/FAB PROCESS DESCRIPTION

Number of Metal Layers: Proprietary Metal Composition: Proprietary

Passivation Type and Materials: Proprietary

Generic Process Technology/Design Rule Proprietary

Gate Oxide Material/Thickness (MOS): Proprietary

Name/Location of Die Fab (prime) Facility: Cypress, Fab 25

Die Fab Line ID/Wafer Process ID: S8P-5P

PACKAGE AVAILABILITY

PACKAGE ASSEMBLY FACILITY SITE QTP NUMBER

100-Lead TQFP 14x14x1.4mm ASEK-Taiwan (G) 174308



Page 4 of 11

MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION

Package Designation: AZ0AB

Package Outline, Type, or Name: 100-Lead TQFP 14x14x1.4mm

Mold Compound Name/Manufacturer: EME-G631H / Sumitomo

Mold Compound Flammability Rating: UL-94 V-0

Mold Compound Alpha Emission Rate: N/A (Not low alpha mold compound)

Oxygen Rating Index: >28% 54%

Lead Frame Designation: Full Metal Pad

Lead Frame Material: Copper

Substrate Material: N/A

Lead Finish, Composition / Thickness: Pure Sn

Die Backside Preparation Method/Metallization: Backgrind

Die Separation Method: Wafer Saw

Die Attach Supplier: Sumitomo

Die Attach Material: CRM-1076WA

Bond Diagram Designation 002-19665

Wire Bond Method: Thermosonic

Wire Material/Size: Au / 0.8mil (20um)

Thermal Resistance Theta JA C/W: 34

Package Cross Section Yes/No: Yes

Assembly Process Flow: 49-41999M

Name/Location of Assembly (prime) facility: ASEK-Taiwan (G)

MSL LEVEL 3

REFLOW PROFILE 260C

ELECTRICAL TEST / FINISH DESCRIPTION

Test Location: CML-R

Note: Please contact a Cypress Representative for other packages availability.



Page 5 of 11

RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENT

Stress/Test Test Condition (Temp/Bias)

Result P/F

High Temperature Operating Life Early Failure Rate

AEC-Q100-008 and JESD22-A108, 150C

Dynamic Operating Condition, Vcc Max = 5.77V P

Endurance /High Temperature Operating Life Latent Failure Rate

JESD22-A108, 150C / Endurance (200k Cycles) Dynamic Operating Condition, Vcc Max = 5.77V P

High Accelerated Saturation Test (HAST)

JESD22-A110, 130C, 5.0V, 85%RH

Precondition: JESD22-A113 Moisture Sensitivity MSL 3

192 Hrs, 30C/60%RH+3IR-Reflow, 260C+0, -5C P

Temperature Cycle JESD22-A104, -65C to 150C Precondition: JESD22-A113 Moisture Sensitivity MSL 3

192 Hrs, 30C/60%RH+3IR-Reflow, 260C+0, -5C

P

Pressure Cooker JESD22-A102, 121C, 100%RH, 15 Psig


192 Hrs, 30C/60%RH+3IR-Reflow, 260C+0, -5C P

Acoustic J-STD-020



P

Endurance/Data Retention Endurance (200k Cycles)

AEC-Q100-005, 150C, non-biased P

Wire Bond Pull Mil-Std 883, Method 2011 P

Post Temperature Cycle Wire Bond Pull

Mil-Std 883, Method 2011 P

Dye Penetrant Test Criteria: No Package Crack P

Electrostatic Discharge Charge Device Model (ESD-CDM)

AEC-Q100-011

250V/500V/ 750V (corner pins) P

Electrostatic Discharge

Human Body Model (ESD-HBM)

AEC-Q100-002

500V/1000V/2000V P

Static Latch-up AEC-Q100-004, 125C, 100mA P

Electrical Distribution AEC-Q100-009 P

Wire Ball Shear AEC-Q100-001 P

Final Visual JESD22-B101B P

Physical Dimensions JESD22B100 and B108 P

Constructional Analysis Criteria: Meet external and internal characteristics of Cypress package P

Solderability JESD22-B102 P



Page 6 of 11

RELIABILITY FAILURE RATE SUMMARY

Stress/Test Device Tested/ Device Hours

# Fails

Activation Energy

Thermal AF3

Failure Rate

High Temperature Operating Life Early Failure Rate

11,597 Devices 0 N/A N/A 0 PPM

High Temperature Operating Life1,2 Long Term Failure Rate

99,960 Device Hours 0 0.7 170 ** FIT

**Insufficient samples to calculate FIT Rate. **Based on Automotive qualification samples size.

1 Assuming an ambient temperature of 55C and a junction temperature rise of 15C. 2 Chi-squared 60% estimations used to calculate the failure rate.. 3 Thermal Acceleration Factor is calculated from the Arrhenius equation

where: EA =The Activation Energy of the defect mechanism. K = Boltzmanns constant = 8.62x10-5 eV/Kelvin. T1 is the junction temperature of the device under stress and T2 is the junction temperature of the device at

use conditions.

AF = E

k

1

T-

1

T

A

2 1

exp



Page 7 of 11


QTP #: 164004

Device Package Fab Lot # Assy Lot # Assy Loc Duration Samp Rej Failure Mechanism

STRESS: ACOUSTIC, MSL3

CY8CTMA616AA2 (8A3866HB) AZ100 3751070 611802728 ASE-G COMP 22 0

CY8CTMA616AE2 (8A3866HB) AZ100 3751087 611802729 ASE-G COMP 22 0


STRESS: BALL SHEAR




STRESS: BOND PULL




STRESS: CHARACTERIZATION


STRESS: CONSTRUCTIONAL ANALYSIS




STRESS: DIE SHEAR




STRESS: DYE PENETRANT






Page 8 of 11


QTP #: 164004


STRESS: ELECTRICAL DISTRIBUTION




STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 5.77V, Vcc Max

CY8CTMA616AA2 (8A3866HB) AZ100 3751070 611802728 ASE-G 48 3008 0

CY8CTMA616AE2 (8A3866HB) AZ100 3751087 611802729 ASE-G 48 4369 0


STRESS: ENDURANCE + DATA RETENTION, 150C

CY8CTMA616AA2 (8A3866HB) AZ100 3751070 611802728 ASE-G CYCLING 76 0


CY8CTMA616AE2 (8A3866HB) AZ100 3751087 611802729 ASE-G CYLING 80 0




STRESS: ENDURANCE + HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 5.77V, Vcc Max







STRESS: ESD-CHARGE DEVICE MODEL






Page 9 of 11


QTP #: 164004


STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22-A114-B





STRESS: FINAL VISUAL INSPECTION




STRESS: HI-ACCEL SATURATION TEST, 130C, 5.5V, 85%RH, PRE COND 192 HR 30C/60%RH, MSL3




STRESS: PRESSURE COOKER TEST







STRESS: PHYSICAL DIMENSION




STRESS: POST TCT BOND PULL




Page 10 of 11


QTP #: 164004


STRESS: PRE/POST LFR CRITICAL PARAMETERS




STRESS: STATIC LATCH-UP (+/-100mA 125C)


STRESS: SOLDERABILITY




STRESS: TC COND. C -65C TO 150C, PRECONDITION 192 HRS 30C/60%RH







STRESS: X-RAY






Document Title: QTP#180907: AUTOMOTIVE PSoC 4000S S8PFHD-10R TECHNOLOGY, Fab25 (Cu BEOL INTERCONNECT)

Document Number: 002-23499


Page 11 of 11

Rev. ECN No.

Orig. of Change


** HSTO Initial Spec Release

Document No.002-24180 Rev. **ECN # 6201199

Company ConfidentialA printed copy of this document is considered uncontrolled. Refer to online copy for latest revision.

Page 1 of 9

Cypress Semiconductor AutomotivePackage Qualification Report

QTP# 174308 VERSION **June 2018

100-lead TQFP (14x14x1.4mm)

Pure Sn leadfinish, Au Wire

MSL3, 260C Reflow

ASEK-Taiwan (G)

FOR ANY QUESTIONS ON THIS REPORT, PLEASE [email protected] or via a CYLINK CRM CASE

Prepared By:Honesto Sintos

Reviewed By:Lorena Zapanta


Approved By:David Hoffman




Page 2 of 9

PACKAGE QUALIFICATION HISTORY

QTPNumber


174308

Qualification of Automotive 100-lead TQFP (14x14x1.4mm) Packagein ASEK-Taiwan (G) using 0.8mil Au wire with EME-G631H moldcompound, CRM1076WA die attach material, Cu leadframe and PureSn leadfinish at MSL3, 260C Reflow Temperature

Jun2018



Page 3 of 9

MAJOR PACKAGE INFORMATION USED IN THIS QUALIFICATION

Package Designation: AZ0AB

Package Outline, Type, or Name: 100-Lead TQFP 14x14x1.4mm

Mold Compound Name/Manufacturer: EME-G631H / Sumitomo

Mold Compound Flammability Rating: UL-94 V-0

Mold Compound Alpha Emission Rate: N/A (Not low alpha mold compound)

Oxygen Rating Index: >28% 54%

Lead Frame Designation: Full Metal Pad

Lead Frame Material: Copper

Substrate Material: N/A

Lead Finish, Composition / Thickness: Pure Sn

Die Backside Preparation Method/Metallization: Backgrind

Die Separation Method: Wafer Saw

Die Attach Supplier: Sumitomo

Die Attach Material: CRM-1076WA

Bond Diagram Designation 002-19665

Wire Bond Method: Thermosonic

Wire Material/Size: Au / 0.8mil (20um)

Thermal Resistance Theta JA C/W: 34

Package Cross Section Yes/No: Yes

Assembly Process Flow: 49-41999M

Name/Location of Assembly (prime) facility: ASEK-Taiwan (G)

MSL LEVEL 3

REFLOW PROFILE 260C

ELECTRICAL TEST / FINISH DESCRIPTION

Test Location: CML (R)

Note: Please contact a Cypress Representative for other package availability.



Page 4 of 9

RELIABILITY TESTS PERFORMED PER SPECIFICATION REQUIREMENTS

Stress/Test Test Condition(Temp/Bias)

ResultP/F

High Temperature Operating LifeEarly Failure Rate

AEC-Q100-008 and JESD22-A108, 150C

Dynamic Operating Condition, Vcc Max = 5.77VP

Endurance /High TemperatureOperating Life Latent Failure Rate

JESD22-A108, 150C / Endurance (200k Cycles)Dynamic Operating Condition, Vcc Max = 5.77V P

High Accelerated Saturation Test(HAST)

JESD22-A110, 130C, 5.0V, 85%RH


192 Hrs, 30C/60%RH+3IR-Reflow, 260C+0, -5CP

Temperature Cycle JESD22-A104, -65C to 150CPrecondition: JESD22-A113 Moisture Sensitivity MSL 3


Pressure Cooker JESD22-A102, 121C, 100%RH, 15 Psig



Acoustic J-STD-020



P

Endurance/Data Retention Endurance (200k Cycles)

AEC-Q100-005, 150C, non-biasedP

Wire Bond Pull Mil-Std 883, Method 2011 P

Post Temperature Cycle WireBond Pull

Mil-Std 883, Method 2011P

Dye Penetrant Test Criteria: No Package Crack P

Electrostatic Discharge ChargeDevice Model (ESD-CDM)

AEC-Q100-011

250V/500V/ 750V (corner pins)P

Electrostatic Discharge

Human Body Model (ESD-HBM)

AEC-Q100-002

500V/1000V/2000VP

Static Latch-up AEC-Q100-004, 125C, 100mA P

Electrical Distribution AEC-Q100-009 P

Wire Ball Shear AEC-Q100-001 P

Final Visual JESD22-B101B P

Physical Dimensions JESD22B100 and B108 P

Constructional Analysis Criteria: Meet external and internal characteristics of Cypress package P

Solderability JESD22-B102 P



Page 5 of 9


QTP #: 174308


STRESS: ACOUSTIC, MSL3




STRESS: BALL SHEAR




STRESS: BOND PULL




STRESS: CHARACTERIZATION


STRESS: CONSTRUCTIONAL ANALYSIS




STRESS: DIE SHEAR




STRESS: DYE PENETRANT






Page 6 of 9


QTP #: 174308


STRESS: ELECTRICAL DISTRIBUTION




STRESS: HIGH TEMP DYNAMIC OPERATING LIFE-EARLY FAILURE RATE, 150C, 5.77V, Vcc Max




STRESS: ENDURANCE + DATA RETENTION, 150C







STRESS: ENDURANCE + HIGH TEMP DYNAMIC OPERATING LIFE-LATENT FAILURE RATE, 150C, 5.77V, Vcc Max







STRESS: ESD-CHARGE DEVICE MODEL






Page 7 of 9


QTP #: 174308


STRESS: ESD-HUMAN BODY CIRCUIT PER JESD22-A114-B





STRESS: FINAL VISUAL INSPECTION




STRESS: HI-ACCEL SATURATION TEST, 130C, 5.5V, 85%RH, PRE COND 192 HR 30C/60%RH, MSL3




STRESS: PRESSURE COOKER TEST







STRESS: PHYSICAL DIMENSION




STRESS: POST TCT BOND PULL




Page 8 of 9


QTP #: 174308


STRESS: PRE/POST LFR CRITICAL PARAMETERS




STRESS: STATIC LATCH-UP (+/-100mA 125C)


STRESS: SOLDERABILITY




STRESS: TC COND. C -65C TO 150C, PRECONDITION 192 HRS 30C/60%RH







STRESS: X-RAY






Document Title: QTP#174308: AUTOMOTIVE 100-LEAD TQFP (14x14x1.4mm) PURE SN LEADFINISH, AUWIRE MSL3, 260C REFLOW ASEK-TAIWAN (G)

Document Number: 002-24180


Page 9 of 9

Rev. ECNNo.

Orig. ofChange


** 6201199 HSTO Initial spec release

Item Marketing Part Number Sample Order Part Number

1 CY8C3666AXA-052 CY8C3666AXA2-052; Subject to lead time

2 CY8CTMA616AA-12 CY8CTMA616AA2-12;

3 CY8CTMA616AA-12T CY8CTMA616AA2-12;

4 CY8CTMA616AA-13 CY8CTMA616AA2-13; Subject to lead time

5 CY8CTMA616AA-13T CY8CTMA616AA2-13; Subject to lead time





10 CY8CTMA616AE-12 CY8CTMA616AE2-12;

11 CY8CTMA616AE-12T CY8CTMA616AE2-12;



14 CY8CTMA616AE-22 CY8CTMA616AE2-22; Subject to lead time

15 CY8CTMA616AE-22T CY8CTMA616AE2-22; Subject to lead time



















34 CG8895AT CG8895XT; Subject to lead time

35 CG8895ATT CG8895XT; Subject to lead time

36 CP7525AT CP7525XT; Subject to lead time



39 CP8085AT CP8085XT;

40 CP8085ATT CP8085XT;

41 CP8143BT CP8143XT;

42 CP8143BTT CP8143XT;

43 CP8143DT CP8143YT; Subject to lead time

44 CP8143DTT CP8143YT; Subject to lead time

45 CP8143FT CP8143YT; Subject to lead time

46 CP8143FTT CP8143YT; Subject to lead time

47 CP8184BT CP8184XT; Subject to lead time

48 CP8184BTT CP8184XT; Subject to lead time

49 CP8361BT CP8361XT;

50 CP8361BTT CP8361XT;

51 CP8428AT CP8428XT;


53 CP8429AT CP8429XT;


55 CP8531AT CP8531XT;

26403-PSoC3_Customer_Char_Report.pdfTable of ContentsIntroductionCharacterization Hardware and SetupElectrical SpecificationPackageDocument HistoryIntroduction1 General DescriptionDatasheetReference Documents and Application NotesQualification ReportPin ListThe Pinout diagram of the available package is shown below.48 - Pin SSOP and 100 Pin TQFP part pinout.1.0 Characterization Hardware and SetupDC Measurement System and HardwareTemperature Forcing SystemTest Conditions2.0 Characterization DataAbsolute Maximum RatingsDevice Level Specification: N/APower Regulators: N/AGPIO DC SpecificationsGPIO AC SpecificationSIO DC SpecificationSIO AC SpecificationXRES DC SpecificationXRES AC SpecificationAnalog Peripherals: N/ADigital Peripherals: N/AMemory: N/APSoC System Resources: N/AClocking: N/A3.0 PackagingPackage CharacteristicsSolder Reflow Peak Temperature48 pin SSOP O483 Package Outline, 51-85061100 pin TQFP (14 x 14 x 1.4 mm) A100SA Package Outline, 51-850484.0 Document History Page