INTELLIGENT CAMERA

XCI-V3

H/W SPECIFICATIONSVersion 0.1a

Change Tracking Revision Status

Changes Date Issued by / Revised by

0.1a First edition 2006/04/28 SONY_IS

Foreword

This is the hardware specification of CPU, CF, MB, TG, PA, and CN boards that constitute XCI-V3.

The contents of description may be subject to change without prior notice.

Reference data

Data sheets of major parts: URL. AMD GeodeTM GX Processors Data Book

November 2004 Publication ID:31505D - Revision D. AMD Geode TM CS5535 Companion Device Data Book

February 2005 Publication ID:31506B - Revision Bhttp://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863,00.html

. EDD2516AKTA (16M words x 16bits)Document No.E0502E20 (Ver.2.0) Date Published February 2005 (K) Japanhttp://www.elpida.com/ja/

. REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH POWER MANAGEMENTRTL8100C (L)2004-11-05 Rev.1.06http://www.realtek.com.tw/

1-1. Outline

XCI-V3 is an intelligent camera that employs x 86-compatible CPU incorporating a graphic controller and hasgeneral-purpose PC compatibility and VGA monitoroutput. Control can be done using a mouse and keyboardbecause USB1.1 is stored as an interface.

2-1. Features

2-1-1. Features of Camera Block

. High resolution330,000-pixels (effective pixel 640 (H) x 480 (V))PS CCD is mounted. This high resolution is mostsuitable for image processing because of square gratingand total-pixel read operation.

. High speed61 fps: VGA standard300 fps: 30 line (Partial scan mode)

. Partial scan functionVertical direction: Divided into 16.Horizontal direction: Divided into 10.

. Binning function1 x 2 binning(Addition of two lines in only the vertical direction)2 x 1 binning(Addition of two pixels in only the horizontal direction)2 x 2 binning(Addition of two pixels in the horizontal direction + twolines in the vertical direction)

. External trigger shutter functionTrigger pulse edge detection operationTrigger pulse width detection operation

. Trigger delay functionRead timing can be fine-adjusted in the range of 0 to 4seconds without changing the position of a camera.(Can be set in units of 1 ms.)

. LUT built-in

. PCI interfaceThis PCI interface conforms to PCI2.3. It is compatiblewith a 32-bit, 33-MHz bus master function.

2-1-2. Features of Processor Block

. High speed and low-power consumptionx86-compatible CPU400 MHz @1.1 WFan-less

. High-capacity memory256M bytes: DDR266128M bytes: Compact flash memory (in which OS,

drivers, and application are stored)8M bits: Flash memory (in which BIOS and a

camera adjustment value are stored)

2-1-3. Features of Interface Block

. 10Base-T/100Base-TX

. USB1.1-compatible

. RS-232C

. D-Sub 15-pin, VGA monitor output

. Digital I/OISO input/output: 1 channel eachTTL input/output: 1 channel input / 2 channel outputTrigger input: Storage start controlExposure output: External illumination control

. PA board/TG boardThis is a CCD driving and video signal processing block.This block is connected to a PCI bus using the TG board.

. DC/DCThis is a power supply block to each board.

. CF boardThis mounts CF of 128M bytes and a CPU companionchip.

. CPU boardThis mounts a Geode GX533 processor and DDR-SDRAM.

. MB boardThis mounts an LAN controller. The MB board is usedfor the interface of each board.

. CN boardThis mounts external input/output connectors (notincluding an LAN/USB connector).

3-1-2. Board Block Diagram

A board block diagram is as shown below.

3-1. System Configuration

3-1-1. System Connection Diagram

A system block diagram is as shown below.

Trigger input

LAN Host PC

DC-700

Power, trigger input, and exposure output

MonitoringProgram creationData IN/OUT

USB1.1

Monitor

RS-232CDigital IN/OUT

Exposure output

Data input/output

System Block Diagram

CF board

CPU board

DC/DC

CNboard

MB board

TG board

PA board

Board Block Diagram

3-1-3. System Block Diagram

A system block diagram is as shown below.

256

System Block Diagram

4-1. Specifications of Camera Block

Main devices are as shown below.

Main device list

N0. Board name Item Specifications

1 PA board CCD 1/3” 330,000-pixel square array interline CCD

Number of effective pixels: 659 (H) x 494 (V)

CCD vertical drive frequency: 31.8 kHz

CCD horizontal drive frequency: 24.5 MHz

Chip size: 5.79 mm (H) x 4.89 mm (V)

Unit cell size: 7.4 µm (H) x 7.4 µm

Video output Standard output: 640 (H) x 480 (V) = 307,200 pixels, 61 pfsspecifications

Video signal resolution 1 pixel: AFE output 10 bits/LUT output 8 bits

2 TG board FPGA Altera Cyclone EP1C12F324

PCI core PLD Applications

32Bit PCI Bus

Master/Target Interface, 33 MHz

Version 7.02

PCI Specification 2.3 compliant

4-1-1. Functions

A block diagram of FPGA is as shown below.A CCD output signal is A/D-converted into a 10-bit digital signal by the PA board and input to FPGA onthe TG board. Data size is changed from 10 bits to 8 bits using LUT installed in FPGA and data is outputto the processor block via a PCI interface. The minimum unit in which data is transferred is 128 bytes.

FPGA Block Diagram

: Video signal

1. TG/SG functionsThe functions below can be activated by setting the PCI setregister of TG/SG.

(1) Camera modeThe XCI-V3 has normal mode (monitoring mode) andtrigger modes. Each mode is set by MODE of a PCIregister.. Normal mode (Monitoring mode)

In the normal mode, a total pixel-independent videosignal is output as a continuous video signal of 1/61seconds. This monitoring mode is used when you wantto obtain a continuous standard image.Sixteen types of shutter speeds can be set in the range of1/100,000 to 2 seconds, and OFF. The shutter speed isset by SHUTTER of a PCI register. Refer to the PCIitem for the setting value.

. Trigger modeIn the trigger mode, exposure is started insynchronization with an external trigger input signal anda total pixel-independent video signal is output afterfixed time passes. This trigger mode is used when youwant to catch a subject moving at high speed in anaccurate position.A shutter is set during trigger pulse edge detection andtrigger pulse width detection. During trigger pulse edgedetection, 15 types of shutter speeds can be set in therange of 1/50,000 to 2 seconds. The shutter speed is setby SHUTTER of a PCI register. Pulse width detectionoperation is performed when the shutter speed is set toTrigger Width. Shutter speed T [s] is represented by theexpression below.T = Trigger width + 5 µsThe time lag between the trigger input and exposure startis approximately 3 µs. Refer to the PCI item for thesetting value.

(2) Binning functionThe frame rate or sensitivity is improved by adding pixelsin the vertical and horizontal directions. A binningfunction is set by BINNING of a PCI register. For detailsof the set value, refer to the PCI item.. V binning (1 x 2) mode

In this mode, the frame rate is made approximatelydouble and the data value is halved, by adding two linesin the vertical direction and reading them from CCD.The sensitivity is made approximately double when theshutter speed is set. The output data size is 640 (H) x240 (V).

. H binning (2 x 1) modeIn this mode, the sensitivity is made approximatelydouble and the data value is halved, by adding two pixelsin the horizontal direction and reading them from CCD.The period of a horizontal sync signal does not differfrom during normal operation, so the frame rate does notchange. The output data size is 320 (H) x 480 (V).

. HV binning (2 x 2) modeIn this mode, the frame rate and sensitivity are madeapproximately double and the data value is made quarter,by adding two lines in the vertical direction and twopixels in the horizontal direction and reading them fromCCD. Moreover, the sensitivity is made approximatelydouble when the shutter speed is set. The output datasize is 320 (H) x 240 (V).

(3) Partial scan functionThis function reads the arbitrary area, obtained when aneffective video period is divided by 1/16 in the verticaldirection and divided by 1/10 in the horizontal direction, asan effective video area and transfers the unnecessary areaat high speed to increase the frame rate. The start position(PSHTL in the horizontal direction and PSVTL in thevertical direction) and effective range (PSHEA in thehorizontal direction and PSVEA in the vertical direction)of an effective area are set to use this function. The high-rate scan function can be independently set to ON or OFFin the horizontal and vertical directions. It is set to ON orOFF by PSSEL of a PCI register.Refer to the PCI item or the setting value.nSet to the value in which PSHTL + PSHEA does notexceed 3 ‘b111 and in which PSVTL + PSVEA does notexceed 4 ‘b1111. The setting that does not satisfy thespecifications may cause malfunction.

The estimated value (highest-speed trigger period) of aframe rate during use of partial scan is as shown in thetable on the next page.

List of Frame Rate at Partial Scanning

131

125

120

Vertical Binning ：ON

160

151

144

137

Vertical

V PSOFF

120

169

120

Horizontal定

H PS OFF 299 237 197

148 140 133 126191 178 167 157

132 125

392 341 302

146

270 245 224 206

H PSON

（PSHEA)

174 163 154233 215 199 186

101

110 255

161 152 144

138

194 182 171225 208

409 356 314 282

131137

137

427 371 329

159

294 267 244

100 190 179 168255 235 218 203279447

011 151268 247 229 213293 177 167 159

389 344 308

159

151 144

151

469 408 361

176

144199 187323

010 210 197 186282 259 240 224

160

493 429 379 340 308

168297 274

167

001 196 186 176254 236 221 208359 325

186 177 169

520 452 400

196423 379 344000 234 220 207314 289 268 250550 478

168 147 130 117 68 65106 97 90 83

224 206

78 73

191 178 167 157 148 140341 302 270 245 133 126 120

61

86

81

77

73

70

67

64

61

Vertical

0000 0001 0010 0011 0100 0101 0110 0111

61

1000 1001 1010 1100 1101 1110 11111011

Vertical Binning ：OFF

1100 1101 1110

V PSOFF

V Partial Scan ON　(PSVEA)

V Partial Scan ON　(PSVEA)

0000 0001 0010 0011 0100 0101

73 6197 90 83 78

101

248

68 65

212

357 284 236 202

341

(fps)

0110

H PSON

（PSHEA)

000

001

010

011

100

(fps)0111

110

111

376 299

1000 1001 1010 1011 1111

86

111

※

Horizontal設

H PS OFF 392

419 333

396 315

277 236

262 224

271 225 192

325 259 215 183

311 248 206 176

299 237 197 168

206 183 165 149

195 173 156 141

185 164 148 134

176 156 140 127

168 149 134 121

160 142 128 116

153 136 122 111

147 130 117 106

137 126 117 109 102 96 91

129 119 111 103 97 91 86 81

123 113 105 98 92 86 81 77

117 107 100 93 87 82 77 73

111 102 95 89 83 78 74 70

106 98 91 85 79 75 70 67

102 94 87 81 76 71 67 64

(4) Trigger delay functionThis function delays the start of exposure proportionally tothe set time with respect to the trigger input signal to acamera. Read timing can be fine-adjusted without chang-ing the position of a camera. The delay value is set byDEL_TRIG of a PCI register. It can be set between 0 and4 seconds in units of 1 ms. Refer to the PCI item for thesetting value.nSet a trigger delay value to the value lower than the inputtrigger period by 10 ms or more. The setting that does notsatisfy the specifications may cause malfunction.

(5) Trigger polarity switching functionThis function can change the trigger input polarity of acamera by the TPOL setting of a PCI register. Refer to thePCI item for the setting value.

(6) Soft trigger functionThis function generates the trigger of a shutter speed (applox.1/15,000seconds) by writing “1” in SOFTT of a PCI register.(When “1” is written in SOFTT, it automatically becomes“0” after 60 micro seconds.) At that time, an arbitrary shutterspeed can be obtained by combining the shutter setting.nThe soft trigger function is invalidated when TPOL is “1:Negative polarity”.

2. AFE functions

(1) CDS gain adjustment functionThis is a gain adjustment function during factory setting.The CDS gain adjustment function is set by CDS of a PCIregister. Refer to the PCI item for the setting value.

(2) CLMP level adjustment functionThis is a video black clamp level adjustment functionduring factory setting. The CLMP level adjustmentfunction is set by CLMP of a PCI register. Refer to thePCI item for the setting value.

(3) Gain adjustment functionThis is a gain adjustment function. The gain adjustmentfunction is set by GAIN of a PCI register. Refer to the PCIitem for the setting value.

3. LUT (Look-Up Table) functionThis function converts the 10-bit video signal data fromAFE into 8-bit data. LUT data can be changed. Anarbitrary curve can be obtained by the LUT setting of aPCI register. Camera setting application has γ = 1, γ =0.45, γ = 2.2, Reverse, and Binarization as default.

LUT is set by writing the 8-bit data corresponding to anoutput luminance value in 1024 bytes (address 1024) in thememory space of PCI corresponding to the luminancevalue of a video input signal.n

Input

Input

Output

γ = 0.45

Input

Output

Binarization

Output

Arbitrary curve

4-1-2. Reflection Timing of Setting

The setting is reflected with the timing below.a. Immediately after a PCI register is rewritten (Monitoring mode and trigger mode in common)

MODE, TPOL, and SOFTTb.VD timing after a PCI register is rewritten (Monitoring mode and trigger mode in common)

CLMP, CDS, GAIN, LUT, BINNING, PSSEL, PSVTL, PSVEA, PSHTL, PSHEA, FSEL, and A11 - A33c. VD timing after a PCI register is rewritten (Monitoring mode)

SHUTTERd.Trigger input timing after a PCI register is rewritten (Trigger mode)

SHUTTER, DEL_TRIG, TRGINH, and DEL_STROB

In the normal mode, VD is self-advanced. In the trigger mode, VD is automatically generated after thefixed time of trigger input passes.nThe first interrupt signal after change in setting is changed is not generated when the setting of MODE,BINNING, PSSEL, PSVTL, PSVEA, PSHTL, and PSHEA is changed during DMA transfer.

4-1-3. Specifications of PCI Interface

1. PCI interface input/output terminalsThe PCI interface input/output terminals on the TG board and their functions are shown in the tablebelow.

PCI Interface Input/Output Terminal Function List

Signal name I/O Number of pins Signal type Function

PCICLK I 1 _ PCI bus clock

PWRST_N I 1 _ Reset

PCIAD I/O 32 t/s Address/data bus

C_BE_N I/O 4 t/s Bus command/byte enable

PAR I/O 1 _ Parity

FRAME_N I/O 1 s/t/s Cycle frame

IRDY_N I/O 1 s/t/s Initiator ready

TRDY_N I/O 1 s/t/s Target ready

DEVSEL_N I/O 1 s/t/s Device selection

STOP_N I/O 1 s/t/s Stop

IDSEL I 1 _ ID select

REQ_N O 1 t/s Request

GNT_N I 1 t/s Grant

INTB_N O 1 o/d Interrupt B

PERR_N I/O 1 s/t/s Parity error

SERR_N I/O 1 o/d System error

t/s: Tristates/t/s: Sustained tristateo/d: Open drainThe signal name to which _N is assigned at the end is an “Active low” signal.

Address

00h

04h

08h

0C h

10h

14h

18h

1Ch

20h

38h

3Ch

4Ch

FCh

31 24 23 16 15 8 7 0

Device ID: Read Only Vender ID: Read Only

1261 h 104D h

Status Register : Read/Write Vender ID: Read Only

Class Code Register : Read Only Revision ID : Read Only

Base Class Sub Class Programming I/F

09 h 80 h 00 h01 h

Header Type : Read Only

00 h

Base address register 3 : Read/Write : I/O space “0”

MAX_LAT : Read Only MIN_GNT : Read Only Interrupt Pin : Read Only Interrupt Line : Read/Write

00 h 00 h 01 h 00 h

Base address register 0 : Write from : Memory space “0”

Video data register

Base address register : Read/Write : Memory space “1”

Register for DMA transfer destination designation

Base address register 2 : Read/Write : Memory space “2”

LUT register

Camera setting register

2. Configuration spaceTable 4-1-3. 1 shows the address map of the configuration register to be installed. Table 4-1-3. 2 showsthe format of each base address register.

Address Map of Configuration Register

Table 4-1-3. 1

The transfer length of a video burst signal is prescribed as 128 bytes.

Memory space “0”10h :4,096Byte

Memory space “1”14h :128Byte

Memory space “2”18h :1,024Byte

Memory Address 0

Memory Type

Propriety of prefetch

31 7 2 1 0

Base Address

I/O space “1”1Ch Base Address 3 00 0000 0 1 :256Byte

I/O Address 1

Reserved

Base Address

31 11 9 6 4 3 2 1 0

Base Add 0 0000 0000 0 0 0 0

Base Address 1 000 1 0 0 0

Base Address 2 00 0000 1 0 0 0

Base Address Register Format

Command Register Format

0

*

I/O space enable

Bus master enable

Parity Error response

SERR_N enable

Memory space enable

Special cycle

Write cycle control

VGA Palette snoop

High-speed BtoB enable

Memory writeInvalidate enable

Reserved

Data is all cleared to zero immediately after reset. “0” indicates that data is fixed to 0.“*” can be changed.

**000*0*00

1234567891015

2

4

6

8

1

3

5

7

9

Status Register Format

66MHz capable

High-speed BtoB enable

Reserved

DEVSEL_N timing(low speed)

Target Abort reception

System Error notification

Data is all cleared to zero immediately after reset. “0” indicates that data is fixed to 0.“*” can be changed.

00 10*01*****

5

76

8

11

4

12

1413

15

UDF supported

Data Parity Error detection

New function

Target Abort notification

Master Abort reception

Parity Error Detection

03456789101112131415

3. Address map and register setting

Base Address Register 1 (Memory space “1”)This register group performs the setting required for DMA transfer.

Memory Address Name Description Setting register : PCI_AD[31:0]

0 ADDRESS0 DMA destination address setting 0 R/W [31:0] 4 ADDRESS1 DMA destination address setting 1 R/W [31:0] 8 MEM_FLAG DMA memory space identification flag Read 0

0

C INT_ACK Frame transfer interrupt reception flag Write reserved

reserved reserved reserved

0048

1-7

C

Category

DMA

0 ADDRESS0 DMA destination address setting0 R/W [31:0]

4 ADDRESS1 DMA destination address setting1 R/W [31:0]

8 MEM_FLAG DMA memory space identification flag Read 1 00

C INT_ACK Frame transfer interrupt reception flag Write 0

0 ADDRESS2 DMA transfer destination address setting2 R/W [31:0]

4 ADDRESS3 DMA transfer destination address setting3 R/W [31:0]

8 reserved 1

C reserved

0 reserved

4 reserved

8 reserved

2

|

7 C

DMA

reserved

Base Address Register 2 (Memory space “2”)This register group stores LUT data. Address 0 corresponds to luminance value 0 of a video input signal. The input signalof luminance value 0 is converted in luminance into the 8-bit data stored in address 0 and then output.

04

8

C

048C

048C

048C

LUT LUT Look up TableParameter setting

User, R/W

0

1-2

3

0

1-E ø

ø

ø

F

ø

0

1-E

F

[31:24][31:24]

[23:16][23:16]

[15:8][15:8]

[7:0][7:0]

[31:24][31:24]

[23:16][23:16]

[15:8][15:8]

[7:0][7:0]

Address 2Address 1

Address 0 <LSB>

Address 1023 <MSB>

Address 1022

Address 1021

Memory Address Name Description Setting register : PCI_AD[31:0]Category

3. Address map and register setting

Base Address Register 1 (Memory space “1”)This register group performs the setting required for DMA transfer.

I/O

address Category name Description Setting

0 CLMP Video black level adjustment Factory, R/W

4 CDS Sensitivity gap adjustment Factory, R/W

8 GAIN Gain adjustment User, R/W 0

C

AFE

0 FSEL Filter ON/OFF User, R/W

1 4-

C reserve

0 A11 Constant 1st line 1st row User, R/W

4 A12 Constant 1st line 2nd row User, R/W

8 A13 Constant 1st line 3rd row User, R/W 2

C reserved

0 A21 Constant 2nd line 1st row User, R/W

4 A22 Constant 2nd line 2nd row User, R/W

8 A23 Constant 2nd line 3rd row User, R/W 3

C reserved

0 A31 Constant 3rd line 1st row User, R/W

4 A32 Constant 3rd line 2nd row User, R/W

8 A33 Constant 3rd line 3rd row User, R/W 4

C

FILTER

reserved

5-

7 φ reserved

0 MODE Mode selection User, R/W

4 TPOL Trigger polarity switching User, R/W

8 SOFTT Software trigger ON User, W 　　　　8

C TRGINH Trigger prohibited User, R/W

0 BINNING Binning function ON/OFF User, R/W

4 PSSEL PS function ON/OFF User, R/W 9

8-

C reserve

0 PSVTL Parameter for V-PS User, R/W

4 PSVEA Parameter for V-PS User, R/W A

8-

C reserve

0 PSHTL Parameter for H-PS User, R/W

4 PSHEA Parameter for H-PS User, R/W B

8-

C reserve

0 SHUTTER Shutter speed setting User, R/W

4 DEL_TRIG Trigger delay setting User, R/W

8 DEL_STROB Strobe delay setting User, R/W C

C reserve

0 OVLP Overlap setting Factory, R/W

D 4-

C

TG/SG

reserve

0 GRAY Test pattern setting User, R/W

E 4-

C

Test reserve

0 VERSION FPGA version information User, R

F 4-

C

System reserve

Base Address Register 3 (I/O space “0”)This register group sets TG/SG and AFE.

register : PCI_AD[31:0]

7 6 5 4 3 2 1 0

5 4 3 2 1 0

4 3 2 1 0

1 0

d

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

10 9 8 7 6 5 4 3 2 1 0

0

0

　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　　 0

0

1 0

1 0

d

3 2 1 0

3 2 1 0

d

2 1 0

2 1 0

d

3 2 1 0

11 10 9 8 7 6 5 4 3 2 1 0

6 5 4 3 2 1 0

d

0

d

1 0

d

[31:0]

d

4.Details of register BAR1 1) ADDRESS0 Sets the DMA register of a PCI core. The DMA transfer destination address is specified in 32 bits. During configuration, a four-frame continuous space (of 1,228,800bytes) is ensured in the main memory of CPU. The start address of the first 1-frame data (of 307,200 bytes prescribed as frame 0) is written in the space. 2) Address1 Sets the DMA register of a PCI core. The DMA transfer destination address is specified in 32 bits. During configuration, a four-frame continuous space (of 1,228,800bytes) is ensured in the main memory of CPU. The start address of the next 1-frame data (of 307,200bytes prescribed as frame 1) is written in the space. 3) MEM_FLAG This flag identifies which frame DMA data is transferred in frame 0 to 3. A MEM_FLAG vale is updated when INT_ACK is received. PCI_AD[1:0] = 2’b00:Frame 0 (Area in which ADDRESS0 is prescribed as a start address) PCI_AD[1:0] = 2’b01:Frame 1 (Area in which ADDRESS1 is prescribed as a start address) PCI_AD[1:0] = 2’b10:Frame 2 (Area in which ADDRESS2 is prescribed as a start address) PCI_AD[1:0] = 2’b11:Frame 3 (Area in which ADDRESS3 is prescribed as a start address) 4) INIT_ACK This flag identifies whether OS (device driver) recognized INTB#. PCI_AD[0] = 0: INTB# not recognized PCI_AD[0] = 1: INTB# recognized After a device driver recognizes INTB#, it reads a MEM_FLAG value and writes 1 rapidly into an INT_ACK register. (“0” is automatically set three clocks after 1 is written.)

5) ADRESS2 Sets the DMA register of a PCI core. The DMA transfer destination address is specified in 32 bits. During configuration, a four-frame continuous space (of 1,228,800bytes) is ensured in the main memory of CPU. The start address of the next 1-frame data (of 307,200bytes prescribed as frame 2) is written in the space. 6) ADDRESS3 Sets the DMA register of a PCI core. The DMA transfer destination address is specified in 32 bits. During configuration, a four-frame continuous space (of 1,228,800bytes) is ensured in the main memory of CPU. The start address of the last 1-frame data (of 307,200bytes prescribed as frame 3) is written in the space. BAR2 1) LUT Operates the following of image.

Binarization (variable threshold) Negative-positive inversion γ correction

I/O space: PCI_AD[31:0] x 256 PCI_AD address = 1024bytes (1024 address) Default value: LSB・PCI_AD[7:0]=0000 0000 - MSB・PCI_AD[31:24]=11111111 10bit image data input to LUT corresponds address of memory space and 8bit data in the address is the luminance value of the image output. Supports updating of LUT in units of 1 bytes. BAR3 1) CLMP Adjusts the video black level (clamp level). The video black level can be changed by 256 steps. Default value is PCI_AD[7:0] = 1111 1010 (250 by decimal number) When factory default, R/W is possible only for ADMIN and the setting is called when Power ON for users.

2) CDS Sets the sensitivity gap between CCD.

Default value is PCI_AD[5:0] = 10 0110 (38 by decimal number ) R/W is possible only when factory default and the setting is called when Power ON for users. 3) GAIN Sets the video gain. In the range of 0 to 18 dB, the video gain can be changed by 19 steps. Note:

Default value is PCI_AD[4:0] = 0 0000 4) MODE Switches each mode. PCI_AD[0] = 0:Monitoring mode (Continuous video output: Default) PCI_AD[0] = 1:Trigger mode (A one-piece video signal is output to one external input trigger pulse.) 5) TPOL Switches the trigger polarity of an external input signal. PCI_AD[0] = 0:Positive polarity (Default) PCI_AD[0] = 1:Negative polarity 6) SOFTT This register generates trigger by application PCI_AD[0] = 1: PCI_AD[0] = 0 is automatically set approximately 60us after trigger is generated.

7) BINNING Turns on and off a binning function. Vertical direction binning: Turned on for PCI_AD[0] = 1 and off（default OFF）for PCI_AD[0]= 0 When the vertical direction binning is ON, the number of vertical direction line is halved for the standard. (480 lines → 240 lines, but the partial scan is OFF) Because of this, vertical cycle is shortened and frame rate is doubled. Horizontal direction binning: Turned on for PCI_AD[1] = 1 and off（default OFF）for PCI_AD[1] = 0 When the horizontal direction binning is ON, the number of horizontal direction pixels is halved for the standard. (640 pixels → 320 pixels, but the partial scan is OFF) Frame rate is not changed. Both of horizontal and vertical binning are turned on for “PCI_AD[1:0] =11” 8) PSSEL Turns on and off a partial scan function. Partial scan in vertical direction: Turned on for PCI_AD[0] = 1 and off for PCI_AD[0] = 0. The read area in the vertical direction with respect to the whole field angle (640 x 480) is changed by the setting of PSVTL and PSVEA. Partial scan in horizontal direction: Turned on for PCI_AD[1] = 1 and off for PCI_AD[1] = 0. The read area in the horizontal direction with respect to the whole field angle (640 x 480) is changed by the setting of PSHTL and PSHEA. The partial scan in the horizontal and vertical directions is turned on for PCI_AD[1:0] = 11. “The number of pixels in the horizontal direction by the number of lines in the vertical direction” represented by PSVTL, PSVEA, PSHTL, and PSHEA corresponds to the number of effective pixels (data size) when PSSEL is set. 9) PSVTL Divides the number of vertical lines (640 lines) in the standard state by 16 and changes the vertical video read start position by the setting of a register.

10) PSVEA Sets what lines (blocks) to be read (“the numbers of effective lines”) using a register, among the blocks obtained when the number of lines (640 lines) in the standard state was divided by 16. PSVEA is interlocked with PSVTL. Video starts from with the defined vertical video read start position. (A register value that cannot be set in PSVEA is generated using a PSVTL value. PSVEA cannot be set to a PSVTL + PSVEA value that is higher than [1111].)

11) PSHTL Divides the number of horizontal pixels (640 pixels) in the standard state by 10 and changes the horizontal video read start position by the setting of a register.

12) PSHEA Sets what pixels (blocks) to be read (“the numbers of effective horizontal pixels”) using a register, among the blocks obtained when the number of horizontal pixels (640 pixels) in the standard state was divided by 10. However, the minimum number of blocks that can be selected is 3. PSHEA is interlocked with PSHTL. Video starts from with the defined horizontal video read start position. (A register value that cannot be set in PSHEA is generated using a PSHTL value. PSHEA cannot be set to a PSHTL + PSHEA value that is higher than [111].)

13) SHUTTER Can set the shutter speed irrespective of the mode.

14) DEL_TRIG Delays the trigger input from the outside in units of 1 [msec] by approximately 4 [sec] (maximum).

15) OVLP This register is used for factory setting. Default value is PCI_AD[0] = 0 16) VERSION This register stores the version information of FPGA. It is used for read operation only.

17) GRAY Sets switching of test pattern (Gray Scale) output for evaluation. PCI_AD[1:0] = 2’b00： CCD OUT PCI_AD[1:0] = 2’b01： Gray Scale 1PCI_AD[1:0] = 2’b10：Gray Scale 2PCI_AD[1:0] = 2’b11：Gray Scale 3 18) FSEL Turns on and off of the filter function Turned off for PCI_AD[1:0] = 00 (Filter unused) Turned on for PCI_AD[1:0] = 01 (Filter used in order of LUT→Filter) Turned on for PCI_AD[1:0] = 10 (Filter used in order of Filter→LUT) Turned on for PCI_AD[1:0] = 11 (Filter used in order of Filter→LUT)

19) FILTER A11～A33 Sets the constant of 3x3 Hardware Filter. Sets signed 11 bit and low 5 bit shall be decimal number. The following is the representative value.

In addition, A11-A33 are each coefficient of 3x3 matrix as follows.

20) TRGINH Sets Trigger input prohibition. Trigger is enabled for PCI_AD[0] = 0 Trigger is not enabled for PCI_AD[0] = 1 Relation between TRGINH and interrupt signal INTB# is as follows. Relation between TRG and INTB# when TRGINH is low fixation

In case of ① and ④, TRG is enabled and also interrupt is generated since TRGINH is low when TRG rising edge. In case of ② and ③, TRG is not enabled and interrupt is not generated since TRGINH is High when TRG rising edge. 21) DEL_STROB Sets 128 patterns of phase differences between Exposure output pulse generated internally and actual exposure time in units of 1[usec] from -67[us] to +60[us].

.

5. Interrupt signal

A frame transfer completion interrupt signal (INTB#) is generated when one-frame data transfer iscompleted. One-frame write operation is judged to have been completed when this interrupt signal isgenerated.

1. A trigger signal that directs the start of exposure is input to the camera block.2. A video output is started.3. DMA transfer is started when the data is accumulated in FIFO. (REQ# is generated.)4. An interrupt signal (INITB#) is generated when one-frame transfer is completed with the DMA

transfer repeated.nAfter ADDRESS0 ,ADDRESS1, ADDRESS2 or ADDRESS3 is set to 0x00000000, DMA transfer is stopped andan interrupt signal is not generated. The first interrupt signal after change in setting is not generated when the settingof MODE, BINNING, PSSEL, PSVTL, PSVEA, PSHTL, and PSHEA is changed during DMA transfer.

Trigger

VIDEO

DMA transfer

Video output start

DMA transfer start DMA transfer completion (One-frame transfer completion)

Time for which the data is accumulated

INTB

PCI Configuration cycle

Specifying DMA transfer destination address to 4 registers of ADDRESS0, ADDRESS1, ADDRESS2 and ADDRESS3 of BAR1

Setting of DMA transfer destination address

DMA is enabled when 4 addresses are set to other than 0x0

CCD output start and data accumulation wait

Data accumulation

DMA start

REQ# generation

GNT# reception

DMA completion

One frame transfer completion

INTB# generation

MEM_FLAG updating

MEM_FLAG recognition

INT_ACK write

When one frame transfer is completed

Determination of ADDRESS

When any of ADDRESS0-3 is 0x0

DMA is disabled and DMA transfer is aborted

DMA transfer right after turning on the power is transferred to ADDRESS0. It is repeated in order of 1, 2, 3, 0

Boot

VD or trigger

6. Data flow

When one frame transfer is not completed

Frame buffer area to be obtained is 1,228,800 bytes. 1frame: 307,200bytes (640 x 480)

When all of ADDRESS0-3 are other than 0x0

Four frame buffers ensured (in main memory)

Power on

: Other

: Device driver operation

: Camera FPGA operation

How to start DMA transfer 1. Set ADDRESS0 register of BAR1 to other than 0x00000000. 2. Set ADDRESS1 register of BAR1 to other than 0x00000000. 3. Set ADDRESS2 register of BAR1 to other than 0x00000000. 4. Set ADDRESS3 register of BAR1 to other than 0x00000000. 5. Input trigger when trigger mode. Nothing has to be done when monitoring mode.

DMA transfer starts automatically after that. Transfer destination address is as follows. 1st frame is in ADDRESS0, 2nd frame is in ADDRESS1. ....

In case of receiving interrupt signal from camera (Camera generates interrupt signal when one frame transfer is completed.) 1. Receive INTB# 2. Refer to MEM_FLAG register of BAR1. The number indicated in MEM_FLAG

register is the frame that image corresponds to INTB# is stored. 3. Write “1” into INT_ACK register of BAR1 after referring to MEM_FLAG. How to stop DMA transfer 1. Set ADDRESS3 register of BAR1 to 0x00000000. 2. Set ADDRESS2 register of BAR1 to 0x00000000. 3. Set ADDRESS1 register of BAR1 to 0x00000000. 4. Set ADDRESS0 register of BAR1 to 0x00000000. 5. DMA transfer is stopped from the next frame.

INTB# is not generated when setting any of ADDRESS0-3 to 0ｘ00000000.

How to resume DMA transfer 1. Set ADDRESS0 register of BAR1 to other than 0x00000000. 2. Set ADDRESS1 register of BAR1 to other than 0x00000000. 3. Set ADDRESS2 register of BAR1 to other than 0x00000000. 4. Set ADDRESS3 register of BAR1 to other than 0x00000000. 5. Input trigger when trigger mode. Nothing has to be done when monitoring mode.

DMA transfer starts automatically after that. Transfering destination starts from the address which was stopped.

7. List of DMA transfer size

1) HV binning OFF

PSHEA 000 001 010 011 100 101 110 111

Number of effective

pixels in 1 line 192 256 320 384 448 512 576 640

PSVEA Number of

effective lines

0000 30 5760 7680 9600 11520 13440 15360 17280 19200 0001 60 11520 15360 19200 23040 26880 30720 34560 38400 0010 90 17280 23040 28800 34560 40320 46080 51840 57600 0011 120 23040 30720 38400 46080 53760 61440 69120 76800 0100 150 28800 38400 48000 57600 67200 76800 86400 96000 0101 180 34560 46080 57600 69120 80640 92160 103680 115200 0110 210 40320 53760 67200 80640 94080 107520 120960 134400 0111 240 46080 61440 76800 92160 107520 122880 138240 153600 1000 270 51840 69120 86400 103680 120960 138240 155520 172800 1001 300 57600 76800 96000 115200 134400 153600 172800 192000 1010 330 63360 84480 105600 126720 147840 168960 190080 211200 1011 360 69120 92160 115200 138240 161280 184320 207360 230400 1100 390 74880 99840 124800 149760 174720 199680 224640 249600 1101 420 80640 107520 134400 161280 188160 215040 241920 268800 1110 450 86400 115200 144000 172800 201600 230400 259200 288000 1111 480 92160 122880 153600 184320 215040 245760 276480 307200

（Unit:

byte)

2) H binning ON

PSHEA 000 001 010 011 100 101 110 111

Number of effective

pixels in 1 line 96 128 160 192 224 256 288 320

PSVEA Number of

effective lines

0000 30 2880 3840 4800 5760 6720 7680 8640 9600 0001 60 5760 7680 9600 11520 13440 15360 17280 19200 0010 90 8640 11520 14400 17280 20160 23040 25920 28800 0011 120 11520 15360 19200 23040 26880 30720 34560 38400 0100 150 14400 19200 24000 28800 33600 38400 43200 48000 0101 180 17280 23040 28800 34560 40320 46080 51840 57600 0110 210 20160 26880 33600 40320 47040 53760 60480 67200 0111 240 23040 30720 38400 46080 53760 61440 69120 76800 1000 270 25920 34560 43200 51840 60480 69120 77760 86400 1001 300 28800 38400 48000 57600 67200 76800 86400 96000 1010 330 31680 42240 52800 63360 73920 84480 95040 105600 1011 360 34560 46080 57600 69120 80640 92160 103680 115200 1100 390 37440 49920 62400 74880 87360 99840 112320 124800 1101 420 40320 53760 67200 80640 94080 107520 120960 134400 1110 450 43200 57600 72000 86400 100800 115200 129600 144000 1111 480 46080 61440 76800 92160 107520 122880 138240 153600

（Unit:

byte)

3) V binning ON

PSHEA 000 001 010 011 100 101 110 111

Number of effective

pixels in 1 line 192 256 320 384 448 512 576 640

PSVEA Number of

effective lines

0000 15 2880 3840 4800 5760 6720 7680 8640 9600 0001 30 5760 7680 9600 11520 13440 15360 17280 19200 0010 45 8640 11520 14400 17280 20160 23040 25920 28800 0011 60 11520 15360 19200 23040 26880 30720 34560 38400 0100 75 14400 19200 24000 28800 33600 38400 43200 48000 0101 90 17280 23040 28800 34560 40320 46080 51840 57600 0110 105 20160 26880 33600 40320 47040 53760 60480 67200 0111 120 23040 30720 38400 46080 53760 61440 69120 76800 1000 135 25920 34560 43200 51840 60480 69120 77760 86400 1001 150 28800 38400 48000 57600 67200 76800 86400 96000 1010 165 31680 42240 52800 63360 73920 84480 95040 105600 1011 180 34560 46080 57600 69120 80640 92160 103680 115200 1100 195 37440 49920 62400 74880 87360 99840 112320 124800 1101 210 40320 53760 67200 80640 94080 107520 120960 134400 1110 225 43200 57600 72000 86400 100800 115200 129600 144000 1111 240 46080 61440 76800 92160 107520 122880 138240 153600

（Unit:

byte)

4）HV binning ON

PSHEA 000 001 010 011 100 101 110 111

Number of effective

pixels in 1 line96 128 160 192 224 256 288 320

PSVEA Number of

effective lines

0000 15 1440 1920 2400 2880 3360 3840 4320 4800 0001 30 2880 3840 4800 5760 6720 7680 8640 9600 0010 45 4320 5760 7200 8640 10080 11520 12960 14400 0011 60 5760 7680 9600 11520 13440 15360 17280 19200 0100 75 7200 9600 12000 14400 16800 19200 21600 24000 0101 90 8640 11520 14400 17280 20160 23040 25920 28800 0110 105 10080 13440 16800 20160 23520 26880 30240 33600 0111 120 11520 15360 19200 23040 26880 30720 34560 38400 1000 135 12960 17280 21600 25920 30240 34560 38880 43200 1001 150 14400 19200 24000 28800 33600 38400 43200 48000 1010 165 15840 21120 26400 31680 36960 42240 47520 52800 1011 180 17280 23040 28800 34560 40320 46080 51840 57600 1100 195 18720 24960 31200 37440 43680 49920 56160 62400 1101 210 20160 26880 33600 40320 47040 53760 60480 67200 1110 225 21600 28800 36000 43200 50400 57600 64800 72000 1111 240 23040 30720 38400 46080 53760 61440 69120 76800

（Unit:

byte)

8. MEM_FLAG　timing chart

The following is the MEM_FLAG timing chart.

Write frame 1 Write frame 2 Write frame 3 書き込みフレーム 3

1 2 0

VBLK

DMA transfer

destination frame

INTB#

MEM_FLAG

MEM_FLAG stores a value indicating

the preceding DMA transfer

destination frame while INTB# is

active (high). In the case described above, 1 (frame 1) is stored.

nnnnnFor the updating of MEM_FLAG, +1 is guaranteed to an INTB# interrupt signal. However,MEM_FLAG may be skipped when the response of INT_ACK to an INTB# interrupt signal is moredelayed than the generation timing of a next image’s INTB# interrupt signal.For the updating ofMEM_FLAG, +1 is guaranteed to an INTB# interrupt signal. However, MEM_FLAG may be skippedwhen the response of INT_ACK to an INTB# interrupt signal is more delayed than the generation timingof a next image’s INTB# interrupt signal.

5-1. Specifications of Processor Block

A main devices are shown in the table below.

Main device list

No. Board name Item Specifications Remarks

1 CPU board CPU Geode GX533Operating clock: 400 MHzI/O power: 3.3 VCore voltage: 1.5 V

. VIDEO RGB Video OUT PortDevice: Geode GX533 built-inConnector: D-Sub half 15-pin

SDRAM Capacity: 256M bytesSpecifications: DDR SDRAMNumber of SDRAMs used: 4

2 CF board CLK Driver MK1491-09Input clock: 14.31818 MHz

Flash ROM Capacity: 1M byte

Companion Device CS5535-UDCI/O power: 3.3 VCore voltage: 1.5 V

. IDE Compact flash type I interfaceDevice: CS5535-UDC built-inConnector: CF1 slotMode: True IDE

. USB USB Ver1.1Device: CS5535-UDC built-inPort: 1 port

. RTC Real Time ClockDevice: CS5535-UDC built-in

. RS-232C Number of ports: 1 CHDevice: CS5535-UDC built-inInterface transceiver: MAX3232

. GP I/O . Insulation input/output: IN x 1, OUT x 1. Photocoupler: TLP281. TTL input/output: IN x 1, OUT x 2. LED: 1-bit externally. DIP SW: 1-bit externally

3 MB board LAN RTL8100CL PCI deviceTransfer rate: 10/100 MbpsCrystal oscillator: 25 MHz

LAN + USB connector LAN: RJ45 Transformer built-inLED: LAN operation display

(Link, Rx, and Tx)USB: Type A

5-1-1. Functions

1. CPUA Geode GX533 processor is used as CPU. The internaloperating frequency is 400 MHz. CPU incorporates aDDR SDRAM memory interface (PC266) and graphiccontroller. A CS5535 companion device is provided asperipheral LSI of a Geode GX533 processor. It isconnected using PCI.Refer to the AMD Geode GX533 processor data book formore details of a register.

2. CS5535 companion deviceThe functions that the CS5535 companion device uses areas follows:. PCI interface. CF (IDE) interface. USB 1.1 OHCI interface. RTC (Real-Time-Clock). Serial port interface. FWH interface. GP I/O interfaces

(DIP switch, LED, and digital I/O)Refer to the AMD Geode CS5535 companion device databook for more details of a register.

3. RTCThe backup power to RTC is supplied from DC/DC. Thepower supply is stopped when DC/DC or a CF board isremoved and inserted. Therefore, RTC is reset.nBackup power supply is used for short-time powershutdown. Respecify RTC when it was reset.

4. BIOSXpress ROM (Insyde Software) is mounted. The BIOSsetting screen can be started by pressing the F1 key duringactivation.

5. LEDSTATUS and POWER LEDs are mounted on the rear panel.STATUS LED: This STATUS LED is connected to

GPIO27.The STATUS LED lights in red whenBIOS is started. It goes off when BIOS isterminated.Since GPIO27 is opened to the user, the STATUS LED can be used freely.

GeodeCS-5535

POWER LED: This POWER LED is connected to powersupply.The POWER LED lights in green afterthe power is turned on.

6. DIP SWA 2-bit DIP switch is mounted on the rear panel. It is connected to GPIO11 and GPIO12.nBit 1 (GPIO11) of EXDIP cannot be used by the userbecause it is used for factory setting.

Rear PanelEXDIP Switch

bit bit1 bit0

Switch 2 1

GPIO GPIO11 GPIO12

Logic ON = “0”/OFF = “1”

7. MemoryDDR SDRAM based on the PC266 standard is mounted onthe CPU board. DDR SDRAM is set using BIOS. The businterface width is 64 bits, and the mounting capacity is 256M bytes.

8. VGA outputA VGA output signal uses the CPU built-in graphic controlled mounted on the CPU board and output tothe outside via the high-density D-Sub 15-pin connector (female) mounted on the CN board. DDC of thedisplay is not supported. For display size, 1600 x 1200 x 16 bits (maximum) can be displayed.nThe resolution varies depending on the OS or video driver used. The resolution during factory setting isSXGA 1280 x 1024 x 16 bits.

9. LANLAN is compatible with 10Base-T/100Base-TX. PCI-connected RTL8100CL is mounted as a LANcontroller, and EEPROM is mounted on the MB board for MAC address storage. A LAN connector iscomposite connector in which a transformer, RJ45 + LED, and USB connector were incorporated. LEDenables LINK (LED1) and ACT (LED0) to be displayed.LAN is set to LEDS1-0:01 of a LAN controller.In PCI bus configuration, IDESL = AD24 is assigned.

10. RS-232CCS5535 built-in UART mounted on the CF board is used as a general-purpose serial interface. Ahardware handshake function is not provided. MAX3232 compatible with 3.3 V power is mounted on theMB board as an RS-232C interface and connected to the outside via the 6-pin round-type connectormounted on the CN board.CS5535 built-in UART uses GPIO8 and GPIO9.

11. USBOne port compatible with USB specification V1.1 is mounted. For a controller, the CS5535 built-incontroller mounted on the CF board is used. A connector type is type A. It is connected to the USBconnector of composite connector mounted on the MB board.The connector is also compatible with OHCI specification V1.0.It is recommended to connect USB equipment as a single model using a mouse or keyboard. We recom-mend the use of a self-power type hub when using a USB hub. (A bus power type hub is not treated.)

12. CFIn CF, one slot of a type I card is mounted. The power supply of a CF card is used for only 3.3 V. It isnot used for a hot swap.

13. PCIThe PCI bus of Geode GX533 conforms to the specifications of 3.3 V, 32 bits, and 33 MHz.The device (board) connected to the PCI bus is LAN controller RTL8100 and a TG board.

(1) PCI arbitrationPCU bus arbitration is shown in the table below.

PCI Arbitration

Bus Master Device Remarks

Internal Geode GX533 Processor

Master0 TG board

Master1 LAN RTL8100

Master2 CS5535 Companion

(2) PCI interrupt routingPCI interrupt routing is shown in the table below.

PCI IRQ Mapping

PCI Device Vendor ID Device ID Device Number IDESL Line Function Number Device or Function Interrupt Line

GX533 100Bh 0028h 01h AD11 0 Host PCI Bridge _

0030h 01h 1 Graphic Controller _

TG board _ _ _ AD22 _ _ INT#B

RTL8100 10ECh 8139h 0Eh AD24 _ Ethernet Controller INT#A

CS5535 100Bh 002Bh 0Fh AD25 0 ISA Bridge _

002Ch 1 (Flash Controller) _

002Dh 2 IDE Controller _

002Eh 3 Audio Controller _

002Fh 4 USB Controller 1 _

002Fh 5 USB Controller 2 _

(3) TG boardThe TG board is connected as a PCI device by a camera board.PCI bus configuration assigns IDESL = AD22.* For more details, refer to the camera block item of the relevant specification.

5-1-2. Configuration

CS5535 GPIO Configuration

The GPIO setting of CS5535 is shown in the table below.

CS5535 GPIO Configuration

Ball# Signal I/O Configuration

GPIO0 nINTA I PCI INTA

GPIO2 IDE_IRQ14 I IDE Channel IRQ14

GPIO3 ISO_IN I Digital input port

GPIO4 TTL_IN I Digital input port

GPIO5 ISO_OUT O Digital output port

GPIO7 nINTB I PCI INTB

GPIO8 UART_TX O UART Transmit

GPIO9 UART_RX I UART Receive

GPIO11 EXSW_IN2 I Input port Dipswitch input bit1:ON =“0”

GPIO12 EXSW_IN1 I Input port Dipswitch input bit0:ON =“0”

GPIO14 NC _ none

GPIO15 NC _ none

GPIO16 LAD0 _ FWH Address and Data 0

GPIO17 LAD1 _ FWH Address and Data 1

GPIO18 LAD2 _ FWH Address and Data 2

GPIO19 LAD3 _ FWH Address and Data 3

GPIO20 NC _ none

GPIO21 NC _ none

GPIO22 nFRAME _ FWH FRAME

GPIO27 EXLED1 O LED Display bit2:ON =“0”

_

GPIO6 TTL_OUT O Digital output port

GPIO1 TTL_OUT2 O Digital output port

GPIO24 NC _ none

GPIO25 NC _ none

GPIO26 NC _ none

GPIO28 NC _ none _

_

GPIO10 NC _ none

GPIO13 NC _ none

Contents of RTL8100CL EEPROMThe contents of RTL8100CL serial ROM (EEPROM) are as shown below.

Contents of EEPROM

0 1 2 3 4 5 6 7 8 9 A B C D E F

MNGNT MXLAT MSRBMCR CONFIG329 81 EC 10 39 81 EC 10 39 81 20 20 12 E5 xx xx

CONFIG0 CONFIG1 CONFIG4 PHY2_PARM_U CONFIG5xx xx xx xx 10 4D C2 F7 01 88 B9 03 F4 60 1A 07

PHY2_PARM_T

A3 DF 36 98 A3 DF 36 98 B9 03 F4 60 1A 1A 1A 1A

PXE_Para00 00 xx xx 00 00 00 00 00 00 00 00 00 00 00 20

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Ethernet ID

Ethernet ID PMC PHY1_PARM_U

VID DID SVID SMIDID

TW_PARM_U TW_PARM_T PHY1_PARM_T

CISPointer CheckSum

VPD_Data

VPD_Data

VPD_Data

VPD_Data

CIS_Data

0

1

2

3

4

5

6

7

8

5-1-3. System Resources

Memory mapThe memory map is as shown below.

Memory Map

00000000h

000A0000h

000C0000h

000C8000h

000E0000h

1010 0000h100F FFFFh

00100000h

System Memory640KByte

Legacy Video Memory128KByte

Video BIOS32KByte

Ext. BIOS96KByte

System BIOS128KByte

System Memory

+ Video Memory

248MByte + 8Mbyte

Interrupt mapThe interrupt map is shown in the table below.

Interrupt Map

Interrupt Level Resource RemarksController1 Controller2

IRQ0 _ System Timer

IRQ1 _ USB Keyboard

IRQ2 _ Controller2 cascade

IRQ3 _ COM2

IRQ4 _ COM1

IRQ5 _ Audio

IRQ6 _ GPIO

IRQ7 _ open

_ IRQ8 Real Time Clock

_ IRQ9 USB Controller

_ IRQ10 Power Management/KEL Emu

_ IRQ11 open

_ IRQ12 USB Mouse

_ IRQ13 Math coprocessor

_ IRQ14 Primary IDE

_ IRQ15 open

* Any of IRQ0 through IRQ15 is assigned to PCI bus INTA through PCI bus INTD.* Any interrupt can be assigned to each PCI bus INT by the setting of BIOS. Default PCI bus INT is assigned as described below by

BIOS setting.. PCI bus INTA = IRQ11. PCI bus INTB = IRQ11. PCI bus INTC = IRQ11. PCI bus INTD = IRQ10

DMA mapThe DMA map is shown in the table below.

DMA Map

DMA CHANNEL No. Resource RemarksController1 Controller2

DMA0 _ open

DMA1 _ open Parallel port

DMA2 _ Floppy Drive

DMA3 _ open Parallel port

_ DMA4 Controller1 cascade

_ DMA5 open

_ DMA6 open

_ DMA7 open

IO mapThe IO map is as shown below.Refer to the AMD Geode CS5535 companion device data book for more details of a register.

IO Map

I/O Address Device Remarks

0000h to 000Fh DMA Controller 1

0020h to 0021h Interrupt Controller 1

0040h to 0043h System Timer Controller

0060h Keyboard Controller

0061h Port B Control

0064h Keyboard Controller

0070h to 0071h RTC RAM

0072h to 0073h High RTC RAM

0080h POST Code

0081h to 008Fh DMA Low Page

0092h Port A Control

00A0h to 00A1h Interrupt Controller 2

00C0h to 00DEh DMA Controller 2

0170h to 0177h Secondary IDE Controller

01F0h to 01F7h Primary IDE Controller

02F8h to 02FFh UART COM2

03B4h to 03BAh Video(VGA) Controller

03C0h to 03DFh

03F8h to 03FFh UART COM1

0481h to 048Fh DMA High Page

04D0h to 04D1h PCI Level/Edge Interrupt Controller

GPIO bit mapThe correspondence table of the LEDs, DIP switches, and I/O ports assigned to GPIO are as shownbelow.*: Refer to the AMD Geode CS5535 companion device data book for more details of GPIO.

(1) LEDsThese LEDs are assigned to GPIO.The GPIO correspondence table of LEDs is shown in the table below.

LEDs

I/O Address LED

6100h Circuit number - EXLED1

- Status LED

+80h GPIOH _ GPIO27

+00h GPIOL _ _

Logic “0” = Lights/“1” = Goes off

Initial value: ALL = “1” (Lights)

(2) DIP switchesThese DIP switches are assigned to GPIO.The GPIO correspondence table of DIP switches is shown in the table below.

DIP Switches

I/O Address EXDIP Switch

6100h bit bit1 bit0

Switch 2 1

+30h GPIOL GPIO11 GPIO12

+B0h GPIOH _ _ _ _

Logic ON = “0”/OFF = “1”

(3) IN portsThese input ports are assigned to GPIO.The GPIO correspondence table of IN ports is shown in thetable below.

IN Ports

I/O Address TTL Insulation

6100h Signal TTL_IN ISO_IN

+30h GPIOL GPIO4 GPIO3

+B0h GPIOH _ _

Logic ON = “0”/OFF = “1”

(4) OUT portsThese output ports are assigned to GPIO.The GPIO correspondence table of OUT ports is shown inthe table below.

OUT Ports

I/O Address TTL Insulation

6100h Signal TTL_OUT TTL_OUT2 ISO_OUT

+00h GPIOL GPIO6 GPIO1 GPIO5

+80h GPIOH - _ _

Logic - - Open-Drain _

ON = “0”/ OFF = “1”

Initial value: ALL = “1” (OFF)

POWERMONITOR

STATUS

MODEDC IN

SERIAL

RESET

2

1

3

5

6

7

4

6-1. Specifications of Interface Block

6-1-1. Features of Interface Block

. 10Base-T/100Base-TX (POE-incompatible)

. USB1.1-compatible

. RS-232C

. D-Sub 15-pin, VGA monitor output

. Digital I/OISO input/output: 1 channel eachTTL input/output: 1 channel input / 2 channel outputTrigger input: Storage start controlExposure output: External illumination control

6-1-2. External View of Rear Panel

The external view of a rear panel is as shown below.

External View of Rear Panel

1 D-Sub 15-pin connector2 12-pin round-type connector3 6-pin round-type connector4 USB/LAN-integrated connector5 Reset switch6 POWER/STATUS switch7 DIP switch

5 4 3 2 1

10 9 8 7 6

15 14 13 12 11

6-1-3. Connector Pin List

1. D-Sub 15-pin connectorThis connector is used for VGA monitor output. Aconnector pin list and pin assignment are shown in thetable below.

Pin Assignment of D-Sub 15-Pin Connector

Pin List of D-Sub 15-Pin Connector

Pin No. Signal name Pin No. Signal name

1 R_OUT 9 NC

2 G_OUT 10 GND

3 B_OUT 11 NC

4 NC 12 NC

5 GND 13 HD_OUT

6 GND 14 VD_OUT

7 GND 15 NC

8 GND _ _

2. 12-pin round-type connectorThis connector is used for power supply, digital I/O,trigger input, and exposure output.A connector pin list and pin assignment are shown in thetable below.

Pin Assignment of 12-Pin Round-Type Connector

Pin List of 12-Pin Round-Type Connector

Pin No. Signal name Pin No. Signal name

1 GND 7 TTL_OUT

2 VCC (12 V/24 V) 8 GND

3 GND 9 ISO_OUT_

4 ISO_OUT+ 10 EXPOSURE_OUT

5 GND 11 TRIG_IN

6 TTL_IN 12 GND

6 1

4 3

25

1 4

8 1

USB

LAN

ACT LINK

4.5-5.0 V

0.0-0.5 V

10 kZ

Input circuit2µs or more

4.0-4.5 V

0 V

Depends on shutter setting

LED Description

Name Form Description Remarks

LINK Green Lights during LAN Refer to theLED linking. illustration.

ACT Green Lights during LAN Refer to theLED transmission/reception. illustration.

6-1-4. Input/Output Specifications

1. TRIG_IN (12-pin connector)This connector is connected from the CN board to FPGAon the TG board. The input specifications are as shownbelow.

2. Exposure OUT (12-pin connector)This connector is connected from FPGA on the TG boardvia the CN board. A buffer is provided in the output stage.The output specifications are as shown below.

3. TTL_IN (12-pin connector)This connector is connected from the CN board to theGPIO4 pin of CS5535 on the CF board via a buffer. Theinput specifications are as shown below.

3. 6-pin round-type connectorThis connector is used for RS-232C communication anddigital I/O.A connector pin list and pin assignment are shown in thetable below.

Pin Assignment of 6-Pin Round-Type Connector

Pin List of 6-Pin Round-Type Connector

Pin No. Signal name Pin No. Signal name

1 TXD 4 ISO_IN+

2 RXD 5 ISO_IN_

3 GND 6 TTL_OUT2

4. USB/LAN-integrated connectorThis connector is used for USB and LAN. USB conformsto USB1.1, and LAN conforms to IEEE802.3.A USB connector pin list, LAN connector pin list, LEDdescription, and pin assignment are shown in the tablebelow.

Pin Assignment of USB/LAN Connector

USB Connector

Pin No. Direction Signal name

1 _ VBUS

2 I/O D_

3 I/O D+

4 _ GND

LAN Connector

Pin No. Signal name Pin No. Signal name

1 TD+ 5 NC

2 TD_ 6 RD_

3 RD+ 7 NC

4 NC 8 NC

4.5-5.0 V

0.0V-0.5 V

10 kz

5. ISO_IN (6-pin connector)This connector is connected from the CN board to the GPIO3 pin of CS5535 on the CF board via photo-coupler TLP281. The external power supply is used within +5 VDC to +25 VDC.

The switching characteristics of TLP281 and an input circuit are shown in the table below.

Switching Characteristics of TLP281

Item Symbol Measurement conditions Minimum Standard Maximum Unit

Rise tr VCC = 10 V, _ 2 _ µstime IC = 2 mA,

RL = 100 Z

Fall time tf _ 3 _ µs

Turn-on time ton _ 3 _ µs

Turn-off time toff _ 3 _ µs

For more details, refer to the TLP281 data sheet.

ISO_IN input circuit diagram

6. ISO_OUT (12-pin connector)This connector is connected from the GPIO5 pin of CS5535 on the CF board via photocoupler TLP281on the connector board. The external power supply is used within +5 VDC to +25 VDC.

ISO_OUT output circuit diagram

4.0-4.5 V

0 V

4. TTL_OUT (6-pin/12-pin connector)This connector is connected from the GPIO1 and 6 ofCS5535 on the CF board via the buffer on the CN board.The output specifications are as shown below.

TLP281VCC3.3 V

GPIO3(CF board)

ISO_IN+3.3 kZ

ISO_IN_

TLP281 3.3 kZVCC3.3 V

From GPIO5(CF board)

ISO_OUT+

ISO_OUT_