Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 152

Performance Analysis and Simulation ofDecimator for Multirate Applications

1Lajwanti Singh, 2Umesh Kumar1,2Assistant Professor

Dept of Electronics & Communication, Anand International College of Engineering, JaipurDepartmentt of CS & IT, Govt. Mahila Engineering College, Ajmer1lajwanti.singh@anandice.ac.in, 2ume2222@gmail.com

Abstarct--In this paper, a decimator design has beenpresented for multirate digital signal processing. Thedecimator design has been analysed and simulated forperformance comparison in terms of filter order andripple factor. Direct form-I with decimation factor 2have been used for performance and ripple analysis. Thedecimators have been designed & simulated usingMATLAB. It can be observed from the simulated resultsthat as we increase the filter order, ripple factor decreases,for the same filter structure. On the other hand,increasing filter order will increase its area andimplementation cost.

Keywords: Decimator, DSP, FIR, MATLAB

1. INTRODUCTION

The demands for digital products with programmabilityare growing day by day. Various industries like audio,video, and cellular industry rely heavily on digitaltechnology. There is a trend in the current design ofDSP wireless communication circuits such as digitalreceivers to implement the whole receiver as an alldigital, single - chip ASIC and to push the signalprocessor closer to the "front end" (of antenna or sensor).One of the main implications of this trend is the needfor flexibly programming or configuring hardware sothat it can accommodate multiple communicationstandards. A digital implementation keeps the ICmanufacturing cost low while still providing the sameperformance as an analog implementation. A great partof digital technology deals with digital signal processing.This aspect in engineering has gained increasing interest,especially with much of the world now turning towireless technology. Finite impulse response (FIR)digital filters are common DSP functions and are widelyused in FPGA implementations. If very high samplingrates are required, full-parallel hardwaremust be used where every clock edge feeds a new inputsample and produces a new output sample [1].

In case fully parallel implementation is not possible thenpartly serial approach can be adopted to enhance thesystem performance. Such filters can be implemented onFPGAs using combinations of the general purpose logicfabric, onboard RAM and embedded arithmetic hardware.Therefore, power consumption has resulted to be themost significant design requirement in portable systemsand this has lead to many low power design techniques

and the algorithms are used for speed and areaoptimization. The key advantage to the approach isCost: 1. Price for high speed components goes upexponentially with sample rate or clock rate. 2.Break the processing into parallel stages operating at alower rate. Different approaches of numberrepresentation are implemented on Decimation (reductionof sample rate) which is useful for:1. Increase effective resolution of A/D.2. Reduce data for processing.3. Create low computational count narrowbandfilters.4. Perform frequency translation.5. Divide a wide band into narrow independent channels6. Relax requirement on anti-aliasing filtering.

2. Multirate Digital Signal Processing

Multirate DSP hardware is an important sub-category ofthe DSP hardware. It deals with the sampling rateconversion of a digital signal, including interpolation anddecimation. There are basically two methods toaccomplish this. One method converts a digital signal toanalog through a digital to analog convertor, and then re-samples the analog signal using a different sampling ratewith an analog to digital convertor, a process thatrequires analog filters. The other method

operates totally in the digital domain, which has agreat advantage over the first method as only digitalfilters are needed [2]. One of the typical applications fordecimation filters in telecommunications is a digitalreceiver. A digital receiver is more complex than ananalog receiver, since the RF signal is transferred todigital domain and then back to analog domain afterbeing processed.Why is a complex structure preferred? One reason is thatdigital filters have certain advantages over analogfilters in terms of performance, implementation cost,and long term stability. Another is that the precision ofmany parameters cannot be easily controlled for theanalog manufacturing process, while it is possible toimplement digital filters with well controlled featuressuch as small pass band ripple, sharp transition bandcharacteristics and linear phase. The high frequencycomponents need to be eliminated, and the unnecessarilyhigh sampling rate needs to be brought down sincethe sampling rate only needs to be greater than twice thebandwidth of the signal .The decimation filter eliminatesfrequency components beyond baseband and reduces

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

153 NITTTR, Chandigarh EDIT-2015

Am

plit

ud

eM

ag

nitu

de

(dB

)

the sampling rate down to Fs/N. Then the signal withthe low sampling rate is ready to be processed by theDSP processor rate. One simple way of decimating adigital signal x(n) by a factor of M is to select every Mthsample of the input signal x(n). An down sampler with adown- sampling factor M, where M is a positiveinteger, develops an output sequence y[n] with asampling rate that is (1/M)th of that of the input sequencex[n].

Down-sampling operation is implemented by keepingevery Mth sample of x[n] and removing M-1 in-between samples to generate y[n]. The input and outputrelation of down sampler can be expressed as [7]:

y[n] = x[nM]

5. PROPOSED DESIGN SIMULATIONThe FIR filter has been developed for different filterorders and compared for output response. Directform-I FIR filter compared for increasing filter orderwhich is analyzed and designed using Matlab7.008.The main advantage of increasing filter length is thatpercentage amount of ripples decreases and thus,effieciency increases.Order 16, Decimation factor 2

3. FIR FILTERFIR filter is a finite impulse response filter which isnon- recursive in nature. That is, there is no feedbackinvolved. The impulse response of an FIR filter willeventually reach zero. FIR filter is stable and haslinear phase. It depends only on inputs and consistsof only zeroes [3]. FIR filters are filters having atransfer function of a polynomial in z- and is an all-zero filter in the sense that the zeroes in the z-planedetermine the frequency response magnitudecharacteristic.

0

-5

-10

-15

-20

-25

-30

-35

-40

Magnitude Response (dB)

Decimator w ith Order 16

0 5 10 15 20Frequency (kHz)

Impulse Response

4. DECIMATORTypically low pass filters are used to reduce thebandwidth of a signal prior to reducing the samplingrate. This is done to minimize aliasing due to thereduction in the sampling rate. Down sampler is basicsampling rate alteration device used to decrease thesampling rate by an integer factor [6]. In signalprocessing, down sampling (or "sub sampling") is theprocess of reducing the sampling rate of a signal.This is usually done to reduce the data rate or the sizeof the data. The down sampling factor (commonlydenoted by M) is usually an integer or a rationalfraction greater than unity. This factor multiplies thesampling time or, equivalently, divides the sampling

0.5

0.4

0.3

0.2

0.1

0

-0.1

Decimator w ith Order 16

0 50 100 150 200 250 300Time (useconds)

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 154

Decimatorw ith Order 32

Decimator w ith Order 16Decimatorw ith Order 32

Decimator w ith Order 64

Decimator w ith Order 64

Ma

gn

itu

de

(dB

)A

mp

litu

de

Magnitude

(dB

)

Mag

nitud

e(d

B)

Am

plitu

de

Order 32, Decimation 20.5

Impulse Response

Magnitude Response (dB) 0.4

0 0.3

-10 0.2

-20 0.1

Decimator w ith Order 64

-30 0

-40

-50

-0.1

0 0.2 0.4 0.6 0.8 1 1.2Time (mseconds)

-60

-70

0.5

0 5 10 1520Frequency (kHz)

Impulse Response

Comparison

0

-20

Magnitude Response (dB)

0.4Decimatorw ith Order 32

-40

0.3-60

0.2-80

0.1

0

-100

-0.1

0 100 200 300 400 500 600Time (useconds)

-1200 5 10 15 20

Frequency (kHz)

Order 64, Decimation 2

0

-20

-40

-60

-80

-100

-120

Magnitude Response (dB)

The hardware requirements of all the designs havebeen calculated in terms of multipliers and adders tocalculate the implementation cost. The cost increasesas we increase the filter length but ripple factor variesgreatly. For order32 and decimation factor 2, ripplefactor reduces to 30% and with order 64, it reduces to60%.

6. CONCLUSION

In this paper, an optimized Direct form FIRpolyphase decomposition technique has beenpresented to implement the decimator for multirateapplications. The proposed design has been

implemented using different filter orders. The design0 5 10 15 20Frequency (kHz) with order 64 has minimum ripple factor in output

response as compared to design having filter order of32 and 16. Thus, performance can be optimized onthe account of area and implementation cost.

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

155 NITTTR, Chandigarh EDIT-2015

REFERENCES[1] Kanu Priya, Rajesh Mehra. “Area Efficient Design of FIRFilter Using Symmetric Structure”, International Journal of AdvancedResearch in Computer and Communication Engineering, Volume

1, Issue 10, December 2012[2] Harry Yang, B.Eng. “Design and Implementation of a CascadedIntegrator Comb (CIC) Decimation Filter”, ME Theses, CarletonUniversity, April 2001[3] Sonika Gupta, Aman Panghal. “Performance Analysis of FIR FilterDesign by Using Rectangular, Hanning and Hamming WindowsMethods”, IJARCSSE, Volume 2, Issue 6, June 2012[4] Florian Achleitner, Philipp Miedl, Thomas Unterluggauer. “FilterStructures For FIR filters”, Conference Paper, Graz University ofTechnology, January 2011[5] N. Parijatha, K. R. Anusha Hinduja, A. Chandra Shaker. “FPGAOptimized Low Power And High Speed FIR Filter Structures For DSPApplications”, International Journal of Engineering Research &Technology, Volume 2, Issue 3, March 2013[6] S K Mitra, Digital Signal Processing, TaTa Mc Graw Hill, Thirdedition, 2006[7] Rajesh Mehra, Swapna Devi, “FPGA Based Design of HighPerformance Decimator using DALUT Algorithm”, ACEEEInternational Journal on Signal and Image Processing, Volume 1, pp. 9-13,2010