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Performance Evaluation of Pulse Compressor-Based Modulators With Very Fast Rise Times for Plasma Channel Drilling

T. Hõbejõgi, J. Biela Power Electronic Systems Laboratory, ETH Zürich

Physikstrasse 3, 8092 Zürich, Switzerland

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IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 42, NO. 10, OCTOBER 2014 2891

Performance Evaluation of Pulse Compressor-BasedModulators With Very Fast Rise Times

for Plasma Channel DrillingTonis Hobejogi and Juergen Biela, Member, IEEE

Abstract— In this paper, limitations of compact and durablesolid state modulators, using a 4.5-kV IGBT in combination witha pulse compression (PC) circuit are evaluated. Two investigatedmodulators uses two separate paths: one for ignition voltage andone for high currents. In the first modulator, ignition voltage isgenerated with a PC circuit based on saturable transformers,which is used to charge a series capacitor. After saturation, thecapacitor is connected to the output. The second modulator com-bines together pulse transformer and magnetic switch. Parasiticshave been estimated to find the optimal modulator configuration.Measurement results for validating the models as well as thesimulation results are presented. Main limitation factors aredescribed and possible solutions are discussed.

Index Terms— Plasma channel drilling (PCD), pulse compres-sion (PC), toroidal transformer.

I. INTRODUCTION

APOSSIBLE concept to improve drilling efficiency isplasma channel drilling (PCD). There, high voltage

pulses with a very short rise times are used for disintegratingrocks (Fig. 1) as for very fast rising voltages the breakdownfield of water is higher than for rock [1]–[4]. For the consid-ered application, pulse voltages in the range 150 kV with risetimes <100 ns are required (Table I).

The most common way for generating such pulses are Marxgenerators based on spark gaps. However, the size of suchconverters is one of the main disadvantage. Several alternativetopologies based on semiconductor switches in combinationwith a pulse compression (PC) circuit have been introduced[1], [5]–[16] (Figs. 2 and 3). In this paper, the focus ison evaluating the performance limits of circuits based onsaturable transformers, as shown in Fig. 2. Additionally, resultswith pulse transformer (PT) together with PC (Fig. 3) areinvestigated.

To design and investigate the circuit performance, a detailedcircuit simulation has been implemented. The transformerparasitics have been calculated analytically and in additionvalidated with COMSOL multiphysics. To verify the models,

Manuscript received October 31, 2013; revised January 8, 2014; acceptedFebruary 10, 2014. Date of publication March 3, 2014; date of current versionOctober 21, 2014. This work was supported by CTI under Grant 10856.1PFIW-IW and in part by Vacuumschmelze for providing the magnetic cores.

The authors are with the Laboratory for High Power Electronic Sys-tems, ETH Zurich, Zurich CH-8092, Switzerland (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPS.2014.2306212

Fig. 1. (a) Sketch of a PCD electrode setup. (b) Breakdown field versusvoltage rise-time curve (Ebd = f (Trise)).

Fig. 2. Scheme of a two stage PC unit, using saturating transformers,investigated in this paper.

Fig. 3. Alternative circuit using PT together with PC.

TABLE I

PULSE PARAMETERS FOR THE CONSIDERED PCD APPLICATION

a test device has been built. In the following, first, theconcept and the design procedure are presented in Section II.Thereafter, the calculation of the parasitics is explained inSection III and prototypes together with simulation results areintroduced in Section V. Finally, in Section VI the limitationsof the topology are discussed.

0093-3813 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

2892 IEEE TRANSACTIONS ON PLASMA SCIENCE, VOL. 42, NO. 10, OCTOBER 2014

Fig. 4. Design procedure block scheme (all parameters will be described inSection III).

II. DESIGN PROCEDURE

The considered topology is shown in Fig. 2. It consistsof two saturable transformers and two series capacitors. Thebasic topology idea has been introduced in [5] and [6] whilethe presented one has a few modifications. So far, mainly, aseries inductor is used at the source side to limit the currentmagnitude while the transformer saturates. Here, a capacitorC1 is used to limit the transformer current (see [1]). Beforethe saturation of TRMV (Fig. 2), capacitor C1 has a low impacton the output voltage. Additionally, the high voltage and thehigh current paths are separated [1].

For the saturable transformers/inductors, a core materialwith a sharp saturation curve and a high magnetizing induc-tance (L M ) as well as low saturation inductance (L Msat)is required. In the considered prototype system, Vacuum-schmelze (VAC) nanocrystalline material is used. This ful-fills these requirements under low frequency as will bediscussed later (Section VI). For the prototype system, theVAC T600006-L2160-V074 (V074) core is selected.

A. Saturable Transformer Circuit

In the first step of the transformer design procedure (Fig. 4),the output voltage is considered and compared between differ-ent configurations (turns ratio, number of turns, etc.). In thesecond step, the mechanical design is considered and theinfluence of the parasitics on the output voltage is determined.The design is based on V074 cores with single layer windingsto limit L Msat . In the third and final step, the best option withthe set constrains is chosen.

B. PT Circuit

Similar to the saturable transformer circuit, same designprinciple can be applied for the PT circuit. On the otherhand, less parameters could be adjusted, thus, the procedureis simplified.

III. PARASITICS CALCULATIONS-SATURABLE

TRANSFORMER CIRCUIT

In the following, analytic calculations scripts for deter-mining the stray capacitance, the leakage inductance, themagnetizing inductance, the ohmic losses, and the corelosses are presented. There, the focus is on the saturable

Fig. 5. Illustrative transformer (left) horizontal and (middle) vertical cutsketch when NPrim = 3, NPrimParallel = 7, NSec = 9, and NSecParallel = 2.On the right built TRHV (N3 = 3, N3p = 11, N4 = 12, and N4p = 2).

transformer system. In Section IV, same calculations are shownfor the PT circuit.

The electrical scheme of a transformer is, e.g., given in [17]together with its capacitances and inductances. One could useCOMSOL multiphysics to calculate the parasitics, althoughthe computation speed is relatively slow and not convenientfor designing purpose. Thus, an analytical calculations scriptfor the stray capacitance, the leakage inductance, and themagnetizing inductance is preferred.

A. Stray Capacitance

As shown in [17], transformers can be modeled with asimplified equivalent network using three capacitors (Fig. 6).For comparing the measurements with the calculated results,the equivalent capacitance for the three measurement setupsshown in Fig. 6 are determined

Ca = C1 + C12 → C1 = Ca − C12 (1)

Cb = C2 + C12 → C2 = Cb − C12 (2)

Cc = C12 → C12 = Cc. (3)

There, C1 and/or C2 could be negative. For computationpurposes, a lumped capacitance Cd is calculated [17] (Fig. 7)

Cd = C1

n2 + C12 · (n − 1)2

n2 + C2 (4)

where n is transformer turns ratio.To analytically model the capacitance, several simplifica-

tions are made. It is assumed that each turn can be representedas a plate, that the spacing between the turns is equal, that thecore voltage is constant and that the toroid core with windingscan be represented as a straight plane (Fig. 8).

The total capacitance for each measurement setup (Fig. 6)can be described as

Ca/b/c = CPC + CPS + CSC + CTT−prim + CTT−sec (5)

where CPC, CPS, and CSC are the primary-to-core, primary-to-secondary, and secondary-to-core capacitance, respectively;CTT−prim and CTT−sec are the primary and the secondary wind-ings turn-to-turn capacitance, respectively. Each capacitancecan be calculated separately and will be discussed shortly.With calculated Ca , Cb, and Cc one can derive Cd using(1)–(4).

HOBEJOGI AND BIELA: PERFORMANCE EVALUATION OF PULSE COMPRESSOR-BASED MODULATORS 2893

Fig. 6. Topologies to measure and simulate transformer capacitances.(a) Ca . (b) Cb . (c) Cc .

Fig. 7. Transformer model used in the full circuit simulation.

Fig. 8. (a) Top-view sketch of the windings of the saturable transformercircuit. (b) Definition of the calculation parameters.

The simulated voltage applied to each setup is Vsim = 1 V,thus the total electrical energy is

Wcap = 1

2· C · dV 2 → Ctotal = 2 · Wtotal. (6)

Consequently

Ctotal =N∑

i=1

Cturn (7)

Cturn = Cturn′ · dV 2 (8)

where Ctotal is total winding capacitance, Cturn is the realcapacitance per turn, Cturn′ is the capacitance per turn whenV = 1 V, and dV is the voltage per turn.

The capacitances in (5) are calculated as parallel-plateconfiguration

Cpp = h · ε0 · ε · lwd

(9)

where h is the average width of a single turn, lw is the windingheight, and d is the distance between the windings and/or core.The assumption is valid as long as several turns are used, thusthe following script is suitable as long as N1 > 1 and N2 ≥ 10.For other cases, a numerical method based on the mirroringmethod [18] is used for calculating the parasitic capacitances.

In Fig. 8, the core layout is given. It has to be kept in mindthat h = f (CoreSize) while d �= f (CoreSize). Therefore,the inner and outer parts of the capacitance are calculated

separately, nevertheless the calculations scheme is the same

CPC =N1∑

i=1

Cpp · (V1,i − V2, j − VCore)2 · N1p (10)

CPS =N1∑

i=1

Cpp · (V1,i − V2, j − VCore)2 · N1p (11)

CSC =N2∑

j=1

Cpp · (V1,i − V2, j − VCore)2 · N2p (12)

where N1 is the number of turns on the primary winding,N1p is the number of parallel primary windings, N2 is thenumber of turns on the secondary winding, N2p is the numberof parallel secondary windings, V1,i and V2, j are the voltageson the i th and j th turn of the primary and the secondarywindings, respectively, and VCore is the core voltage. As thesecondary winding covers much wider area than the primarywinding, V2, j has to be computed with care. The distancedefinitions can be observed in Fig. 8. Voltage values for eachcase with the transformer TRHV (Fig. 2) can be observed inTable II. The main error is caused by defining the VCore value.Based on COMSOL simulations analytical formulas have beenderived empirically.

The turn-to-turn capacitance is calculated with the pair ofparallel wire formula. Combining it with (8) results in

CTT = π · ε0 · ε · lw · (N − 1) · ( 1N )2 · Np

ln(

dTT2·rwire

+√(

dTT2·rwire

)2 − 1) (13)

where (1/N) is the voltage per turn, (N − 1) is the number ofparallel turns, dTT is the distance between the turns, rwire isthe wire radius, and Np is the number of parallel windings.

B. Leakage Inductance

The leakage inductance Lσ (Fig. 7) is calculated with [17]

Emagnetic = 1

2· μ ·

∫

V

�H 2dV = 1

2· Lσ · I 2

1 (14)

TABLE II

VOLTAGES USED FOR ANALYTIC CAPACITANCE CALCULATIONS FOR

TRHV (dPC = 4 mm AND dPS = 10 mm). ISOLATION DISTANCES ARE

UNCHANGED DURING THE DESIGN PROCESS. HERE, V1,i AND V1,i

ARE THE PRIMARY AND THE SECONDARY WINDING VOLTAGES

PER TURN, RESPECTIVELY; VCore IS THE CORE POTENTIAL


Fig. 9. Inductance dependency of current (core VAC V140, VITROPERM500 F, din = 44.5 mm, dout = 85.8 mm, AFe = 228 mm2, and N = 4).

| �H | = N1 · I1

hL. (15)

Combining (14) and (15), yields

Lσ = μ · μ0 · N21 · lL · dL

hL· 1

N1p(16)

where lL is the height of the winding, dL is the distancebetween the two windings, and hL is the apparent width ofthe primary winding. In the simulations, it has been assumedthat one winding is represented by a single layer, no spacingbetween the turns (Figs. 5 and 8). In the analytic calculations,only the volume covered by the primary winding is consideredas empirically studies showed that there the main magneticenergy is stored. The same constrains apply to Lσ as for thecapacitance calculation.

C. Magnetizing Inductance

The magnetizing inductance L M (Fig. 7) significantly influ-ences the modulator operation. The nonsaturated inductancevalue is determined by

L M = μ0 · μ · N22 · NFe · AFe

lFe(17)

where μ is the permeability of the core, N2 is the num-ber of turns on the secondary side, NFe is the number ofV074 cores, AFe is the core area of a single core element,NFe · AFe is the total core area, and lFe is the average iron

TABLE III

TRANSFORMER TRHV PARASITICS. THE MEASUREMENTS AND THE

CALCULATIONS FOR Lσ AND Rs DIFFER DUE TO RELATIVELY LONG

MEASUREMENT WIRES (ISOLATION REQUIREMENTS)

Fig. 10. Calculated E- and H-field with mirroring method for a PT shownin Fig. 13.

length. After saturation (17) is still valid, although with a fewimportant changes

L Msat = μ0 · N22 · ASat

lFe(18)

where ASat is the secondary winding core area after saturation(in simulations L M is used on the secondary side, Figs. 7and 11).

The saturation current can be calculated as

ISat = NFe · AFe · N2 · BSat

L M(19)

where BSat is the saturation flux density for the core material.The data sheet of the V074 core provides the necessary

information for calculating L M and ISat for low frequencyoperation. Nevertheless, the core material is highly frequencydepending (Fig. 9) what has a large impact on the modulatorperformance. The permeability is reduced largely at higherfrequencies (Table III and Fig. 9), consequently affecting thesaturation current and the performance.

For simulations, the saturating inductor is described asL = f (I ). In Fig. 9, the inductance dependency on the currentfor the same material as used to build the transformers isdescribed. The same normalized dependencies have been usedin the simulations.

D. Copper Losses

The winding resistance is modeled with RS (Fig. 7). Bothwinding resistances are calculated and added together aslumped resistance

RS = R1 · 1

N1p+ R2 ·

(N2

N1

)2

· 1

N2p(20)

where R1 and R2 are the resistance of the primary and thesecondary windings, respectively. The high frequency effectscan be included with the approach presented in [19].

E. Core Losses

The core losses are modeled with RP (Fig. 7). In [20], itis shown that RP dependents on the core volume and time tosaturate. Using curve fitting and pulse duration simulations,RP can be estimated. However, during pulse operation, RP

has a relatively low effect [17].


Fig. 11. Full simulation circuit for saturable transformer modulator with measured and simulated voltages. The measured curves are obtained at no loadconditions.

IV. PARASITICS CALCULATIONS–PT CIRCUIT

The design of the PT is similar to the mentioned procedures.The PC parameters can be estimated with (17) (LPC and LMTRin Fig. 14), (18) (LPC, Fig. 14), and (19) (LPC, Fig. 14).To reduce the stray capacitance (CPC, Fig. 14), the inductorcan be split into groups (for example, Fig. 13).

PT calculations are well described in [17]. In this project,the transformer leakage Lσ and capacitance CdTR (Fig. 14) arecalculated using the mirroring method [18]. Transformer core(RTR, Fig. 14) and copper losses (RTR1, Fig. 14) are estimatedas mentioned above.

V. MEASUREMENT RESULTS

In this paper, measurement results for two systems, thesaturable transformer and the PT, are presented.


In the considered saturable transformer PC modulator, VACV074 ring cores are used for both transformers. In Fig. 5,

TABLE IV

PARAMETERS OF THE SATURABLE TRANSFORMERS (MEASURED)

Fig. 12. Constructed saturable transformer modulator (LHC is added forillustration).

the physical layout sketch is shown together with TRHV. Theprimary and secondary windings are made of 2.5 mm2 wire.To reduce leakage inductance, several primary windings areconnected in parallel. Additionally, two secondary windingsare connected in parallel to reduce the saturation inductance.To ensure good electrical strength, the complete transformer ispotted with epoxy (Fig. 5). The minimum spacing between thewindings and core is designed with COMSOL multiphysics.

The transformer core is on a floating potential, thus spacingcould be reduced between the core and the primary winding.The stray capacitance is reduced due to the lower voltagedifference between the core and windings. Besides, accessingthe core is hardly possible because of the plastic housingand fragile nanocrystalline material. Still, due to the floating


Fig. 13. Prototype of the PT circuit.

potential some isolation distance is required between the coreand the windings. Additional safety distance between theprimary and the secondary windings is provided.

The prototype transformers are designed with NFe1 =NFe2 = 3 V074 cores in parallel. All the parameters can befound in Fig. 11 and Table IV. Simulation and measurementresults for TRHV can be observed in Table III. As can be seen,the calculated and measured capacitances have difference lessthan 20%. It must be noticed that the analytical script for C12(C34 in Table III) tend to result in higher capacitance valuesthan COMSOL and measurements. The leakage inductance hasa considerable difference. As the simulated value is relativelylow, it is assumed that the difference comes from the measure-ment error caused by relatively long measurement connections.

The modulator uses high voltage ceramic pulses capacitors.As can be observed in Fig. 11, resulting in CMV = 9.43 nF(six 1.6 nF 50-kV capacitors in parallel, Fig. 12) and CHV =397 pF (two 800 pF 100 kV capacitors in series, Fig. 11). Theinductor LHV is realized as an air core inductor (LHV = 47 μHand CLhv ≈ 25 pF, Figs. 11 and 12).

As can be observed in Fig. 11, the performance of thepractical unit follows well with the calculated one. In themodel for TRMV, the 100-kHz parameters are used for the corematerial (L M = 21 mH, L Msat = 15 μH, and ISat = 1.69 Aand normalized saturation curve at 100 kHz from Fig. 9).Whereas for TRHV, the 1 MHz parameters are used (L M =2.0 mH, L Msat = 3 μH, and ISat = 591 A and normalizedsaturation curve at 1 MHz from Fig. 9).

B. PT Circuit

In Fig. 13, a picture of the PT modulator prototype can beseen. It consists of a PT (AFe = 4800 mm2, lFe = 875 mm,N1 = 1, N2 = 50, and m = 34 kg), a high voltagecapacitor bank (CHV = 533 pF, Fig. 14) and a PC inductor

TABLE V

PT PARASITICS

Fig. 14. Measured and simulated load voltage with PT circuit (Vin = 2 kV),deionized water load without water breakdown.

(NFe−PC = 8, NPC = 35, Fig. 14). In this setup, the PT coreis over dimensioned for test purposes. Calculations show thathalf the size should be sufficient.

Like with the saturable transformer circuit, VAC V074 coresare used for the PC inductor. Measurements and parameterscan be observed in Table V for the transformer and in Table VIfor the PC inductor. The circuit itself is shown in Fig. 14together with the measured voltage curves.

VI. DISCUSSION


As can be observed by investigating different designs(Figs. 15–18) in the saturable transformer topology, the mainlimiting factors are caused by the core material. Namely, ascan be observed in Fig. 9 nanocrystalline material is highlyfrequency dependent. The simulations are performed in time-domain and therefore the frequency dependency is challengingto count. Good modulator performance requires L M � L Msat.As one can observe in Fig. 11, TRMV operates in a range of afew hundred kilohertzs and TRHV in a much higher range(>1 MHz). Therefore, the inductance change from L M toL Msat is low and slow if Fig. 9 is considered. Moreover, onecould observed in Fig. 11, the high voltage drop after CMV,which is caused by a high LMsat value resulting in a lowerinput voltage of the next stage.

For reducing the high L Msat value, one could use lessturns (18). In Figs. 15–17, one can observe the change

TABLE VI

PARAMETERS OF THE PC


Fig. 15. Load voltage dependency on N2 while N1 =1...3 (NFe1 =NFe2 = 3, N3 = 3, and n2-turns ratio of TRHV).

Fig. 16. Load voltage dependency on N4 while N3 = 1...3 (NFe1 =NFe2 = 3, N1 = 3, and n1-turns ratio of TRMV).

in the output voltage as a function of number of turns.With increasing number of turns, the voltage increases, until apoint when the output voltage starts to reduce due to voltagedrop on LMsat.

Other option to reduce L Msat value could be by using othermaterials, e.g., ferrites [10], [11]. However, the latter one hasmuch lower permeability values. Moreover, saturation is notas fast as with nanocrystalline materials (especially at 0 Hz).

In Fig. 18, theoretical voltages for improved material areplotted. In the simulations (Fig. 11), μ values for L M at1 MHz) calculations are multiplied by a constant k to see thechange of output voltage. The L M value itself has an impact,but much more important is to use the correct saturationbehavior curve. If one could use dc material properties, theoutput voltage is doubled compared with the 1 MHz case.Therefore, in the very high frequency range, the change of theL M limits the performance.

B. PT Circuit

The total physical size of the PT circuit without high currentpath is 750×260×350 mm (Fig. 13) while the presented sat-urable transformer circuit size is 240×240×440 mm (Fig. 12).In the contrast to the saturable transformer circuit, a muchlarger (physically and magnetically) magnetic switch for PCcircuit still allows faster voltage rise time (Fig. 11 versusFig. 14). With deionized water, the load voltage reaches morethan 100 kV with 2/3 of the designed input voltage.

Although the rise time in general is fast, the slowlyincreasing voltage at the beginning of the pulse could be

Fig. 17. Load voltage dependency on total number of core elements(NFe1 + NFe2) while n1 = 12 and n2 = 4.

Fig. 18. Load voltage dependency on the core material behavior, if all otherparameters are unchanged [Fig. 11, μsim = k · μ (at 1 MHz)].

observed. This phenomenon is directly connected with the corefrequency behavior.

C. Comparison

As shown, with a two stage saturable transformer topology,higher voltages are possible if more cores and different wind-ing arrangement are used (N1/N2 = 2/24, N3/N4 = 3/9,and NFe1/NFe2 = 8/7). If adding an extra stage evenhigher voltages are possible (N1/N2 = 1/7, N3/N4 = 1/5,N5/N6 = 1/3, and NFe1/NFe2/NFe3 = 14/12/12). Never-theless, with the topology described in [1] (Figs. 3 and 13)similar voltages are achieved with less cores. In Table VII,possible output voltages and the required number of V074cores together with the total core weight are shown. As canbe observed using a PT setup, the required voltage is achievedwith similar iron weight as with the three stages saturabletransformer arrangement. One should keep in mind that nopremagnetization is counted in this comparison.

TABLE VII

POSSIBLE OUTPUT VOLTAGES FOR OPTIMAL DESIGN AND

IRON WEIGHT (WITHOUT HIGH CURRENT PATH)


The PT circuit with PC is favorable, due to a simplerand compact design. In the practical PCD operation suchmodulators would be too large to be used in the drill head, butcould be used as a separate unit with connection cable to theelectrodes in the drill head. Additionally, the semiconductorsmay limit the usage of the modulator in the drill head as theambient temperature should be below 100 °C. Despite modu-lator limitations PCD has still high potential for the future asit would be smaller than a conventional Marx generator.

VII. CONCLUSION

PCD is a promising method to improve drilling technology.To perform efficient drilling compact, efficient and reliablegenerators are required. In this paper, limitations of a topologyusing saturable transformers are investigated and an alternativeis shown.

To better understand the modulator performance, all theparasitics are evaluated. With the parasitics the limits of theinvestigated modulator can be estimated. Particularly, trans-former capacitances and leakage inductance have minor impactto the performance. In contrast, the dependency of the corepermeability on frequency and a relatively high saturatedmagnetizing inductance are major limiting effects.

Due to the frequency dependency, transformers have lowmain inductance at high frequencies. Thus, difference betweenthe unsaturated and the saturated inductances is not as high asdesired. Therefore, after saturation of the core the switchingaction is not as big as desired. Additionally, the high saturatedmagnetizing inductance cause high voltage drop, thereforeoutput voltage is limited.

A possible solution would be to use three stages or a PTtopology combined with a PC stage (Fig. 13). The latterone suffers much less on frequency dependency while overalldesign is simpler.

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Tonis Hobejogi received the Degree in electricalengineering and the bachelor’s (Hons.) degree fromthe Tallinn University of Technology, Tallinn, Esto-nia, and the Master Diploma degree with minorin industrial engineering and management from theChalmers University of Technology, Göteborg, Swe-den. His master thesis focused on the harmon-ics in transformer core. He is currently pursuingthe Ph.D. degree with the High Power ElectronicsLaboratory, Swiss Federal Institute of Technology,Zurich, Switzerland, where he focused on pulsed-

power applications.His current research interests include the high voltage, power electronics,

power systems, and management.

Juergen Biela (S’04–M’06) received the Diploma(Hons.) degree from Friedrich-Alexander-UniversitätErlangen-Nürnberg, Erlangen, Germany, and thePh.D. degree from ETH Zurich, Zurich, Switzerland,in 1996 and 2006, respectively.

He dealt in particular with resonant dc-link invert-ers with the University of Strathclyde, Glasgow,U.K., and the active control of series-connectedIGCTs with the Technical University of Munich,Munich, Germany. In 2000, he joined the ResearchDepartment, Siemens A&D, Erlangen, where he was

involved in inverters with very-high switching frequencies, SiC components,and EMC. In 2002, he joined the Power Electronic Systems Laboratory(PES), ETH Zurich, for pursuing the Ph.D. degree, focusing on optimizedelectromagnetically integrated resonant converters. From 2006 to 2007, hewas a Post-Doctoral Fellow with PES and a Guest Researcher with theTokyo Institute of Technology, Tokyo, Japan. From 2007 to 2010, he wasa Senior Research Associate with PES. Since 2010, he has been an AssociateProfessor of High-Power Electronic Systems with ETH Zurich. His currentresearch interests include the design, modeling, and optimization of PFC, dc-dc and multilevel converters with emphasis on passive components, the designof pulsed-power systems, and power electronic systems for future energydistribution.

performance evaluation of pulse compressor-based ...€¦ · ieee transactions on plasma science,...

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