Performance of a TDC based on FPGA

By: Vyome SinghFor: IPM FermiLab

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What is a TDC?

• TDC stands for Time to digital convertor.

• It is a time Stamp.

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Applications

• The flight time of particles.

• The life time of particles.

• The decay time of scintillators.

• Laser range finding.

• Time of flight mass spectrometry.

• Time of flight Positron Emission Tomography (TOF - PET).

• The module I tested will be used in LArIAT experiment (Liquid Argon Time Projection Chambers)

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Motivation for a FPGA based TDC• Higher Resolution

• Cheap

• Low-Power consumption

• Flexibility

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Brief overview of the working of TDC

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[1]

• Clock (250MHz) ~ 4ns• Coarse Counter• Fine measurement

Bigger picture

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Even Bigger Picture!

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FPGA TDC module

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DX InputCX Input

VME Interface

Discriminator Card

FPGA TDC module

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FPGA TDC

VME Interface Map

Register Base Address + Function

REG0 0x0 Firmware Version number(read only)

REG4 0x4 Threshold Voltage Setting

REG8 0x8 Testing Constant (read only)

REGC 0xC Lower 16 bits: operation control RegisterHigher 16 bits: Status (Read only)

REG10 0x10 Channel Mask

Data P0 0x1000 to 0x17FC

512 data long words (32- bit)

Data P1 0x1800 to 0x1FFC

512 data long words (32-bit)

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Data Bit Layout

• We get 8 hexadecimal number (32 bit) for each word. A Time Frame looks like

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0x00000000 Time Frame Separator

F (4 bit) TCY, LSB=256us

4(4 bit)

TCY:LSB=16us (4 bit)

CH: 0-15(4 bit)

Coarse Time: LSB=4ns(12 bit)

Fine Time: LSB=15.625ps(8 bit)

4(4 bit)

TCY:LSB=16us(4 bit)

CH: 0-15(4 bit)

Coarse Time:LSB=4ns(12 bit)

Fine Time:LSB=15.625ps(8 bit)

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Registers

REG C

Data P0

Data P1

Result for D3 input

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13nanoseconds

Num

ber o

f hits

Channel C

Resolution = 49.02 Pico second

Result for C3 input

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nanoseconds

Num

ber o

f hits

Resolution = 26.61 Pico Seconds

Intrinsic time difference between channel e and f

Bin widths

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15nanoseconds

Num

ber o

f hits

Resolution = 65.36 Picosecond

Summary

• Importance of TDC in detectors.

• FPGA TDC is fulfilling the role of a high resolution TDC

• Low power consumption.

• Different family of FPGA chip will give better resolution.(Current FPGA : Cyclone III)

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References

• [1] Firmware-only Implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA) by Jinyuan Wu, Zonghan Shi and Irena Y. Wang for CKM Collaboration.

• [2] A Low-Power Wave Union TDC Implemented in FPGA by Jinyuan Wua*, Yanchen Shib and Douglas Zhub

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