performance summary (ta - analog.com · 2 dc1730afa demo manual dc1370a quick start procedure...

1dc1730afa

DEMO MANUAL DC1370A

LTC2262-14/-12, LTC2261-14/-12, LTC2260-14/-12, LTC2259-14/-12, LTC2258-14/-12, LTC2257-14/-12, LTC2256-14/-12,

14-/12-Bit, 25Msps to 150Msps ADCs

Demonstration circuit 1370A supports a family of 14-/12-Bit 25Msps to 150Msps ADCs. Each assembly features one of the following devices: LTC2262-14, LTC2262-12 LTC2261-14, LTC2261-12, LTC2260-14, LTC2260-12, LTC2259-14, LTC2259-12, LTC2258-14, LTC2258-12, LTC2257-14, LTC2257-12, LTC2256-14, LTC2256-12, high speed, high dynamic range ADCs.

Demonstration circuit 1370A supports the LTC2262 family full rate CMOS, and DDR CMOS output mode. This family of ADCs is also supported by demonstration circuit 1369, which is compatible with DDR LVDS output modes. L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks

and QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Several versions of the 1370A demo board supporting the LTC2262 14-/12-Bit series of A/D converters are listed in Table 1. Depending on the required resolution and sample rate, the DC1370A is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 170MHz. Refer to the data sheet for proper input networks for different input frequencies.

Design files for this circuit board are available at http://www.linear.com/demo

(TA = 25°C)

PARAMETER CONDITIONS VALUE

Supply Voltage – DC1370A Depending on Sampling Rate and the A/D Converter Provided, this Supply Must Provide up to 150mA

Optimized for 3.6V [3.5V ⇔ 6.0V Min/Max]

Analog Input Range Depending on SENSE Pin Voltage 1VP-P to 2VP-P

Logic Input Voltages Minimum Logic High 1.3V

Maximum Logic Low 0.6V

Logic Output Voltages (OVDD = 1.8V)) Minimum High Level Output Voltage 1.750V (1.790V Typical)

Maximum Low Level Output Voltage 0.050V (0.010V Typical)

Sampling Frequency (Convert Clock Frequency) See Table 1

Convert Clock Level Single-Ended Encode Mode (ENC – Tied to GND) 0V to 3.6V

Convert Clock Level Differential Encode Mode (ENC – Not Tied to GND) 0.2V to 3.6V

Resolution See Table 1

Input Frequency Range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

Performance Summary

DeScriPtion

2dc1730afa

DEMO MANUAL DC1370A

Quick Start ProceDure

Demonstration circuit 1370A is easy to set up to evaluate the performance of the LTC2262 A/D converters. Refer to Figure 1 for proper measurement equipment setup and follow the procedure:

Setup

If a DC890 QuikEval™II Data Acquisition and Collection System was supplied with the DC1370A demonstration circuit, follow the DC890 Quick Start Guide to install the required software and for connecting the DC890 to the DC1370A and to a PC.

DC1370A Demonstration Circuit Board Jumpers

The DC1370A demonstration circuit board should have the following jumper settings as default positions: (as per Figure 1)

JP2: PAR/SER: Selects Parallel or Serial programming mode. (Default - Serial)

JP3: Duty Cycle Stabilizer: Enables/Disable Duty Cycle Stabilizer. (Default - Enable)

JP4: SHDN: Enables and disables the LTC2262. (Default - Enable)

Applying Power and Signals to the DC1370A Demonstration Circuit

If a DC890 is used to acquire data from the DC1370A, the DC890 must FIRST be connected to a powered USB port or provided an external 6V to 9V BEFORE applying 3.6V to 6.0V across the pins marked V+ and GND on the DC1370A. DC1370A requires 3.6V for proper operation. Regulators on the board produce the voltages required for the ADC. The DC1370A demonstration circuit requires up to 150mA depending on the sampling rate and the A/D converter supplied.

The DC890 data collection board is powered by the USB cable and does not require an external power supply unless it must be connected to the PC through an un-powered hub, in which case it must be supplied an external 6V to 9V on turrets G7(+) and G1(–) or the adjacent 2.1mm power jack.

Analog Input Network

For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequen-cies above 170MHz, refer to the LTC2262 data sheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz.

Table 1. DC1370A VariantsDC1370A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY

1370A-A LTC2261-14 14-Bit 125Msps 5MHz to 170MHz

1370A-B LTC2260-14 14-Bit 105Msps 5MHz to 170MHz

1370A-C LTC2259-14 14-Bit 80Msps 5MHz to 170MHz

1370A-D LTC2258-14 14-Bit 65Msps 5MHz to 170MHz

1370A-E LTC2257-14 14-Bit 40Msps 5MHz to 170MHz

1370A-F LTC2256-14 14-Bit 25Msps 5MHz to 170MHz

1370A-G LTC2261-12 12-Bit 125Msps 5MHz to 170MHz

1370A-H LTC2260-12 12-Bit 105Msps 5MHz to 170MHz

1370A-I LTC2259-12 12-Bit 80Msps 5MHz to 170MHz

1370A-J LTC2258-12 12-Bit 65Msps 5MHz to 170MHz

1370A-K LTC2257-12 12-Bit 40Msps 5MHz to 170MHz

1370A-L LTC2256-12 12-Bit 25Msps 5MHz to 170MHz

1370A-M LTC2262-14 14-Bit 150Msps 5MHz to 170MHz

1370A-N LTC2262-12 12-Bit 150Msps 5MHz to 170MHz

3dc1730afa

DEMO MANUAL DC1370A

Figure 1. DC1370A Setup


In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR. In the case of the DC1370A the bandpass filter used for the clock should be used prior to the DC1075A.

The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50Ω outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion.

If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a Gallium Arsenide gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and High IP3 point required. A high order filter can be used prior to this final

amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit.

Encode Clock

NOTE: Apply an encode clock to the SMA connector on the DC1370A demonstration circuit board marked J7. As a default the DC1370A is populated to have a single ended input.

For the best noise performance, the ENCODE INPUT must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VP-P or 13dBm. When using a sinusoidal signal generator a squaring circuit can be used. Linear Technology also provides demo board DC1075A that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2262 family.

3.5V to 6V JUMPERS ARE SHOWN INDEFAULT POSITIONS

PARALLEL DATA OUTPUTTO DC890

ANALOG INPUT

N

+

SINGLE ENDEDENCODE CLOCK

PARALLEL/SERIALPROGRAMMING MODE

DUTY CYCLESTABILIZER SHDN

4dc1730afa

DEMO MANUAL DC1370A

Using bandpass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1370A a bandpass filter used for the clock should be used prior to the DC1075A. Data sheet FFT plots are taken with 10 pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, nonharmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used with TTE bandpass filters for both the clock input and the analog input.

Apply the analog input signal of interest to the SMA con-nectors on the DC1370A demonstration circuit board marked J5 AIN

+. These inputs are capacitive coupled to balun transformers ETC1-1-13.

An internally generated conversion clock output is avail-able on J1 which could be collected via a logic analyzer, or other data collection system if populated with a SAMTEC MEC8-150 type connector or collected by the DC890 QuikEval™II Data Acquisition Board using PScope™ software.

Software

The DC890 is controlled by the PScope System Software provided or downloaded from the Linear Technology website at http://www.linear.com/software/. If a DC890 was provided, follow the DC890 Quick Start Guide and the instructions below.

To start the data collection software if PScope.exe is in-stalled (by default) in \Program Files\LTC\PScope\, double click the PScope Icon or bring up the run window under the start menu and browse to the PScope directory and select PScope.

If the DC1370A demonstration circuit is properly connected to the DC890, PScope should automatically detect the DC1370A, and configure itself accordingly. If necessary the procedure below explains how to manually configure PScope.

Under the Configure menu, go to ADC Configuration.... Check the Config Manually box and use the following configuration options, see Figure 2:

Manual Configuration settings:

Bits: 14 (or 12 for 12-bit parts)

Alignment: 14

FPGA Ld: CMOS

Channs: 2

Bipolar: Unchecked

Positive-Edge Clk: Checked


Figure 2. ADC Configuration

If everything is hooked up properly, powered and a suit-able convert clock is present, clicking the Collect button should result in time and frequency plots displayed in the PScope window. Additional information and help for PScope is available in the DC890 Quick Start Guide and in the online help available within the PScope program itself.

Serial Programming

PScope has the ability to program the DC1370A board serially through the DC890. There are several options available in the LTC2262 family that are only available through serially programming. PScope allows all of these features to be tested.

These options are available by first clicking on the Set Demo Board Options icon on the PScope toolbar (Figure 3).

5dc1730afa

DEMO MANUAL DC1370A

This will bring up the menu shown in figure 4.


Figure 4. Demo Board Configuration Options

Figure 3. PScope Toolbar

Clock Inversion: Selects the polarity of the CLKOUT signal

• Normal (Default): Normal CLKOUT polarity

• Inverted: CLKOUT polarity is inverted

Clock Delay: Selects the phase delay of the CLKOUT signal:

• None (Default): No CLKOUT delay

• 45 deg: CLKOUT delayed by 45 degrees



Clock Duty Cycle: Enable or disables Duty Cycle Stabilizer

• Stabilizer off (Default): Duty Cycle Stabilizer Disabled

• Stabilizer on: Duty Cycle Stabilizer Enabled

Output Current: Selects the LVDS output drive current. This option is not used on the DC1370A

• 1.75mA (Default): LVDS output driver current

• 2.1mA: LVDS output driver current






Internal Termination: Enables LVDS Internal Termination. This option is not used on the DC1370A

• Off (Default): Disables internal termination

• On: Enables internal termination

Outputs: Enables Digital Outputs

• Enabled (Default): Enables digital outputs

• Disabled: Disables digital outputs

This menu allows any of the options available for the LTC2262 family to be programmed serially. The LTC2262 family has the following options:

Power Control: Selects between normal operation, nap, and sleep modes

• Normal (Default): Entire ADC is powered, and active

• Nap: ADC core powers down while references stay active

• Shutdown: The entire ADC is powered down

6dc1730afa

DEMO MANUAL DC1370A

Output Mode: Selects Digital Output Mode

• Full Rate (Default): Full rate CMOS output mode

• Double LVDS: double data rate LVDS output mode (This mode is not supported by the DC1370A, please use the DC1369)

• Double CMOS: double data rate CMOS output mode

Test Pattern: Selects Digital Output Test Patterns

• Off (Default): ADC data presented at output

• All out =1: All digital outputs are 1

• All out = 0: All digital outputs are 0

• Checkerboard: OF, and D13-D0 Alternate between 101 0101 1010 0101 and 010 1010 0101 1010 on alternat-ing samples

• Alternating: Digital outputs alternate between all 1’s and all 0’s on alternating samples

Alternate Bit: Alternate Bit Polarity (ABP) Mode

• Off (Default): Disables alternate bit polarity

• On: Enables alternate bit polarity (Before enabling ABP, be sure the part is in offset binary mode)

• Randomizer: Enables Data Output Randomizer

• Off (Default): Disables data output randomizer

• On: Enables data output randomizer

• Two’s complement: Enables Two’s Complement Mode

• Off (Default): Selects offset binary mode

• On: Selects two’s complement mode

Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1370A demo board.


7dc1730afa

DEMO MANUAL DC1370A

PartS LiStITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER

1 0 C1 CAP, 0402 OPTION OPTION

2 12 C2, C3, C6, C7, C38, C39, C52, C53, C58, C60, C61, C63

CAP, 0402, 0.01µF, 10%, 16V, X7R AVX 0402YC103KAT

3 2 C10, C9 CAP, 0402, 8.2pF, 5%, 50V, COG AVX 04025A8R2JAT2A

4 6 C12, C15, C18, C19, C21, C37 CAP, 0402, 0.1µF, 10%, 10V, X5R TDK C1005X5R1A104K

5 3 C13, C17, C23 CAP, 0402, 1µF, 10%, 10V, X5R TDK C1005X5R1A105K

6 3 C14, C22, C57 CAP, 0603, 1µF, 10%, 16V, X7R TDK C1608X7R1C105K

7 1 C20 CAP, 0402, 1µF, 10%, 10V, X5R MURATA GRM155R61A105KE15D

8 1 C24 CAP, 0603, 4.7µF, 20%, 6.3V, X5R TDK C1608X5R0J475MT

9 13 C26–C36, C40, C56 CAP, 0603, 0.1µF, 10%, 50V, X7R TDK C1608X7R1H104K

10 1 C51 CAP, 0402, 4.7pF, ±0.25pF, 50V, NPO AVX 04025A4R7CAT2A

11 3 C54, C55, C59 CAP, 1206, 22µF, 10%, 6.3V, X5R AVX 12066D226KAT2A

12 9 R9, R10, R46, R48, R54, R56, C62, C64, R75

RES, 0402, 0Ω JUMPER VISHAY CRCW04020000Z0ED

13 1 D1 DIODE, SCHOTTKY SOT-23 AVAGO HSMS-2822

14 3 JP2, JP3, JP4 HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S

15 3 J5, J7, J9 CONN, BNC, SMA 50Ω EDGE-LANCH E.F.JOHNSON, 142-0701-851

16 1 J8 HEADER, 2 × 7, 2mm MOLEX 87331-1420

17 1 L1 IND, 0603, 56µH, 5% MURATA LQP18MN56NG02D

18 3 L2, L3, L4 FERRITE BEAD, 1206 MURATA BLM31PG330SN1L

19 1 L5 IND, 0603 BEAD OPTION

20 0 L6 IND, 0603 OPT OPTION

21 6 RN1, RN2, RN3, RN4, RN5, RN6 RES ARRAY, 33Ω VISHAY CRA04SS08333R0JTD

22 2 R1,R2 RES, 0402, 301Ω, 1%, 1/16W VISHAY CRCW0402301RFKED

23 0 R4, R5, R49, R52, R53, R55, R57, R74

RES, 0402 OPTION OPTION

24 1 R6 RES, 0402, 10kΩ, 5%, 1/16W VISHAY CRCW040210K0JNED

25 1 R7 RES, 0402, 64.9kΩ, 1%, 1/16W VISHAY CRCW040264K9FKED

26 2 R8, R47 RES, 0402, 100kΩ, 1%, 1/16W YAGEO RC0402FR-07100KL

27 4 R14, R33, R34, R35 RES, 0402, 1kΩ, 5%, 1/16W PANASONIC ERJ-2GEJ102X

28 1 R16 RES, 0402, 100Ω, 5%, 1/16W VISHAY CRCW0402100RJNED

29 1 R24 RES, 0402, 100kΩ, 5%, 1/16W VISHAY CRCW0402100KJNED

30 3 R25, R26, R29 RES, 0603, 4.99kΩ, 1%, 1/16W AAC CR16-4991FM

31 3 R36, R44, R45 RES, 0402, 86.6Ω, 1%, 1/16W VISHAY CRCW040286R6FKED

32 2 R40, R39 RES, 0402, 24.9Ω, 1%, 1/16W YAGEO RC0402FR-0724R9FL

33 1 R50 IND, 36nH COILCRAFT 0402CS-36NXJB

34 1 R51 RES, 0402, 301Ω, 1%, 1/16W OPTION OPTION

35 5 TP1, TP2, TP3, TP4, TP5 TURRETS MILLMAX 2501-2-00-80-00-00-07-0

36 1 T1 XFMR, 1:1 MACOM MABA-007159-000000

37 1 T2 XFMR, 1:1 CT M/A-C0M MABAES0060

38 1 T3 XFMR, 1:4 CT COILCRAFT WBC4-1WLB

39 1 U1 IC, 24LC025-I/ST MICROCHIP TECH. 24LC025-I/ST

40 2 U7, U3 IC, BI-DIRECTIONAL INTERFACE FAIRCHILD FXLH42245

8dc1730afa

DEMO MANUAL DC1370A

Schematic Diagram

41 1 U4 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE-1.8

42 1 U5 IC, 8-BIT, I/0 EXPANDER PHILIPS SEMI PCF8574TS/3

43 2 U10, U6 IC, LDO Micropower Regulators LINEAR TECH. LT1763CDE

44 1 U8 IC, ULP INVERTER FAIRCHILD NC7SP14P5X

45 1 U9 IC, EEPROM MICROCHIP TECH. 24LC32A-I/ST

46 3 XJP2, XJP3, XJP4 SHUNT, 2mm SAMTEC 2SN-BK-G

47 4 STANDOFF, SNAP ON KEYSTONE_8831

PartS LiSt

9dc1730afa

DEMO MANUAL DC1370A

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Schematic Diagram

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

GN

D

FA

ST

DA

AC

S B

OA

RD

ID

CIR

CU

ITR

Y

3.5

V -

6V

OX

A2

OX

40

3.1

Ch

an

ge

05

/21

/12

Cla

ren

ce M

.

SC

L

VC

C_

IN

SD

A

VS

S

PA

R/S

ER

EN

AB

LE

PA

R/S

ER

CS

SC

LS

DA

SC

KS

DI

SD

I

CS

SCK

SDI

SD0

D6

D7

D1

D2

D3

D0

D5

D4

CS

SD

IS

D0

D1

1

D9

D1

2

D8

D1

3

D1

0

SD

0

EN

AB

LE

VS

S

SD

A

VC

C_

IN

SC

L

VC

C_

IN

SC

L

SC

L

SD

A

SD

A

VS

S

SC

KC

S

+C

LK

-CL

K

VC

C_

IN SD

AS

CL

VS

S

VD

D

VD

D

VD

D

OV

DD

VD

D

+3

.3V

VD

DV

DD

VD

D

+3

.3V

+3

.3V

+3

.3V

OV

DD

+3

.3V

+3

.3V

OV

DD

OV

DD

VD

D

+3

.3V

OV

DD

+3

.3V

VD

D

VIN

OV

DD

Cu

sto

me

r N

oti

ce

:Lin

ear

Tech

nolo

gy

has

made a

best

eff

ort

to

desi

gn a

cir

cuit

that

meets

cust

om

er-

supplie

d s

peci

ficatio

ns;

how

eve

r, it

rem

ain

s th

e c

ust

om

ers

resp

onsi

bili

ty t

o v

eri

fy p

roper

and r

elia

ble

opera

tion in

the a

ctual a

pplic

atio

n,

Com

ponent

subst

itutio

n a

nd p

rinte

d c

ircu

it board

layo

ut

may

signifi

cantly

aff

ect

cir

cuit

perf

orm

ance

or

relia

bili

ty.

Conta

ct L

inear

Applic

atio

ns

Engin

eeri

ng f

or

ass

ista

nce

.

This

cir

cuit

is p

ropri

eta

ry t

o L

inear

Tech

nolo

gy

and s

upplie

dfo

r use

with

Lin

ear

Tech

nolo

gy

part

s.C

us

tom

er N

oti

ce

:Lin

ear

Tech

nolo

gy

has

made a

best

eff

ort

to

desi

gn a

cir

cuit

that

meets

cust

om

er-

supplie

d s

peci

ficatio

ns;

how

eve

r, it

rem

ain

s th

e c

ust

om

ers

resp

onsi

bili

ty t

o v

eri

fy p

roper

and r

elia

ble

opera

tion in

the a

ctual a

pplic

atio

n,

Com

ponent

subst

itutio

n a

nd p

rinte

d c

ircu

it board

layo

ut

may

signifi

cantly

aff

ect

cir

cuit

perf

orm

ance

or

relia

bili

ty.

Conta

ct L

inear

Applic

atio

ns

Engin

eeri

ng f

or

ass

ista

nce

.

This

cir

cuit

is p

ropri

eta

ry t

o L

inear

Tech

nolo

gy

and s

upplie

dfo

r use

with

Lin

ear

Tech

nolo

gy

part

s.C

us

tom

er N

oti

ce

:Lin

ear

Tech

nolo

gy

has

made a

best

eff

ort

to

desi

gn a

cir

cuit

that

meets

cust

om

er-

supplie

d s

peci

ficatio

ns;

how

eve

r, it

rem

ain

s th

e c

ust

om

ers

resp

onsi

bili

ty t

o v

eri

fy p

roper

and r

elia

ble

opera

tion in

the a

ctual a

pplic

atio

n,

Com

ponent

subst

itutio

n a

nd p

rinte

d c

ircu

it board

layo

ut

may

signifi

cantly

aff

ect

cir

cuit

perf

orm

ance

or

relia

bili

ty.

Conta

ct L

inear

Applic

atio

ns

Engin

eeri

ng f

or

ass

ista

nce

.

This

cir

cuit

is p

ropri

eta

ry t

o L

inear

Tech

nolo

gy

and s

upplie

dfo

r use

with

Lin

ear

Tech

nolo

gy

part

s.R

EV

ISIO

N H

IST

OR

Y

DE

SC

RIP

TIO

ND

AT

EA

PP

RO

VE

DE

CO

RE

V

PR

OT

O3

08

/20

/08

RE

VIS

ION

HIS

TO

RY

DE

SC

RIP

TIO

ND

AT

EA

PP

RO

VE

DE

CO

RE

V

PR

OT

O3

08

/20

/08

RE

VIS

ION

HIS

TO

RY

DE

SC

RIP

TIO

ND

AT

EA

PP

RO

VE

DE

CO

RE

V

PR

OT

O3

08

/20

/08

SIZ

E

SC

AL

E:C

AG

E C

OD

ED

WG

NO

RE

V

SH

EE

TO

FF

ILE

NA

ME

:

TIT

LE

CO

NT

RA

CT

NO

.

AP

PR

OV

AL

SD

AT

E

DR

AW

N

CH

EC

KE

D

AP

PR

OV

ED

EN

GIN

EE

R

DE

SIG

NE

R

TE

CH

NO

LO

GY

16

30

McC

art

hy

Blv

d.

Milp

itas,

CA

95

03

5P

hon

e:

(40

8)4

32

-19

00

Fax:

(4

08

)43

4-0

50

7

3D

C1370A

05/2

2/1

2 0

6:3

0:3

51

2

SC

H,

LT

C2261C

UJ,

HIG

H S

PE

ED

LO

W P

OW

ER

13

70

A-3

.DS

NN

ON

E

MI

10

/31

/07

125M

SP

S A

DC

FA

MIL

Y,

CM

OS

SIZ

E

SC

AL

E:C

AG

E C

OD

ED

WG

NO

RE

V

SH

EE

TO

FF

ILE

NA

ME

:

TIT

LE

CO

NT

RA

CT

NO

.

AP

PR

OV

AL

SD

AT

E

DR

AW

N

CH

EC

KE

D

AP

PR

OV

ED

EN

GIN

EE

R

DE

SIG

NE

R

TE

CH

NO

LO

GY

16

30

McC

art

hy

Blv

d.

Milp

itas,

CA

95

03

5P

hon

e:

(40

8)4

32

-19

00

Fax:

(4

08

)43

4-0

50

7

3D

C1370A

05/2

2/1

2 0

6:3

0:3

51

2

SC

H,

LT

C2261C

UJ,

HIG

H S

PE

ED

LO

W P

OW

ER

13

70

A-3

.DS

NN

ON

E

MI

10

/31

/07

125M

SP

S A

DC

FA

MIL

Y,

CM

OS

SIZ

E

SC

AL

E:C

AG

E C

OD

ED

WG

NO

RE

V

SH

EE

TO

FF

ILE

NA

ME

:

TIT

LE

CO

NT

RA

CT

NO

.

AP

PR

OV

AL

SD

AT

E

DR

AW

N

CH

EC

KE

D

AP

PR

OV

ED

EN

GIN

EE

R

DE

SIG

NE

R

TE

CH

NO

LO

GY

16

30

McC

art

hy

Blv

d.

Milp

itas,

CA

95

03

5P

hon

e:

(40

8)4

32

-19

00

Fax:

(4

08

)43

4-0

50

7

3D

C1370A

05/2

2/1

2 0

6:3

0:3

51

2

SC

H,

LT

C2261C

UJ,

HIG

H S

PE

ED

LO

W P

OW

ER

13

70

A-3

.DS

NN

ON

E

MI

10

/31

/07

125M

SP

S A

DC

FA

MIL

Y,

CM

OS

U1

24

LC

02

5-I

/ST

U1

24

LC

02

5-I

/ST

A0

1

A1

2

A2

3

A3

4S

DA

5S

CL

6W

P7

VC

C8

C3

6

0.1

uF

C3

6

0.1

uF

U6

LT

17

63

CD

EU

6L

T1

76

3C

DE

GN

D7

SH

DN

8

SE

NS

E5

BY

P6

NC

9

IN1

0O

UT

2

NC

4

IN1

1O

UT

3

NC

12

NC

1

C1

7

1u

F

C1

7

1u

F

C1

4

1u

F

C1

4

1u

F

C2

0.0

1u

FC

20

.01

uF

C6

0.0

1u

F

C6

0.0

1u

F

12

JP4

SH

DN

EN

DIS

JP4

SH

DN

EN

DIS

1 32

RN

43

3R

N4

33

1 2 3 4

8 7 6 5

R5

OP

TR

5O

PT

C1

20

.1u

FC

12

0.1

uF

C3

0.0

1u

F

C3

0.0

1u

F

12

T2

MA

BA

ES

00

60

T2

MA

BA

ES

00

60

R5

03

6n

HR

50

36

nH

R2

94

.99

K1

%R

29

4.9

9K

1%

R7

64

.9K

1%

R7

64

.9K

1%

C2

70

.1u

FC

27

0.1

uF

RN

53

3R

N5

33

1 2 3 4

8 7 6 5

R2

64

.99

K1

%R

26

4.9

9K

1%

R1

41

KR

14

1K

R5

2

OP

T

R5

2

OP

T

T1

MA

BA

-00

71

59

-00

00

00

T1

MA

BA

-00

71

59

-00

00

00

R3

31

KR

33

1K

TP

4T

P4

RN

33

3R

N3

33

1 2 3 4

8 7 6 5

R5

1O

PT

R5

1O

PT

C2

6

0.1

uF

C2

6

0.1

uF

C2

0

1u

F

C2

0

1u

F

U8 N

C7

SP

14

P5

X

U8 N

C7

SP

14

P5

X

24

5 3

C3

2

0.1

uF

C3

2

0.1

uF

C6

4

C6

4

12

T3

WB

C4

-1W

LT

3W

BC

4-1

WL

C3

9

0.0

1u

F

C3

9

0.0

1u

F

C5

60

.1u

FC

56

0.1

uF

J7

EN

C+

J7

EN

C+

C2

8

0.1

uF

C2

8

0.1

uF

C6

10

.01

uF

C6

10

.01

uF

12

R3

9

1%

24

.9R

39

1%

24

.9

C3

1

0.1

uF

C3

1

0.1

uF

R3

68

6.6

1%

R3

68

6.6

1%

C3

4

0.1

uF

C3

4

0.1

uF

R5

60

R5

60

P1

ED

GE

-CO

N-1

00

P1

ED

GE

-CO

N-1

00

2 4 6 81

01

21

41

61

82

02

22

42

62

83

03

23

43

63

84

04

24

44

64

85

05

25

45

65

86

06

26

46

66

87

07

27

47

67

88

08

28

48

68

89

09

29

49

69

81

00

1 3 5 7 9 11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

81

83

85

87

89

91

93

95

97

99

R7

4O

PT

1%

R7

4O

PT

1%

C5

2

0.0

1u

F

C5

2

0.0

1u

F

C3

3

0.1

uF

C3

3

0.1

uF

C1

8

0.1

uF

C1

8

0.1

uF

D1

HS

MS

-28

22

D1

HS

MS

-28

22

12

3

L5

BE

AD

L5

BE

AD

C2

1

0.1

uF

C2

1

0.1

uF

C9

8.2

pF

C9

8.2

pF

C6

0

0.0

1u

F

C6

0

0.0

1u

F

12

C6

3

0.0

1u

F

C6

3

0.0

1u

F

12

R4

OP

TR

4O

PT

C2

4

4.7

uF

C2

4

4.7

uF

R8

10

0K

1%

R8

10

0K

1%

C5

5

22

uF

C5

5

22

uF

R4

71

00

K1

%R

47

10

0K

1%

C6

2

C6

2

12

C5

9

22

uF

C5

9

22

uF

C2

2

1u

F

C2

2

1u

FC

37

0.1

uF

C3

7

0.1

uF

U3

FX

LH

42

24

5U

3F

XL

H4

22

45

B1

20

B2

19

A7

10

A2

5A

14

A0

3

TR

2

OE

22

B7

14

VCCA1

B6

15

A3

6

VCCB24

VCCB23

GND11

GND12

GND13

A6

9

B3

18

B0

21

B5

16

B4

17

A5

8A

47

GND25

R9

0R

90

R4

0

1%

24

.9R

40

1%

24

.9

R3

51

KR

35

1K

L4

BE

AD

L4

BE

AD

R1

30

11

%

R1

30

11

%

RN

63

3R

N6

33

1 2 3 4

8 7 6 5

R5

40

R5

40

RN

13

3R

N1

33

1 2 3 4

8 7 6 5

R1

61

00

R1

61

00

TP

3

GN

DT

P3

GN

D

L6

OP

T

L6

OP

T

R5

5O

PT

R5

5O

PT

TP

5

GN

DT

P5

GN

D

R4

48

6.6

1%

R4

48

6.6

1%

R2

30

11

%

R2

30

11

%

C3

0

0.1

uF

C3

0

0.1

uF

J8

J8

5V

2

SC

K/S

CL

4C

S6

GND8

EE

VC

C1

0

EE

GN

D1

2

NC

14

VU

NR

EG

1

GND3

MIS

O5

MO

SI/

SD

A7

EE

SD

A9

EE

SC

L1

1

GND13

C1

5

0.1

uF

C1

5

0.1

uF

U1

0L

T1

76

3C

DE

U1

0L

T1

76

3C

DE

GN

D7

SH

DN

8

SE

NS

E5

BY

P6

NC

9

IN1

0O

UT

2

NC

4

IN1

1O

UT

3

NC

12

NC

1

C7

0.0

1u

FC

70

.01

uF

12

U2

*U

2*

D1132

AIN

+1

AIN

-2

GN

D3

RE

FH

4

RE

FH

5

RE

FL

6

RE

FL

7

PA

R/S

ER

8

VD

D9

VD

D1

0

ENC+11

ENC-12

CS13

SCK14

SDI15

SDO16

D017

D118

D219

D320

D4

21

D5

22

D6

23

D7

24

OG

ND

25

OV

DD

26

CL

KO

UT

-2

7

CL

KO

UT

+2

8

D8

29

D9

30

D1031

D1233

D1334

OF+36

OF-35

VCM37

VREF38

SENSE39

VDD40

GND41

C2

3

1u

F

C2

3

1u

F

C5

1

4.7

pF

C5

1

4.7

pF

R5

3O

PT

R5

3O

PT

C1

9

0.1

uF

C1

9

0.1

uF

R5

7O

PT

R5

7O

PT

C3

8

0.0

1u

F

C3

8

0.0

1u

F

L1

56

uH

L1

56

uH

R2

41

00

KR

24

10

0K

C5

3

0.0

1u

F

C5

3

0.0

1u

F

R4

60

R4

60

C5

4

22

uF

C5

4

22

uF

J5

AIN

+J5

AIN

+

C1

3

1u

F

C1

3

1u

F

L3

BE

AD

L3

BE

AD

R2

54

.99

K1

%R

25

4.9

9K

1%

RN

23

3R

N2

33

1 2 3 4

8 7 6 5

C4

0

0.1

uF

C4

0

0.1

uF

U4

LT

17

63

CD

E-1

.8U

4L

T1

76

3C

DE

-1.8

GN

D7

SH

DN

8

SE

NS

E5

BY

P6

NC

9

IN1

0O

UT

2

NC

4

IN1

1O

UT

3

NC

12

NC

1

R3

41

KR

34

1K

J9

EN

C-

J9

EN

C-

U5

PC

F8

57

4T

S/3

U5

PC

F8

57

4T

S/3

P0

10

P1

11

P2

12

P3

14

SD

A4

P4

16

P5

17

P6

19

P7

20

GND15

SC

L2

INT

1

VDD5

A0

6

A1

7

A2

9

NC

8N

C3

NC

13

NC

18

R6

10

KR

61

0K

C1

OP

T

C1

OP

T

12

U7

FX

LH

42

24

5U

7F

XL

H4

22

45

B1

20

B2

19

A7

10

A2

5A

14

A0

3

TR

2

OE

22

B7

14

VCCA1

B6

15

A3

6

VCCB24

VCCB23

GND11

GND12

GND13

A6

9

B3

18

B0

21

B5

16

B4

17

A5

8A

47

GND25

U9

24

LC

32

A-I

/ST

U9

24

LC

32

A-I

/ST

A0

1

A1

2

A2

3

A3

4S

DA

5S

CL

6W

P7

VC

C8

R4

58

6.6

1%

R4

58

6.6

1%

TP

2

V+

TP

2

V+

JP2

PA

R

SE

R

PA

R/S

ER

JP2

PA

R

SE

R

PA

R/S

ER1 32

C5

8

0.0

1u

F

C5

8

0.0

1u

FR4

9

OP

T

R4

9

OP

T

C1

08

.2pF

C1

08

.2pF

R4

80

R4

80

R7

50 1

%

R7

50 1

%

JP3

DU

TY

CY

CLE

ST

AB

.

EN

DIS

JP3

DU

TY

CY

CLE

ST

AB

.

EN

DIS

1 32

C3

5

0.1

uF

C3

5

0.1

uF

L2

BE

AD

L2

BE

AD

R1

00

R1

00

C5

7

1u

F

C5

7

1u

F

TP

1

EX

T R

EF

TP

1

EX

T R

EF

C2

9

0.1

uF

C2

9

0.1

uF

10dc1730afa

DEMO MANUAL DC1370A

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2012

LT 0712 REV A • PRINTED IN USA

DEMONSTRATION BOARD IMPORTANT NOTICE

Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:

This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.

If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.

The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).

No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.

LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.

Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.

This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-tion engineer.

Mailing Address:

Linear Technology

1630 McCarthy Blvd.

Milpitas, CA 95035

Copyright © 2004, Linear Technology Corporation

performance summary (ta - analog.com · 2 dc1730afa demo manual dc1370a quick start procedure...

Documents