Phase 1 – Lecture – 2/25/2013

Background

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Background

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Design Process

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1. Identify a problem and define solution requirements

2. Break problem into smaller pieces

3. Research all possible solutions

4. Design all pieces to solution

5. Prove functionality of each piece separately

6. Integrate all pieces into working unit

Process

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Research

Determine components used for each individual stage of our Pipelined CPU

Transition components to be used with other team’s stages of our Pipelined CPUWhat are Reg Files?What is Pipelining?

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Pipelining

6Computer Organization and Design, 4th Ed, D. A. Patterson and J. L. Hennessey

Pipelining Our CPU

Stage Instruction For

IF Instruction fetch from memory

all

ID Instruction decode & register read

Decode for all

EX Execute operation or calculate address

All but j

MEM Access memory operand

lw, sw

WB Write result back to register

lw, R-type

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Our CPU

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Front EndThe United States Postal Service

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Research - Roles Park Lamerton – Lead Engineer Nik Marinov – Intra Team Relations Taylor Foster – Team Worker Kelle McCan – Wiki Specialist Melissa Allee - Historian

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Research - Timeline

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Front End

Collect the mail. Fetch instruction from memory.

Sort the mail. Decode instruction. Distribute data to desired locations.

Process replies. Write back to destination register.

Front end mimics a mailing service

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Instruction Fetch

PC tells MEMORY what instruction to fetch.

PC controlled by two multiplexers.

One instruction fetched at a time.

Collecting the Mail

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Instruction Encoding

OPCODE RS RT RD SHAMT FUNCT

OPCODE RS RTIMMEDIATE

(offset, int, bit sequence)

32 26 21 16 0

OPCODE JUMP ADDRESS

32 26 0

32 26 21 16 11 6 0

R-TYPE

I-TYPE

J-TYPE

Types of instructions on the MIPS processor

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Instruction DecodeSort the mail

Distribute data to proper locations.

Sign or Zero extend immediate value.

Forward register data to execution.

Write back computed results into desired register.

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Register File Read Data

Registers contain previously written or default values.

Mux forwards data based on the 5-bit register address.

All logic operations are performed on the rising edge of clock.

Sort the mail

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Register File Write Back

Decode write back address.

Wait for control bit. Write data to

destination register. All logic operations are

performed on the falling edge of clock.

Process replies

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ExecutionThe Executives

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The Team

Michael Bowman – Lead Engineer Laly Vang – Wiki Specialist Matt Goranson – Intra Team Relations Darryle Parker – Intra Team Relations Matthew Horton – Report Compiler Austin O’Neil – Historian

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Phase 1 Schedule

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Exposition

Responsible for instruction execution and address calculation

Topics: ALU Branch/Jump

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Branch Logic

Why?

What?

Where?

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Branch Logic

BEQ

BNE

Opcode Rs Rt Address/Immediate

6 bits 5 bits 5 bits 16 bits

0001 00 xxxxx xxxxx xxxx xxxx xxxx

Opcode Rs Rt Address/Immediate

6 bits 5 bits 5 bits 16 bits

0001 01 xxxxx xxxxx xxxx xxxx xxxx

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Branch Logic

Depends on 3 signals Zero BNE Control BEQ Control

PC + 4 is the default case (No branching/jumping)

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Jump Register

It can take you places…

Opcode Rs Rt Rd Shamt Function

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

0000 0 xxxxx 00000 00000 00000 001000

R-type

.org 0x1000000

here:lui $t0 0xdeadori $t0 $t0 0xbeefjr $t0nop

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Jump… and Link Register

Hey! Listen!

Go places… and remember where we were (sort of).

Opcode Rs Rt Rd Shamt Function

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

0000 0 xxxxx 00000 xxxxx 00000 001001

R-type

.org 0x1000000

here:li $t0 joyjalr $ra $t0nop

done:j done

joy:jr $ra

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Jump and Link Register

Logic Required Jump control signal – allows a jump Jump register control – allows a jump from register New address (register value) – where we’re going Link control signal – pass a linked address to a register

Resultants New PC address – where we’re going PC control signal – allows update of PC Next instruction address (PC+4) for write back – the linked

address

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Jump

Very much like Jump Register, only we’re jumping to an immediate

But we’re limited. Instructions are 32 bits with the most significant six bits being the operation code. We’ve only got 26 bits to work with, but we can use up to 28. First two bits 0 next 26 bits from the jump address field and upper

four bits from the old PC value

Jump logic Jump Immediate – allows an immediate jump to a new location Value from register – the new address Jump Control – to allow a jump

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Jump and Link

Similar to JALR but uses the same address scheme used in Jump

Saves address for future use

Jump logic Jump Immediate – allows an immediate jump to a new location Jump Register Control Signal – allows register value to be taken Value from register – the new address Link Control Signal – to pass a linked address to a register

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ALU Main math unit

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Exposition: ALU

“Arithmetic and Logic Unit” Performs arithmetic and logical operations. Does any calculations necessary to execute an instruction

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Encoding

Operation Encoding Sub

ADD 0000 0

SUB 0000 1

SLT 0001 1

SLTU 0010 1

AND 0011 0

NOR 0100 0

OR 0101 0

SRL 0110 0

SLL 0111 0

LUI 1000 0

MULLO 1001 0

MULHI 1010 0

5-bits: 4-bit encoding with extra Sub bit12 Operations

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Adder/SubtractorOperation Encoding Sub

ADD 0000 0

SUB 0000 1

ADD

Result = Op1 + Op2

SUB

Result = Op1 - Op2 = Op1 + (!Op2 + 1) = (Op1 +!Op2) + 1

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SLT

Easy

SLTU

Similar, but a caveat

SLT/SLTU

Operation Encoding

Sub

SLT 0001 1

SLTU 0010 1

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Simple LogicOperation Encoding Sub

AND 0011 0

NOR 0100 0

OR 0101 0

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Logical ShiftsOperation Encoding Sub

SRL 0110 0

SLL 0111 0

SLL SRL

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LUIOperation Encoding Sub

LUI 1000 0

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MULLO/MULHI

Operation Encoding Sub

MULLO 1001 0

MULHI 1010 0

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ControlsControlling your life, everyday.

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The Team Kory Teague – Lead Engineer Kyle Lawler – Wiki Specialist Andres Vega – Intra Team Relations Bryan Rogers – Team Worker Michael Oltmanns - Historian

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Responsibilities Manage the Control Path

All non-hazard control logic Memory Stage Writeback Stage

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Processor Design

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Control Signals

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Declared Signals

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Signal Definitions

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X ≡ 0 on all signals except SE, where X ≡ 1Research47

Control Unit Design

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ALUControl Unit Design

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MEM and WB

Provided Allow for data flow MemRead, MemWrite LW, data first appears in

MEM Requires stall Hazards

Writes to Reg File MemToReg, RegWrite

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HAZARDSThe Hazarding

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Team Introduction Spencer Hood – Lead Engineer Jessie Monterroso – Wiki Specialist Zach Smith Max Jeter – Report Compilations Evan Novotny

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IntroductionOne down side of the pipeline is hazardsIf hazards aren’t properly handled then the processor will behave in unexpected ways and can lower throughput

There are three types of hazards that will be covered in this presentation

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Types of HazardsData HazardsControl HazardsStructural Hazards

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Data HazardsRAR (Read after Read)RAW (Read after Write)WAR (Write after Read)WAW (Write after Write)RAW is the only one of the above hazards that effects the MIPS pipeline

Load use

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Example of RAW Hazard

ADD $t0, $t1, $t2SUB $t3, $t0, $t4

Register $t0 is used in the instruction immediately after it is written to

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Solution for RAW Hazard

Forwarding

http://cs-alb-pc3.massey.ac.nz/notes/59304/Image168.gif

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Example of Load use Hazard

lw $t0, 4($t1)addiu $t2, $t0, 0x0badbeefMemory is the fourth stage of the pipeline

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Solution for Load use Hazard Stall the pipeline

http://upload.wikimedia.org/wikipedia/commons/thumb/d/d0/Data_Forwarding_%28Two_Stage%29.svg/370px-Data_Forwarding_%28Two_Stage%29.svg.png

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Control Hazards

Conditional BranchingBranch predictionAssume branch is always takenWhen its not taken flush the pipeline

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Questions?