phase change memory: an architecture and systems...

Phase Change MemoryAn Architecture and Systems Perspective

Benjamin C. LeeStanford University

[email protected]

Fall 2010, Assistant Professor @ Duke University

Benjamin C. Lee 1

Memory Scaling◦ ⇑ density, capacity; ⇓ cost-capability ratio

◦ Emerging challenges for prevalent technologies

“Process integration, devices, and structures,” ITRS 2009.

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Memory in Transition

• Charge Memory◦ Write data by capturing charge Q◦ Read data by detecting voltage V◦ Examples: Flash, DRAM

• Resistive Memory◦ Write data by pulsing current dQ/dt◦ Read data by detecting resistance R◦ Examples: PCM, STT-MRAM, memristor

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Limits of Charge Memory

◦ Difficult charge placement and control

◦ Flash: floating gate charge

◦ DRAM: capacitor charge, transistor leakage

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Towards Resistive Memory

• PCM◦ Inject current to change material phase◦ Resistance determined by phase

• STT-MRAM◦ Inject current to change magnet polarity◦ Resistance determined by polarity

• Memristors◦ Inject current to change atomic structure◦ Resistance determined by atom distn

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Benefits of Resistive Memory

• Scalable◦ Program cell with scalable current◦ Map resistance to logical state

• Non-Volatile◦ Alter structure of storage element◦ Incur activation cost to alter properties

• Competitive◦ Achieve viable latency, power, endurance◦ Scale to improve performance metrics

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TechnologyBenjamin Lee, Engin Ipek, Onur Mutlu, Doug Burger. “Architecting phase change

memory as a scalable DRAM alternative.” ISCA 2009.

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Phase Change Memory

◦ Store data within phase change material

◦ Set phase via current pulse

◦ Detect phase via resistance (amorphous/crystalline)

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PCM Scalability

◦ Program with current pulses, which scale linearly

◦ PCM demonstration at 30nm, DRAM roadmap to 40nm

[1] Raoux et al., IBM J Res & Dev 2008; [2] Lai, IEDM 2003; [3] Pirovano et al., IEDM 2003.

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PCM Non-Volatility

• Joule Effect◦ Program with current pulses◦ Melt material by heating material (e.g., 650 ◦C)◦ Cool material to desired phase

• Activation Cost◦ Isolate thermal effects to target cell◦ Retain data for >10 years at 85 ◦C

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Technology Parameters

◦ Survey prototypes from 2003-2008 (ITRS, IEDM, VLSI, ISSCC)

◦ Derive PCM parameters for F=90nm

• Cell Size◦ 9-12F2 using BJT◦ 1.5× DRAM, 2-3× NAND

• Endurance◦ 108 writes per cell◦ 10−8× DRAM, 103× NAND

[1] Lee et al., ISCA 2009; [2] Russo, Workshop Emerging Memory Technologies 2010

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Technology Parameters

◦ Survey prototypes from 2003-2008 (ITRS, IEDM, VLSI, ISSCC)

◦ Derive PCM parameters for F=90nm

• Read Latency◦ 50 ns Rd◦ 4× DRAM, 10−3× NAND

• Write Bandwidth◦ 5-10 MB/s◦ 0.1× DRAM, 1.0× NAND

• Dynamic Energy◦ 40µA Rd, 150µA Wr◦ 2-43× DRAM, 1.0× NAND

[1] Lee et al. ISCA 2009; [2] Russo, Workshop Emerging Memory Technologies 2010

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PCM Comparison

• vs. Flash◦ Advantage in endurance, performance◦ Comparable in energy◦ Scalable Flash alternative

• vs. DRAM◦ Disadvantage in endurance, performance, energy◦ Within competitive range of DRAM◦ Scalable DRAM alternative

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PCM as DRAM Alternative

◦ Deploy PCM on memory bus

◦ Begin by co-locating PCM, DRAM

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Price of Scalability

◦ Replace DRAM with PCM in present architectures

◦ 1.6× delay, 2.2× energy, 500-hour lifetime

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Architecture and ScalabilityBenjamin Lee, Engin Ipek, Onur Mutlu, Doug Burger. “Architecting phase change

memory as a scalable DRAM alternative.” ISCA 2009.

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Architecture Objectives

• DRAM-Competitive◦ Reorganize row buffer to mitigate delay, energy◦ Implement partial writes to mitigate wear mechanism

• Area-Efficient◦ Minimize disruption to density trends◦ Impacts row buffer organization

• Complexity-Effective◦ Encourage adoption with modest mechanisms◦ Impacts partial writes

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Buffer Organization

• On-Chip Buffers◦ Use DRAM-like buffer and interface◦ Evict modified rows into array

• Narrow Rows◦ Reduce write energy ∝ buffer width◦ Reduce peripheral circuitry, associated area

• Multiple Rows◦ Reduce eviction frequency◦ Improve locality, write coalescing

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Buffer Area Strategy

◦ Narrow rows :: fewer expensive S/A’s (44T)

◦ Multiple rows :: additional inexpensive latches (8T)

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Buffering and Locality

◦ Read locality: number of array reads

◦ Write coalescing: number of array writes per buffer write

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Buffer Design Space◦ Derive DRAM, PCM area model

◦ Explore space of area-neutral buffer designs

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Wear Reduction

• Wear Mechanism◦ Writes induce phase change at 650 ◦C◦ Contacts degrade from thermal expansion/contraction◦ Current injection is less reliable after 1E+08 writes

• Partial Writes◦ Reduce writes to PCM array◦ Write only stored lines (64B), words (4B)◦ Add cache line state with 0.2%, 3.1% overhead

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Partial Writes◦ Derive PCM lifetime model

◦ Quantify eliminated writes during buffer eviction

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Scalable Performance

◦ 1.2× delay, 1.0× energy, 5.6-year lifetime

◦ Scaling improves energy, endurance

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Systems and Non-VolatilityJeremy Condit, Edmund Nightingale, Christopher Frost, Engin Ipek, Benjamin Lee,

Doug Burger, Derrick Coetzee. “Better I/O through byte-addressable, persistent

memory.” SOSP 2009.

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Storage Systems

◦ Persistent data in slow, non-volatile memory

◦ Buffered data in fast, volatile memory

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Storage System Trade-offs

• Design Objectives◦ Safety :: security against crashes◦ Consistency :: accurate description of file state◦ Performance :: buffering in volatile memory

• Byte-addressable Persistence (BPRAM)◦ Narrows gap between volatile/non-volatile memory◦ Byte-addressable like DRAM◦ Persistent like disk, Flash

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Byte-addressable Persistent File System (BPFS)

• Safety◦ Use PCM as DRAM alternative◦ Reflect writes to PCM in O(ms), not O(s)

• Consistency◦ Enforce atomicity, ordering in hardware◦ Support shadow paging, copy-on-write

• Performance◦ Exploit byte-addressability for small, in-place writes◦ Propose short-circuit shadow paging

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Tree-Based File System

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File System (FS) Consistency

• Computer Crash◦ Update to FS may require multiple writes◦ Crash between writes leaves FS invalid◦ State of files not as described by FS

• Consistency Checker◦ Traverse FS◦ Compares directory structure, data blocks◦ Depends on allocator, free-space manager

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Disks & Journaling

◦ Writes to journal before to file system

◦ Requires twice the writes

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Disks & Shadow Paging

◦ Copy-on-writes up to file system root

◦ Incurs copying overhead

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PCM & Short-Circuit Shadow Paging (1)

◦ Exploit PCM byte-addressability

◦ Write in-place when possible (e.g., 64b updates)

◦ Ex: In-place write

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◦ Ex: In-place append

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◦ Ex: Partial copy-on-write

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Hardware Support for Atomicity

• Volatile Buffers◦ PCM row buffers are volatile 8T latches◦ BPFS updates 64b pointer to buffer◦ BPFS requires atomic 64b eviction to array

• Atomicity◦ PCM writes atomically into memory array◦ PCM writes complete in O(100ns)◦ Capacitors guard against power failures

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Hardware Support for Ordering

• Modern Performance Optimizations◦ Controller for write-back caches re-order stores◦ Controller for memory bus re-orders transactions

• Ordering◦ Epochs define barrier-delimited BPFS writes◦ Copy-on-write updates may be re-ordered◦ Pointer update must follow barrier

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BPFS Evaluation

◦ NTFS-Disk: baseline

◦ NTFS-RAM: current FS on DRAM, proxy for PCM

◦ BPFS-RAM: proposed FS on DRAM, proxy for PCM

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BPFS Evaluation

◦ Safety: no DRAM buffer

◦ Consistency: shadow paging

◦ Performance: short-circuit shadow paging

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For more information...

• Workshop on Emerging Memory Technologies 2010◦ Survey of emerging memories◦ www.stanford.edu/∼bcclee/emt.html

• Phase Change Memory◦ Lee et al., “Architecting phase change memory as a

scalable DRAM alternative.” ISCA 2009.◦ Condit et al., “Better I/O through byte-addressable,

persistent memory.” SOSP 2009.

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Conclusions

• Scaling Challenges◦ Fundamental limits in charge memory◦ Transition towards resistive memory

• Architecture and Scalability◦ PCM position as Flash replacement◦ PCM viable as DRAM alternative◦ Architect buffers, partial writes

• Systems and Non-Volatility◦ Apply non-volatility for new capabilities◦ Change storage system trade-offs◦ Improve durability, performance

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Phase Change MemoryAn Architecture and Systems Perspective

Benjamin C. LeeStanford University

[email protected]

Fall 2010, Assistant Professor @ Duke University

Benjamin C. Lee 42

phase change memory: an architecture and systems...

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