Modelling and Characterisationof the SOI MOSFET for MMIC Applications

Renaud GILLONJury

Prof. P. Sobieski (President)Prof. D. Vanhoenacker (Promoteur)Prof. A. Vander VorstProf. J.-P. ColingeProf. P. JespersDr Ch. Raynaud

These presentee en vue del’obtention du grade dedocteur en Sciences Appliquees

Juin 1998

UNIVERSITE CATHOLIQUE DE LOUVAINLABORATOIRE D’HYPERFREQUENCES

Louvain-la-Neuve

Ce doctorat n’aurait pu exister sans l’etroite collaboration entre les Lab-oratoires d’Hyperfrequences et de Microelectronique, mise sur pied par lesprofesseurs Danielle Vanhoenacker et Jean-Pierre Colinge. Je leur suis pro-fondement reconnaissant d’avoir cree cet environnement de recherche riche etstimulant. Merci, egalement, au professeur Andre Vander Vorst, responsable del’unite, pour la qualite du cadre de travail au Laboratoire d’Hyperfrequences.

La trame de cette these est tissee de nombreux avis et conseils recueil-lis aupres des professeurs Danielle Vanhoenacker, Jean-Pierre Colinge, AndreVander Vorst, Paul Jespers et Fernand Van de Wiele. Je tiens a leur temoignerici ma gratitude et a rendre hommage a leur savoir-faire. Plusieurs resultatspresentes dans cet ouvrage sont issus de discussions fructueuses avec des col-legues. En particulier, avec Jean-Pierre Raskin pour la modelisation et les ex-tractions, avec Jian Chen pour les aspects technologiques, avec Isabelle Huynenpour les lignes et les etalonnages, avec Jean-Paul Eggermont pour les amplifi-cateurs operationnels, et avec Denis Flandre, Luis Ferreira et Benjamin Inıguezpour le modele “charge-sheet”. Je les remercie tous chaleureuseme nt pour leurdisponibilite et leur aide.

Aux membres du Jury, qui ont consacre leur temps a la lecture des manu-scrits et ont contribue a en ameliorer la qualite par leur remarques, je souhaiteexprimer ma reconnaissance. A Danielle Vanhoenacker tout specialement, quien tant que promoteur, m’a judicieusement guide et abondamment encourage.

Les travaux de recherche associes a cette these ont necessites de nombreusesrealisations techniques. Merci a Andre Crahay et a toute l’equipe de fabrica-tion de circuits integres ; a Pierrot Loumaye pour l’encapsulation des puces ; aRobert Platterborze pour les fabrications de circuits imprimes et pour toutes lesameliorations apportees aux stations de caracterisation ; a Hubert Sablain pourson aide minutieuse lors des mesures sur tranche ; a Francois-Michel Plennevauxet Christian Renaux qui ont repris le fardeau de la caracterisation. Merci, enfin,a tous les ingenieurs, techniciens et informaticiens qui ont apporte le soutienindispensable a mes travaux.

Ce travail a beneficie du soutien financier de la Region Wallonne, de laCommunaute Francaise par son programme “d’Actions Concertees” et de laCommunaute Europeenne grace au programme “ESPRIT”.

Je remercie affectueusement mon epouse pour sa patience et son couragelors des difficiles periodes d’intense redaction.

Je dedie cet ouvrage a ceux qui m’ont transmis leur gout de la technique.

Renaud

Preface

Silicon-on-insulator technology has been under development for more thanthree decades. Interest in thin-film SOI for high performance applicationsdates back from the late 70’s, when several commercial companies undertookresearch efforts in this area. SOI remained an exotic technology, confined inniche applications for some time, until recently, when the quest for low-voltageperformance driven by the boom in portable electronics and mobile communi-cations brought it under the spotlight. Thin-film SOI MOSFET’s offer indeedinteresting low-voltage performances, higher speed and increased integrationdensity, all with simpler processing than bulk silicon MOSFET’s of compa-rable size, [1]. Many recent realisations of logic circuits, memories, and RFcircuits, [2], have confirmed both the advantages and the viability of thin-filmSOI circuits, even in the case of very large systems.

To support the development of thin-film SOI circuits, adequate device mod-els must be made available concurrently with the maturation of fabricationprocesses. Several models have already been proposed for thin-film SOI MOS-FET’s, [3,4,5,6,7]. Very few of them have however been tailored to the designof analogue microwave circuits. The majority of these models is indeed targetedat the prediction of quasi-static characteristics, failing to account properly forchannel propagation delays which become significant at microwave frequencies.Some of these models do not meet the strict continuity requirements necessaryfor the non-linear simulation of analogue circuits. None of the existing mod-els deals properly with substrate coupling effects and particularly with theirinfluence on the back gate at high frequencies.

This thesis concerns the development and the validation of a comprehensivemodel of the thin-film SOI n-MOSFET intended for the simulation of analoguecircuits in the microwave domain. To enable model validation at microwavefrequencies, new characterisation techniques and parameter extraction proce-dures are proposed, which will be shown to be accurate and reliable. Finally,the model is used to evaluate the feasibility of microwave SOI MOSFET mixers.

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Preface

The text is structured as follows :

Chapter I : Introduction The global context of this work is presented.The evolution of technology under the impulse of the recent boom in mobiletelecommunications is briefly analysed. Silicon-on-insulator and bulk silicontechnologies are compared in the perspective of this evolution, and the specificadvantages of SOI CMOS technology for low-voltage applications are illus-trated. The main-stream fabrication processes of SOI material are described.Finally, several aspects of characterisation and modelling are discussed.

Chapter II : On-wafer characterisation at microwave frequenciesThe scattering parameters measurement techniques developed in this work aredescribed. The chapter starts with an introduction to the rigorous frameworkwhich forms the foundation of scattering parameters measurements. The cal-ibration procedures of interest to on-wafer characterisation are reviewed, andnew reference impedance determination methods are proposed, which enableto use powerful scattering parameters calibrations directly for the complete de-embedding of devices integrated on any kind of wafer. The new de-embeddingstrategy is shown to be more reliable than the conventional immittance correc-tion approach.

Chapter III : Modelling fully depleted SOI MOSFET’s Several mod-els are developed with the specific needs of analogue microwave circuit designin mind. Such issues as short-channel effects, channel propagation delays, dis-persive behaviour of the interface states and continuity of all characteristics areaddressed. For the intrinsic device, a large-signal current and charge model,a small-signal equivalent circuit model, and a distributed channel model atVDS = 0 are proposed. The picture is completed with a small-signal equivalentcircuit accounting for device parasitics : series resistances, gate-diffusion ca-pacitances, substrate capacitances, etc. Finally, model limitations concerningdevice dimensions, biasing conditions and maximum frequency are discussed.

Chapter IV : Extraction of the SOI MOSFET model parameters Aprogressive extraction strategy is demonstrated which leads to the identifica-tion of the majority of model parameters. All extractions can be formulatedas optimisation problems, which are solved by selective optimisation on themost influencing parameters in order to minimise uncertainty. Original directextraction schemes are proposed as advantageous alternatives, being inherentlyrobust and efficient. The chapter includes numerous comparisons of predictedand measured characteristics, providing confidence in the validity of the newlyintroduced models.

Chapter V : Microwave MOSFET down-conversion mixers The an-alytical current and charge model is used to evaluate the performance of mi-crowave mixer designs based on SOI MOSFET’s. The feasibility of resistiveSOI MOSFET mixers at 2.0 GHz is established by simulations and confirmed

vi

REFERENCES

by measurements performed on basic mixing cells. The implementation of asingle-chip down-conversion stage with image rejection is presented.

References

[1] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI. Boston– Dordrecht – London: Kluwer Academic Publ., 2nd ed., 1997.

[2] S. R. Wilson et al., “TFSOI circuit applications,” in Proc. of the 8th IntlSymp. on SOI technology and devices (S. Cristoloveanu, ed.), vol. 97-23,pp. 359–372, The Electrochemical Society, 1997.

[3] Dept of Electrical Engineering and Computer Sciences, University of Cal-ifornia, Berkeley, BSIM3SOI v1.0 Manual, 1997.

[4] E. Arnold, “Double-charge-sheet model for thin silicon-on-insulator films,”IEEE Trans. on Electron Devices, vol. 43, pp. 2153–2163, Dec. 1996.

[5] B. Inıguez, L. F. Ferreira, B. Gentinne, and D. Flandre, “A physically-based C∞-continuous fully-depleted SOI MOSFET model for analog ap-plications,” IEEE Trans. on Electron Devices, vol. 43, pp. 568–575, Apr.1996.

[6] C. Mallikarjun and K. N. Bhat, “Numerical and charge sheet models forthin-film SOI MOSFET’s,” IEEE Trans. on Electron Devices, vol. 37,pp. 2039–2051, Sept. 1990.

[7] S. Veeraraghavan and J. G. Fossum, “A physical short-channel model forthe thin-film SOI MOSFET applicable to device and circuit CAD,” IEEETrans. on Electron Devices, vol. 35, pp. 1866–1875, Nov. 1988.

vii

Contents

Preface vReferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Main scientific publications xiii

List of abbreviations xvii

I Introduction I-1I.1 RF and microwave monolithic IC’s . . . . . . . . . . . . . . . . I-1

I.1.1 New driving forces . . . . . . . . . . . . . . . . . . . . . I-2I.1.2 Technology directions . . . . . . . . . . . . . . . . . . . I-4

I.2 Competing technologies for emerging RF applications . . . . . I-8I.2.1 Bulk MOSFET’s . . . . . . . . . . . . . . . . . . . . . . I-9I.2.2 Thin-film SOI MOSFET’s . . . . . . . . . . . . . . . . . I-13I.2.3 Bulk bipolar transistors . . . . . . . . . . . . . . . . . . I-14I.2.4 Thin-film lateral bipolar SOI transistors . . . . . . . . I-14I.2.5 Low-voltage systems-on-a-chip, the future of SOI . . . . I-16

I.3 Silicon-on-Insulator substrate technology . . . . . . . . . . . . . I-16I.3.1 Silicon-on-sapphire . . . . . . . . . . . . . . . . . . . . . I-16I.3.2 Separation by Implantation of Oxygen . . . . . . . . . . I-17I.3.3 Wafer-bonding . . . . . . . . . . . . . . . . . . . . . . . I-18I.3.4 The blooming of a SOI era ? . . . . . . . . . . . . . . . . I-19

I.4 Characterisation and modelling of MMIC’s . . . . . . . . . . . I-20I.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-22References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-23

II On-wafer characterisation at microwave frequencies II-1II.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1II.2 Uniform waveguides . . . . . . . . . . . . . . . . . . . . . . . . II-2

II.2.1 Modal electro-magnetic fields . . . . . . . . . . . . . . . II-2II.2.2 Waveguide voltage and current . . . . . . . . . . . . . . II-3

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II.2.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-4II.2.4 Characteristic impedance . . . . . . . . . . . . . . . . . II-4II.2.5 Normalisation of waveguide voltage and current . . . . . II-5II.2.6 Transmission line equivalent circuit . . . . . . . . . . . . II-6

II.3 General waveguide circuit theory . . . . . . . . . . . . . . . . . II-7II.3.1 Travelling wave intensities . . . . . . . . . . . . . . . . . II-7II.3.2 Pseudo-waves . . . . . . . . . . . . . . . . . . . . . . . . II-8II.3.3 Power-waves . . . . . . . . . . . . . . . . . . . . . . . . II-9II.3.4 Load impedance . . . . . . . . . . . . . . . . . . . . . . II-10II.3.5 Scattering matrix for pseudo-waves . . . . . . . . . . . . II-11II.3.6 Transfer matrix . . . . . . . . . . . . . . . . . . . . . . . II-12II.3.7 Immittance matrices . . . . . . . . . . . . . . . . . . . . II-13II.3.8 Change of reference impedance . . . . . . . . . . . . . . II-14

II.4 Measurement set-up . . . . . . . . . . . . . . . . . . . . . . . . II-15II.5 Calibration methods . . . . . . . . . . . . . . . . . . . . . . . . II-17

II.5.1 The transfer-matrix formalism . . . . . . . . . . . . . . II-18II.5.2 SOLT procedure . . . . . . . . . . . . . . . . . . . . . . II-20II.5.3 TAN self-calibration procedures . . . . . . . . . . . . . . II-21

II.6 Reference impedance determination . . . . . . . . . . . . . . . . II-27II.6.1 Propagation constant measurement . . . . . . . . . . . . II-27II.6.2 Load measurement . . . . . . . . . . . . . . . . . . . . . II-28II.6.3 Calibration comparison . . . . . . . . . . . . . . . . . . II-31

II.7 De-embedding strategies . . . . . . . . . . . . . . . . . . . . . . II-34II.7.1 Immittance corrections . . . . . . . . . . . . . . . . . . . II-35II.7.2 In-situ calibration . . . . . . . . . . . . . . . . . . . . . II-36

II.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-37References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-37

IIIModelling fully depleted SOI MOSFET’s III-1III.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-1

III.1.1 The SOI MOSFET structure . . . . . . . . . . . . . . . III-3III.1.2 Operating modes of the generic SOI MOSFET structure III-3III.1.3 Thin-film SOI MOSFET’s . . . . . . . . . . . . . . . . . III-4III.1.4 Splitting the device in intrinsic and extrinsic regions . . III-5III.1.5 Requirements for a good MOSFET model for analogue circuit designIII-5

III.2 Charge-sheet models for the intrinsic device . . . . . . . . . . . III-7III.2.1 Surface potential and charge density equations . . . . . III-8III.2.2 A numerical charge-sheet model . . . . . . . . . . . . . III-12III.2.3 An analytical approximate charge-sheet model . . . . . III-13III.2.4 A dynamic model for the interface traps . . . . . . . . . III-16III.2.5 Short channel effects . . . . . . . . . . . . . . . . . . . . III-17

III.3 Static conduction current . . . . . . . . . . . . . . . . . . . . . III-20III.3.1 Carrier velocity . . . . . . . . . . . . . . . . . . . . . . . III-20III.3.2 Triode operation . . . . . . . . . . . . . . . . . . . . . . III-21III.3.3 Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . III-23III.3.4 Unified model . . . . . . . . . . . . . . . . . . . . . . . . III-28

III.4 Dynamic currents . . . . . . . . . . . . . . . . . . . . . . . . . . III-30

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III.4.1 Surface potential profile . . . . . . . . . . . . . . . . . . III-31III.4.2 Front-gate charge . . . . . . . . . . . . . . . . . . . . . . III-32III.4.3 Back-gate charge . . . . . . . . . . . . . . . . . . . . . . III-34III.4.4 Ward’s channel-charge partitioning scheme . . . . . . . III-34III.4.5 Drain and source charges . . . . . . . . . . . . . . . . . III-35III.4.6 Alternative formulation of the charge model . . . . . . . III-36

III.5 Operation at microwave frequencies . . . . . . . . . . . . . . . . III-38III.5.1 The non-quasi-static small-signal model topology . . . . III-39III.5.2 The distributed channel model at VDS = 0 . . . . . . . . III-41III.5.3 A non-quasi-static large-signal channel model . . . . . . III-44

III.6 Small-signal model for the extrinsic device . . . . . . . . . . . . III-46III.6.1 Diffusion and contact resistances . . . . . . . . . . . . . III-46III.6.2 Parasitic capacitances . . . . . . . . . . . . . . . . . . . III-47III.6.3 Lateral signal distribution in the basic MOSFET cell . . III-50III.6.4 Dedicated model for the common-source configuration . III-53

III.7 Model limitations . . . . . . . . . . . . . . . . . . . . . . . . . . III-55III.7.1 Channel length . . . . . . . . . . . . . . . . . . . . . . . III-55III.7.2 Biasing conditions . . . . . . . . . . . . . . . . . . . . . III-56III.7.3 Scaling rules . . . . . . . . . . . . . . . . . . . . . . . . III-57III.7.4 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . III-57

III.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-58References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III-59

IV Extraction of SOI MOSFET model parameters IV-1IV.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-1IV.2 Substrate resistivity . . . . . . . . . . . . . . . . . . . . . . . . IV-3IV.3 Three-terminal MOSFET model . . . . . . . . . . . . . . . . . IV-3

IV.3.1 Shunt parasitic elements . . . . . . . . . . . . . . . . . . IV-7IV.3.2 Channel length . . . . . . . . . . . . . . . . . . . . . . . IV-12IV.3.3 Series parasitic elements . . . . . . . . . . . . . . . . . IV-16

IV.4 Four-terminal MOSFET model . . . . . . . . . . . . . . . . . . IV-25IV.4.1 Corrections to the shunt parasitic elements . . . . . . . IV-25IV.4.2 Corrections to the series parasitic elements . . . . . . . IV-29

IV.5 Intrinsic MOSFET in the linear operating regime . . . . . . . . IV-32IV.5.1 Determination of the C-V curve from broadband measurementsIV-32IV.5.2 Threshold voltage . . . . . . . . . . . . . . . . . . . . . IV-35IV.5.3 Mobility . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-36IV.5.4 Unified analytical model from depletion to inversion . . IV-38

IV.6 Intrinsic MOSFET in saturation . . . . . . . . . . . . . . . . . IV-40IV.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-44References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IV-44

V Microwave MOSFET downconversion mixers V-1V.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-1V.2 Single FET mixers . . . . . . . . . . . . . . . . . . . . . . . . . V-2

V.2.1 Active mixers . . . . . . . . . . . . . . . . . . . . . . . . V-3V.2.2 Passive mixers . . . . . . . . . . . . . . . . . . . . . . . V-6

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V.2.3 The MOSFET switch . . . . . . . . . . . . . . . . . . . V-7V.3 Balanced mixers . . . . . . . . . . . . . . . . . . . . . . . . . . V-8

V.3.1 The Gilbert cell . . . . . . . . . . . . . . . . . . . . . . . V-9V.3.2 The resistive ring . . . . . . . . . . . . . . . . . . . . . . V-11

V.4 A low-IF down-conversion architecture . . . . . . . . . . . . . . V-13V.4.1 Basic IF cell . . . . . . . . . . . . . . . . . . . . . . . . V-15V.4.2 Quadrature generation . . . . . . . . . . . . . . . . . . . V-15V.4.3 Evaluation chip . . . . . . . . . . . . . . . . . . . . . . . V-17

V.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-17

xii

Main scientific publications

Published

1. J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge,“Accurate SOI MOSFET characterization at microwave frequencies fordevice performance optimisation and analogue modelling,” IEEE Trans.on Electron Devices, May 1998.

2. R. Gillon, J.-P. Colinge, D. Flandre, J.-P. Raskin, and D. Vanhoenacker,“Silicon-on-insulator for RF and microwave low-power applications,” inWorkshop on New Technologies for RF devices, (London Heathrow, U.K.),Microwave Engineering Europe, Miller Freeman, PLC, May 21 1998.

3. J.-P. Raskin, R. Gillon, and G. Dambrine, “Direct extraction of the se-ries equivalent circuit parameters for the small-signal model of SOI MOS-FET’s,” IEEE Microwave and Guided Waves Letters, vol. 7, pp. 408–410,Dec. 1997.

4. I. Huynen, J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge,“Integrated microwave inductors on silicon-on-insulator substrate,” in27th European Microwave Conference Digest, (Jerusalem, Israel), pp. 1008–1013, Sep. 8–12 1997.

5. R. Gillon, J.-P. Raskin, D. Vanhoenacker, J.-P. Colinge, and G. Dambrine,“Characterisation of soi mosfets at microwave frequencies,” in Proceedingsof the 8th Int. Symp. on SOI Technology and Devices (S. Cristoloveanu,ed.), vol. 97-23, (Paris), pp. 149–154, Electrochemical Society, Inc., Aug.31 – Sep. 5 1997.

6. J. Chen, J.-P. Colinge, D. Flandre, R. Gillon, J.-P. Raskin, and D. Van-hoenacker, “Investigation of SALICIDE processes for thin-film SOI mi-crowave applications,” in Proceedings of the 8th Int. Symp. on SOI Tech-nology and Devices (S. Cristoloveanu, ed.), vol. 97-23, (Paris), pp. 98–103,Electrochemical Society, Inc., Aug. 31 – Sep. 5 1997.

xiii

Main scientific publications

7. J. Chen et al., “Comparison of TiSi2 , CoSi2 and NiSi for thin-film silicon-on-insulator applications,” J. Electrochem. Soc., vol. 144, pp. 2437–2442,July 1997.

8. R. Gillon, “Modelisation et caracterisation du transistor MOS SOI auxhyperfrequences en vue de la conception d’une tete de reception pourcommunications mobiles,” in Forum URSI 1996 (P. M. Blondel, ed.),(Faculte Polytechnique de Mons), pp. 40–42, Comite URSI (Belge), Dec.11 1996.

9. J.-P. Colinge, J. Chen, D. Flandre, J.-P. Raskin, R. Gillon, and D. Van-hoenacker, “A low-votlage, low-power microwave SOI MOSFET,” in Proc.IEEE Intl SOI Conf., (Sanibel Island - Fort Myers, Florida), pp. 128–129,Oct. 1-3 1996.

10. I. Huynen, J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Col-inge, “Modelling and measurement of inductive elements on SIMOX sub-strates,” in Proc. IEEE Intl SOI Conf., (Sanibel Island - Fort Myers,Florida), Oct. 1-3 1996.

11. J.-P. Raskin, I. Huynen, R. Gillon, D. Vanhoenacker, and J.-P. Colinge,“An efficient design tool for transmission line on SIMOX substrates,”in Proc. IEEE Intl SOI Conf., (Sanibel Island - Fort Myers, Florida),pp. 28–29, Oct. 1-3 1996.

12. R. Gillon, J.-P. Raskin, D. Vanhoenacker, and J.-P. Colinge, “Determin-ing the reference impedance of on-wafer TLR calibrations on lossy sub-strates,” in 26th European Microwave Conference Digest, (Prague, CzechRepublic), pp. 170–173, Sep. 9–12 1996.

13. J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, “Directextraction method of SOI MOSFET transistor’s parameters,” in Proc.of the 7th Intl Symp on SOI Technology and Devices, vol. 96-3, (LosAngeles), pp. 225–229, Electrochemical Society, Inc., May 5–10 1996.

14. J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, “Directextraction method of SOI MOSFET transistor’s parameters,” in ICMTSConf. Proc., (Trento, Italy), pp. 191–194, Mar. 26–28 1996.

15. J.-P. Eggermont et al., “A 1.0 GHz operational transconductance ampli-fier in SOI technology,” in Proc. IEEE Int. SOI Conference, (Tucson(Arizona)), pp. 127–128, Oct. 3–5 1995.

16. R. Gillon, J.-P. Raskin, D. Vanhoenacker, and J.-P. Colinge, “Modellingand optimizing the SOI MOSFET in view of MMIC applications,” in25th European Microwave Conference Digest, (Bologna, Italy), pp. 543–547, Sep. 4–7 1995.

17. R. Gillon, J.-P. Raskin, J.-P. Colinge, J. Chen, and D. Vanhoenacker,“Modelling and optimization of the SOI MOSFET in view of MMICapplications,” in Workshop on Si-Processing and High Frequency Devices,(Kista, Sweden), N.U.T.E.K. Consortia, June 15–16 1995.

xiv

18. Z. Zhu, R. Gillon, and A. Vander Vorst, “A new approach to broadbandmatching for p-i-n photodiodes,” Microwave and Optical Technology Let-ters, vol. 8, pp. 8–13, Jan. 1995.

19. A. Vander Vorst, D. Vanhoenacker, R. Gillon, Z. Zhu, B. Stockbroeckx,J. F. Michotte, and J. Singh, “Laser diode matching,” in Colloque PAI no24, (Brussels, Belgium), “Technologies de l’information optoelectroniques”,May 1994.

20. A. Vander Vorst, D. Vanhoenacker, R. Gillon, Z. Zhu, B. Stockbroeckx,M. Serres, and J. Singh, “Design and fabrication of a PIN diode, togetherwith RUG-INTEC, for its transmission line parameters measurement,” inColloque PAI no 24, (Brussels, Belgium), “Technologies de l’informationoptoelectroniques”, May 1994.

21. A. Vander Vorst, D. Vanhoenacker, R. Gillon, Z. Zhu, B. Stockbroeckx,and P. Delisse, “S-matrix theory applied to optical systems and com-ponents,” in Colloque PAI no 24, (Ghent, Belgium), “Technologies del’information optoelectroniques”, Nov. 1993.

Accepted

1. J.-P. Raskin, R. Gillon, D. Vanhoenacker, and J.-P. Colinge, “Direct Ex-traction of the non-quasi-static small-signal Model of MOSFET’s,” in28th European Microwave Conference Digest, (Amsterdam, The Nether-lands), pp. 170–173, Oct. 5–9 1998.

2. D. Flandre, J.-P. Colinge, D. De Ceuster, J.-P. Eggermont, L. F. Ferreira,B. Gentinne, P. Jespers, A. Viviani, R. Gillon, J.-P. Raskin, A. Van-der Vorst and D. Vanhoenacker, “Fully-depleted SOI CMOS technologyfor low-voltage, low-power mixed digital / analog / microwave circuits,”Analog Integrated Circuits and Signal Processing, 1997.

Submitted

1. C. Raynaud, O. Faynot, J.-L. Pelloie, S. Deleonibus, D. Vanhoenacker,R. Gillon, J. Sevenhans, and E. Mackoviak, “Fully-depleted 0.25µm SOIdevices for low power RF mixed analog-digital circuits,” in IEEE Intl SOIConf., 1998.

In preparation

1. R. Gillon, I. Huynen, J.-P. Raskin, D. Vanhoenacker, and J.-P. Colinge,“Macroscopic modelling of CPW’s on silicon substrates,” IEEE Trans.on Microwave Theory and Techniques, 1998.

xv

Main scientific publications

2. R. Gillon, D. Vanhoenacker, and J.-P. Colinge, “Modelling non-quasi-static effects in the SOI MOSFET at microwave frequencies,” AnalogIntegrated Circuits and Signal Processing, 1998.

xvi

List of abbreviations

AC Alternating CurrentA/D Analog to DigitalBJT Bipolar Junction TransistorBiCMOS Bipolar / Complementary MOS Transistor technologyCMOS Complementary MOS Transistor technologyCPW Coplanar WaveguideDC Direct CurrentDIBL Drain-induced Barrier LoweringDuT Device under TestFET Generic Field Effect TransistorGSM Global System Mobile

(formerly : “Groupe Speciale Mobile”)HBT Hetero-junction Bipolar TransistorHEMT High Electron Mobility TransistorIC Integrated CircuitIF Intermediate FrequencyIIP3 Third-order Intermodulation Intercept PointLDD Lightly Doped Drain

LETI Laboratoire d’Electronique, de Technologie et d’Instrumentation(CENG, Grenoble)

LO Local Oscillator (frequency)MESFET Metal Semiconductor Field Effect TransistorMMIC Monolithic Microwave Integrated CircuitsMOS Metal-Oxide-SemiconductorMOSFET Metal-Oxide-Semiconductor Field Effect TransistorMS Microstrip lineNQS Non-quasi-staticOTA Operational Transconductance AmplifierPCB Printed Circuit BoardPTFE Poly-Tetrafluoro-ethylene

xvii

List of abbreviations

QS Quasi-staticRC Resistance-capacitanceRF Radio FrequencySIMOX Separation by Implantation of oxygenSOI Silicon-On-InsulatorSOLT Short-Open-Load-Through calibrationSOS Silicon-On-SapphireTAN Through-Attenuator-Network calibrationTE Transverse electric field modeTEM Transverse electric and magnetic fields modeTM Transverse magnetic field modeTRL Through reflect line calibrationTRM Through-Match-Reflect calibrationUCL Universite catholique de LouvainUniBond UniBond SOI material from SOITECVNA Vector network analyser

xviii

Chapter I

Introduction

I.1 RF and microwave monolithic IC’s

Analogue circuits functioning in the microwave frequency range use passivecomponents extensively. At high frequencies, transistor and amplifier gainis limited so that passive impedance matching becomes an important meansof optimising circuit performance. Passive components are typically used toeliminate unwanted reflections at the circuit ports, to maximise the powertransfer or to enhance the noise performance. They are also useful as resonatorsin filters or oscillators.

For years, microwave systems have been realised by mounting discrete tran-sistors together with lumped-element or distributed components on printed cir-cuit boards. The advantages of the hybrid design approach are the following :

• It is simple to combine devices fabricated with very different materials sothat optimum performance can be achieved for each component.

• Devices can be individually selected in function of their measured char-acteristics.

• Post-assembly trimming is feasible thanks to the large size of the resultingprinted circuit board.

Microwave systems realised on PCB’s tend however to be rather bulky andcostly to manufacture. Together with the need for systems of ever increasingcomplexity, these drawbacks fostered the development of fabrication processesallowing the monolithic integration of all passive components and active deviceson a single chip. The principal benefits of monolithic integration are :

I-1

Introduction

• The length of interconnections is reduced and the package parasitics areminimised, so that signals are less attenuated and power savings can berealised.

• Device and component uniformity is enhanced and a higher yield is achievedas the number of packaging and mounting operations is reduced.

• Smaller size and light weight can be achieved.

In contrast to the hybrid approach, monolithic integration necessitates a trade-off in the performance of individual devices, as only compatible fabrication stepscan be merged into a single process.

Figure I.1: A typical MMIC amplifier. The spiral inductors are used as RF-chokes in the DC-biasing circuit. The two comb-like structures are MESFET’s.The input and output pads on the left and right are metal-insulator-metal DC-blocking capacitors.

Monolithic microwave integrated circuits were first used for radio com-munications, radar and guidance in military, naval and aero-space applica-tions. MMIC’s eventually found their way into commercial applications viahigh-frequency instrumentation, broad-band networks, and mobile communi-cations, [I.1].

I.1.1 New driving forces

The boom of mobile communications and the advent of high-speed data net-works have upset the dominant position traditionally held by military appli-cations in the MMIC market. Military and aero-space systems were typicallyhigh-quality products manufactured in limited quantities, while the marketsfor mobile communications and high-speed data networks are calling for mass-production of low-cost products. For example, the number of mobile communi-cation terminals sold annually already overtook the number of annual car sales

I-2

I.1 RF and microwave monolithic IC’s

during the year 1995, and it is even expected to rise above the number per-sonal computers sold during the year 1998, [I.2]. This shift of the MMIC markettowards large volume production has fostered the development of alternativeMMIC technologies based on silicon rather than on compound semiconductorswhich used to dominate previously.

The mobile terminals themselves also experienced an important evolution.From the heavy car-phone at the beginning of the ’80s to the ergonomicallydesigned hand-sets of the ’90s, the range of available services has been consid-erably extended from simple voice communications to a complete communica-tor with electronic mail, fac-simile and internet access. The miniaturisationof mobile terminals opened up the possibility of integrating communicationcapabilities into such systems as palm-top notebooks, as the one featured infigure I.2. In the future, mobile communication terminals are expected to be-come capable of multi-mode operation, that is to say, capable to access variouscommunications services using different signalling protocols and modulationschemes, [I.3].

Figure I.2: The Communicator 9000i from Nokia, [I.4]. A GSM handset andpalm-top PC : based on an Intel-386 processor with 8 Mb of memory. Whenthe screen is folded down onto the keyboard, the unit looks like any standardhand-set.

The major technical challenges encountered in the development phase ofsuch advanced terminals stem from four key parameters : volume, weight,power consumption and components count. Volume and weight have been de-

I-3

Introduction

creasing steadily since the introduction of the first portable mobile communi-cation appliances and are now reaching a level of comfortable use, as indicatedby Neuvo in [I.2]. Power consumption and components count remain as criticalissues where improved solutions are being sought.

Power consumption is critical because mobile terminals must operate onbatteries which have a limited capacity due to weight restrictions. Battery ca-pacity improvements are slow and major breakthroughs are still to be awaited,so that the most straightforward solution is presently the reduction of the powerconsumption of IC’s.

The number of components involved in the assembly of a mobile commu-nication appliance influences the reliability, the quality and the manufacturingcosts. Mobile phones still contain an important amount of discrete devices,especially in the RF sections where 80 % of the parts count is due to discretepassive devices. Monolithic integration of these devices would not only allowto enhance manufacturing yield and product reliability, but would also con-tribute to reduce the power consumption and allow to evolve towards software-reconfigurable multi-mode transceivers.

I.1.2 Technology directions

The new challenges resulting from the trend towards low-cost, monolithicallyintegrated, low-power microwave appliances have triggered an important re-search effort aiming at the development of adequate MMIC technologies.

Fabrication processes for mass-production

Silicon-based technologies have proven more suitable for mass-production aimedat consumer markets than compound-semiconductor materials such as gallium-arsenide. 300 mm-wide silicon wafers of very high quality are presently availableallowing to drive fabrication costs to very low levels by simultaneous processingof a large number of devices. The largest GaAs wafers available today have adiameter of only 150 mm.

Handling of GaAs wafers is complicated by the fact that the GaAs materialis brittle. GaAs material is therefore produced by epitaxial growth on a siliconwafer to facilitate handling. Epitaxial growth is a low-throughput fabricationstep which drives the manufacturing costs up, as investments pay-off must bespread on a limited number of wafers.

The defect density on GaAs wafers is higher than on Si wafers, so thatcircuit manufacturing yield is bound to be lower. Furthermore, isolation tech-niques available in Si-based technologies allow a much higher integration den-sity than the isolation processes used in GaAs . The compound semiconductormaterial does indeed not possess a stable insulating oxide comparable to silicon-dioxide. A high integration density is of primary importance for the fabricationof complex systems as more devices and hence more functions can be integratedon a single chip.

Together with the fact that Si technologies have had more time to mature,the larger wafer size, the good material quality and the high integration level are

I-4

I.1 RF and microwave monolithic IC’s

definite advantages favouring the development of silicon MMIC’s for consumerapplications in mobile communications.

Systems on a chip

The demand for increasing functionality of mobile communication terminals hasforced the integration of all base-band parts on to a single chip : the necessarymicroprocessors, memories, digital logic circuits and digital signal processorsare now implemented on a single silicon dice using CMOS technology.

Figure I.3: The super-heterodyne architecture proposed by Motorola for digitalcellular phones, [I.5]. It consists of bipolar chips for the receiver and transmitterIC’s, together with one CMOS chip for the base-band processing and one forthe micro-controller. Five ceramic filters are used.

The RF part, on the other hand, is still a mix of discrete components,together with bipolar or GaAs chips. The low integration level of the RF partis a direct consequence of the super-heterodyne architecture used presently forcommercial transceivers. Super-heterodyne receivers rely on filters to select theadequate RF-channel and to reject the image frequency at IF. The constraintson the filters are relatively tight and can only be met using ceramic filters whichare mounted in separate packages on the motherboard. Figure I.3 illustratesthe architecture proposed by Motorola using the company’s products.

As outlined in subsection I.1.1, there exist several economical and tech-nical incentives pushing towards the monolithic integration of the completetransceiver on a single chip. Briefly, these are : Lower assembling costs, higher

I-5

Introduction

yield and reliability because of the reduced number of components; Power sav-ings as the interconnection lengths and the number of package pins drivenby high-frequency signals are reduced; Smaller occupied surface on the moth-erboard allowing for an increased complexity — e.g., software reconfigurablefront-ends. However, single chip integration can not be achieved unless somealternative architectures are introduced which do away with the need for high-performance filters.

Candidate architectures for the single-chip integration of the transceiverhave been identified. They use quadrature down-conversion schemes to discrim-inate between the wanted signal and its image and rely on low-frequency on-chipfiltering to isolate the wanted signal from neighbouring channels, [I.6, I.7]. Thelow-frequency filtering can be performed either using analogue or digital signalprocessing techniques. The most promising solution is the low-IF architecturedemonstrated by Crols in his thesis, [I.8].

The technology of choice for the single chip integration of the transceiver isof course CMOS, which is the mass-market technology which already allowedto integrate all the base-band and control functions monolithically at low-costand with a very low power-consumption. Several microwave CMOS technologyoptions are presently being actively developed. One of them is thin-film silicon-on-insulator to which the other chapters of this work are entirely devoted.

Low-power operation

To ensure a sufficient autonomy for battery-powered mobile communicationterminals, power consumption must be kept low. In digital CMOS circuitry,the dynamic power consumption per gate is known to be proportional toCload V

2swg fclk , where Cload is the load capacitance, Vswg is the voltage swing

and fclk is the clock frequency. Lowering the biasing voltage and hence thevoltage swing is thus the most effective way to reduce the power consumptionof digital MOS circuits, [I.9]. In order to maintain the current drive capabilityand the switching speed of the devices, the threshold voltage is lowered and thechannel length is scaled down. If the threshold voltage is too low, then the off-state leakage current will become too important, causing a noticeable increaseof the static power consumption. The optimum threshold voltage must hencebe chosen in function of the acceptable level of leakage current. In conventionalbulk MOS technology the optimum lies around 450 mV, while for thin-film SOIMOSFET it lies about 10 mV lower, [I.10].

For low-frequency designs, the analogue performance of MOSFET’s is mostsuitably characterised by the open-loop voltage gain of a single device AV =Gm/GDS where GD is the output conductance. The output conductance can beapproximated over a wide bias range by ID/VA, where VA is the early voltage.Finally :

AV =Gm

IDVA (I.1)

The “Gm/ID” ratio is a measure of the efficiency to translate current — hencepower — into transconductance, [I.10]. In low-power applications, Gm/ID can

I-6

I.1 RF and microwave monolithic IC’s

be maximised by operating the transistors in weak inversion, with a low gatevoltage overdrive above the threshold, [I.9]. In conventional bulk MOS transis-tors the peak “Gm/ID” ratio attains about 25 V−1 in weak inversion. For SOIMOSFET this peak value lies around 35 V−1.

0 0.5 1 1.5 2 2.5 3

fT

[GHz

]

Bias Voltage

[V]

0.5µm Bulk MOSFET

0.65µm Bulk Bipolar

0.75µm SOI MOSFET

0

5

10

15

20

25

0.5µm SOI MOSFET

Figure I.4: Evolution of the transition frequency fT in function of the biasvoltage for various technologies and their particular minimum feature width.The bulk MOS and bipolar transistor data comes from a BiCMOS technology,[I.11]. The 0.75µm channel-length SOI MOSFET data was obtained at theUCL, [I.12]. The 0.5µm SOI MOSFET data is an extrapolation based on theeffective channel length and a linear scaling of fT .

In high-frequency applications, capacitive loading becomes the determiningfactor and the analogue device performance is best analysed using the currentgain, AI = Gm/( ω CG), where CG is the total gate capacitance of the MOS-FET. The current gain can be evaluated for any type of device, either bipolar,MOSFET or MESFET, and its transition frequency, fT , is a direct measureof the high-frequency performance which allows to compare different technolo-gies. The evolution of fT versus biasing voltage presented in figure I.4 allows tocompare the low-voltage performance of various technologies at microwave fre-quencies. The bipolar transistor is already within 20 % of its peak performanceat 0.6 V, the SOI MOSFET at 0.8 V and the bulk MOSFET at 1.2 V.

Thin-film SOI MOS technology thus appears to be a very good candidate forthe implementation of mixed-mode low-power systems comprising digital andhigh-frequency analogue components, the latter being capable of operation atmicrowave frequencies. A detailed comparison of MOS and bipolar technologiesfor microwave applications is proposed in the next section.

I-7

Introduction

I.2 Competing technologies for emerging RF ap-

plications

The competing device technologies for the emerging mass-market applicationsare bipolar, CMOS, and mixed bipolar-MOS (BiCMOS). Bulk-silicon and silicon-on-insulator options are available for all three. Bipolar-only processes, andSiGe bipolar in particular, are high-performance technologies which are prob-ably shooting to high with respect to the needs of the mobile communicationmarket in the near future, [I.13]. Bipolar-only processes target high-speed ap-plications and are in particular not well suited for the implementation of thelow-power digital base-band part of portable communication terminals. CMOSand BiCMOS are thus the best candidates for the single chip integration of mo-bile communication transceivers.

High performance sub-micrometre-channel MOSFET’s are capable of ana-logue operation at microwave frequencies, [I.13]. The record transition fre-quencies of 150 GHz recently attained with experimental nanometre MOS-FET’s show that present-day MOS technology still has potential for improve-ment, [I.14]. Using a silicon-on-insulator substrate, circuit speed can be sub-stantially improved, but the ultimate advantage of SOI CMOS circuits is tobe expected in low-power applications when using thin-film, fully depleted SOIMOSFET’s, [I.10].

The use of MOSFET’s in microwave circuits does however cause a fewproblems which bipolar transistors can remedy, so that BiCMOS technologiesare very appealing.

1. Optimal tuning of the MOSFET noise performance is more difficult thanfor bipolar devices. Indeed, the input load resulting in the minimumnoise figure is for MOSFET’s a large inductance with a high qualityfactor, which can not be practically be implemented on-chip. Worse even,the sensitivity of the noise figure to the input load is high, so that thenoise figure degrades rapidly when the input load departs for its optimalvalue, [I.15]. One solution to this is to increase the device size at theexpense of larger drain current and power dissipation. In such a case, acircuit with BJT’s requires lower bias current and dissipates less powerfor comparable noise figures, [I.11].

2. Short-channel MOSFET’s, and fully depleted SOI MOSFET’s in partic-ular, have a rather high output conductance in saturation which mayaffect amplifier gain. Typical values for the Early voltage of MOSFET’s,VA = GDS ID , lye around 30 V, while for BJT’s VA = GCE IC lies around50 V.

3. MOSFET’s are less efficient to handle large signals than BJT’s, as theyrequire a considerably larger biasing current to attain high power-levels,[I.13].

Being more complex than CMOS technology, BiCMOS is of course more costly,and must be targeted at high-end products which can absorb the extra cost.

I-8

I.2 Competing technologies for emerging RF applications

Plain CMOS can however be expected to prevail in low-cost and less demandingapplications.

I.2.1 Bulk MOSFET’s

Silicide

Silicide

n+ diffusion

n− diff. (LDD)

Pocket implants

p well

Channel-stop implants

Source Gate Drain

Poly-silicon Oxide

Silicide

Depletion limit

n+ diffusion

n− diff. (LDD)

p− substrate

Field oxideField oxide

Channel region

Figure I.5: Cross-section of a short-channel bulk-silicon MOSFET.

Characteristic of bulk technologies is that the transistors are fabricated di-rectly on monocristalline silicon wafers and are thus all in contact with thesubstrate material. Bulk has been the main-stream technology for years, butsilicon-on-insulator has now evolved into a mature contender, [I.16]. A specificadvantage of bulk technology is that the substrate acts as an efficient heat-sink,thanks to the high thermal conductivity of silicon. Bulk technology is howeverconfronted with isolation problems. Bulk MOS transistors suffer from high par-asitic capacitances — diffusion capacitances, body effect — and require specialtechniques for submicrometer scaling. Figure I.5 shows the cross-section of ahigh-performance bulk MOSFET.

Isolation

The standard isolation technique in bulk technology is the use of reverse-biasedjunctions. This technique is only efficient at low frequencies and at moder-ate operating temperatures : Indeed, high-frequency signals may easily crossreverse-biased junctions because of the finite capacitance, while leakage cur-rents increase rapidly with temperature up to a point were reverse biasedjunctions have little blocking effect. Junction isolation may even fail catas-trophically when neighbouring p- and n-wells combine to form a thyristor-likestructure which can be triggered by a transient injecting a sufficient amount of

I-9

Introduction

current in any of the wells. These issues can be partly resolved by increasingthe inter-well spacing, at the cost of a lower integration density, or by usingadvanced techniques such as trench isolation.

Parasitic capacitances

At low frequencies, when the substrate is essentially conductive, bulk MOS-FET’s are loaded by large capacitances due to the depletion region associatedwith the source and drain diffusions as well as with the inversion channel. Thelower limit of the depletion region is represented in figure I.5 by the dashedline. The presence of a large depletion region underneath the gate oxide hasa detrimental effect on the characteristics of the MOSFET. The influence ofthe gate voltage, VG , on the surface potential, ψs , which controls the inversioncharge density in the channel, is diminished :

dψs

dVGu

C′′ox

C′′ox + C′′d< 1 (I.2)

For an ideal device, the derivative should approach unity. This body effectwhich reduces the effective control of the gate on the channel, is responsiblefor the low rate at which the transition frequency fT of the bulk MOSFETincreases as a function of bias voltage on figure I.4. The off-state performanceof bulk MOSFET’s is also affected, as the gate voltage must be driven lowerbelow threshold to restrain the leakage current below a specified level. BulkMOSFET’s must therefore be designed with higher threshold voltages — seefigure I.4.

Substrate

Gate-oxide capacitance

Depletion capacitance

Gate

ψs

Substrate capacitance

Wafer back-plane

Gate

ψs

VG VG

Low-frequency High-frequency

Figure I.6: The body-effect for a bulk MOSFET at low-frequencies. (Interfacestates have been negelected)

Paradoxally, the body effect has a less dramatic influence on high-frequency

I-10

I.2 Competing technologies for emerging RF applications

signals. The reason is that, for signals located in a band above the dielectricrelaxation frequencies of the silicon material, the substrate behaves rather asa lossy dielectric, which adds a small capacitance in series with the depletioncapacitance so that the body effect is attenuated.

Short-channel effects

The large depletion zones associated with the source and drain diffusions ofbulk MOSFET’s are also an obstacle to the submicrometer scaling of the chan-nel length. Indeed, the finite width of these depletion zones set a lower boundon the channel length. Below this limit, the source and drain depletion zonesoverlap, creating a region where a strong electric field can sweep electrons di-rectly from source to drain independently of the gate voltage. Even, at channellengths above this punch-through limit, the source and drain depletion zoneshave a detrimental impact on scaling, as they contribute to lower the thresholdvoltage, [I.10].

Present-day submicrometer MOSFET technologies compensate the punch-through and threshold voltage roll-off effects using special pocket implants,which are designed to locally divert the electric field, [I.17]. These pocketsmust be very precisely located at the lower tip of the diffusions. To achievethe proper doping profile, a tilted implantation technique is used where thewafer is tilted at an angle with respect to the ion-beam. Four of these implantsare required to provide pockets at the drain and source of MOSFET’s alignedin two orthogonal directions. Specific masks are also required to select theimplantation regions.

Partially depleted SOI MOSFET’s

Silicon-on-insulator technology can be used to enhance the performance of bulkMOSFET’s, particularly speed and packing density. The latter is increased onSOI essentially thanks to the very efficient isolation of individual devices by thefield and buried oxides. This all-round isolation alleviates the need for diffusedwells which require specific contacts and careful spacing and are limiting theintegration density in bulk technology.

The buried oxide layer, with its low dielectric constant, contributes to sig-nificantly reduce the parasitic capacitances loading the source and drain dif-fusions, allowing SOI designs to book speed gains with respect to their bulkcounter-parts, [I.16, I.18].

The partially depleted device shown in figure I.7 is a rather conservative SOIMOSFET design : it is merely a bulk MOSFET transposed onto a SOI sub-strate. In particular, the existence of a quasi-neutral region below the depletionzone associated with the transistor ensures that the body effect in the partiallydepleted SOI MOSFET is identical to that of the bulk MOSFET, so that theSOI device shows no improvement in the subthreshold characteristics, [I.10],which are essential for low-voltage applications.

Partially depleted SOI MOSFET’s have a also a problem of their own :floating body effects. It is mainly a lowering of the threshold voltage due to theaccumulation holes generated by hot carriers in the drain region. The result is

I-11

Introduction

an ugly kink in the current characteristics occuring at moderately high drainvoltage. The effect can be suppressed by using special body contacts which tiethe neutral region of the film to the source potential.

Silicide

Silicide

n+ diffusion

n− diff. (LDD)

Pocket implants

p film

Source Gate Drain

Poly-silicon Oxide

Silicide

Depletion limit

n+ diffusion

n− diff. (LDD)

p− substrate

Field oxideField oxide

Pocket implants

Channel region

Buried oxide

Figure I.7: Cross-section of a short-channel partially-depleted SOI MOSFET.

Silicide

Silicide

n+ diffusion

p film

Source Gate Drain

Poly-silicon Oxide

Silicide

n+ diffusion

p− substrate

Channel region

Buried oxide

Field oxide Field oxide

Figure I.8: Cross-section of a short-channel fully-depleted SOI MOSFET.

I-12

I.2 Competing technologies for emerging RF applications

I.2.2 Thin-film SOI MOSFET’s

It has been shown in the last subsection that silicon-on-insulator technologyremedies elegantly to the isolation problems of conventional bulk technologiesand even contributes to circuit speed improvements. The use of fully depletedSOI MOSFET’s extends the advantages of SOI even further to easier down-scaling and nearly optimal low-voltage performances. Fully depleted SOI de-vices are obtained by using silicon film thicknesses thinner than the depth ofthe depletion zone, typically below 100 nm.

Low-voltage operation

Figure I.9 reveals that in all cases the body effect in fully depleted SOI MOS-FET’s is less pronounced, because the series connection of the film capacitance,C′′b , and the buried oxide capacitance, C′′ob , is smaller than the depletion ca-pacitance of a bulk transistor. The control of the gate voltage on the surfacepotential, ψsf , and hence the channel, is even almost optimal as the buriedoxide capacitance is very small :

dψsf

dVGfu

1/C′′b + 1/C′′ob

1/C′′of + 1/C′′b + 1/C′′ob

u 1 (I.3)

where C′′of is the gate oxide capacitance, the interface states have been ne-glected. For high-frequency operation, the situation is even more favorable,thanks to the substrate capacitance.

ψsf

ψsb

Gate-oxide capacitance

Si film capacitance

Gate

Buried oxide capacitance

Wafer back-plane

Gate

VGf VGf

Low-frequency High-frequency

Substrate

ψsf

ψsb

Substrate capacitance

Figure I.9: The body-effect for a fully-depleted SOI MOSFET.

I-13

Introduction

The very small body effect of fully depleted SOI MOSFET’s is the keyto their outstanding low-voltage performances and their good high-frequencyperformance. Interestingly, the fabrication of these devices is less complicatedthan that of bulk MOSFET’s of comparable channel lengths, notwithstandingtheir better performances. The comparison of figures I.5 and I.8 shows indeedthat the SOI MOSFET structure is inherently simpler than that of the bulkdevice.

Short-channel effects

In fully depleted SOI MOSFET’s, the small thickness of the silicon film stronglylimits the extent of the depletion zones associated with source and drain, sothat the risk of punch-through and the threshold-voltage roll-off are stronglyattenuated. This feature alleviates the need for complex pocket implants, al-lowing to reach smaller channel lengths with a simpler fabrication process,comparatively to bulk technology. Even other short-channel effects such aschannel-length modulation and drain-induced barrier lowering have been shownto be less severe in fully depleted SOI MOSFET’s.

I.2.3 Bulk bipolar transistors

As already stated at the beginning of section I.2, bipolar junction transis-tors can help to optimise the overall circuit performance, particularly in RFanalogue circuits, where the difficult noise tuning, the larger output conduc-tance and the limited power handling capability of MOSFET’s may have adetrimental impact, [I.13,I.19]. Bulk BiCMOS technology, because of the 30 %cost-overhead due to the higher process complexity, targets essentially high-tierproducts in the mobile communications equipment market.

Figure I.10 presents the cross-section of a npn-BJT in a typical bulk BiC-MOS process, [I.20]. Additional processing steps with respect to CMOS tech-nology are :

• Epitaxial crystal growth, necessary to stack the collector n-well on top ofthe n+ region.

• Second poly-siclicon layer for the emitter contact.

Vertical BJT structures such as the one displayed in figure I.10 have beenimplemented on SOI. This kind of structure requires a minimum film thicknessof about 1µm, so that vertical BJT’s are not compatible with fully depletedMOSFET’s.

I.2.4 Thin-film lateral bipolar SOI transistors

The lateral bipolar structure shown in figure I.11 can be used to implement aBiCMOS process in thin-film SOI technology, [I.21]. Current-gain transitionfrequencies around 15 GHz have been attained for such devices integrated to-gether with 0.5µm fully-depleted MOSFET’s, demonstrating the viability of a

I-14

I.2 Competing technologies for emerging RF applications

CollectorBase

EmitterBase

Poly-silicon (E.)

Oxide

Polysilicon (B.)

Field oxide

p+ extrinsic B. diff.

n+ emitter p intrinsic B. diff.

Polysilicon (B.)

Oxide

Oxide

n+ C. diffusion

n− C. well

p− substrate

Figure I.10: Cross-section of a bipolar junction transistor in a bulk-siliconBiCMOS process.

CollectorEmitter Base

Polysilicon (B.)

Field oxide

n+ E. diffusion

p B. diffusion

Oxide

n+ C. diffusion

n− collector

p− substrate

Metal (E.) Oxide Metal (C.)

Buried oxide

Field oxide

Figure I.11: Cross-section of a lateral bipolar junction transistor in a thin-filmSOI BiCMOS process.

I-15

Introduction

microwave, thin-film SOI BiCMOS technology, [I.22]. Interestingly, the fabrica-tion of the lateral BJT structure is fairly simple, involving exclusively standardCMOS processing and requiring the addition of only two extra lithographysteps.

I.2.5 Low-voltage systems-on-a-chip, the future of SOI

The comparison of technologies and their basic building blocks in the previoussubsections has shown that thin-film SOI has a strong potential for large-scaleintegrated systems where integration density and power savings are a premium.Thin film SOI MOS and bipolar devices offer excellent microwave performancesin low-voltage biasing conditions at a reasonable cost, because of their inher-ently simple device structure. Thin-film SOI hence appears as a technology ofchoice for the single-chip integration of advanced mobile communication ter-minals.

I.3 Silicon-on-Insulator substrate technology

SOI substrate technology has been under development for more than twodecades. Many options have been investigated, but, presently, three solutionsseem to dominate : silicon-on-sapphire, oxygen implantation and wafer bond-ing. Silicon-on-sapphire was the first to reach maturity, but it is not suited formass-production and will probably survive in niche applications. The remain-ing SOI wafer technologies have both evolved to meet the the constraints ofhigh-volume production, but it seems that wafer-bonding may gain the lead.

I.3.1 Silicon-on-sapphire

Silicon-on-sapphire substrates are obtained by growing a silicon substrate ontop of a monocristalline sapphire substrate. This process is called hetero-epitaxyas silicon and sapphire are different materials with slightly different cristalstructures. The differences in lattice dimensions generate stress in the siliconlayer, which is absorbed by the formation of cristal defects. Such defects reducethe carrier mobility and can induce leakage currents.

In order to achieve reasonable transistor performances on SOS, the densityof cristal defects is reduced using specific processing techniques, [I.23]. Theseallow to heal the cristal structure in most of the silicon film, except for a thinbuffer-layer in the vicinity of the sapphire, where cristal defects compensate thelattice mismatch. This residual defect concentration at the bottom of the filmmakes SOS substrates unsuitable to integrate thin-film fully depleted MOS-FET’s. Cristal defects would indeed be activated by variations of the surfacepotential ψsb at the bottom of the film, modifying the device characteristics inan unpredictable manner and generating noise. In partially depleted deviceson the other hand, the quasi-neutral region is tied to the source, so that thepotential ψsb is fixed, and that defects are not activated.

Sapphire is a very attractive substrate, having a very high resistivity, alow dielectric constant and a high thermal conductivity. The hetero-epitaxial

I-16

I.3 Silicon-on-Insulator substrate technology

(a) (b)

Silicon film Cristal defects

Sapphire substrate

Figure I.12: Silicon-on-sapphire substrate fabrication : (a) Hetero-epitaxy ofsilicon on a sapphire substrate; (b) Successive amorphisation and recrystallisa-tion steps.

growth and the recrystallisation steps are however costly and low through-put processing steps, which disqualify SOS in the competition for mass-marketapplications.

I.3.2 Separation by Implantation of Oxygen

(a) (b)

O− Buried oxydeSilicon film

Figure I.13: The SIMOX fabrication process : (a) Oxygen implantation, for-mation of oxide precipitates; (b) Annealing. Steps (a) and (b) are repeateduntil the buried oxide attains the desired thickness.

SIMOX is a trade-mark of Ibis Corp. which developed the process andcommercialises SOI wafers. In this process, oxygen is implanted inside a sil-icon wafer in order to form a buried SiO2 layer underneath a thin cristalline

I-17

Introduction

film. Compared to implantation doses usually required in transistor fabrica-tion, where the implanted impurities form a small fraction of the total numberof atoms in the material, in the SIMOX process the implanted O− dose inenormous, as the number oxygen ions must be twice the number of Si atomsnecessary to form the buried oxide layer. In order to avoid damaging the cristalstructure of the top silicon film irreversibly, the implantation is performed pro-gressively, alternating implantation and annealing steps. The technique pro-duces high-quality films, with a defect density comparable to that of bulk-siliconwafers, so that giga-bit memories have been successfully integrated on SIMOXwafers.

High-capacity implanters have been developped specifically for mass-produc-tion in the SIMOX process, however the fabrication cost is high, and will prob-ably remain higher than that of bulk-silicon wafers, [I.10].

I.3.3 Wafer-bonding

(c) (d)

(a) (b)

H+

Wafer A Wafer A

WaferA

Wafer B

Recycled as new wafer B

Smart-Cut layer

SiO2

Figure I.14: The UniBond fabrication process.

Wafer-bonding relies on the attraction of two hydrophilic surfaces for eachother. Once brought in contact these surfaces attract each other so strongly,that hydrogen bonds can form spontaneously. The bonding can then be furtherstrengthened by a proper annealing. Wafer bonding is used to form SOI wafers,

I-18

I.3 Silicon-on-Insulator substrate technology

but can eventually be used to transfer a silicon-film containing processed cir-cuits onto a different substrate, for example alumina, chosen for its outstandingdielectric properties.

UNIBOND material

UniBond is a trade-mark of SOITEC which commercialises SOI wafers pro-duced using the patented Smart-Cut process. SOI wafer fabrication startswith the growth of a high-quality oxide on a bulk silicon wafer, figure I.14(a).Then hydrogen atoms are implanted in the silicon below the oxyde, at a depthcorresponding to the wanted film thickness, figure I.14(b). The wafer A anda second wafer B are prepared for bonding by a cleaning step. Wafer A isthen turned over and brought into contact with B for bonding, figure I.14(c).The bonded wafers are heated to 500C, at which temperature the implantedhydrogen activates and creates a cleavage plane cutting wafer A in two andleaving a thin cristalline silicon film on top of a buried oxide layer on wafer B— the Smart-Cut process, figure I.14(c). The new SOI wafer is then annealed,and the surface roughness is adjusted on both wafers by a touch polishing step.Wafer A is finally recycled as a new wafer B.

All of the fabrication steps involved in the production of UniBond wafershave been tailored for high-volume production. On the basis of the productioncapacity being installed, some projections even dare to predict lower prices for8 inch UniBond wafers than for equivalent bulk silicon wafers.

Silicon-on-anything

Bonding or even glueing can be used to transfer thin silicon films containingfully operational circuits onto various substrates. Applications of such tech-niques are typically : the creation of three-dimensional structures as memorycapacitors, [I.16], the substitution of high-quality substrates (instead of the na-tive silicon) for microwave operation, [I.24], or the transfer onto adhesive tapes,etc.

I.3.4 The blooming of a SOI era ?

Silicon-on-insulator has evolved into a mature technology, offering not onlyhigher performance and simpler device processing, but also opening up a wealthof new design possibilities, such as the vertical stacking of structures, the lift-offand transfer of circuits and the integration of sensors, micro-mechanical ele-ments, optical waveguides, etc. The break-through of SOI into large volumeapplications will be driven by the demand for highly integrated low-voltagesystems, such as portable and personal communications equipment. The rangeof applications of SOI will then rapidly spread to computer memories, automo-tive, aircraft and spaceborne electronics, where in addition to their low-voltageperformance, the exceptional isolation, the high-temperature stability and theradiation hardness of SOI circuits will be appreciated.

I-19

Introduction

I.4 Characterisation and modelling of MMIC’s

The availability of adequate device models is essential for the design of high-performance integrated systems. Design methods rely heavily on computersimulations of circuits to investigate alternative solutions using virtual proto-typing, which is both more flexible, faster and less expensive than the effectivefabrication of a prototype. During a simulation, information about the be-haviour of individual devices is extracted from their models and combined toevaluate global circuit responses. The accuracy and the reliability of circuitsimulations is thus conditionned by the quality of available models. To en-sure a sufficient level of accuracy, model predictions must be systematicallyconfronted with measured device characteristics in order to tune parametersvalues to obtain a good agreement. In the case of microwave devices, charac-teristics used for model validation and for parameter extraction are basicallythe evolution of scattering parameters versus frequency and biasing conditions.

Figure I.15: A close-up view of the probing setup on a Karl Suss PM-8-HFstation, showing the coaxial cables feeding the microwave on-wafer probes. Theprobes are 40 GHz PicoProbes from GGB Industries. (Photograph courtesy ofKarl Suss, [I.25])

On-wafer characterisation is the measurement of device characteristics di-rectly on the silicon die, immediately after fabrication, before slicing and encap-sulation. It is both an important productivity tool and a powerful modellingtool. Indeed, on-wafer characterisation allows to test individual circuits in ahighly automated way, so that the whole production can be scanned and faultychips eliminated prior to packaging and assembly. On-wafer characterisationalso allows to access transistors, passive devices or any circuit building blockdirectly with minimal interfering parasitics, facilitating model development andvalidation.

I-20

I.4 Characterisation and modelling of MMIC’s

Figure I.16: ACP 40 GHz on-wafer probes from Cascade. The inset shows amicroscope view of the probe tips.

Using adequate probes, the test-signals can be transferred from the coaxialcables connected to the measuring equipment onto the integrated transmissionlines feeding the test-devices. To ensure optimal measurement conditions, mi-crowave probes must provide a seamless transition between the millimetre-scaleconnectors of the coaxial cables and the micrometre-scale integrated coplanarwaveguide structures. As is usually the case in microwave hardware, high-performance translates in tight mechanical tolerances which explain the highcost of such probes.

The quality of the transition realised by the probes depends on the abilityto obtain simultaneous contacts with the three probe-tips on the aluminummetallisation of the test-structures. Planarity of the probe with respect to thesubstrate is therefore critical and careful adjustments of the rolling angle arerequired. The quality of the contacts further depends on the pressure of theprobe tips onto the aluminum contact pads. This pressure is controlled by theamount of overtravel, the vertical distance by which the probe body is loweredafter the initial touch-down of the probe tips, typically around 100µm.

In order to perform accurate and reliable measurements on small-size inte-grated devices, a high horizontal positionning accuracy must be achieved witha good repeatability. Micro-metric screws used for positionning typically havea resolution on the order of 5µm which can be fully exploited if adequate refer-ence marks are provided on the test-wafer. Figure I.4 shows a probing structurewith its sets of alignment marks designed reduce the positionning uncertaintybelow 5µm. Other important features of this design are that :

• the ground-to-ground spacing of the coplanar waveguide sections is di-mensioned so as to closely fit the average transistor size, allowing toreduce the inductance of ground connections.

• the structure implements a smooth transition between the geometry of the

I-21

Introduction

Signal

Ground

Ground

Probe-tips

Contact pads Passivated metal

Alignment marks

150 µm

150 µm

Figure I.17: Artist’s view showing microwave on-wafer probes contacting aMOSFET test structure.

probe-pads dictated by layout rules and the feeding waveguide sectionsnaturally associated with the transistor geometry.

• the spacing between opposing sets of probe-pads is large in order to reducethe risk of direct coupling between the probes.

To achieve the required control on the probes motion and attitude, eachprobe is mounted on a positionner equiped with three orthogonal micrometrictranslation stages and one tilting stage. The positionners themselves are bolteddown on a single rigid platen, which rests on an antivibration table. Vibrationisolation is further enhanced by feeding the probes with flexible cables disposedin an ample meander curve.

Such an on-wafer probing station was used intensively in the framework ofthis thesis. All scattering parameters measurements shown in the text were per-formed on the probing station installed at the “Laboratoire d’Hyperfrequences”.The characterisation procedure is described in more detail in chapter II.

I.5 Conclusion

The global context of the thesis has been reviewed. SOI and bulk technologieswere compared in the perspective of the evolution towards portable, multi-functional personal (communication) appliances. The specific advantages of thefully depleted SOI CMOS technology for low-voltage, low-power applicationswere illustrated. The major types of SOI material were presented. Importantaspects of characterisation and modelling were discussed and the microwaveon-wafer probing station has been described.

I-22

REFERENCES

References

[I.1] N. Sclater, Gallium Arsenide IC Technology. TAB Books Inc., 1988.

[I.2] Y. Neuvo, “Future directions in mobile communications,” in Proceedingsof the 22nd European Solid-State Circuits Conference (H. Grunbacher,ed.), pp. 35–39, Sept. 1996.

[I.3] Y. Neuvo, “Rf mobile communications circuits - comparision of technolo-gies,” in Proceedings of the 27th European Solid-State Device ResearchConference (H. Grunbacher, ed.), pp. 24–27, Sept. 1997.

[I.4] Nokia, <http://www.forum.nokia.com>, Nokia 9000i communicator.

[I.5] Motorola Inc., <http://mot-sps.com>, Reference Designs : Yellow-stone 900 MHz — Preview, Sep 1997.

[I.6] A. A. Abidi, “Direct-conversion radio transceivers for digital communi-cations,” IEEE J. of Solid-State Circuits, vol. 30, pp. 1309–1410, Dec.1995.

[I.7] J. Crols and M. S. J. Steyaert, “A single-chip 900 MHz CMOS receiverfront-end with a high performance low-IF topology,” IEEE J. of Solid-State Circuits, vol. 30, pp. 1483–1492, Dec. 1995.

[I.8] J. Crols, Full integration of wireless transceveir systems. PhD thesis,Katholieke Universiteit Leuven, Leuven, Belgium, 1996.

[I.9] E. A. Vittoz, “Low-power design : Ways to approach the limits,” in Di-gest of Technical Papers, IEEE International Solid-State Circuits Con-ference, pp. 14–18, 1994.

[I.10] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI.Boston – Dordrecht – London: Kluwer Academic Publ., 2nd ed., 1997.

[I.11] S. P. Voinigescu, S. W. Tarasewicz, T. MacElwee, and J. Ilowski, “Anassessment of the state-of-the-art 0.5µm bulk CMOS technology for RFapplications,” in IEDM ’95, Technical Digest, pp. 721–724, 1995.

[I.12] J.-P. Colinge, J. Chen, D. Flandre, J.-P. Raskin, R. Gillon, and D. Van-hoenacker, “A low-votlage, low-power microwave SOI MOSFET,” inProceedings of the IEEE Int. Silicon-on-Insulator Conference, pp. 128–129, 1996.

[I.13] J. Burghartz, “Silicon RF technology — the two generic approaches,”in Proceedings of the 27th European Solid-State Device Research Con-ference (H. Grunbacher, ed.), Sept. 1997.

[I.14] C. Wann et al., “High-performance 0.07µm CMOS with 9.5 ps gate delayand 150 GHz ft ,” IEEE Electron Device Letters, vol. 18, pp. 625–627,Dec. 1997.

I-23

Introduction

[I.15] J.-P. Raskin, Modeling, Characterizatiiion and Optimization of MOS-FET’s and Passive Elements for the Synthesis of SOI MMIC’s. PhDthesis, Universite catholique de Louvain, Dec. 1997.

[I.16] A. J. Hauberton-Herve, “SOI : Materials to systems,” in InternationalElectron Device Meeting, Technical Digest, pp. 3–10, 1996.

[I.17] C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, “A compar-ative study of advanced MOSFET concepts,” IEEE Trans. on ElectronDevices, vol. 43, pp. 1742–1752, Oct. 1996.

[I.18] Y. Ohtomo, S. Yasuda, M. Nogawa, J.-i. Inoue, K. Yamakoshi,H. Sawada, M. Ino, S. Hino, Y. Sato, Y. Takei, T. Watanabe,and K. Takeya, “A 40 Gb/s 8 × 8 ATM switch LSI using 0.25µmCMOS/SIMOX,” in ISSCC ’97, Digest of Technical Papers, pp. 154–155, Feb. 1997.

[I.19] A. R. Alvarez, ed., BiCMOS Technology and Applications. Kluwer Aca-demic Publ., 2nd ed., 1993.

[I.20] J. Teplik, “Device design, optimisation and scaling,” in Alvarez [I.19],ch. 2, pp. 21–65.

[I.21] B. Edholm, J. Olsson, and A. Soderbarg, “A self-aligned lateral bipo-lar transistor realized on SIMOX-material,” IEEE Trans. on ElectronDevices, vol. 40, pp. 2359–2360, Dec. 1993.

[I.22] W.-L. M. Huang, K. M. Klein, M. Grimaldi, M. Racanelli, S. Ra-maswami, J. Tsao, J. Foerstner, and B.-Y. C. Hwang, “TFSOI comple-mentary BiCMOS technology for low power applications,” IEEE Trans.on Electron Devices, vol. 42, pp. 506–512, Mar. 1995.

[I.23] C. A. Garcia, R. E. Reedy, and M. L. Burgener, “High-quality CMOS inthin (100 nm) silicon on sapphire,” IEEE Electron Device Letters, vol. 9,pp. 32–34, Jan. 1988.

[I.24] A. Wagemans, P. Baltus, A. Hoogstraate, D. R., A. Tombeur, and J. vanSinderen, “A 3.5 mW 2.5 GHz diversity receiver and a 1.2 mW 3.6 GHzVCO in Silicon-On-Anything,” in Digest of Technical Papers, IEEE In-ternational Solid-State Circuits Conference, 1998.

[I.25] Karl Suss Dresden Gmbh, Manual Probe System PM 8 HF, 1996.

I-24

Chapter II

On-wafer characterisationat microwave frequencies

II.1 Introduction

Scattering parameters measurements are probably the fundamental micro- wavemeasurement technique. At least are they at the origin of all results shown inthe present work. This urged the need to develop a thorough insight intothe foundation of the measurement technique. Particularly because there ex-isted some shadow areas around the way to deal properly with difficult casessuch as very lossy planar lines. The publication of results from an investiga-tion mandated by service providers to the microwave industry in the UnitedStates, [II.1], came at the right time. The paper proposed a rigorous frameworkallowing to deal very generally with the problems concerning lossy waveguides,and announced several convincing results, such as a the comparison of a mea-surement of the power dissipated in a resistor with the prediction based on themeasured scattering parameters. The theory from [II.1] has been adopted here,and verified repeatedly by several experiments reported below.

Some new solutions had however to be found concerning the practical as-pects of the theory, particularly the operational determination of the referenceimpedance. Two original schemes have been proposed. Some material is shownin this chapter indicating the validity of the method, but the most convincingvalidation remains unseen : the megabytes of data satisfactorily de-embeddedby the technique ...

A deliberate and unique choice made in this work is the option for in-situcalibration : using scattering parameters de-embedding techniques to correctfor the parasitic influence of probe-pads and feeding lines. This choice proved

II-1

On-wafer characterisation at microwave frequencies

to be successful and effectively remedies to several problems experienced byother techniques and reported in the literature.

This chapter is organised as follows :

• Section II.2 introduces the basic concepts related to electro-magneticfields propagating in waveguides.

• Section II.3 builds forth on these basic concepts to develop a waveguidecircuit theory providing the general framework for scattering parametersmeasurements.

• The calibration methods of interest for on-wafer probing are reviewed insection II.5.

• Section II.6 provides an in-depth discussion of reference impedance de-termination methods.

• Finally, two de-embedding strategies are analysed and compared in sec-tion II.7 : the newly proposed in-situ calibration and the widely usedimmittance correction.

II.2 Uniform waveguides

This section introduces rigorous definitions of the basic concepts which areuseful to describe the electro-magnetic behaviour of waveguides. A uniformwaveguide may be broadly defined as an axially independent structure sup-porting electro-magnetic waves. These waves are described by the Maxwellequations in the frequency domain coupled to appropriate boundary conditionsaccounting for materials interfaces and impenetrable surfaces. The eigenvalueproblem is separable and the axial solutions are exponential, [II.2, II.3]. Ingeneral there are many linearly independent solutions of this problem, each ofwhich is proportional to a mode of the waveguide.

In this section, only a single mode is considered which propagates alongOZ , the longitudinal axis, in both directions. All materials will be assumed tobe isotropic, so that the permitivity ε and the permeability µ reduce to scalars.

II.2.1 Modal electro-magnetic fields

In order to have a unique representation of each mode, normalised modal fieldsare introduced. For a mode propagating in the forward direction — increasingz — the normalised modal electric and magnetic fields are denoted by −→e e−γ z

and−→h e−γ z, respectively where −→e and

−→h are independent of z. The normali-

sation scheme used need not be specified here, any fixed but otherwise arbitrarynormalisation of the modal fields will do. For example, a widely used schemeis : ∫

S|−→et |

2dS = 1 (II.1)∫

S

∣∣∣−→ht

∣∣∣2 dS = 1 (II.2)

II-2

II.2 Uniform waveguides

The modal propagation constant γ is composed of real and imaginary parts :

γ , α+ β (II.3)

To get a clear understanding of the eigenvalue problem, the transverse com-ponent of the modal fields, −→et and

−→ht , are expressed in terms of their longitu-

dinal component, −→ez = ez−→uz and

−→ht = hz

−→uz :(ω2 µ ε + γ2

)−→et = −γ∇ez + ω µ−→uz ×∇hz (II.4)(ω2 µ ε + γ2

)−→ht = −γ∇hz − ω µ−→uz ×∇ez (II.5)

The differential equations governing the longitudinal components can then beformulated as : (

∇2 + ω2 µ ε + γ2)ez =

γ

ε−→et ∇ε (II.6)(

∇2 + ω2 µ ε + γ2)ez =

γ

µ

−→ht ∇µ (II.7)

These equations are in general quite complicated. In many conventional waveg-uides, µ and ε are piecewise homogeneous, so that the right-hand side of equa-tions (II.6) and (II.7) vanish. Even so, these equations remain complicatedsince the various fields components are coupled through the boundary condi-tions. In general, the solutions of the boundary value problem possess a fullsuite of components. In certain cases, it may be possible to find either a TE(ez = 0) or TM (hz = 0) solution. Equation (II.4) and (II.5) ensure that TEM(ez = 0 = hz ) exist only in a domain of homogeneous µε with the eigenvalue γsatisfying γ = −ω2µε. This forbids TEM solutions in the presence of multipledielectrics, as often exist in open planar waveguides or waveguides bounded bylossy conductors.

II.2.2 Waveguide voltage and current

For every mode propagating in the forward direction, described by[−→et , −→ez ,

−→ht ,

−→hz

], there exists a mode propagating in the opposite direction and and satis-

fying equations (II.4)–(II.7) with propagation constant (−γ) and components[−→et , −−→ez , −−→ht ,−→hz

]. This latter is the backward propagating mode.

In general, the total fields−→E and

−→H in a single mode of the waveguide are

linear combinations of the forward and backward mode fields. Their transversecomponents can therefore be represented by :

−→Et = C+e−γz −→et + C−eγz −→et ,

V

Vc

−→et (II.8)

−→Ht = C+e−γz

−→ht − C−eγz

−→ht ,

I

Ic

−→ht (II.9)

where V and I are the waveguide voltage and the waveguide current. Thenormalisation constants Vc and Ic were originally suggested by Marks andWilliams in [II.1]. They allow V and Vc to have the units of voltage, I and Ic

II-3

On-wafer characterisation at microwave frequencies

those of current, while−→Et , −→et ,

−→Ht and

−→ht have the units appropriate to fields.

Omitting Vc and Ic forces to use unnatural dimensions.One interesting consequence of the formulation of (II.8)–(II.9) is that the

normalised forward mode has waveguide voltage V(z) = Vc e−γz and waveguidecurrent I(z) = Ic e−γz. For the normalised backward-propagating mode, thewaveguide voltage and current are : V(z) = Vc e+γz and I(z) = −Ic e+γz .

II.2.3 Power

The net complex power P(z) crossing a given transverse plane is given by theintegral of the Poynting vector over the cross section S :

P(z) =

∫S

−→Et ×

−→Ht∗ −→uz dS =

V(z) I∗(z)

Vc Ic∗ Pc (II.10)

where the absence of the 1/2 factor is due to the use of phasers. The power Pc

is defined as :

Pc ,∫S

−→et ×−→ht∗ −→uz dS (II.11)

In accordance with the analogy to electrical circuit theory, one requires that :

P = V I∗ (II.12)

This can not be achieved with arbitrary choices of the normalisation constantsVc and Ic, so that the following constraint must be imposed :

Pc = Vc Ic∗ (II.13)

which allows equations (II.10) and (II.12) to be simultaneously satisfied. EitherVc or Ic may be chosen arbitrarily; the other is determined by equation (II.13).The magnitude of Pc depends on the normalisation which determined the modalfields −→e and

−→h ; in fact, equation (II.13) can even be used to specify the

normalisation. The phase of Pc does not depend on this normalisation since thephase relationship between −→e and

−→h is fixed, to within a sign, by Maxwell’s

equations. This sign ambiguity can be resolved by explicitly distinguishingbetween the forward and backward modes. The most concise means of makingthis distinction is to define the forward mode as that in which the power flowsin the +z direction; that is :

Re(Pc) ≥ 0 (II.14)

II.2.4 Characteristic impedance

The forward-mode characteristic impedance can then be defined by :

Zc ,Vc

Ic=

∣∣Vc

∣∣2Pc∗ =

Pc∣∣Ic∣∣2 (II.15)

II-4

II.2 Uniform waveguides

The equivalence of these expressions again demonstrates the analogy to elec-trical circuit theory. According to Brews, [II.4], Marks, [II.1], and Schelkunoff,[II.5], the equivalence of the three definitions of Zc follows from equation (II.13).The three definitions would in general be inconsistent if Pc, Vc and Ic were de-fined independently — for example, in terms of some power, voltage drop andcurrent in the waveguide — without regard to (II.13).

Zc is independent of the normalisation of the modal fields −→e and−→h which

affected |Pc |. While its magnitude does depend on the choice of either Vc orIc , its phase is independent of all normalisations. As pointed out by Brews,[II.6, II.4], the phase of the characteristic impedance Zc of the mode is a fixed,inherent and unambiguous property of the mode. Equations (II.14) and (II.15)constrain the sign of Zc such that :

Re(Zc) ≥ 0 (II.16)

In order to illustrate the close correspondence between this definition of Zc

and conventional definitions of the characteristic impedance, the special case ofTE, TM and TEM modes in homogeneous matter is considered. Each of thesehas fields which satisfy :

−→uz ×−→et = η−→ht (II.17)

where the wave impedance η is constant over the cross section. In this case,

Zc =

∣∣Vc

∣∣2∫S

∣∣−→et

∣∣2dS η (II.18)

Since the modal field−→et is normalised, the denominator is fixed. The magnitudeof Zc therefore depends only on Vc . However, the phase of the characteristicimpedance is equal to that of the wave impedance. This corresponds to mostconventional definitions.

For TEM modes, η is equal to the intrinsic wave impedance√µ/ε (u 377 Ω

in free space), with the result that :

arg(Zc) =1

2

[arg(µ)− arg(ε)

](II.19)

For example, if µ is real, then arg(Zc) = − 12 δ where tan δ , Im(ε)/Re(ε) is

the dielectric loss tangent. When Vc is chosen to be the voltage between theground and signal conductors, Zc is equal to the conventional TEM character-istic impedance.

II.2.5 Normalisation of waveguide voltage and current

Although the phase of either Vc or Ic can be chosen arbitrarily, the choice isof little significance. The important quantity is the phase relationship betweenVc and Ic , which, due to the constraint (II.13) and the fact that the phase of Pc

is fixed, is unalterable. The phase relationship between Vc and Ic is a uniqueproperty of the mode.

II-5

On-wafer characterisation at microwave frequencies

The magnitude of Zc is determined by the choice of Vc and Ic. Given theconstraint (II.13) and having selected a modal field normalisation, a value maybe assigned to only one of the two variables.

1. One useful normalisation defines the constant Vc by analogy to a voltageusing a line integral along the path L :

Vc = −

∫L

−→et −→ul dl (II.20)

The path L is confined to a single transverse plane. The integral doesnot in general represent a potential difference because it depends on thepath between a given pair of points.

2. Another widely used normalisation defines the constant Zc as the currentflowing along the axial direction in the principal conductor. The crosssection Scond lies in the transverse plane and its normal −→un points along−→uz .

Ic =

∫Scond

ε−→ez −→un dS (II.21)

The choice of either scheme 1 or 2 is purely a matter of convenience, dictatedby the type of waveguide considered and the applications which are envisioned.In particular, when dealing with small devices embedded in transmission lines,it is very useful to ensure that either the waveguide voltage V or the I correspondto the voltage or current experienced by these loads.

In the case of coplanar waveguides (CPW) on SOI substrates, the domi-nant propagation mode is of the TM type, in fact a quasi-TEM mode — seeappendix A. Marks pointed out in [II.1], that in such case, the integral in (II.20)depends only on the end-points, not on the path between them.

Considering loads embedded in a typical CPW on SOI, the normalisationscheme 1 seems more appropriate for shunt loads. The integration path L canindeed be chosen so that its end-points correspond to the “terminals” of theloads. In the case of a small shunt resistor, this will ensure that the measuredhigh-frequency conductance will correspond to the measured DC-value. Forseries loads, the scheme 2 is more appropriate for identical reasons. As thedominant propagation mode of the CPW is quasi-TEM, the difference in theamplitude of Zc resulting from scheme 1 or 2 may be expected to be relativelysmall. Typically around 5 %, [II.7].

II.2.6 Transmission line equivalent circuit

In analogy with classical transmission line theory it is possible to define a dis-tributed equivalent circuit for a single waveguide mode. Brews, [II.4], proposedto base the definition of the distributed immittances on the following equations :

Z ′σ , γ · Zc (II.22)

Y ′π , γ/Zc (II.23)

II-6

II.3 General waveguide circuit theory

These definitions allow to derive expressions of the distributed immittancesZ ′σ and Y ′π in terms of the modal fields −→e and

−→h . Details are presented in

appendix A.

II.3 General waveguide circuit theory

In this section, the previous results are applied to develop a waveguide cir-cuit theory. This theory will provide the tools necessary to describe the mi-crowave on-wafer measurement system. Travelling waves, pseudo-waves andpower waves are discussed first. Then the scattering and pseudo scatteringmatrices are introduced, followed by the transfer matrix and the impedancematrix. Finally, the transformation of reference impedance is investigated andthe question of the load impedance is discussed.

II.3.1 Travelling wave intensities

The forward and backward travelling waves are defined according to Marks andWilliams, [II.1], by normalising the forward and backward modes with respectto power :

ac ,√

Re(Pc)C+ e−γz =

√Re(Pc)

2 Vc

(V + Zc I

)(II.24a)

bc ,√

Re(Pc)C− e+γz =

√Re(Pc)

2 Vc

(V − Zc I

)(II.24b)

This normalisation ensures that, in the absence of the backward wave, the unitforward wave with ac = 1 carries unit power.

It can be shown that ac and bc are independent of the arbitrary normali-sation of Vc . While their phases depend on the phase of the modal field −→et inthe same way that C+ and C− do, ac and bc are independent of the magnitudeof −→et . This normalisation independence suggests that ac and bc are physicalwaves rather than simply mathematical artifacts.

Expressing the waveguide current and voltage in function of the travellingwaves ac and bc, one may then apply equation (II.12) to obtain the net realpower as a function of ac and bc :

V(z) =Vc√

Re(Pc)

(ac(z) + bc(z)

)(II.25)

I(z) =Ic√

Re(Pc)

(ac(z)− bc(z)

)(II.26)

Re(P(z)) = |ac(z)|2 − |bc(z)|2 + 2 Im(ac(z) bc∗(z))

Im(Zc)

Re(Zc)(II.27)

This demonstrates that the net real power crossing a reference plane is notequal to the difference of of the powers carried by the forward and backwardwaves acting independently, except when the characteristic impedance is realor when either ac or bc vanishes.

II-7

On-wafer characterisation at microwave frequencies

The reflection coefficient Γc is defined by :

Γc(z) , bc(z)

ac(z)(II.28)

It is related to the voltage standing wave ratio, VSWR, which is usually mea-sured by the slotted waveguide technique :

VSWR ,maxz

∣∣−→Et (z)∣∣

minz∣∣−→Et (z)

∣∣ =maxz

∣∣Vc(z)∣∣

minz∣∣Vc(z)

∣∣ =

∣∣ac

∣∣+∣∣bc

∣∣∣∣∣∣ac

∣∣− ∣∣bc

∣∣∣∣ =1 +

∣∣Γc

∣∣∣∣1− ∣∣Γc

∣∣∣∣ (II.29)

The reflection coefficient is however not a power reflection coefficient, and itmay exceed 1 if Zc is not purely real.

Particular values of Γc occur in the presence of a short circuit or of an opencircuit, defined, respectively, as a perfectly conducting wall, or a magneticwall, spanning the entire cross section of the waveguide. The conducting wallforces the tangential electric field to vanish at the reference plane and thereforerequires V = 0 and bc = −ac. As a result, the reflection coefficient of the shortis −1. The magnetic wall forces the tangential magnetic field to vanish andhence I = 0 and bc = ac. The reflection coefficient of the open is thus +1.

II.3.2 Pseudo-waves

A new set of parameters will now be introduced, the pseudo-waves, which incontrast to the travelling waves, are mathematical artifacts, but with ratherconvenient properties. Pseudo-waves are a formal generalisation of the travel-ling waves, based on the choice of an arbitrary reference impedance Zr , withthe sole stipulation that Re(Zr ) ≥ 0. According to Marks and Williams, [II.1],the complex pseudo-wave amplitudes can the be defined by :

a ,∣∣Vc

∣∣Vc

√Re(Zr )

2∣∣Zr

∣∣ (V + Zr I

)(II.30a)

b ,∣∣Vc

∣∣Vc

√Re(Zr )

2∣∣Zr

∣∣ (V − Zr I

)(II.30b)

These equations may be inverted and the real net power crossing a transverseplane evaluated in function of the newly defined parameters :

V =Vc∣∣Vc

∣∣∣∣Zr

∣∣√Re(Zr )

(a + b

)(II.31)

I =Vc∣∣Vc

∣∣∣∣Zr

∣∣√Re(Zr )

(a − b

)(II.32)

Re(P) = |a|2 − |b|2 + 2 Im(a b∗)Im(Zr )

Re(Zr )(II.33)

Comparing equations (II.24) and (II.30), one can see that a(Zr = Zc) =ac and b(Zr = Zc) = bc. Although the multiplicative factor in (II.30) is

II-8

II.3 General waveguide circuit theory

complicated, it is the only factor that satisfies this criterion and also ensuresthat a and b satisfy the simple power expression II.33.

Since pseudo-waves are equivalent to the actual travelling waves when thereference impedance is equal to the characteristic impedance of the mode, thisis the natural choice of reference impedance. On the other hand, it is notalways the most convenient choice. For instance, when Zc varies greatly withfrequency — as is the case for CPW on low-resistivity SOI substrates — theresulting measurements using Zr = Zc may be difficult to interpret; a constantZr may be preferable.

Another choice of reference impedance is in common use : that which makes(Zr ) vanish at a given point on the line. The primary effect of this choice of

Zr is to make the pseudo-reflection coefficient Γ , b/a vanish. As discussedlater in this chapter, several calibration schemes force the pseudo-reflectioncoefficient of some “standard” termination, usually a resistive load, to vanish.Those schemes thereby impose this particular choice of reference impedance.

Interestingly, the open and the short circuit, Ic = 0 and Vc = 0, respec-tively, result in pseudo-reflection coefficient values which are independent ofZr : Γopen = +1 and Γshort = −1.

II.3.3 Power-waves

In addition to the travelling waves and the pseudo-waves, other quantitiesmay be defined using linear combinations of V and I. A popular alternativeare the power-waves first introduced by Belevitch, [II.8, II.9], and revisited byKurokawa in his famous paper [II.10] :

a , V + Zp I

2√

Re(Zp)(II.34a)

b , V − Zp∗ I

2√

Re(Zp)(II.34b)

where Zp is the impedance of the “generator” — either source if turned on orsink if turned off — connected at the some waveguide port.

The power-waves were devised specifically to satisfy the following equationindependently of the value of Zp :

P , Re(V I∗) =∣∣a∣∣2 − ∣∣b∣∣2 (II.35)

where P is the net real power transfered at the port. Equation II.34 shows thatwhen V/I = Zp

∗, the quantity b vanishes. In other words when the generator

is conjugate matched to the loading waveguide circuit, P = Pav =∣∣a∣∣2. The

quantity a is thus an intensity corresponding to the available power of thegenerator, Pav .

When Zp is real, the power-waves reduce to pseudo-waves with Zr = Zp .Otherwise they do not coincide. The power-waves are not equal to the travellingwaves for any choice of Zp unless the characteristic impedance is real.

II-9

On-wafer characterisation at microwave frequencies

Power-waves have some peculiar properties. For instance, they are not aseasily connectable as pseudo-waves or current and voltage are. At the junc-tion of two identical waveguides characterised by their own inward referentialsystem, the continuity of the electric and magnetic fields must be imposed,translating into the following connection rules :

V1 = V2 (II.36)

I1 = −I2 (II.37)

b1 = a2 (II.38)

a1 = b2 (II.39)

For the power-waves, however, the continuity of the electric and magnetic fieldstranslates into the following awkward connection rules :[

b1

a1

]=

1∣∣Re(Zp)∣∣[

Re(Zp) Im(Zp)− Im(Zp) Re(Zp)

] [a2

b2

](II.40)

These counter-intuitive rules are related to the fact that the net power crossinga plane is not simply the difference of the power carried by the travelling wavesconsidered independently. When the port impedance Zp is real, the connectionrules coincide with those of the pseudo-waves.

Another remarkable peculiarity of the power-waves, is that their reflectioncoefficient Ξ , b/a is not generally equal to −1 in the case of a short circuit,V = 0, but rather :

Ξshort = −Zp∗

Zp(II.41)

These considerations illustrate the fact that power-waves are not a judiciousconcept to use when attempting to measure devices embedded in lossy waveg-uides which are characterised by a complex Zc. Marks and Williams developthe argument further in [II.1], stating that no specific calibration techniqueexist which allows direct measurement of power-waves and that modificationof existing calibration methods to measure power-waves rather than pseudo- ortravelling waves is not feasible. At present, the only method to measure apower-wave reflection coefficient is to deduce it from the pseudo-wave reflec-tion coefficient, provided the reference impedance is known. The impossibilityto measure directly the power-wave reflection coefficient, does not precludethe value of this concept as a design tool for microwave circuits, particularlyamplifiers and filters.

II.3.4 Load impedance

At a reference plane, at which only a single mode exists, the load impedance isdefined in terms of the waveguide voltage and current :

Zload ,V

I(II.42)

II-10

II.3 General waveguide circuit theory

The load impedance, like I and V is independent of the reference impedance.Unlike the result of low-frequency circuit theory, however, Zload is not a uniqueproperty of the one-port itself but instead depends on the fields of the modeincident upon it. Illumination of the same device by a different waveguide,or even a different mode of the same waveguide may result in a drasticallydifferent Zload . Zload also depends on the normalisation which determines Vc

and Ic for this affects V and I. Combining equations II.42, II.32 and II.31, theload impedance can be related to the reflection coefficient Γ :

Γload(Zr ) =Zload − Zr

Zload + Zr(II.43)

This equation may also be solved for Zload :

Zload = Zr1 + Γload(Zr )

1− Γload(Zr )(II.44)

This produces the same result regardless of the reference impedance with re-spect to which Γload is defined. If Zr is chosen equal to the characteristicimpedance Zc , these two equations become identical to those of ordinary waveg-uide circuit theory.

Equation (II.43) defines the reflection coefficient Γload as a bilinear trans-form of the normalised load impedance zload , Zload/Zr . Interesting propertiesof this class of transforms is that circles and lines — circles of infinite radius —in the plane of complex impedances zload are mapped onto circles in the com-plex reflection coefficient plane and vice-versa. Particular cases are Γload = 1which corresponds to the open circuit Zload = ∞, and Γload = −1 which cor-responds to the short circuit Zload = 0, both independently of the actual valueof Zr . These features form the basis of the Smith chart, where normalisedresistance and reactance loci are represented as circles or arcs.

In the case of complex port impedances, the expression of the power reflec-tion coefficient in function of the load impedance is not a bilinear transforma-tion of the normalised impedance zload , Zload/Zp :

Ξload(Zp) =Zload − Zp

∗

Zload + Zp(II.45)

This prohibits the application of the Smith chart and its associated constructsto the power reflection coefficient normalised to complex port impedances.

II.3.5 Scattering matrix for pseudo-waves

A linear waveguide circuit is considered which connects an arbitrary numberof (generally) non identical, uniform semi-infinite waveguides which are uncou-pled away from the junction. In each waveguide, a cross-sectional referenceplane is chosen at which only a single mode exists. If the mode of interest isdominant, this can be ensured by choosing the reference plane sufficiently farfrom the junction so that higher-order modes have decayed to insignificance.For each waveguide port i, a reference impedance is chosen Zr(i), in terms of

II-11

On-wafer characterisation at microwave frequencies

which the pseudo-wave amplitudes ai(Zr(i)) and bi(Zr(i)) at port i are definedby equations (II.30). The orientation is such that the “forward” direction is to-ward the junction. Column vectors are defined which contain the pseudo-waveamplitudes :

b =

b1

...bN

a =

a1

...aN

(II.46)

The vector of outgoing pseudo-waves b is linearly related to the vector of in-coming pseudo-waves a by the pseudo-scattering matrix S :

b = S a (II.47)

Although S depends on the choice of reference impedance at each port, explicitreference to this fact has been suppressed to simplify the notations.

Likewise, vectors containing incoming and outgoing travelling wave inten-sities, ac and bc, can be defined. These vectors are related by the (true)scattering matrix Sc :

bc = Sc ac (II.48)

If Zr(i) = Zc(i) for each port i, the S = Sc. In other words, the pseudo-scattering matrix is equal to the scattering matrix, when the reference impedanceat each port is chosen equal to the respective characteristic impedance. A typ-ical example is the scattering matrix of a waveguide section of length L :

S =

[0 e−γL

e−γL 0

](II.49)

The reflection coefficient Γc is the single elements scattering matrix S of aone-port.

II.3.6 Transfer matrix

In the case of a linear waveguide circuit possessing an even number of accessports, the transfer matrix can be defined. The definition relies on the classifi-cation of ports as input or output accesses, the number of inputs and outputsbeing equal. Let bi denote the vector of outgoing pseudo-waves at the inputports and bo the outgoing pseudo-waves at the output ports. ai and ao denotethe incoming pseudo-waves at the input and output ports, respectively. Thewave vectors at the input and output ports are then linearly related by thetransfer matrix : [

bi

ai

]= T

[ao

bo

](II.50)

In order to relate the transfer matrix T to the scattering matrix S, it is firtnecessary to ensure that this latter is properly organised:[

bi

bo

]= S

[ai

ao

]=

[Sii Sio

Soi Soo

] [ai

ao

](II.51)

II-12

II.3 General waveguide circuit theory

The transfer matrix T is then given by :

T =

[Sio − Sii S−1

oi Soo Sii S−1oi

−S−1oi Soo S−1

oi

](II.52)

The transfer matrix of a waveguide section of length L referred to the charac-teristic impedance Zc can be obtained from equation (II.49) above,

T =

[e−γL 0

0 e+γL

](II.53)

The transfer matrix of a cascade of compatible multi-port circuits is simplythe product of the individual transfer matrices as long as the connecting portsare composed of identical waveguides, with identical reference impedances,joined without discontinuity. The definition of the transfer matrix impliessome preferential forward direction, from the input ports to the output ports.A transfer matrix may equally well be defined in the opposite, reverse direction.Trev is however not equal to the inverse of Tfor :[

bi

ai

]= Tfor

[ao

bo

](II.54)[

bo

ao

]= Trev

[ai

bi

](II.55)

Trev =

[0 II 0

]T−1

for

[0 II 0

](II.56)

where 0 is the null matrix of dimension N2 ; I is the identity matrix of dimension

N2 ; N being the total number of ports.

II.3.7 Immittance matrices

The impedance matrix Z and the admittance matrix Y relate the column vec-tors V and I, whose elements are the waveguide voltages and currents at thevarious ports :

V = Z I (II.57)

I = Y V (II.58)

In contrast to S and T, Z and Y are independent of the reference impedancesince V and I are also. This makes them particularly interesting for metro-logical purposes. Also, most of the existing active device models are basedon predictions of charge and currents in function of applied voltages, so thattheir equivalent circuits are naturally formulated in terms of admittance orimpedance.

According to Marks and Williams, [II.1], the relation between Z and S is :

S = U(Z − Zr

)(Z + Zr

)−1U−1 (II.59)

II-13

On-wafer characterisation at microwave frequencies

and inversely :

Z =(I−U−1 S U

)−1(I + U−1 S U

)Zr (II.60)

Here Zr is a diagonal matrix whose elements are the Zr(i) and U is anotherdiagonal matrix defined by :

U , diag[∣∣Vc(i)

∣∣Vc(i)

√Re(Zr(i))∣∣Zr(i)

∣∣ ](II.61)

Marks and Williams claim that the factor U generalises previously publishedresults to problems including complex fields and reference impedances. Similarresults may be obtained for the admittance matrix Y, which is the inverse ofZ.

II.3.8 Change of reference impedance

As discussed earlier, the most convenient choice of reference impedance de-pends on the circumstances. In order to accommodate the various choices, therelationship between the pseudo-wave amplitudes based on different referenceimpedances is considered. By expressing a(Zrn) and b(Zrn) in terms of V andI using equation (II.30) and then V and I in terms of a(Zrm) and b(Zrm) usingequations (II.31) and (II.32), the following linear relationship can be obtained :

[a(Zrn)b(Zrn)

]= Qnm

[a(Zrm)b(Zrm)

](II.62a)

where the impedance transformation matrix is given by :

Qnm ,√

1− Im(Zrm)/Re(Zrm)

1− Im(Zrn)/Re(Zrn)

1

1− Γ2nm

[1 Γnm

Γnm 1

](II.62b)

Γnm ,Zrm − Zrn

Zrm + Zrn(II.62c)

Marks and Williams, [II.1], pointed out that (II.62) constitutes the exactexpression of a complex impedance transform. Pseudo-waves can hence be ac-curately referred to as impedance-transformed travelling waves. Interestingproperties of the transforms are that :

1. Two consecutive transforms can be represented as a single transform byfrom the initial to the final reference impedance by :

Qnm Qmp = Qnp (II.63)

2. The transform from a reference impedance to itself is represented by theidentity matrix :

Qnn = I (II.64)

II-14

II.4 Measurement set-up

3. As a result the inverse transformation is represented by :[Qnm

]−1= Qmn (II.65)

Equation (II.62) allows to evaluate the effect of the complex impedancetransformation on the reflection coefficient. The reflection coefficient is trans-formed by :

Γ(Zrn) =Γnm + Γ(Zrm)

1 + Γnm Γ(Zrm)(II.66)

This expression confirms the statement made previously that the reflection ofthe perfect short and open circuits is independent of the reference impedance.Γ(Zrm) = −1 indeed results in Γ(Zrn) = −1, and Γ(Zrm) = +1 in Γ(Zrn) = +1independently of Γnm. The unique status of the short and open is related totheir unique physical manifestation. A perfect match Γ(Zrm) = 0 results inΓ(Zrn) = Γnm. Conversely, if Γ(Zrm) = −Γnm then Γ(Zrn) = 0.

II.4 Measurement set-up

Figure II.1 shows the flow-chart of the on-wafer measurement setup. The vectornetwork analyser (VNA) is connected by 90 cm coaxial cables to the on-waferprobes which launch the signal in a coplanar waveguide structure on the SOIwafer. Reflected and transmitted signals from the device-under-test (DuT )travel back to the analyser, are picked-up by the directional couplers, detected,and normalised with respect to the emitted signal to give the raw S-parametersreadings.

Systematic errors. At 1.0 GHz, the wavelength in the coaxial cables is onthe order of 20 cm, so that signals travelling through the system experienceimportant phase-shifts. The total attenuation from the cabling and probes atthe same frequency lies around 1.0 dB. The signals are finally also affectedby multiple reflections caused by the connectors at the cables ends and thewaveguide transitions occurring inside the probes.

The combination of all these effects tend to mask the influence of the DuTon the raw VNA readings. The calibration methods developed in section II.5characterise the systematic errors of the measurement systems and allow tocorrect them. They are however constrained in their accuracy by hardwarelimitations such as the finite directivity of the couplers, the dynamic range ofthe receivers, the noise level, ..., which tend to put a lower bound on the level ofthe DuT signals which can be discriminated from parasitic system responses.

To keep the measurement accuracy to an acceptable level, it is of primaryimportance to limit the total attenuation of the measurement system as well asthe number of sources of signal reflections. In practice, this means the use of theshortest possible length of cable with the minimum number of interconnections.

II-15

On

-wafe

rch

ara

cte

risatio

nat

mic

row

ave

frequencie

sSOI Wafer

Wiltron 360B Vector Network Analyser

DuT

Probe Probe

CPW CPW

Coaxial Cable Coaxial Cable

Directional Couplers Directional Couplers

Matched Load

Source

Switch

Receiver Receiver Receiver Receiver

2 dB

90 cm, 3 dB

245 µm, 0.5dB 245 µm, 0.5 dB

90 cm, 3 dB

2 dB

aA←−

bB←−

aB−→

bA−→

b1←−

a1−→

a2←−

b2−→

Figure II.1: Flow-chart of the measurement setup. Line lengths and maximal attenuation (at 40 GHz) are given.

II-16

II.5 Calibration methods

Repeatability errors. Calibration schemes do not correct for random orrepeatability errors. The possible sources of such errors must be well controlled.The most delicate issue is, in the case of on-wafer probing, the repeatability ofthe signal launch from the probes to the coplanar waveguide.

Positioning : Horizontal position is important, as any offset of probeposition in the axial direction will translate into a similar offset of the ref-erence planes, which may significantly influence the apparent performance ofsmall devices. Using adequate positioning marks, it was possible to reducethe uncertainty in axial position below 10.0µm, probably around 5.0µm. Thislatter value translates into a 2.0 % uncertainty on the parasitic capacitances ofa typical MOSFET.

Contacts : A second important factor is the quality of the three contactsestablished by the probe with the metal of the CPW. In the case of an alu-minium metallisation, which is a rather soft material covered by a thin rigidoxide layer, the probe-tips must be able to cut through the oxide and establishcontact with the metal on a wide area. Narrow probe tips — below 5.0µm— tend to pierce through the metallisation and reach the underlying insula-tion layer. Skating motions induced by vibrations then repel the metal awayfrom the probe tips until the contact is broken. Carbonero et al., [II.11], haveshown that tungsten probe-tips making 20µm wide footprints are an adequatesolution for aluminium metallisations.

In order to obtain three simultaneous contacts of good quality — one forthe signal conductors, two for the ground — the planarity of the probe withrespect to the landing pads must be carefully checked. A mismatch in the resis-tance of the ground contacts can cause an unbalanced excitation of the CPW,generating unwanted modes and modifying the apparent value of the scatteringparameters. It has been experienced that a single deteriorated ground contact,hardly detectable by DC resistance measurements of an integrated short cir-cuit, modifies the apparent scattering parameters of that device substantially,in a way which recalls the influence of a large inductance.

II.5 Calibration methods

The most important VNA calibration methods will be reviewed in this section.Their characteristic features will be analysed in function of the specific needsof on-wafer measurements.

The purpose of calibration is to characterise the measurement apparatus interms of some model in order to be able to remove unwanted influences on themeasurements. VNA calibration methods characterise the network analysertogether with its cables and probes as a linear waveguide circuit, according tothe theory of section II.3. De-embedding techniques then allow to evaluate thescattering parameters of a device connected at the reference planes from themeasurements of the distant network analyser. For on-wafer characterisation,it is particularly interesting to able to locate the reference planes on the silicon

II-17

On-wafer characterisation at microwave frequencies

wafer as close as possible to the devices. This allows to remove probe-padparasitics from the device response by “absorbing” them into the measurementapparatus. Appending the probe-pads to the apparatus requires to have strictlyidentical pads for all devices, including the calibration structures.

This major constraint can practically only be met by implementing thecalibration structures with the adequate probe-pads in-situ on the wafer, inthe vicinity of the devices to be tested. This in order to reduce the variationof substrate and metallisation parameters to a minimum. Implementation ofcalibration structures to very strict absolute requirements in a CMOS SOI tech-nology is rather an utopia. A more realistic approach is to fabricate calibrationstructures that can be used as transfer standards. The notion of transfer stan-dard is taken here in the broad sense, meaning either structures characterisedwith respect to a master calibration or structures whose parameters may beaccurately determined a posteriori.

II.5.1 The transfer-matrix formalism

Several authors [II.12, II.13] have shown that, in the absence of leakage at thereference planes, the network analyser together with its cables and probes couldbe rigorously modelled by two transfer matrices, one for each port.[

bA

aA

]= TA

[b1

a1

] [b1

a1

]= TDuT

[a2

b2

] [bB

aB

]= TB

[a2

b2

](II.67)

The VNA is supposed to measure the waves bA and aA at its first port, and bB

and aB at its second. The VNA usually operates in two modes, the forward andthe reverse mode. In the forward mode, denoted by index “f”, the microwavesource is connected to port A, emitting a wave aAf . In the reverse mode denotedby index “r”, the microwave source is connected to port B, emitting a waveaBr . Due to the finite isolation of the internal switch some leakage will occur,so that aBf and aAr are rarely exactly zero. Combining the readings in theforward and the reverse mode, the basic measurement equation is obtained :[

bAf bAr

aAf aAr

]︸ ︷︷ ︸

,MA

= TA TDuT TB−1

[aBf aBr

bBf bBr

]︸ ︷︷ ︸

,MB

(II.68)

where TB−1 stands for the reverse transfer matrix at port B. It should benoted that :

• Equation (II.68) allows some level of indetermination in the error coeffi-cients. Indeed, multiplying TA and TB by the same scalar constant doesnot affect the result.

• Strictly speaking, equation (II.68) is only valid when the device-under-test, DuT , has a non zero forward transmission. It will be shown next howthis equation can be modified to be able to deal with double one-ports.

II-18

II.5 Calibration methods

Normalised error-boxes

In order to lift the indetermination on the error matrices TA and TB , thenormalised transfer matrix is introduced :

TX = tX tX tX ,[

tX11 tX12

tX21 1

](II.69)

The reverse normalised transfer matrix is defined as :

TX−1 =, 1

tXTX−1 (II.70)

These definitions allow to transform the measurement equation (II.68) into :

MA =tA

tBTA TDuT TB−1 MB (II.71)

Where it appears clearly that the level of the constants tA and tB can bechosen arbitrarily, as long as their ratio is kept equal to the value imposed bythe calibration.

Double one-ports

A double one-port is a two-port device with zero forward and reverse trans-mission. It will be shown below, that det(MB ) is in all cases proportional tothe forward S-parameter of the DuT , SDuT . This will allow to formulate amodified measurement equation which is valid in all situations.

Multiplying the equation (II.68) on both sides with the transposed adjoint

matrix of MB , denoted MB, yields :

MA MB =tA

tBTA TDuT TB−1 det(MB ) (II.72)

Other algebraic manipulations and the substitution of TDuT by its expressionsin S-parameters give :

tA

tBT−1

A MA MB T−1B−1 =

det(MB )

SDuT21

[− det(SDuT ) SDuT11

−SDuT22 1

](II.73)

This last equation clearly shows that, when non-zero, the forward transmissionis directly proportional to det(MB ). Looking at the flow-chart of the measure-ment setup, [II.14], one can see that if the DuT has no forward transmissionthen the apparent reflection coefficient at port B, ΓB , bB/aB , has a uniquevalue depending principally on the reflection coefficient seen at the DuT , bothin forward and in reverse mode. As result, det(MB ) is also zero.

The determinant of the readings matrix MB being at all times proportionalto SDuT , the modified measurement equation presented below is valid in allcases.

MA MB =tA

tBTA T′DuT TB−1 (II.74a)

where T′DuT , det(MB ) TDuT (II.74b)

II-19

On-wafer characterisation at microwave frequencies

De-embedding formula

Heuermann and Schiek published in [II.15] the following de-embedding formu-lae, which are robust and computationally quite efficient :

C , TA MA MB

[0 11 0

]TB

[0 11 0

](II.75a)

S11 =C12

C22(II.75b)

S12 =det(MA) det(TB)

C22(II.75c)

S21 =det(MB ) det(TA)

C22(II.75d)

S22 = −C21

C22(II.75e)

where the “·” denotes the transposed adjoint matrix.

II.5.2 SOLT procedure

The Open-Short-Load-Through calibration method is typically a transfer stan-dard method. Indeed the implementations of the calibration structures in aplanar technology are affected by significant parasitics which must be properlycharacterised as the SOLT method requires accurate knowledge of all reflectioncoefficients. The SOLT method has been used in the present work to extend thebandwidth of the calibration beyond the limits imposed by the TRL method— presented below. A TRL calibration was first performed, and the SOLTstructures were measured. An equivalent circuit was extracted and used topredict the characteristics of the SOLT independently of the bandwidth limitof TRL. This complicated procedure has however been rarely used, mainly be-cause validity of TRL was found to extend far enough below the recommendedlow-frequency limit.

The SOLT method proceeds in two steps : a single port calibration isperformed at each VNA port separately using the open, the short and the load;then a two-port calibration is obtained by combining the single-port correctionswith a coefficient deduced from the measurement of the through.

One-port calibration

The single port measurement is described by :

bX = ΛDuT aX bi = ΓDuT ai (II.76)

where Λ is the raw reading of the VNA at port X , and Γ is the pseudo-reflection coefficient to be determined. The measurement equation can finallybe constructed as follows :

ΛDuT =tX11 ΓDuT + tX12

tX21 ΓDuT + 1(II.77)

II-20

II.5 Calibration methods

This last equation clearly shows that the normalisation constants tA and tB donot influence the one-port measurement.

Using the measurements of the short, Λσ, the open, Λo and the load, Λλtogether with their known true characteristics, Γσ, Γo and Γλ, respectively, thecalibration equations may be formulated :Γσ 1 −Λσ Γσ

Γo 1 −Λo ΓoΓλ 1 −Λλ Γλ

tX11

tX12

tX21

=

ΛσΛoΛλ

(II.78)

Two-port calibration

When both VNAports are individually calibrated in reflection, their normalisedtransmission matrix is known. To be able to correct transmission measure-ments, the ratio of the scaling factors tA and tB must be determined.

Marks and Williams, [II.1, II.16] investigated the effects of the electro-magnetic reciprocity on the pseudo-scattering parameters. They concludedthat in all generality, the electro-magnetic reciprocity does not necessarily leadto symmetry of the scattering matrix; It does result in symmetry in some par-ticular cases, such as a junction with identical waveguides at all ports. Thescattering matrix of the through is thus symmetric, so that the determinant ofthe its transfer matrix det(Tτ ) is equal to 1. This property may be used todetermine tA/tB . From the two-port measurement equation (II.68),

det(MAτ ) =tA

tBdet(tA) det(Tτ )︸ ︷︷ ︸

=1

det(tB−1 ) det(MBτ ) (II.79)

and finally :

tA

tB=

det(MAτ ) det(tB)

det(MBτ ) det(tA)(II.80)

The index “τ” indicates measurements of the through structure.

II.5.3 TAN self-calibration procedures

The TAN method makes use of the redundancy of the calibration equations tocompensate for the partial knowledge of the characteristics of the calibrationstructures. This process, called self-calibration, consists in two steps : thedetermination of the true characteristics of the calibration structures, followedby the actual calibration of the system.

Calibration structures

Three structures are required : a through connection (T), a matched attenuatoror transmission line (A) and a symmetrical, not necessarily reciprocal, network(N). The TAN method thus postulates the following form for the scattering

II-21

On-wafer characterisation at microwave frequencies

and transfer matrices of the calibration structures :

Sτ =

[0 11 0

]Sα =

[0 Sαr

Sαf 0

]Sν =

[Rν Sνr

Sνf Rν

](II.81)

Tτ =

[1 00 1

]Tα =

[Sαr 00 S−1

αf

]Tν =

1

Sνf

[Sνf Sνr − R2

ν RνRν 1

](II.82)

where index τ stands for the through, index α for the attenuator or line andindex ν for the network. The consequences of these assumptions are the fol-lowing, [II.1, II.12] :

1. The expression of Sτ forces to have identical reference impedances at bothports. It also ensures that the reference planes are located in the middleof the section of transmission line serving as through connection.

2. The shape of Sα forces the reference impedance to be equal to the charac-teristic impedance of the line, or to some more complicated combinationof the parameters of the attenuator, [II.1]. If the α-structure is a pair ofidentical one-port loads, then Zr is set equal to the load impedance.

3. The ν-structure serves essentially to lift the indetermination on the ratiotA/tB .

The measurement equation (II.68) applied to the through-connection yields :

Nτ ,MAτ M−1Bτ =

tA

tBtA Tτ tB−1 =

tA

tBtA tB−1 (II.83)

For the attenuator and the ν-device, the modified measurement equation (II.74)is used in order to accommodate for a possible zero transmission :

N′α ,MAτ MBτ =tA

tBtA T′α tB−1 (II.84)

N′ν ,MAν MBν =tA

tBtA T′ν tB−1 (II.85)

where the modified transfer matrices are defined by :

T′α , det(MBα) Tα =

[S ′αr 00 S ′−1

αf

](II.86)

T′ν , det(MBν) Tν =1

S ′νf

[S ′νf S ′νr − R2

ν RνR ′ν 1

](II.87)

Determining the characteristics of the standards

Combining equations (II.84) and (II.85) with (II.83) to eliminate tB−1 yieldsthe following two equations :

N′α N−1τ = tA T′α t−1

A (II.88)

N′ν N−1τ = tA T′ν t−1

A (II.89)

II-22

II.5 Calibration methods

Multiplying these two equations a third useful equation is obtained :

N′α N−1τ N′ν N−1

τ = tA T′α T′ν t−1A (II.90)

These three equations show that the true characteristics of the calibrationstructures — on the right-hand side — are related to the measurements by asimilarity transform defined by matrix tA. The properties of such a transformare that the eigenvalues are conserved, as well as the determinant and thetrace. These features allow to determine the elements of T′α and T′ν from themeasured data without any knowledge of tA.

Equation (II.88) is particularly interesting in this respect, as it establishesthat the transmission characteristics of the α standard can be determined inde-pendently of any assumption on the error networks tA and tB . This equationcan be easily generalised to coupled lines or multi-mode propagation : eachof the propagation constant can be determined from the eigenvalues of themeasurement matrix !

Following the method outlined by Eul and Schiek in [II.15], a set of fiveequations is obtained allowing to determine the five unknowns :

θατ , trace(N′α N−1τ ) = trace(T′α) (II.91)

δατ , det(N′α N−1τ ) = det(T′α) (II.92)

θντ , trace(N′ν N−1τ ) = trace(T′ν) (II.93)

(II.94)

δντ , det(N′ν N−1τ ) = det(T′ν) (II.95)

θαντ , trace(N′α N−1τ N′ν N−1

τ ) = trace(T′α) (II.96)

The α-standard Solving equations (II.91) and (II.92) allows to determinethe transmission parameters of the α-structure :

S ′αr =θατ ±

√θ2ατ − 4 δατ2

(II.97)

S ′αf =1

θατ − S ′αr

(II.98)

If the magnitude of S ′αr is below a very small threshold, then the α-structure ismost probably a double one-port and a sign distinction for S ′αr is not necessary.In the alternative, the sign ambiguity on the root for the normalised inversetransmission S ′αr must be lifted.

1. If there are significant losses, then the right choice is the root which leadsto Sαr < 1 and Sαr < 1.

2. If the losses are expected to be small, then the root must be chosenaccording to an approximate knowledge of the electrical length of theα-device.

II-23

On-wafer characterisation at microwave frequencies

The ν-standard The remaining equations (II.94)–(II.96) yield :

S ′νf =1− S ′αf S ′αr

S ′αf

(θαντ − S ′αr θντ

) (II.99)

S ′νr = S ′νf δντ (II.100)

Rν = ±√

S ′νf

(S ′νr − θντ

)+ 1 (II.101)

The sign ambiguity in the third equation can be easily resolved using a prioriinformation on the phase of the reflection coefficient Rν .

Solving for the error coefficients

The resolution method shown below was published by Heuermann and Schiek,[II.15]. It is robust, in the sense that the set of equations never becomes sin-gular. Their original paper contains however several errors in the final systemof equations. All these errors have been corrected in the expressions below,which were extensively tested and verified, both by computer simulations andexperimentation.

The measurement equation (II.83) is solved for the product of the B errorcoefficients with the scaling factor :

tBtB

tA= N′−1

τ tA (II.102)

Substituting the results in equations (II.84) and (II.85), yields :

N′α N−1τ tA = tA T′α (II.103)

N′ν N−1τ tA = tA T′ν (II.104)

Only three equations are needed to determine the normalised coefficients forport A. From the set concerning the α-standard, the equations involving theforward and reverse transmission are used directly. From the set of equationsconcerning the ν-standard, the sum of the two equations being linear withrespect to the reflection coefficient is used.

Nατ11 + Nατ21 − S ′αr 0 Nατ12 + Nατ22 − S ′αr

0 Nατ11 + Nατ21 + S ′−1αf 0

−Rν S ′−1νf Nντ11 + Nντ21 + S ′−1

νf −Rν S ′−1νf

×

tA11

tA12

tA21

=

0S ′−1αf − Nατ12 − Nατ22

S ′−1νf − Nντ12 − Nντ22

(II.105)

where the following notations where used :

Nατ , N′α N−1τ Nντ , N′ν N−1

τ (II.106)

II-24

II.5 Calibration methods

Line

Short Open Through 50.0 Ω Resistor

Figure II.2: Calibration kit allowing to perform a TRL calibration and todetermine the reference impedance.

Practical applications

The TAN procedure described in the previous subsections is generic. Manypractical calibration procedures may be derived. The most wide-spread arethe TRL, Through-Line-Reflect and the TRM, Through-Match-Reflect. Someauthors prefer to substitute the “L” of line to the “T” of through.

The TRL calibration The method relies on the measurements of two linesections of different length and of a reflection element, which is usually anoffset-short or offset-open. The scattering matrix of the line, the α-standardand of the reflect, the ν-standard are given below :

Sα =

[0 e−γ (Lα−Lτ )

e−γ (Lα−Lτ ) 0

](II.107)

Sν =

[Γν e−γ (2Lν−Lτ ) 0

0 Γν e−γ (2Lν−Lτ)

](II.108)

Lτ and Lα are the physical line lengths measured from end to end, Lν isthe offset length, measured from the device itself to the end of the abuttingline. The propagation constant γ is a natural by-product of the calibrationmethod. This is allows to move the reference planes along the CPW, andhence compensate offset lengths.

Because of the finite length of the transmission lines, the method is band-limited. Indeed, in the absence of substantial losses, the system of equationscollapses at every frequency where the length difference is a multiple of half awavelength. The system is considered to be numerically sound when :

π

9≤ Im

(γ(Lα − Lτ

))− nπ ≤

8π

9where n ∈ N (II.109)

II-25

On-wafer characterisation at microwave frequencies

The TRL algorithm has been used intensively for the present work. Therequired calibration standards are easily implemented in a SOI CMOS tech-nology, even with a single metallisation level. The imperative constraint ofsymmetry for all calibration structures can be readily obeyed using a properlayout. Horizontal non-uniformity in the SOI substrate and contact repeata-bility were the principal problems encountered. To minimise the impact of asometimes poor contact repeatability, the reflect standard is implemented asa pair of open circuits. Open circuits are however very sensitive to the sub-strate parameters, so that non-uniformity becomes critical. The problem maybe avoided by presenting the same individual structure to both ports alterna-tively.

As indicated in the discussion about the calibration structures on page II-22,it is the line standard which sets the reference impedance in the TRL algorithm.The reference impedance Zr is set to the characteristic impedance Zc of theline. This latter is generally unknown, as it depends in a complex fashion onthe substrate parameters, several of which being not accurately known. It isthus necessary to find some means of determining the reference impedance inorder to be able to exploit the measurement results. Several original solutionsto this problem have been developed. They are described in section II.6 below.

The TRM calibration The method uses two identical broadband loads asα-standard to set the reference impedance. Eul and Schiek introduced thisscheme in [II.17], with the idea that resistors would mimic infinite transmissionlines, thereby resolving the bandwidth limitation of TRL. Resistors were fabri-cated and precisely trimmed to 50.0 Ω at DC, assuming that the load impedanceseen the by the coplanar waveguide at microwave frequencies would be equal tothis value. Williams and Marks, [II.18], warned against the inaccuracies result-ing from that assumption and proposed to model the resistor parasitics withan inductance which was determined with respect to a reference calibration.

The scattering matrices of the TRM standards have the following expres-sions :

Sα =

[0 00 0

]Sν =

[Γν e−γ (2Lν−Lτ )Γν 0

0 Γν e−γ (2Lν−Lτ )Γν

](II.110)

Major advantagse of the TRM method are that it requires only three cal-ibration structures which can all be compactly implemented, and that it isinherently broadband. The TRM method does not allow to determine thepropagation constant, so that the reference planes can not be moved.

TRM has never been used for in-situ calibrations on the SOI wafers. Themain reason is that to obtain a coherent calibration setting the referenc impedanceto some well defined value requires to fabricate a pair of identical resistors.Systematic DC resistance measurement of microwave resistors designed to benominally 50.0 Ω have shown that the discrepancies between matched resistorswere rarely lower than 5.0 % in the UCL technology. This was considered tobe too high to be tolerable for the TRM calibration. The discrepances are dueto the weak resistivity of the silicided polysilicon which was used as resistivematerial. Weak resistivity translated into narrow strip widths, the length of the

II-26

II.6 Reference impedance determination

resistor being fixed by the waveguide geometry. This narrow width renderedthe resistor very sensitive to lithographic process variations. A possible solu-tion would have been to measure a single resistor alternatively at both ports.This implies however a 180 degrees rotation of the wafer on the chuck wich isa cumbersome manipulation. TRL was finally found much more adequate.

TRM calibrations using standards on a commercial alumina substrate werenevertheless routinely applied as a preliminary to the in-situ TRL on SOI. Thepurpose of this calibration was mainly to locate the reference planes sufficientlyclose to the probe-tips to render fault detection easier during the measurementof the SOI calibration structures. The alumina TRM calibration eventuallyserved as reference calibration for the calibration comparison method devel-opped in section II.5.3.

II.6 Reference impedance determination

Accurate knowledge of the reference impedance of a scattering parameters cal-ibration is of primary importance. It is required in order to transform theS-parameters to impedance or admittance, which are the basic parameters forthe description of integrated active or passive devices. The presence of di-electric relaxation frequencies of the SOI substrate in the measurement bandcauses important variations of the characteristic impedance of CPW’s, whichin the case of a TRL calibration translate into important variations of thereference impedance. A proper scheme for the determination of the referenceimpedance is thus mandatory if one wants to exploit the results of an in-situTRL calibration.

II.6.1 Propagation constant measurement

Marks and Williams proposed in [II.19] to base the determination of the char-acteristic impedance of a CPW on the following equation :

Y ′π = G ′π + ω C ′π = γ/Zc (II.111)

On low-loss material, the conductance can be neglected with respect tothe susceptance, provided that the frequency is not so high that transversecurrents in the conductors become significant. Furthermore, taking advantageof the fact that the dominant mode of a CPW is of the quasi-TEM-type, theyproposed to compute C ′π theoretically from the waveguide dimensions usingthe quasi-static approximation. This allows to reduce the determination of thecharacteristic impedance to a propagation constant measurement.

As the propagation constant is a natural by-product of the TRL calibrationprocedure, the present method is very well suited to estimate the referenceimpedance of such a calibration. This approach is of course not suitable forlossy substrates such as low-resistivity SOI wafers, where the contribution ofG ′π is non-negligible. Furthermore, due to the layered structre of the SOIsubstrate, the capacitance C ′π varies importantly in the measurement band. Analternative scheme based on the distributed series impedance equation (II.22)

II-27

On-wafer characterisation at microwave frequencies

is also excluded not only because of the skin-effect, but also due to the dielectrictransitions of the substrate, see appendix A.

II.6.2 Load measurement

According to section II.3.4, the load impedance and the reflection coefficientare related by :

Zload = Zr1 + Γload

1− Γload(II.112)

= Zr zload (II.113)

To obtain the value of the reference impedance Zr , it is necessary to comparethe normalised impedance zload obtained from the scattering parameters, to theabsolute impedance value Zload measured according the appropriate primarydefinition : power-current, power-voltage or voltage-current. On MMIC’s athigh frequencies, voltage and current are not readily measurable, so that esti-mates of the load impedance must be obtained indirectly, by deduction fromother measurable quantities. Here, it is inferred from combined DC resistanceand scattering parameters measurements of a resistor, a short and an open.

It has been shown by Walker et al. [II.20], that the intrinsic resistance ofthin-film planar resistors can be reasonably considered not to vary with fre-quency from DC to 40 GHz. The parasitics involved in every practical reali-sation of the resistors are, however, well frequency dependent. In their paper,Walker et al. introduced an equivalent circuit model based on a parallel capac-itance and a series inductance, which allowed them to account for the parasiticeffects. Equation (II.114) shows the generic model proposed here, which gen-eralises the one from Walker et al., in the sense that no assumptions are madeon the behaviour of the parasitics, so that both substrate and conductor lossescan be included.

Zload(Ri) =Ri + Ze

1 + Ye (Ri + Ze)(II.114)

The parallel and series extrinsic parasitics, Ye and Ze , are estimated bycharacterising the open and the short derived from the resistor structure by,respectively, removing the thin-film conductive strip or replacing it with a goodconductor. Letting Ri tend accordingly to infinity or zero yields :

Zload(∞) =1

Ye, Zo (II.115)

Zload(0) =Ze

1 + Ye Ze, Zσ (II.116)

The absolute value for the intrinsic resistance Ri of the resistor is postulatedto be equal to the intrinsic resistance value obtained from DC measurementsof the three devices :

Riρ =Rρ(DC)Ro(DC)

Rρ(DC) −Ro(DC)−

Rσ(DC)Ro(DC)

Rσ(DC) −Ro(DC)(II.117)

II-28

II.6 Reference impedance determination

where index “ρ” indicates the resistor, index “o” the open and index “σ” theshort. On the other hand, at high frequency, the normalised value of the intrin-sic resistance, ri , can be deduced from the scattering parameters measurementsof the devices, using :

ri =zρ zo

zo − zρ−

zσ zo

zo − zσ(II.118)

Finally, the reference impedance is determined by relating equations (II.117)and (II.118) using equation (II.113) :

Zr =Ri

ri(II.119)

Validation

This procedure has been tested on a variety of substrates and compared totheoretical predictions and to other measurement-based methods. Figures II.3shows results obtained on a low-loss alumina substrate after calibrating theVNA system with the TRL algorithm. The impedance values resulting fromthe new method, Zc[new ], deviate over the whole band less than 2.0 % both fromthe values measured according to the method of Marks and Williams, [II.21],Zc[Marks], and from numerical predictions of the characteristic impedance forthe line standard according to Heinrich, [II.22], Zc[Heinrich]. The good agree-ment between Zc[Marks] and Zc[Heinrich] can be partly explained by the factthat the distributed capacitance required as input by the method of Marks andWilliams was deduced from the calculations by Heinrich.

Figure II.4 compares results obtained on lossy silicon substrates, after aVNA system calibration using the TRL procedure with standards fabricatedon the silicon wafer. Measurement results using the new method, Zc[new ],agree very well with theoretical predictions of the characteristic impedance byHuynen, [II.23], Zc[Huynen].

Discussion

The method described above determines primarily a reference impedance. Itcould be applied equally well to determine the reference impedance of a SOLT,a TRL or a TRM calibration. The examples shown above concern howeveronly TRL calibrations which impose the characteristic impedance as referenceimpedance.

As explained in section II.2.4, the magnitude of the characteristic impedanceZc is arbitrary, while its phase is a unique property of the propagation mode.The present load measurement method sets the magnitude of Zc by forcing DCand high-frequency measurements of the intrinsic resistance of a thin film resis-tor to coincide. The interesting feature is that at least some level of coherencebetween the DC and microwave measurements is ensured, provided that thecurrent density in the resistive strip has the same distribution at DC and RF.This will be the case if the strip is sufficiently resistive and has small transverse

II-29

On-wafer characterisation at microwave frequencies

0 10 20 30 40

−5

−4

−3

−2

−1

0

Im(Zr )

[GHz

]

[Ω]

Zr[Heinrich]

Zr[Marks]

Zr[new]

50

51

52

53

54

55

0 10 20 30 40

[Ω]

[GHz

]

Re(Zr )

Zr[Heinrich]

Zr[Marks]

Zr[new]

Figure II.3: Comparing various reference impedance determination methods inthe case of a CPW on low-loss alumina.

II-30

II.6 Reference impedance determination

[Ω]

[GHz

]

Re(Zr )

0

10

20

30

40

50

60

0 5 10 15 20 0 5 10 15 20

10

15

20

0

5

Im(Zr )

[GHz

]

[Ω]

Figure II.4: Comparing Zc[new ] (dotted lines) and Zc[Huynen] (solid lines), themeasured and the predicted characteristic impedance, respectively. The CPWwas fabricated on a SOI substrate having a resistivity of 20 Ω cm. .

dimensions so that skin-effect and lateral current-crowding are minimised. Thelongitudinal dimension must also be small in order to avoid distributed effectsinside the resistor.

Finally, one may wonder to which current or voltage normalisation schemethe extracted characteristic impedance corresponds best. Initial hints havebeen given in section II.2.5. It is not possible to say much more as the voltageand the current normalisation scheme proposed there do not result in importantvariations of the theoretically predicted Zc. The result of figure II.4 are basedon the voltage normalisation scheme.

II.6.3 Calibration comparison

Williams and Marks, [II.24], proposed the concept of calibration comparison.The idea is to apply two calibrations consecutively so that information can beextracted from the error matrix relating the two. The normalised measurementequation (II.71) after the first calibrations yields :

MA(1 ) MB(1) = TA(01 ) T′DuT(1 ) TB−1 (01 ) (II.120)

The second set of calibration standards is then measured, and the second cali-bration is applied, transforming the measurement equation into :

MA(2 ) MB(2) = TA(01 ) TA(12 ) T′DuT(2 ) TB−1 (12 ) TB−1 (12 ) (II.121)

The matrices TA(12 ) and TB−1 (12 ) describe the differences between calibra-tions 1 and 2. These differences are due to the use of different calibration stan-dards which may impose different reference impedances and reference planes.

II-31

On-wafer characterisation at microwave frequencies

Each set of standards may be implemented differently, on separate wafers. Ageneral model for the matrices TX (12 ) is the following :

TX (12 ) = TL−11

TYo︸ ︷︷ ︸→Zr1

Q12 TL2︸︷︷︸→Zr2

(II.122)

The matrix TL2 accounts for the length of transmission line separating theprobe from the reference planes of the second calibration. The matrix is referredto Zr2 . Q12 is the impedance transformation from reference impedance Zr2 toZr1 , the reference impedance of the first calibration. TYo account for the shuntload seen at the probe-tips when transferring the probes with calibration 1 ontothe substrate of calibration 2. This shunt load is typically due to differences insubstrate material and in CPW geometry. TL−1

1is the transfer matrix allowing

to rewind the reference plane of calibration 1 back to the probe tips. TL−11

and

TYo are referred to Zr1 .

TYo =

[1− Zr1 Yo

12 Zr1 Yo

− 12 Zr1 Yo 1 + Zr1 Yo

](II.123)

The expression for TYo shows that the influence of this matrix on TX (12 ) maybe neglected provided that Zr1 Yo 1, as TYo then tends towards the unitymatrix, I. This occurs when the calibration standards of both sets are suffi-ciently similar. This will be assumed to be true, for the sake of developmentsbelow.

Setting TYo = I in equation (II.122) and developping the expressions forthe transmission line matrices yields :

TX (12 ) = Q1c1

[e+γ L1 0

0 e−γ L1

]Qc1 1 Q12 Q2c2

[e−γ L2 0

0 e+γ L2

]Qc2 2

(II.124)

where the additional impedance transform matrices allow to switch from thereference impedance Zr to the characteristic impedance Zc for each line sec-tion. Exploiting the commutativity of the product of symmetric matrices andthe specific properties of the impedance transform allows to simplify equa-tion (II.124) into :

TX (12 ) = Q12

[e−γ (L2−L1) 0

0 e+γ (L2−L1)

](II.125)

Williams and Marks, [II.24], used equation (II.125) to extract estimates ofΓ12 allowing to relate both reference impedances according to the theory devel-opped in section II.3.8. Their result is however based on simplified expressionsassuming that the reference impedances are real. This assumption is too re-strictive for the needs of the present work, and a new expression was derivedfrom equations (II.62) and (II.125) allowing to determine Γ12 in the case of

II-32

II.6 Reference impedance determination

Im(Zr )[Ω]

[GHz

]0 10 20 30 40

−20

−10

0

10

20

[Ω]

[GHz

]

Re(Zr )

20

30

40

50

60

0 10 20 30 40

Figure II.5: Comparing the load measurement method (rings) and the cali-bration comparison method (crosses), applied without correcting for the shuntstub admittance.

II-33

On-wafer characterisation at microwave frequencies

complex reference impedances :

Γ12 = ±

√TX (12 )12 TX (12 )21

TX (12 )11 TX (12 )22= ±

√tX (12 )12 tX (12 )21

tX (12 )11(II.126)

where : Γ12 ,Zr2 − Zr1

Zr2 + Zr1(II.127)

Equation (II.126) allows to determine Zr1 if Zr2 is known or vice-versa,provided that the sign ambiguity can be lifted. The ambiguity can not beeasily resolved, unless one has some estimate of what the phase of Γ12 shouldbe. For example by building estimates of the unknown impedance Zr .

Discussion

This method has been compared to the load measurement method in the caseof a 20 Ω cm SOI substrate. The results presented in figure II.5, show that bothmethods agree well at low frequencies, while they diverge continuously whenthe frequency is increased. This divergence can be explained by the fact thatthe reference calibration used structures implemented on an alumina substrate,while the target calibration relied on the SOI structures shown in figure II.2,which have a different layout. As a consequence, the assumption of similarcalibration structures does not apply, and TYo 6= I induces an error on theestimation of Γ12 in (II.125).

Correct results will be obtained if Yo can be somehow estimated and cor-rected for in equation (II.122). This may be performed by measuring an adhocstructure — for example, the head to head connection of two identical openstubs, yielding Y = 2 Yo when measured with a probe-tip calibration. Theneed for this additional calibration structure is perceived as a disadvantage ofthe calibration comparison method. The application of the calibration compar-ison method is also somewhat complicated by the fact that when Zr1 and Zr2

are close to each other, Γ12 may experience many zero crossings requiring tobe careful about the sign to choose in equation (II.126). These considerationsexplain that the calibration comparison method was used only when resistorstructures were not available or unusable for the determination of the referenceimpedance according to subsection II.6.2.

II.7 De-embedding strategies

The organisation of the de-embedding process for on-wafer measurements willbe discussed here. It rarely consists in a single calibration mainly becauseof the metrology constraint of traceability. To make valid comparisons withmeasurements made elsewhere one is required to be able to relate his ownmeasurements to some master standard. In the case of on-wafer scatteringparameters measurements this can be done by using commercially availablecalibration kits which should be delivered with adequate correction factorsdetermined with respect to a master calibration — at present, suppliers ofcalibration kits all refer to the National Institute of Standards and Technology

II-34

II.7 De-embedding strategies

of the United States of America. These commercial calibration kits are usuallyfabricated on an alumina substrate with a thick gold metallisation.

To measure its own devices, a user must transfer the probes after calibrationon the standards substrate onto the wafer of interest. This wafer is generallynot alumina, but rather silicon or another semiconductor. The dimensions ofthe probe pads and of the waveguides are most probably also different. It isthus necessary to perform additional corrections to obtain the characteristicsof the DuT corresponding to its intended use in a future circuit. The mostwidespread approach is the immittance correction method described below.This method suffers several serious drawbacks, which have been avoided in thiswork by introducing an alternative approach : in-situ calibration.

II.7.1 Immittance corrections

This method was first proposed by van Wijnen for bipolar devices, [II.25]. Itwas later enhanced by Fraser, [II.26], and by Cho, [II.27]. The method is basedon the adoption of the equivalent circuit depicted in figure II.6 to describethe probing structure into which the DuT is embedded. Cho showed that allsix elements of the equivalent circuit can be determined from the measuredcharacteristics of three devices :

1. An open circuit, obtained by removing the DuT and leaving the linescorresponding to access nodes 1 and 2 open.

2. A short circuit, obtained by replacing the DuT by metal lines connectingall three access nodes together.

3. A through connection, obtained by replacing the DuT by a metal lineconnecting nodes 1 and 2 together, while node 3 is left dangling.

DuT

1 2

3

Port A Port B

Za1 Za2

Za3Ya1 Ya2

Ya3

Figure II.6: Equivalent circuit model for the immittance correction method.

The method is unable to determine the true characteristics of the threedevices used, so that ideal characteristics are assumed : There is no fringingcapacitance for the open ends, the metal lines of the short and through have

II-35

On-wafer characterisation at microwave frequencies

neither inductance nor resistance. These assumptions limit the applicabilityof the method to small device geometries where the parasitics of the shortand the through are negligible. These assumptions also result in a generaloverestimation of the corrections to apply which, in the case of transistors,may result in artificially high apparent values for several characteristics, suchas the current gain, as discovered by Kim, [II.28].

Finally, the model topology uses only two complex parameters to charac-terise the transition from the probe-tips to the device itself. The two remainingparameters, Ya3 and Za3 , account only for some parasitic coupling between in-put and output. The theory of the electro-magnetic reciprocity, [II.16], showsthat three complex parameters are generally required to model the passive two-port transition corresponding to a single set of probe-pads, accommodating oneprobe. The model of figure II.6 is thus an oversimplification which may notaccount properly for the characteristics of the probe-pads at high-frequencies.

II.7.2 In-situ calibration

To avoid the limitations imposed by restricted equivalent circuit topologies,a very general model is used, in agreement with the developments of subsec-tion II.6.3. This model, shown in figure II.7, is compatible with the rigorouscalibration methods described in section II.5, so that any of these algorithmsmay be used to determine TA(12 ) and TB(12 ), where index “1” refers to thealumina calibration and index “2” to the in-situ calibration on SOI.

DuT

1 2

3

Port A Port B

TA(12 ) TB(12 )

Figure II.7: Equivalent circuit model for the in-situ TRL calibration.

According to the discussion at the end of subsection II.5.3, the TRL methodis preferred and used in conjunction with a reference impedance determinationmethod. Both procedures use as sole calibration structures those shown infigure II.2, which are all implemented in the immediate vicinity of the DuT ’s,hence the name in-situ. Aside from the comprehensive model for the transitionsat port A and B, the in-situ TRL calibration has the advantage to be able tolocate the reference planes at precise positions along the CPW’s feeding thetest devices. This allows to minimise the input and output adjacent parasitics,while allowing to avoid the pitfall of overestimated corrections : The referenceplanes can always be located at some distance from the device themselves, sothat probe placement errors do not result in an incursion of the reference plane

II-36

II.8 Conclusion

inside the device region.

II.8 Conclusion

This chapter presented the rigorous framework which is the foundation of thescattering parameters measurements performed in this work. The main featurein the theory of Marks and Williams, [II.1], which proved essential for thedevelopment of the present work, is the ability to deal very generally withlossy waveguides. This allowed to consider the application of S-parameterscalibration techniques to the de-embedding of coplanar waveguide structuresfabricated with standard metallisation processes on any type of silicon material,either high- or low-resistivity.

In-situ calibration was introduced as an efficient and reliable de-embeddingstrategy, remedying to the limitations of the widely used immittance correctionmethod. The error-model associated with S-parameters calibration techniquessuch as the SOLT, the TRM or the TRL, is indeed more general, providing anincreased flexibility in the design of the probing structure. Furthermore, theTRL calibration algorithm has the ability to locate the reference planes of themeasurements precisely at an arbitrary position along the feeding waveguide,minimising the risk of overestimated corrections which is the major drawbackof the immittance correction approach.

Two original solutions were presented for the determination of the referenceimpedance of S-parameters calibrations on lossy substrates : the load measure-ment method and the calibration comparison method. Accurate determinationof the reference impedance is indeed mandatory if one wants to exploit theresults of a TRL calibration, as this calibration sets the reference impedanceequal to the characteristic impedance of the CPW, which is generally unknowna priori.

The load measurement method proceeds by comparison of the DC and RFcharacteristics of a resistor, while the calibration comparison method extractsinformation about the impedance transform from the T-matrices relating twosuccessive calibrations. The load measurement method was found to be moreflexible, allowing more freedom in the design of the probing structure. Bothmethods were extensively tested and validated by a long series of measurementsat the microwave laboratory of the UCL.

References

[II.1] R. B. Marks and D. F. Williams, “A general waveguide circuit theory,”J. Res. of the Natl Inst. Stand. and Technol., vol. 97, pp. 533–562,Sep–Oct 1992.

[II.2] A. Vander Vorst and D. Vanhoenacker, Bases de l’ingenierie micro-onde. Bruxelles: De Boeck Universite, 1996.

[II.3] R. E. Collin, Foundations for microwave engineering. Mc Graw-Hill,second ed., 1992.

II-37

On-wafer characterisation at microwave frequencies

[II.4] J. R. Brews, “Transmission line models for lossy waveguide intercon-nections on VLSI,” IEEE Trans. on Electron Devices, vol. 33, pp. 1356–1365, Oct. 1986.

[II.5] S. A. Schelkunoff, “Impedance concept in wave guides,” Quart. Appl.Math., vol. 2, pp. 1–14, 1944.

[II.6] J. Brews, “Characteristic impedance of microstrip lines,” IEEE Trans.on Microwave Theory and Techniques, vol. 35, pp. 30–34, Jan. 1987.

[II.7] F.-M. Plennevaux and I. Huynen, “Evolution de l’impedance car-acteristique d’une micro-ruban,” tech. rep., Universite catholique deLouvain, Apr. 1997.

[II.8] V. Belevitch, “Transmission losses in 2n-terminal networks,” J. of Appl.Phys., vol. 19, pp. 636–638, July 1948.

[II.9] V. Belevitch, Theorie des Circuits de Telecommunication. Libr. Univ.de Louvain, 1954.

[II.10] K. Kurokawa, “Power waves and the scattering matrix,” IEEE Trans.on Microwave Theory and Techniques, vol. 49, pp. 194–202, Mar. 1965.

[II.11] J.-L. Carbonero, G. Morin, and B. Cabon, “Comparison betweenberyllium-copper and tungsten high frequency air coplanar probes,”IEEE Trans. on Microwave Theory and Techniques, vol. 43, pp. 2786–2793, Dec. 1995.

[II.12] H. J. Eul and B. Schiek, “A generalized theory and new calibrationprocedures for network analyser self-calibration,” IEEE Trans. on Mi-crowave Theory and Techniques, vol. 39, pp. 724–731, Apr. 1991.

[II.13] D. Rytting, “An analysis of vector measurement accuracy enhancementtechniques,” application note, Hewlett Packard, 1982.

[II.14] Witron Co., 360B Vector Network Analyser Manual.

[II.15] H. Heuermann and B. Schiek, “Robust algorithms for txx network an-alyzer self-calibration procedures,” IEEE Trans. on Instrumentationand Measurement, vol. 43, pp. 18–22, Feb. 1994.

[II.16] D. F. Williams and R. B. Marks, “Reciprocity relations in waveg-uide junctions,” IEEE Microwave and Guided Waves Letters, vol. 41,pp. 1105–1110, June 1993.

[II.17] H. J. Eul and B. Schiek, “Thru-Match-Reflect : One result of a rigoroustheory for de-embedding and network analyser calibration,” in 18th Eu-ropean Microwave Conference Digest, (Stockholm), pp. 909–914, Sept.1988.

[II.18] D. F. Williams and R. B. Marks, “LRM probe-tip calibrations us-ing non-ideal standards,” IEEE Microwave and Guided Waves Letters,vol. 43, pp. 466–469, Feb. 1995.

II-38

REFERENCES

[II.19] R. B. Marks and D. F. Williams, “Characteristic impedance determina-tion using propagation constant measurement,” IEEE Microwave andGuided Waves Letters, vol. 1, June 1991.

[II.20] D. K. Walker, D. F. Williams, and J. M. Morgan, “Planar resistors forprobe station calibration,” in 40th ARFTG Conference Digest, pp. 1–7,Dec. 1992.

[II.21] R. B. Marks, “A multiline method of network analyser calibration,”IEEE Trans. on Microwave Theory and Techniques, vol. 39, pp. 1205–1215, July 1991.

[II.22] W. Heinrich, “Full-wave analysis of conductor losses on mmic transmis-sion lines,” IEEE Trans. on Microwave Theory and Techniques, vol. 38,Oct. 1990.

[II.23] I. Huynen and B. Stockbroeckx, “Variational principles compete withnumerical iterative methods for analyzing distributed electromagneticstructures,” in Proceedings of the NUMELEC’97 Conference, (Lyon,France), pp. 19–21, Mar. 1997.

[II.24] D. F. Williams, R. B. Marks, and A. Davidson, “Comparison of on-wafer calibrations,” in 38th ARFTG Conference Digest, pp. 68–81, Dec.1991.

[II.25] P. J. van Wijnen, H. R. Claessen, and E. A. Wolsheimer, “A newstraightforward calibration and correction procedure for on-wafer highfrequency S-parameters measurements (45 MHz - 18 GHz),” in IEEE1987 Bipolar Circuits and Technology Meeting, 1987.

[II.26] A. Fraser, R. Gleason, and E. W. Strid, “GHz on-silicon-wafer probingcalibration methods,” in IEEE 1988 Bipolar Circuits and TechnologyMeeting, 1988.

[II.27] H. Cho and D. Burk, “A three-step method for the de-embedding ofhigh-frequency s-parameters measurements,” IEEE Trans. on ElectronDevices, vol. 38, pp. 1371–1375, June 1991.

[II.28] C.-H. Kim, C. S. Kim, H. K. Yu, and K. S. Nam, “An isolated-open pat-tern to de-embed pad parasitics,” IEEE Microwave and Guided WavesLetters, vol. 8, pp. 96–98, Feb. 1998.

II-39

Chapter III

Modelling fully depletedSOI MOSFET’s

III.1 Introduction

This chapter describes the development of a model for the SOI MOSFET, ded-icated to the simulation and design of analogue microwave circuits. To attainthe level of computational efficiency required in circuit simulators, simplifyingassumptions are needed which allow to formulate the model as a set of explicitanalytical expressions. As many other successful MOSFET models, the modeldetailed below relies on the charge-sheet and gradual channel approximationsfor the development of its fundamental expressions. These assumptions are,strictly speaking, only applicable to long-channel devices operating in the linearregime. Microwave MOSFET’s, on the other hand, are typically short chan-nel devices operated in saturation in order to obtain the desired high-frequencyperformances. Several model enhancements will be proposed allowing to extendthe applicability of the basic charge-sheet model to short-channel devices : Amodification of the threshold voltage accounting for the Drain Induced BarrierLowering effect and a semi-analytical model of the saturation region accountingfor the channel length modulation effect.

Various important microwave circuits such as mixers and oscillators, operatein large signal conditions, with transistors being driven across several operatingregimes. To deal with such cases, the model relies on infinitely derivable inter-polation functions to ensure smooth transitions of the characteristics betweenseveral operating regimes. Two such interpolation functions are introduced :one for the inversion charge density, allowing to predict both the weak andstrong inversion characteristics with a single mathematical expression, and a

III-1

Modelling fully depleted SOI MOSFET’s

second interpolation function controlling the transition between the linear andthe saturated operating regimes.

The most original contributions contained in this chapter concern the dy-namic aspects of the transistor behaviour at microwave frequencies. An al-ternative formulation of the charge model is proposed which better accountsfor the distribution of dynamic currents inside the SOI MOSFET than theconventional model which was initially intended for bulk devices. This alterna-tive charge model is then generalised into a multi-section channel model whichallows to simulate charging delays occurring in the channel at microwave fre-quencies. The dispersive behaviour of the interface traps, which react onlyto low-frequency stimuli, is correctly rendered thanks to the introduction ofdedicated state-variables representing the charging level of the traps. Finally,an elaborate substrate coupling model is presented, which reproduces the be-haviour of the SOI structure in a very wide band around its dielectric relaxationfrequencies.

This chapter covers the elaboration of the MOSFET model in detail, start-ing from the fundamental equations, pointing at underlying assumptions andworking towards the evaluation of the macroscopic quantities used to representthe device in circuit simulators : terminal currents and charges. This com-prehensive approach facilitates the assessment of basic model limitations andgives direct insight in the relationship between macroscopic model concepts —threshold voltage, inversion charge, ... — and microscopic concepts such asthose used in device simulators — carrier densities, electric field distributions,etc. Comparison of model predictions with measurements will be avoided here,as chapter IV is entirely devoted to parameter extraction and model validation.

The present chapter is thus organised as follows :

• After a brief description of the device structure and its operation modes,the present section discusses the modelling needs which are translatedinto specific modelling objectives.

• Section III.2 presents the development of a charge-sheet model with aspecial attention devoted to bidimensional effects and the dispersive be-haviour of the interface states.

• Section III.3 introduces the transport equations to obtain an expressionof the static conduction current.

• Section III.4 deals with the quasi-static evaluation of dynamic currentsand proposes a new topology of the charge model which is better suitedfor the SOI MOSFET.

• Section III.5 presents several original schemes allowing to extend the ap-plicability of the quasi-static current and charge expressions to higherfrequencies where non-quasi-static effects become important.

• Section III.6 completes the modelling task by presenting a global equiva-lent circuit accounting for both the useful and the parasitic effects whichinfluence the device response at microwave frequencies.

III-2

III.1 Introduction

• Section III.7 reviews the limitations of the model in terms of layout di-mensions, biasing conditions and frequency range.

III.1.1 The SOI MOSFET structure

Figure III.1 depicts the cross-section of a typical SOI MOSFET device. As ex-plained in the introductory chapter, the MOS transistor is fabricated in a thincrystalline film on top of an oxide layer which isolates it from the wafer sub-strate. Metal interconnections with contact to the source and drain diffusionsare also shown.

Polysilicon (Gate)

Silicide (Source)

p silicon (Film)

Silicide (Gate)

Diffusion (Source)

p− silicon (Substrate)

Passivation oxide

Metal (Drain)

Field oxide

Gate oxide

Buried oxide

Figure III.1: The SOI MOSFET structure

The device presented here is an enhancement n-channel MOSFET. Due tothe higher mobility of electrons, n-channel transistors have better performanceat high-frequencies, and these devices will most probably constitute the core ofcircuits designed for microwave operation. For this reason, the present chapterconcentrates exclusively on n-channel enhancement MOSFET’s. The comple-mentary transistor in the SOI CMOS technology of the micro-electronics labo-ratory of the UCL is an accumulation p-channel device. Far less has been pub-lished about the modelling of accumulation devices as for enhancement devices.However, a static current and charge model of the accumulation transistor isunder development at the micro-electronics laboratory and all refinements pre-sented in the present chapter for high-frequency, short-channel n-MOSFET’scould be transposed to it.

III.1.2 Operating modes of the generic SOI MOSFETstructure

The operating modes of the generic SOI structure have been extensively studiedby Flandre in [III.1]. The four most important ones for enhancement MOS-FET’s are illustrated here for convenience. The figure shows the profile of theelectric potential across the film, with respect to the Fermi potential, φF . Thefirst mode is characteristic of thick film SOI devices which are partially depleted

III-3

Modelling fully depleted SOI MOSFET’s

VGf

ψsf

ψsb

VGb

φF φF φF φF

1. 2. 3. 4.

Gate

Oxide

Si film

Oxide

Substrate

Figure III.2: Operating modes of the SOI MOSFET. Horizontally, the poten-tial. Vertically, the position in the SOI structure.

in normal operation. The three other modes are more specific to fully depleted,thin-film devices in normal operating conditions.

1. A quasi-neutral exists at the centre of the film, which decouples the frontand back depletion regions. The front and back interface are inverted.The structure behaves as two back-to-back bulk-MOS devices.

2. A coupling exists between the front and back depletion regions and bothinterfaces are inverted.

3. The front surface is inverted, the depletion regions spans across the wholefilm and the back surface is depleted.

4. The front surface is inverted, the back surface is accumulated.

A single SOI transistor can be forced into all four of regimes by applyingsuitable bias voltages to the front and back gates, but the natural condition isconsidered to be the one occurring at VGf = 0 = VGb .

III.1.3 Thin-film SOI MOSFET’s

In the case of sufficiently thin films, the coupling between the front and the backdepletion regions always exists, so that only the operating modes listed aboveunder (2–4) need to be considered. The fully-depleted mode (3) is the mostfavourable one. The body-factor and the sub-threshold slope are then close toideal and the normal electric field at the front interface is reduced comparedto the other modes, allowing higher mobility in the inversion channel. Thesefeatures allow fully depleted SOI MOSFET’s to show very good performances,as explained by Colinge in his book, [III.2]. Accordingly, the remainder of thiswork is devoted to thin-film, fully depleted MOSdevices.

III-4

III.1 Introduction

III.1.4 Splitting the device in intrinsic and extrinsic re-gions

In order to simplify the modelling task, the various phenomena governing thebehaviour of the MOSFET are considered separately, identifying the regionswhere each dominates and neglecting eventual weak interactions between them.Applying this ”divide et impera”, one is lead to consider the region where theuseful effect originates : The intrinsic region which encloses the semiconduc-tor film, and is horizontally delimited by the source and drain diffusions, andvertically by the front and back gates. This region is modelled by currentsand charges, which can be expressed as non-linear functions of the controllingvoltages, so that the corresponding small-signal equivalent-circuit elements arebias-dependent. The complementary effects are then termed extrinsic, as theycan generally be located around (outside) the intrinsic region. They are theoverlap capacitances, the diffusion resistances, the gate resistance, etc. Mostof these effects can be modelled using linear circuit elements.

III.1.5 Requirements for a good MOSFET model foranalogue circuit design

In an interesting paper, [III.3], Tsividis and Suyama reviewed the most currentshort-comings of MOSFET models, and proposed a set of guidelines applicableto new models for analogue circuit design. According to them,

”The ideal model should :

1. meet common requirements for digital work, such as reasonable I-V char-acteristic accuracy, ..., charge conservation, etc;

2. give accurate values for all small-signal quantities such as transconduc-tances and capacitances. In particular, all of these parameters should becontinuous with respect to any terminal voltage;

3. give good results even when the device operates non- quasi-staticly, or atleast degrade gracefully for such operation, as frequency is increased;

4. give accurate predictions for both white noise and 1/f noise, including inthe triode region;

5. meet requirements 1–3 above over large bias ranges, including when non-zero back gate voltage, and encompassing the weak, moderate and stronginversion regions;

6. do all of the above over the temperature range of interest;

7. do all of the above for any combination of channel width and length valuesfor a given technology;

8. require the user to specify the geometrical dimension for each device, andone set of model parameters valid for all devices of the same type andindependent of dimensions;

III-5

Modelling fully depleted SOI MOSFET’s

9. provide a flag every time an attempt is made to use it outside of its limitsof validity;

10. have as few parameters as possible (but just enough), and those param-eters should be linked as strongly as possible to the ones related to thedevice structure and fabrication process;

11. be linked to an efficient and simple parameter extraction method requiringas few test devices and test points as possible;

12. provide links to device simulators.”

This work does not attempt to meet the above requirements in all generality,but rather tries to focus on the aspects which are specific to SOI MOSFET’soperating in RF front-ends of portable communications equipment.

Microwave operation at low-voltage, low-power

To obtain useful gain at microwave frequencies, short-channel transistors mustbe considered. Accurate modelling of short-channel effects on both the currentand the charges is thus mandatory.

Although carrier transit-times as small as a few picoseconds can be achievedin short-channel devices driven strongly into saturation, channel propagationdelays nevertheless have a significant influence on the microwave performanceof the device in the majority of biasing conditions. The need for adequate non-quasi-static extensions of the model can be further explained by an increasedvisibility of the non-quasi-static effects due to the drastic reduction of the gate,source and drain resistances by the silicidation steps.

Finally, low-voltage operation requires proper modelling of weak and mod-erate inversion characteristics, which are more sensitive to the back-gate biasconditions.

Nonlinear behaviour

To model the nonlinear behaviour of the device at DC and at high-frequencycoherently, it is necessary to account for the dispersive character of some phys-ical phenomena. Indeed, such processes as self-heating or dynamic thresholdvoltage variations due to interface states exhibit time-constants in excess of100 microseconds. Such large time-constants render these processes essentiallyinactive at microwave frequencies, while still allowing a response to slow (DC)stimuli. To develop a unified model capable of accurate predictions of boththe DC and RF device characteristics, it is necessary to account properly forthe time-constants governing the dispersive processes by introducing additionalstate-variables such as the temperature or the occupation level of the interfacestates.

The purpose of nonlinear modelling is the prediction of mixing and inter-modulation products in mixers, of the level of harmonics in oscillators, of thegain-compression in amplifiers, etc. For most of these applications it is neces-sary to produce good estimates of the higher-order derivatives of the current

III-6

III.2 Charge-sheet models for the intrinsic device

and charges versus the terminal voltages. Mixing products, for example, de-pend upon the second-order derivatives, while inter-modulation products in-volve at least the third-order derivatives. The continuity of all current- andcharge-voltage characteristics, as well as of all their derivatives is thus a veryimportant requirement for the model, together with the ability to reproduce themeasured characteristics with sufficient accuracy, including even their higherorder derivatives.

Parameter extraction - Noise modelling - Statistical modelling

As indicated by Tsividis and Suyama it is important to devise models basedon physical considerations and to avoid introducing purely empirical param-eters. Having model parameters which can be related to physical propertiesof the materials helps not only to reduce the number of unknowns, but alsoallows to formulate bounds which are very useful when using an optimiser toperform parameter extraction. Additionally, a physical framework favours thedevelopment of model enhancements, such as the ability to predict noise orto evaluate the influence of statistical variations. Extraction procedures usingan optimiser require many evaluations of the model responses to compute theerror functions and their derivatives. It is highly desirable to have an efficientimplementation of the model in order to avoid that the extraction procedurebecomes prohibitively time- consuming. It is also very important to have awell-behaved program, which is able to handle extreme cases nicely, in orderto avoid the waste of computation time which would result from aborting theexecution because of one single irrealistic test-point chosen by the optimiser.

III.2 Charge-sheet models for the intrinsic de-

vice

In static operation, the intrinsic SOI MOSFET structure can be considered tobe two-dimensional. The polysilicon gate strip behaves as an equipotential,because it does not support any charging current. The diffusions are laterallyequipotential too, as they are connected at regular intervals to metal linesrunning parallel to the gate strip.

However, this first level of simplification does not allow an analytical treat-ment of sufficient generality, and fails to produce the framework required todevise efficient numerical models for circuit simulation. Solutions of the 2DPoisson equation in restricted operating conditions have been reported, as e.g.,for sub-threshold conduction, by Agrawal et al., in [III.4]. Even in that casethe resolution of a set of transcendental equations is required, which representsa heavy numerical burden. To make the problem analytically tractable in thecase of the bulk MOSFET, Brews, [III.5], suggested to combine the followingtwo additional assumptions :

1. The gradual channel approximation, which states that the longitudinalcomponent of the electric field, responsible for carrier motion in the chan-

III-7

Modelling fully depleted SOI MOSFET’s

nel region, is much smaller than the transverse component, so that thesurface potential can be evaluated using the 1D Poisson equation.

2. The charge-sheet approximation states that the thickness of the inversionregion is infinitely small, and allows to simplify considerably the evalua-tion of the inversion charge, as described by Tsividis in [III.6].

These two assumptions form the foundation of the modelling approachwhich is used here. Strictly speaking, they are only applicable to long-channeldevices operating in the triode mode or being slightly saturated. Several meansof extending the validity of the expressions to short-channel devices and theirspecific behaviour will be introduced. It will be shown additionally how re-sponses to time-varying excitations can be evaluated using the (quasi-) staticmodel.

III.2.1 Surface potential and charge density equations

When studying SOI films, the potential reference is conveniently chosen equalto the level of the source-diffusion. Combined with the fact that at thermalequilibrium the source sets the Fermi-level of the film, this choice allows towrite concise carrier densities expressions.

VGf

VS VD

VGb

OX

OY

Gate width : L

Gate oxide thickn. : tof

Film thickn. : tb

Buried oxide thickn. : tob

Figure III.3: Idealised geometry of the SOI MOSFET structure, showing thedefinition of the geometrical parameters.

Electric field

In agreement with the gradual channel approximation, a single section of theSOI MOSFET structure at some point along OX is considered. Gauss’law isapplied to the region enclosing the front gate-oxide, so that a first equation is

III-8

III.2 Charge-sheet models for the intrinsic device

obtained relating the electric field and the potential at the front interface ofthe SOI film, Esf and ψsf , respectively, to the potential of the gate, VGf :

C′′of (VGf −∆W f − ψsf ) +Q′′of +Q′′if (ψsf ) = εSi Esf (III.1)

where C ′′of is the front oxide capacitance per unit area.A similar procedure at the back of the film yields a relationship between

the back gate potential, VGb , the electric field at the interface with the backoxide, Esb , and the corresponding potential, ψsb :

C′′ob (VGb −∆W b − ψsb) +Q′′ob + Q′′ib(ψsb) = −εSi Esb (III.2)

Q′′of and Q′′ob are effective charge densities located at the interfaces andaccounting for the total fixed charge trapped in the oxide layers. Q′′if and Q′′ibrepresent the variable charge stored in surface states or in oxide traps locatedin the immediate vicinity of the Si–SiO2 interfaces . The occupation level ofthese interface traps is controlled by the surface potential. To account properlyfor the time-constants involved in the trapping mechanisms, Q′′if and Q′′ib areconsidered as additional state variables, the behaviour of which is governed bya specific model that will be developed in a following section.

Carrier densities

In a semiconductor material at thermal equilibrium, the electrons concentrationn and the holes concentration p are governed by the following equations :

n = ni exp(EF − Ei

kT

)(III.3)

p = ni exp(Ei − EF

kT

)(III.4)

where EF is the Fermi level and Ei = (Ev + Ec) /2 is the intrinsic energy level,half-way between the valence and the conduction band. In the absence of anyexternally applied electric field (at Ei = Ei0 ), the material is neutral, and themobile carriers must compensate for the charge density of the acceptor ions,Na :

Na = p0 − n0 (III.5)

When a vertical electric field is present, the carrier concentrations change,and are given at thermal equilibrium by the next pair of equations, whereφF = (Ei0 − EF ) is the Fermi potential in the absence of electric field, φT isthe thermal voltage (k T/q) and ψ is the electric potential :

n = ni exp(ψ − φF

φT

)(III.6)

p = ni exp(φF − ψ

φT

)(III.7)

When the SOI MOSFET is turned on, the silicon film is not in thermalequilibrium anymore, and the above equations have to be modified. Non-equilibrium conditions are introduced into the equations using different Fermi

III-9

Modelling fully depleted SOI MOSFET’s

levels for electrons and holes. For an n-channel fully-depleted SOI MOSFET,the contribution of holes to the current is negligible with respect to that ofthe electrons, so that, according to Mallikarjun and Bhat [III.7], the quasi-Fermi level of the holes can be assumed to be constant across the film andequal to the Fermi-level in the absence of conduction. The quasi-Fermi levelof the electrons, on the other hand, varies along the channel (OX direction),reflecting the forces driving the electron current : diffusion and drift. It isconstant perpendicularly to the channel (OY ), as there is no current flow inthat direction. Finally, equations (III.3) and (III.4) can be rewritten as :

n(x, y) = ni exp(ψ(x, y)− φFn(x)

φT

)(III.8)

p(x, y) = ni exp(ψ(x, y)− φFp(x)

φT

)(III.9)

Surface potential equations

Applying now the gradual channel approximation, a single section of the struc-ture is considered at some point along the OX axis, where the electric field andthe potential are related to the charge density, neglecting the contribution ofelectric field components parallel to the channel :

dE

dy=%(y)

εSi(III.10)

E = −dψ

dy(III.11)

%(y) = q(p(y)− n(y)−Na

)(III.12)

To obtain suitable expressions relating the front and back surface potentials, thedifferential form of Gauss’law, (III.10), is transformed into expression (III.13),where the explicit spatial dependency has been removed :

d(E2)

dψ= −

2%(ψ)

εSi(III.13)

Equation (III.13) can then be integrated analytically across the silicon film :

E2sf − E

2sb =

∫ ψsf

ψsb

−2%(ψ)

εSidψ (III.14)

The integral on the right-hand side has been computed by Mallikarjun andBhat in [III.7] as the difference of the following primitive, evaluated at the

III-10

III.2 Charge-sheet models for the intrinsic device

front and at the back interfaces :

G2(ψ, φF , φFn)

,∫−

2%(ψ)

εSidψ

=2qp0

φT εSi

[exp(−ψ

φT

)+

ψ

φT+ exp

(−

2φF

φT

)×(

exp(ψ + φF − φFn

φT

)−

ψ

φT− exp

(φF − φFn

φT

))](III.15)

Finally, by rearranging the terms of (III.14), a new equation is obtained whichrelates quantities evaluated separately on both sides of the film, thus revealingthe coupling existing between the surface potentials at the front and the backinterface :

E2sf −G

2(ψsf , φF , φFn) = E2sb −G

2(ψsb , φF , φFn) , α (III.16)

Integrating equation (III.13) from the back interface to any point in the film,one can see that relationship (III.16) is valid everywhere, and allows to obtainthe following useful expression for the electric field :

E(ψ) =√α+G2(ψ, φF , φFn ) (III.17)

Combining this expression of the electric field with (III.11) to obtain dy, andintegrating across the film, an additional equation is obtained which, togetherwith (III.1), (III.2), (III.16) and (III.17), can be solved numerically for thesurface potentials ψsf and ψsb :

tb =

∫ ψsf

ψsb

dψ

E(ψ)(III.18)

This solution scheme was first used for SOI MOS structures at thermal equi-librium by Ortiz-Conde et al. in [III.8]. It was later applied to conductingMOSFET structures by Mallikarjun and Bhat in [III.7].

The charge-sheet and the depletion approximations

The charge-sheet assumption, christened as such by Brews in [III.5], states thatthe inversion layer can be considered to be infinitesimally thin. Knowing fromquantum mechanical simulations that the actual inversion layer thickness is inthe order of 1.0 nanometer, which is about one hundredth of the film thicknessof a fully depleted device, this approximation seems quite reasonable.

Applying Gauss law over the front- and back-channel regions, equationsare obtained, which relate the sheet densities to the surface electric field andthe field just inside the film, past the inversion layers. This latter electricfield is evaluated using (III.17) by virtue of the depletion approximation (d .a.),considering the same device, with the same applied surface potentials, but

III-11

Modelling fully depleted SOI MOSFET’s

neglecting the contribution of the mobile charge carriers in the expression of G(III.15).

Q′′nf = −εSi

(Esf − Esf (d.a.)

)(III.19)

Q′′nb = εSi

(Esb − Esb(d.a.)

)(III.20)

III.2.2 A numerical charge-sheet model

Using the numerical device model outlined on page III-10, Ortiz-Conde, [III.8],and Mallikarjun, [III.7], have shown that the value of parameter α can be closelyapproximated by computing G using the depletion approximation :

G2(d.a.)(ψ) =

2qp0

εSi

(ψ − φT

)(III.21)

Substituting this value in (III.17) and solving (III.18) then yields an expressionfor parameter α depending explicitly on the surface potentials :

α(d.a.) =(ψsf − ψsb

tb−qp0

2εSi

)2−

2qp0

εSi

(ψsb − φT

)(III.22)

This expression is very important as it allows to circumvent the numericalevaluation of integral (III.18), and simplifies considerably the resolution of thesurface potential equations. Indeed, it is now sufficient to solve numericallythe two explicit equations derived from (III.16) using (III.22) together with(III.1) and (III.2) for the surface potentials ψsf and ψsb . Developments can bedriven even further, using equations (III.21) and (III.22) in (III.17) to evaluateEsf (d.a.) and Esb(d.a.), and finally obtain the channel charge densities :

Q′′nf = −C′′of

(VGf − Vfbf +

Q′′b2C′′of

+Q′′ifC′′of

− ψsf −C′′bC′′of

(ψsf − ψsb

))(III.23)

Q′′nb = −C′′ob

(VGb − Vfbb +

Q′′b2C′′ob

+Q′′ibC′′ob

− ψsb −C′′bC′′ob

(ψsb − ψsf

))(III.24)

Where Vfbf and Vfbb are the flat-band voltages at the front and back interfacerespectively, and are given by :

Vfbf , ∆W f −Q′′of

C′′of

(III.25)

Vfbb , ∆W b −Q′′ob

C′′ob

(III.26)

Q′′b is the fixed body charge, while C′′b is the unit-area capacitance measuredacross the body :

C′′b ,εSi

tb(III.27)

Q′′b , −qNatb (III.28)

III-12

III.2 Charge-sheet models for the intrinsic device

This numerical procedure was originally proposed by Mallikarjun and Bhatin [III.7]. According to the authors, it is quite general, as it allows to treat alloperating modes of SOI devices from fully depleted to partially depleted withback-accumulation. This procedure forms the core of the charge-sheet modeldeveloped for thin-film fully-depleted devices by Luiz Ferreira in his doctoralthesis, [III.9].

The originality of expressions (III.23) and (III.24) reside in their explicitdependency upon the trapped interface charges Q′′if and Q′′ib .

III.2.3 An analytical approximate charge-sheet model

Depleted back channel

The present work focuses on thin-film SOI MOSFET’s which are known tooperate normally in the fully-depleted mode with a single inversion layer locatedat the interface of the silicon film with the front oxide. Taking that into account,some simplifications to the model developed in the previous section can beobtained. Indeed, if the back channel is depleted, then its inversion charge willbe very small and approximately zero :

Q′′nb = 0 (III.29)

Imposing this condition and using equation (III.24), it is possible to expressthe back surface potential as a function of the front surface potential and theapplied gate voltages. Substituting in (III.23) yields a simplified expression ofthe inversion charge in the front channel :

Q′′nf = −C′′of

(VGf − Vfbf +

Q′′b2C′′of

+Q′′ifC′′of

− κf ψsf

+C′′bob

C′′of

(VGb − Vfbb +

Q′′b2C′′ob

+Q′′ibC′′ob

))(III.30)

κf , 1 +C′′bob

C′′of

(III.31)

C′′bob ,C′′b C

′′ob

C′′b + C′′ob

(III.32)

Inversion charge expressions

At this point, however, the model is not explicit, as the front surface potentialmust still be derived numerically from equation (III.22), taking (III.29) intoaccount. Iniguez proposed an interesting alternative in his paper [III.10], basedon the work by Shur et al., [III.11]. Shur’s group used quantum mechanicsto evaluate the inversion charge density in bulk MOSFET’s as a function ofthe surface electric field. They also proposed a formula relating the gate-source voltage to the inversion charge density, which agrees well with their

III-13

Modelling fully depleted SOI MOSFET’s

quantum mechanical results at all bias points. Adapted to the fully depletedSOI MOSFET by Iniguez, this formula reads :

VGf − VThf (VC ) = κf φT log(Q′′nf

Q′′nfTh

)−Q′′nf −Q

′′nfTh

C′′of

(III.33)

where VThf is the front gate threshold voltage which depends upon the channel

potential VC , φFn , κf is the body factor, and Q′′nfTh is the inversion chargedensity at threshold. As such, equation (III.33) does not make the modelexplicit, because it can not be solved directly for Q′′nf . Nevertheless, in weakinversion, when the inversion charge is small, the first term on the right handside dominates, and (III.33) can be approximated by :

Q′′nf = Q′′nfTh exp(VGf − VThf

κf φT) (III.34)

In strong inversion, the second term on the right hand side dominates, and(III.33) reduces to :

Q′′nf = −C′′of

(VGf − VThf

)(III.35)

To cover the whole bias range with a single expression, Iniguez proposedin [III.10] to interpolate between weak and strong inversion using infinitelyderivable functions :

Q′′nf =− C′′of κf φTθwk−stg ×

log(

1 +−Q′′nfTh(wk)

C′′of κf φT θwk−stgexp(VGf − VThf (wk)

κf φT

)+ exp

(VGf − VThf (stg)

κf φTθwk−stg

)) (III.36)

In this formula θwk−stg is a parameter controlling the transition from weak tostrong inversion, VThf (wk) and VThf (stg) represent, respectively, the thresholdvoltage in weak and strong inversion. It can be verified that (III.36) tends to(III.35) in strong inversion, as the sum inside the logarithm is then dominatedby the third term, where the exponential rises more sharply because of θwk−stg

. In weak inversion, on the other hand, because of its sharper slope, the thirdterm vanishes and the logarithm can be approximated around 1.0 by its Taylorseries expansion, the first term of which is equal to (III.34).

q′′nf =− C′′of κf φTθwk−stg

log(

1 +

√−Q′′nfTh(wk)

C′′of κf φTθ2wk−stg

exp(VGf − VThf (wk)

κf φT

)+ exp

(VGf − VThf (stg)

κf φT θwk−stg

)) (III.37a)

Q′′nf =−4q′′nf

2

C′′of κf φT +√(

C′′of κf φT

)2+ 4q′′nf

2(III.37b)

III-14

III.2 Charge-sheet models for the intrinsic device

Equations (III.37a) and (III.37b) form together an enhanced version of (III.36),which has, according to Iniguez, more precise derivatives. Using either (III.37a)– (III.37b) or (III.36) together with (III.29) and (III.30) an explicit model isobtained which allows to compute the surface potential, ψsf , as well as theinversion charge density, Q′′nf , directly from the externally applied voltages.Aside from being explicit, the model of this section has also the distinctiveadvantage of covering the whole bias range from weak to strong inversion.Nowhere else in the literature has any other model been found up till now,which features these two major advantages.

Threshold voltages and associated inversion charge

To complete the analysis, expressions have to be found for the threshold volt-ages, VThf (wk) and VThf (stg) and for the inversion charge density at threshold,Q′′nfTh(wk). It is commonly accepted that the transition between weak andstrong inversion occurs when the surface potential ψsf is about 2φF above theFermi-level; see Tsividis, [III.6], page 88, or Lim and Fossum [III.12]. Usingψsf = VC + 2φF in equation (III.30) one obtains :

VThf (mod) = Vfbf −Q′′b

2C′′of

−Q′′ifC′′of

+ κf

(VC + 2φF

)−C′′bob

C′′of

(VGb − Vfbb +

Q′′b2C′′ob

+Q′′ibC′′ob

)(III.38)

In this transition region, designated as moderate inversion by Tsividis, neitherthe weak inversion nor the strong inversion approximations hold. Typically,these approximations are valid for surface potentials up to a few φT away fromVC + 2φF , on either side. This explains why different values are needed forthe threshold voltages, which represent the upper limit of weak inversion forVThf (wk) , and the lower limit of strong inversion for VThf (stg) .

VThf (wk) = VThf (mod) + κf φwk where − φT ≤ φwk < 0 (III.39)

VThf (stg) = VThf (mod) + κf φstg where φstg u 2φT (III.40)

where φwk and φstg are the surface potential differences at the front interfacebetween moderate and weak or strong inversion respectively.

Mallikarjun and Bhat published analytical expressions of the sub-thresholdcharge densities for thin-film SOI MOSFET’s in [III.13], from which Q′′nfTh(wk)

can be readily obtained :

Q′′nfTh(wk) =Q′′bφT

C′′b−f

(κf

(VC + 2φF + φwk

)−(2− κf

)(VGb − Vfbb +

Q′′ibC′′ob

+Q′′b

2C′′ob

)−

Q′′b2C′′b−f

)−1

(III.41)

III-15

Modelling fully depleted SOI MOSFET’s

III.2.4 A dynamic model for the interface traps

Surface states or traps located in the vicinity of the Si–SiO2 interface maycapture electrons from the channel. The amount of charge stored in thesetraps at equilibrium (when all transients have decayed) depends on the theapplied electric field, the energy distribution of the traps and the Fermi-level ofthe carriers. It is common practice in MOSFET modelling to assume a uniformdistribution of traps across the bandgap, [III.1], [III.13], [III.14], as it leads tosimple expressions of the threshold voltage and inversion charge. For a staticanalysis, the simplified expressions of Q′′if and Q′′ib are :

Q′′if (φsf ) = −C′′if φsf with φsf , ψsf − VC − φF (III.42)

Q′′ib(φsb) = −C′′ib φsb with φsb , ψsb − VC − φF (III.43)

They can be injected directly into (III.23), (III.24) to obtain adequate thresholdvoltage and inversion charge expressions.

Capture of electrons by surface states is a recombination process whichinvolves the emission of phonons. Capture of electrons by oxide traps involvestunnelling through the potential barrier of the oxide, either directly from theconduction band to a trap at the corresponding energy level, or indirectly aftercapture by a surface-state. According to Tewksbury, [III.14], the time-constantsinvolved in these trapping mechanism range from a fraction of a nanosecond,in the case of fast surface-states, down to a few milliseconds, even seconds, foroxide traps.

Tewksbury explains in his paper, [III.14], that, even in modern technologieswith high-quality oxide material and interfaces, traps may significantly degradethe performance of analogue circuits. They can induce transient thresholdvoltage shifts of several millivolts which take a few milliseconds to decay. This isparticularly the case in switched-capacitor networks, or A/D converters. Trapshave also been found responsible for the dispersive behaviour of the outputconductance in MOSFET’s. In the case of short-channel MOSFET’s, accurateprediction of the output conductance is necessary, which, in turn, calls for theability to predict the level of trapped charge. As microwave circuits (e.g. :mixers, oscillators) may involve both slowly and rapidly varying signals, thedynamic behaviour of the traps must by properly accounted for.

dφif

dt+φif − φsf

τif= 0 with φif , −Q′′if /C′′if (III.44)

dφib

dt+φib − φsb

τib= 0 with φib , −Q′′ib/C′′ib (III.45)

Equations (III.44)–(III.45) constitute a first order model for the dynamic be-haviour of the interface traps. It is similar to the RC model introduced byTewksbury in SPICE. It could be refined by introducing a more complicateddependency of Q′′if and Q′′ib on φif and φib and also by splitting up the interfacecharges in several components responding with different time-constants.

III-16

III.2 Charge-sheet models for the intrinsic device

VGf

VS VD

VGb

(0, 0)

(L, tb)

% = Q′′nb(x)

% = Q′′nf (x)

(0, HF ilm)

(L, 0)

% = −q Na

Figure III.4: Boundary conditions for the 2D Poisson equation.

III.2.5 Short channel effects

All the previous developments are based on the gradual channel approximationwhich considers that the longitudinal component of the electric field Ex , −∂ψ∂xis negligible with respect to the transverse component Ey , −∂ψ∂y , so thatthe 2D Poisson equation reduces to a one-dimensional differential equation asindicated below :

∇2ψ(x, y) = −%(x, y)

εSi=−q Na

εSi(III.46a)

∇2ψ(x, y) u∂2ψ(x, y)

∂y2(III.46b)

The boundary conditions for the potential ψ at the diffusions are :

ψ(0, y) = φJn and ψ(L, y) = VDS + φJn (III.46c)

where φJn is the built-in potential of the junctions at source and drain. At theinterfaces with the front and back oxides the conditions are :

−∂ψ

∂y

∣∣∣(x, 0)

=1

εSi

[Q′′nf +Q′′if + C′′of

(VGf − Vfbf − ψ(x, 0)

)](III.46d)

∂ψ

∂y

∣∣∣(x, tb)

=1

εSi

[Q′′nb +Q′′ib + C′′ob

(VGb − Vfbb − ψ(x, tb)

)](III.46e)

The gradual channel approximation is no longer valid when short-channeldevices are considered. Several effects limit the applicability of gradual channelapproximation in this case. Veeraraghavan and Fossum, [III.15], analysed themand proposed modelling solutions for the SOI MOSFET. They identified thefollowing effects : channel-length modulation, charge-sharing and drain-inducedconductivity enhancement.

III-17

Modelling fully depleted SOI MOSFET’s

Channel-length modulation

This effect results from the velocity-saturation of carriers at high field andinduces a complex two-dimensional electric field distribution in the vicinity ofthe drain. It will be treated in more detail later as it is more closely related tocarrier transport.

Charge-sharing

It is due to the “fringing field” emanating from the source and drain diffusionstowards the back gate, which reduce the fraction of depletion-charge controlledby the front gate. Charge-sharing is introduced in the charge-sheet model byreplacing the film charge density Q′′b by an effective value which is a function ofVD and VS . Colinge, [III.2], showed that the voltage-shift due to charge-sharingremains small as long as the channel-length is kept above 0.5 micrometer fora film-thickness on the order of 100 nanometer. Additionally, the thresholdvoltage shift can be controlled by reducing the film-thickness when scalingdown to deep sub-micrometer devices. As a result, this issue will not be dealtwith in more detail here.

Drain-induced conductivity enhancement

The presence of a non-zero longitudinal electric field modifies the potentialdistribution and hence the concentration of carriers as can be anticipated fromequation (III.6). Veeraraghavan and Fossum, [III.15] proposed to express thepotential in the active zone as the sum of ψ0 , the solution at VDS = 0, with∆ψ, a correction for VDS 6= 0 :

ψ(x, y) = ψ0 (x, y) + ∆ψ(x, y) (III.47)

Substituting expression (III.47) in the 2D Poisson equation yields a differentialequation describing the distribution of the incremental potential ∆ψ :

∇2[∆ψ(x, y)

]= 0 (III.48a)

−∂∆ψ

∂y

∣∣∣(x,0)

=1

εSi

(∆Q′′nf + ∆Q′′if − C

′′of ∆ψ

)(III.48b)

∂∆ψ

∂y

∣∣∣(x,tb)

=1

εSi

(∆Q′′nb + ∆Q′′ib − C

′′ob∆ψ

)(III.48c)

∆ψ(0, y) = 0 (III.48d)

∆ψ(L, y) = VDS (III.48e)

The boundary conditions (III.48b) and (III.48c) are obtained considering thatthe electric field in the oxide is mainly vertical. This assumption is quitereasonable for the front-gate oxide which is rather thin and supports a ratherhigh transverse field, particularly in inversion. For the back-gate oxide, theassumption is rather approximate, but results in an acceptable mean value forthe transverse field Esb . Conditions (III.48d) and (III.48e) simply state thatthe diffusions are equipotentials.

III-18

III.2 Charge-sheet models for the intrinsic device

Considering that the longitudinal electric field at VDS = 0 is very almostzero everywhere in the active region, one may correctly approximate the po-tential distribution ψ0 by ψ(1D), the solution obtained by the one-dimensionalapproach developed on page III-10.

To obtain closed-from expressions relating the incremental surface poten-tials, ∆ψsf and ∆ψsb , to the incremental inversion charges, ∆Q′′nf and ∆Q′′nb

in a manner similar to (III.23) and (III.24), Veeraraghavan and Fossum in-troduced the additional assumption that the partial derivatives of ∆ψ are notstrongly coupled :

∂2∆ψ

∂x2= −

∂2∆ψ

∂y2, −ζ (III.49)

Computer simulations showed that ζ can be considered constant across theactive region and approaches zero as the channel-length increases. Integrating(III.49) along the OX axis, the dependence of ζ is inferred :

ζ =2

L2

(VDS + ∆Ex (0, y)L

)u

2VDS

L2(III.50)

since the incremental longitudinal field ∆Ex at the source is typically much lessthan the average field VDS/L. Next, by integrating (III.49) twice along theOY direction one obtains equations relating the values of ∆ψ and ∂∆ψ

∂yat the

front and the back interface together. Combined with the boundary conditions(III.48b) and (III.48c), these allow finally to write the incremental counter-partof equations (III.23) and (III.24) :

∆Q′′nf (x) = −C′′of

[∆Q′′if (x)

C′′of

−∆ψsf (x)

−C′′bC′′of

(∆ψsf (x) −∆ψsb(x) +

t2bL2VDS

)] (III.51)

∆Q′′nb(x) = −C′′ob

[∆Q′′ib(x)

C′′ob

−∆ψsb(x)

−C′′bC′′ob

(∆ψsb(x) −∆ψsf (x) +

t2bL2VDS

)] (III.52)

Combining equations (III.51) and (III.52) with (III.23) and (III.24) writtenin terms of ψ0 , expressions are obtained which relate the inversion charges Q′′nf

and Q′′nb to the surface potentials ψsf and ψsb in the two-dimensional case :

Q′′nf = −C′′of

[VGf − Vfbf +

Q′′b2C′′of

+Q′′ifC′′of

− ψsf

−C′′bC′′of

(ψsf − ψsb +

t2bL2VDS

)] (III.53)

Q′′nb = −C′′ob

[VGb − Vfbb +

Q′′b2C′′ob

+Q′′ibC′′ob

− ψsb

−C′′bC′′ob

(ψsb − ψsf +

t2bL2VDS

)] (III.54)

III-19

Modelling fully depleted SOI MOSFET’s

Applying the condition for a depleted back-channel (III.29), a new expression isobtained for VThf (mod) which now accounts for the drain-induced conductivityenhancement effect :

VThf (mod) = VThf (mod)

∣∣VDS =0

−(

1 +C′′b

C′′b + C′′ob

) C′′b t2b

C′′of L2VDS (III.55)

where VThf (mod)

∣∣VDS =0

stands for the value given by equation (III.38), whichdoes not account for two-dimensional effects.

III.3 Static conduction current

In this section the conduction current in the linear regime is evaluated basedon the gradual-channel approximation using the inversion charge equations de-veloped in section III.2. For the current in saturation, a specific model isdeveloped to obtain the surface potential profile in the saturation region, andevaluate the channel-modulation effect.

III.3.1 Carrier velocity

A realistic carrier transport model for short-channel MOS devices needs toaccount for the following phenomena :

1. The saturation of velocity at high longitudinal field, caused by collisionswith other carriers and atoms in the crystal;

2. The reduction of mobility with increasing normal field, as the carriersare pressed harder onto the oxide interface and experience a more surfaceroughness scattering.

Results of rigorous analyses of carrier transport in nMOSFET’s have beenpublished, but it has not been possible yet to obtain analytical expressions ofthe current using them, as indicated by, amongst others, Sodini et al., [III.16].Therefore, simplified or empirical expressions are used, such as :

vn = µ∣∣E‖(x)

∣∣ =µeff

∣∣E‖(x)∣∣

1 +µeff

∣∣E‖(x)∣∣

ηvn(sat)

(III.56)

which relates the longitudinal electric field E‖ to the carrier velocity and is,strictly speaking, valid only for pMOSFET’s with η = 1. Expression (III.56)was used for nMOSFET’s by Veeraraghavan and Fossum in [III.15], with η = 2.One can see that when η > 1, (III.56) reaches vn(sat), when the longitudinalfield is equal to the finite value E‖sat :

∣∣E‖sat

∣∣ , ηvn(sat)

µeff

(η − 1

) (III.57)

III-20

III.3 Static conduction current

In this case, a piece-wise model may be used which strictly limits the carriervelocity to vn(sat) :

vn =

µeff

∣∣E‖(x)∣∣(1 +

µeff

∣∣E‖(x)∣∣

ηvn(sat)

)−1for∣∣E‖∣∣ < ∣∣E‖sat

∣∣vn(sat) otherwise

(III.58)

The longitudinal field can be estimated in the framework of the charge-sheetmodel using :

E‖(x) = −∂ψsf

∂x=−1

κfC′′of

(dQ′′nf

dx+dQ′′if

dx+C′′bob

C′′ob

dQ′′ibdx

)(III.59)

The reduction of mobility due to surface roughness scattering is evaluatedby means of an effective electric field, E⊥eff , which reflects the normal fieldexperienced on the average by all carriers in the channel.

µeff =µ0

1 + χ∣∣E⊥eff

∣∣=

µ0

1 + χ2

∣∣E⊥effD + E⊥effS

∣∣ (III.60)

E⊥eff , Esf −Q′′nf

2εSi=(ψsf − ψsb

tb−

Q′′b2εSi

)−Q′′nf

2εSi(III.61)

where equation (III.61) computes the average electric field inside the inversionlayer.

III.3.2 Triode operation

According to Tsividis, [III.6], the front-channel current can be split into driftand diffusion components, Jdrift and Jdiff and can be related to the evolutionof the quasi-Fermi level for the electrons :

ICf (x) = Jdrift (x) + Jdiff (x) = −W µQ′′nf (x)dVC

dx(III.62)

The drift current density is obtained by multiplying the drift velocity vn from(III.56) with the charge density Q′′nf and the device width W :

Jdrift (x) = W vn = W Q′′nf (x)µ E‖(x)

= −W µQ′′nf

κfC′′of

(dQ′′nf

dx+dQ′′if

dx

) (III.63)

where, for simplicity, Q′′ib(x) is replaced by the uniform value 12 (Q′′ibS + Q′′ibD)

for the evaluation of the mobility, µ, and of the inversion charge, Q′′nf , while the

dependency∂Q′′ib∂x

is neglected. The expression for the diffusion current densityis :

Jdiff (x) = −W Dnd

dx

[Q′′nf

−q

]= W µφT

dQ′′nf

dx(III.64)

III-21

Modelling fully depleted SOI MOSFET’s

Injecting expressions (III.63) and (III.64) into (III.62) yields an equation whichrelates the current to the local inversion charge :

ICf (x) = Wµ( −Q′′nf

κf C′′of

d

dx

[Q′′nf +Q′′if

]+ φT

dQ′′nf

dx

)(III.65a)

µ = µeff

(1 +

µeff

η vn(sat) κf C′′of

d

dx

[Q′′nf +Q′′if

])−1

(III.65b)

In static operation, the current is constant along the channel, so that, writ-ing ICf (x) = IDS , one finally obtains a differential equation describing theinversion-charge profile as a function of the drain-source current and the inter-face charge :( Q′′nf

κfC′′of

+IDS

Wηvn(sat)κfC′′of

) d

dx

[Q′′nf +Q′′if

]− φT

dQ′′nf

dx+

IDS

Wµeff= 0 (III.66)

This last result was obtained assuming that the longitudinal field is below thecritical field for velocity saturation E‖sat , so that the first option of (III.58) isvalid. Consequently, (III.66) is only valid in the portion of the channel whichis in linear operation. Integrating along the channel from x = 0 to x = Land solving for IDS , yields the expression of the static drain-source conductioncurrent as a function of the inversion charge densities at the source and drain :

IDS =W

L

µeff

1 +µeff

(Q′′

nifD−Q′′

nifS

)ηvn(sat)κfC

′′ofL

×

[φT

(Q′′nfD −Q

′′nfS

)−

(Q′′nfS +Q′′nfD

)(Q′′nifD −Q

′′nifS

)2κfC

′′of

](III.67)

where Q′′nif is defined by :

Q′′nif (x) , Q′′nf (x) +Q′′if (x) (III.68)

Equation (III.67) has been developed for static operation. As a result, onecould use (III.42) together with (III.30) to relate Q′′if directly to Q′′nf and elimi-nate it from the expressions of the static current and the static inversion-chargeprofile. However, one of the purposes of the developments in this work is to ob-tain expressions which would be valid in dynamic operation, and in particular,in situations where the signals are so fast that the interface charge has no timeto respond. In this case, its profile corresponds to a long-term average of theinversion-charge profile which may be very different from the instantaneous pro-file. For this reason (III.67) assumes that Q′′nf (x) and Q′′if (x) are independentfunctions of position. It is noteworthy that the equation depends exclusivelyon the values of the charge densities at the end-points of the channel. It isthus not necessary to track the evolution in time of the whole interface-chargedensity profile, but only to compute the state of the interface-charge densityat the source and drain using two separate lumped RC circuits.

III-22

III.3 Static conduction current

VGf

[V]

IDS

[A]

10−6

10−5

10−4

10−3

10−2

−0.2 0 0.2 0.4 0.6 0.8−0.4

“Frozen” interface charge

Dynamic interface charge

Figure III.5: Influence of the interface charge on the drain current at VDS = 0.1V. The density of interface states Nif is 1.67 1011 cm−2 V−1

III.3.3 Saturation

Saturation appears at the drain of the MOSFET when the inversion chargedensity in the channel becomes so small, that the carriers must be driven attheir saturation velocity to maintain the current flow. A further increase ofthe drain potential extends the region where the saturation velocity is reachedtowards the source, and forces the inversion layer to fan out vertically. Inthese conditions, the longitudinal component of the electric field becomes soimportant that the gradual channel approximation is not accurate anymore.

Taking into account that the continuity of the steady-state current implies aconstant inversion charge in the saturation region and using an integral form ofthe potential equations, it is however possible to build a useful model includingvelocity saturation and channel length modulation, as shown by El-Banna andEl-Nokali in [III.17] for bulk MOSFET’s, and by Veeraraghavan and Fossumin [III.15] for SOI MOSFET’s. This approach will be adapted to the frameworkdeveloped in the present work, and a peculiar attention will be devoted to theinfluence of interface states.

Saturation voltage

When saturation occurs, the channel is conveniently subdivided into two parts :

• the linear region, extending from the source to the point where the chan-nel is virtually pinched off, that is to say, where the minimal inversioncharge is reached and, hence, where the saturation velocity is attained;

• the saturated region, extending from the pinch-off point to the drain.

III-23

Modelling fully depleted SOI MOSFET’s

In the linear region, the modelling approach from section III.3.2 is applicable,and using equation (III.67) with the appropriate charge density and channellength, a first expression of the current is obtained :

IDS(sat) =W

L(sat)

µeff

1 +µeff

(Q′′

nifP(sat)−Q′′

nifS

)η vn(sat) κf C

′′of L

×

[φT

(Q′′nfP(sat) −Q

′′nfS

)−

(Q′′nfS +Q′′nfP(sat)

)(Q′′nifP(sat) −Q

′′nifS

)2 κf C′′of

](III.69)

where Q′′nfP(sat) and Q′′nifP(sat) stand for the charge densities evaluated at thepinch-off point. L(sat) is the distance between the pinch-off point and thesource. In the saturated region, the current is simply the product of the satu-ration velocity and the inversion charge density :

IDS(sat) = −Q′′nfP(sat) vn(sat) W (III.70)

At the pinch-off point, the continuity is ensured by equating the expressionsfrom the linear and saturated regions, (III.69) and (III.70). Solving this set ofequations yields an expression for the inversion charge density Q′′nfP(sat) whichcan be re-injected in either of the above equation to obtain the saturationcurrent.

Q′′nfP(sat) =2 q0

−q1 +√q1

2 − 4 q2 q0

(III.71a)

q2 , η − 2 (III.71b)

q1 , 2Q′′nfS +(η − 2

)(Q′′ifP(sat) −Q

′′ifS

)− 2ηκfC

′′of

(φT +

vn(sat)L(sat)

µeff

) (III.71c)

q0 , η Q′′nfS

(2κf C

′′of φT −Q

′′nfS +Q′′ifP(sat) −Q

′′ifS

)(III.71d)

Evaluating equation (III.33) at the source and at the pinch-off point, it ispossible to relate the saturation channel potential to the source voltage andthe charge densities. The value obtained from (III.72) can then be comparedto the applied drain voltage to decide whether the MOSFETis operating insaturation or not.

VP(sat) = VS + φT log(Q′′nfS

Q′′nfP(sat)

)−Q′′nfS −Q

′′nfP(sat)

κf C′′of

−Q′′ifS −Q

′′ifP(sat)

κf C′′of

(III.72)

Strictly speaking, Q′′ifP(sat) is not known at this stage. Indeed, only Q′′ifS and

Q′′ifD are evaluated using the model developed in section III.2.4 and no expres-sion of the distribution Q′′if (x, t) is available. For the sake of simplicity, Q′′if (x, t)is assumed to be constant across the saturation region and equal to Q′′ifD .

III-24

III.3 Static conduction current

Surface potential profile in the saturation region

In the saturation region, the inversion charge has a constant value imposedby (III.70) combined with the continuity of the steady-state current. Theexact distribution of the inversion charge in the OY direction is governed bythe 2D Poisson equation for which no closed-form solution exist. However amacroscopic approach based on the integral form of Gauss’law allows to derivesome useful results as demonstrated by several authors, [III.15], [III.18], [III.17].Gauss’law applied to an infinitesimally thin strip of the active film yields :

∮εSi−→E ·−→dS =

∫% dV =

(Q′′b +Q′′nf (sat)

)dx (III.73)

In the same manner as in section III.2.5, the electric field and the charges areexpanded in a component satisfying the equation at VDS = 0, and an incrementfor VDS 6= 0.

∮εSi−→E0 ·−→dS =

(Q′′b +Q′′nf0

)dx for VDS = 0 (III.74)∮

εSi∆−→E ·−→dS = ∆Q′′nf (sat) dx for VDS 6= 0 (III.75)

VGb

VGf

VS VD

L(sat)

Pinch-off point

dx

Gaussian box

-- - -

---- -- - - - -- --- - - - - --

Figure III.6: The boundary between the linear region and the saturation re-gion : the pinch-off point

Only equation (III.75) is of interest here, as the solution of (III.74) cor-responds to the one-dimensional developments of section III.2. The surface

III-25

Modelling fully depleted SOI MOSFET’s

integral on the electric field can be expanded as follows :∮εSi∆−→E ·−→dS

=

∫ tb

0

(∆Ex (x+ dx, y)−∆Ex (x, y)

)dy + dx

(∆Ey(x, tb)−∆Ey(x, 0)

)= εSi dx

(∫ tb

0

∆Ex (x+ dx) −∆Ex (x, y)

dxdy + ∆Esb −∆Esf

)= εSi dx

(∫ tb

0

∂∆Ex

∂xdy + ∆Esb −∆Esf

)= εSi dx

(−

∫ tb

0

∂2∆ψ

∂x2dy + ∆Esb −∆Esf

)= εSi dx

(−∂2

∂x2

[∫ tb

0

∆ψ dy]

+ ∆Esb −∆Esf

)(III.76)

The integral of the surface potential is approximated by the value tb2 (∆ψsf +

∆ψsb) and equation (III.52) with the condition ∆Q′′nb = 0 is used to obtain arelationship linking ∆ψsf and ∆ψsb , so that :

∂2

∂x2

[∫ tb

0

∆ψ dy]utb

2

(1 +

C′′bC′′b + C′′ob

)d2∆ψsf

dx2(III.77)

Assuming that the electric field are mainly vertical in the front and back oxidelayers, the incremental surface electric field can be expressed in function of thesurface potential increments :

∆Esf =∆Q′′if − C

′′of ∆ψsf

εSi(III.78)

∆Esb = −∆Q′′ib − C

′′ob ∆ψsb

εSi

=−1

εSi

∆Q′′ib −

C′′ob

C′′b + C′′ob

[∆Q′′ib − C

′′b

( tbL

)2VDS + C′′b ∆ψsf

] (III.79)

The constant value of the inversion charge increment in the saturation region∆Q′′nf (sat) can be related to ∆ψsf at the pinch-off using the charge-sheet model :

∆Q′′nf (sat) = −C′′of

[∆Q′′ifC′′of

− κf ∆ψsfP(sat) +C′′bob

C′′of C′′b

∆Q′′ib

+C′′bC′′of

( tbL

)2(C′′ob + 2C′′bC′′ob + C′′b

)VDS

](III.80)

Substituting the new expressions back into equation (III.75), and rememberingthat Q′′if and Q′′ib were assumed constant across the saturation region, onefinally obtains a differential equation which governs the potential profile from

III-26

III.3 Static conduction current

the pinch-off point to the drain :

l2CLM

d2∆ψsf

dx2−∆ψsf + ∆Ψ0 = 0 (III.81a)

The boundary conditions are :

∆ψsf (x = L(sat)) = ∆ψsfP(sat) (III.81b)

d∆ψsf

dx

∣∣∣∣x=L(sat)

=∣∣E‖sat

∣∣ (III.81c)

∆ψsf (x = L) = ∆ψsfD (III.81d)

The characteristic length lCLM and the independent term ∆Ψ0 are defined as :

lCLM , tb

√C′′b

2 κf C′′of

(1 +

C′′bC′′b + C′′ob

)(III.82)

∆Ψ0 , ∆ψsfP(sat) −2C′′b

2

C′′ob + C′′b

( tbL

)2 VDS

κf C′′of

(III.83)

Channel-length modulation

The solution of (III.81) has the general form :

∆ψsf = ∆Ψ1 sinh(x − L(sat)

lCLM) + ∆Ψ2 cosh(

x− L(sat)

lCLM) + ∆Ψ0 (III.84)

where ∆Ψ0 is the independent term of the equation, while ∆Ψ1 and ∆Ψ2 areare determined by the boundary conditions at x = L(sat).

∆Ψ1 =∣∣E‖sat

∣∣ lCLM (III.85a)

∆Ψ2 =2C′′b

2

C′′ob + C′′b

( tbL

)2 VDS

κf C′′of

(III.85b)

The third boundary condition, which imposes the surface potential value atthe drain, allows to determine the length of the saturation region, ∆L(sat) ,L− L(sat) :

∆L(sat) = lCLM

(asinh(

∆ψsfD −∆ψsfP(sat) −∆Ψ2√(∆Ψ1 )2 − (∆Ψ2 )2

)

− asinh(∆Ψ2√

(∆Ψ1 )2 − (∆Ψ2 )2))

(III.86)

This last equation describes the channel length modulation effect. It ismainly influenced by the drain voltage over-drive with respect to the channelpinch-off voltage as suggested by the argument ∆ψsfD−∆ψsfP(sat). Veeraragha-van and Fossum suggested in [III.15] to use the following approximation :

∆ψsfD −∆ψsfP(sat) u VD − VP(sat) (III.87)

III-27

Modelling fully depleted SOI MOSFET’s

When the channel length is not excessively short with respect to the film thick-ness, then ∆Ψ2 u 0 and the channel length modulation equation reduces to :

∆L(sat) = lCLM asinh(VD − VP(sat)

∆Ψ1) (III.88)

As the interface charge density was assumed to be constant across the satu-ration region, there is no explicit influence of the interface charge density onequation (III.88). However, the charging level of the interface states at thedrain-end influences VP(sat) and thus ∆L(sat) indirectly.

Together with (III.71) and (III.72), equation (III.88) forms the channellength modulation model. This model is not explicit, but can be resolved byrelaxation, starting with L(sat) = L, that is to say ∆L(sat) = 0. Convergencealways occurs within less than 10 iterations.

III.3.4 Unified model

The previous section focussed on the saturated operating mode on its own.When trying to combine the expressions developed there, with the ones re-sulting from the analysis of the triode (linear) operating mode of the MOS-FET some problems arise. Classically, the transistor is considered to switchabruptly into saturation as soon as the drain voltage exceeds the saturationvoltage VP(sat).

This approach has as major draw-back, that if the continuity can be ensuredfor the quantities themselves, their derivatives are not generally continuous,which as mentioned in section III.1.5, can cause simulation problems. To eludethese problems, McAndrew et al. proposed in their paper on bulk MOSFET’s,[III.19], to use infinitely derivable interpolation schemes to generate smoothtransitions between the continuous chunks of the piece-wise model. Iniguezapplied this idea when developing his physical models, and particularly theone for the SOI MOSFET’s, [III.20]. According to this approach, an effectivevalue is introduced for the channel potential at the pinch-off point, which iscomputed in such a way that it evolves to the required limits in saturation andin linear operation :

VP(eff ) = VP(sat) − VP(sat)

log(

1 + exp(θlin−sat [1− VD/VP(sat)]

))log(1 + exp(θlin−sat ))

(III.89)

where θlin−sat is a fitting parameter controlling the transition from triode tosaturated operation. One can easily verify that, in all cases VP(eff ) ≤ VP(sat),and that it tends to VP(sat) when VD VP(sat) and to VD when VD VP(sat).

The effective pinch-off potential VP(eff ) is substituted to VP(sat) in (III.88)to obtain the effective value for the channel length modulation, ∆L(eff), whichdetermines the length of the linear region, L(eff). This new length is theninjected in (III.71), so that an updated value is obtained for VP(sat) from equa-tion (III.72). This iterative process converges after less than ten iterations.It ensures a smooth transition from the triode operating regime to satura-tion. The final value of VP(eff ) allows to evaluate the effective inversion charge

III-28

III.3 Static conduction current

VGf VS VGb ∆L(eff)

∣∣0

= 0VD

Q′′nfS

VP(sat)

∣∣k

VP(eff )

∣∣k

Q′′nfP(sat)

∣∣∣k

∆L(eff)

∣∣k

Q′′nfP(eff )

k = 0

k = k + 1

k 6= 0

(III.37)

(III.71)

(III.72)

(III.89)

(III.88)

(III.37)

Figure III.7: The flowgraph of the unified model.

III-29

Modelling fully depleted SOI MOSFET’s

density at the pinch-off point, Q′′nfP(eff ), with equation (III.37) and hence thedrain-source current.

0 0.5 1 1.5 2 2.5 30

5

10

15

20

25

30

35

403

2.5

2

1.5

1

0.5

0-0.5

VD

[V]

IDS

[mA

]

VGf

[V]

Figure III.8: Static current versus drain voltage at various gate voltages.

III.4 Dynamic currents

When the voltages applied at the terminals of the MOSFET vary, dynamic —transient — current components appear. For the intrinsic MOS device, thesecurrent are mainly related to charge rearrangement in the device, as opposed toinductive effects. The complete dynamic current model for the SOI MOSFETtakes the form :

IGf (t) =d

dt

[QGf

(VGf (t), VGb(t), VD (t), VS (t)

)](III.90)

IGb(t) =d

dt

[QGb

(VGf (t), VGb(t), VD (t), VS (t)

)](III.91)

ID (t) =d

dt

[QD

(VGf (t), VGb(t), VD (t), VS (t)

)]+ IDS

(VGf (t), VGb(t), VD (t), VS (t)

) (III.92)

IS (t) =d

dt

[QS

(VGf (t), VGb(t), VD (t), VS (t)

)]− IDS

(VGf (t), VGb(t), VD (t), VS (t)

) (III.93)

In the next subsections the charges associated with device terminals will becomputed. The surface potential distribution is first introduced, as it is a

III-30

III.4 Dynamic currents

prerequisite for the integration of the charge densities across the device. Frontand back gate charges are then easily evaluated. The partition of the totalchannel charge into source and drain components is also briefly discussed. Afterevaluation of the source and drain charges, an alternative formulation of thecharge model is presented.

III.4.1 Surface potential profile

The static surface potential distribution along the channel has been discussedin section III.3.2. When dynamic signals are applied at the device terminals,the profile described by equation (III.66) may be significantly altered by thepresence of charging currents. A general treatment of this problem is found innumerical device simulators which are capable of transient analyses. Reportsexist which describe the interfacing of a device simulator and a circuit simulator,and the successful simulation of some basic circuits. The computational burdenis however quite heavy, so that for design purposes alternative — simplified —solutions are still required.

When the input signals vary sufficiently slowly with respect to the timeneeded for the rearrangement of the channel charge, one may assume that,however varying in time, the profile corresponds at all instants to one solu-tion of (III.66). This quasi-static assumption has proven very useful for thedevelopment of device models of all types, which, regardless of the inherentspeed limitation of the approach, demonstrated the ability to correctly predictresponses up to high frequencies. The quasi-static assumption will be exploitednext to obtain expressions of the charges, while its limitations will be addressedin section III.5.

In order to simplify the computation of the charge integrals, equation(III.66) is reformulated as :

dx = −Wµeff

IDS

( Q′′nf

κf C′′of

+IDS

Wηvn(sat)κfC′′of

− φT

)dQ′′nif + φT dQ′′if

(III.94)

This formulation reveals that the differential dQ′′nif is present in all terms exceptthe last one, which will be considered negligible. Indeed, the contribution ofthis last term might become significant only in deep sub-threshold operationwhen the inversion charge density Q′′nf and the applied longitudinal electric fieldare small. In this case the total charge stored in the intrinsic device is small,so that an eventual bias in its evaluation will remain of marginal importance.Neglecting the term φT dQ′′if and replacing the IDS by a fictitious “current”FDS :

dx = −Wµeff

FDS

Q′′nf

κf C′′of

+FDS

W η vn(sat) κf C′′of

− φT

dQ′′nif (III.95)

The fictitious “current” FDS is evaluated in the same way as IDS in section

III-31

Modelling fully depleted SOI MOSFET’s

III.3.2, by integrating equation (III.95) along the whole channel :

FDS =W

L(eff)

µeff

1 +µeff

η vn(sat) κf C′′of L(eff)

[Q′′nif

]P(eff )

S

×

φT −

⟨Q′′nf

⟩P(eff )

S

κfC′′of

[Q′′nif

]P(eff )

S

(III.96)

where the following short-hand notations were introduced :[f]ba, f(b)− f(a) (III.97)⟨

f⟩b

a,(f(b) + f(a)

)/2 (III.98)

As indicated previously, FDS very closely approximates IDS above threshold,and eventually departs from IDS in sub-threshold operation — if at all, de-pending on the state of the interface charge.

The advantage of the manipulation described above is that, in all subsequentintegrations, a common factor Q′′nifx −Q

′′nifS will appear which will cancel the

corresponding factor contained in FDS rendering the model numerically robustat VDS = 0. This manipulation is also transparent, in the sense that in the limit,when Q′′if uniformly tends to zero along the channel, the present model and thestandard one coincide.

Integration of expression (III.95) yields a relationship between the chargedensities and the position along the channel :

x = −Wµeff

FDS

[Q′′nif

]xS

⟨Q′′nf

⟩x

S

κf C′′of

+IDS

Wηvn(sat)κfC′′of

− φT

(III.99)

III.4.2 Front-gate charge

The charge density on the gate is estimated using the one-dimensional modeldeveloped in section III.2, which is a parallel plate approximation of the gatestructure. As a result, the effect of fringing fields in the vicinity of the sourceand drain diffusions is not accounted for. Applying accordingly Gauss’law to anarrow vertical strip crossing the gate polysilicon, yields :

Q′′Gf (x, z) = C′′of

(VGf −∆W f − ψsf (x)

)(III.100)

The total gate charge is then evaluated by integration of Q′′Gf over the wholegate area. The linear and the saturation region are treated separately, as theexpression of ψsf differ in each region.

QGf =

∫∫Q′′Gf dx dz

= W(∫ L(eff)

0

Q′′Gf dx+

∫ L

L(eff)

Q′′Gf dx)

= QGf [0 ,L(eff )] +QGf [L(eff ),L]

(III.101)

III-32

III.4 Dynamic currents

Linear region In the linear region, equation (III.30) can be used to obtain anexpression of Q′′Gf in function of the applied voltages and the inversion chargedensity :

QGf [0 ,L(eff )] = −Qnif [0 ,L(eff )]

κf−C′′bob Qib[0 ,L(eff )]

κf C′′ob

+W L(eff) ×C′′of

κf − 1

κf

(VGf − Vfbf

)−

Q′′b2 κf

−Q′′of −C′′bob

κf

(VGb − Vfbb +

Q′′b2C′′ob

)(III.102)

where Qib corresponds to the charge stored in the back interface states, whileQnif corresponds to the sum of the charge stored in the channel, Qnf , and thecharge trapped in the front interface states, Qif .

Qnif [0 ,L(eff )] ,W∫ L(eff)

0

(Q′′nf +Q′′if

)dx (III.103)

Qib[0 ,L(eff )] ,W∫ L(eff)

0

Q′′ib dx (III.104)

Using the expression of dx from (III.94) the integral in (III.103) can be com-puted analytically :

Qnif [0 ,L(eff )] = W 2µeff

[Q′′nif

]P(eff )

S

FDS×

(φT −

FDS

W η vn(sat) κf C′′of

+

⟨Q′′if⟩P(eff )

S

κf C′′of

) ⟨Q′′nif

⟩P(eff )

S

2 κf C′′of

−Q′′nifP(eff )

2+Q′′nifP(eff )Q

′′nifS +Q′′nifS

2

3 κf C′′of

(III.105)

For the back interface charge, a uniform value has been assumed, chosen as theaverage of the interface charge density at the source and the pinch-off point :

Qib[0 ,L(eff )] uW L(eff)

⟨Q′′if⟩P(eff )

S(III.106)

Saturation region From the results of section III.3.3, the following expres-sion for the front surface potential can be readily deduced :

ψsf (x) = ψsfP(eff ) +∣∣E‖sat

∣∣ lCLM sinh(x− L(eff)

lCLM) (III.107)

III-33

Modelling fully depleted SOI MOSFET’s

In combination with equation (III.101) this last expression allows to evaluatethe contribution of the saturation to the total gate charge :

QGf [L(eff ),L] = C′′of

∣∣E‖sat

∣∣ l2CLM

cosh(

∆L(eff)

lCLM)− 1

−Qnif [L(eff ),L]

κf−C′′bob Qib[L(eff ),L]

κf C′′ob

+W ∆L(eff) ×C′′of

κf − 1

κf

(VGf − Vfbf

)−

Q′′b2 κf

−Q′′of −C′′bob

κf

(VGb − Vfbb +

Q′′b2C′′ob

)(III.108)

where Qnif [L(eff ),L] and Qib[L(eff ),L] are given by :

Qnif [L(eff ),L] = W ∆L(eff)Q′′nifP(eff ) (III.109)

Qib[L(eff ),L] uW ∆L(eff)

⟨Q′′if⟩P(eff )

S(III.110)

III.4.3 Back-gate charge

The most straightforward way to obtain the charge on the back-gate is toimpose the charge neutrality to the MOSFET. This condition is expressed bythe following equation :

0 = QGf +QGb +Qnf +Qif +Qof +Qib +Qob (III.111)

where Qof and Qob account for the fixed charge trapped in the front and backoxides.

III.4.4 Ward’s channel-charge partitioning scheme

In order to evaluate the drain and source charges, a proper scheme must befound to perform the partition of the channel charge. Fossum indicated in[III.21] that the partition scheme is of importance for the correct evaluationof the transient currents at the drain and source. They pointed out that themost appropriate scheme was first introduced by Ward in [III.22]. Ward’spartitioning scheme is derived from the continuity equation, which describesthe charging of the inversion layer and the interface states at some point alongthe channel :

∂ICf (x, t)

∂x= W

∂Q′′nf (x, t)

∂t+∂Q′′if (x, t)

∂t+∂Q′′ib(x, t)

∂t

(III.112)

Integrating (III.112) twice along OX , the following general relationships areobtained which relate the time-dependent current at the source and drain to

III-34

III.4 Dynamic currents

modifications of the charge density profiles :

IS (t) =d

dt

[W

∫ L

0

(1− x/L

) (Q′′nf (x, t) +Q′′if (x, t) +Q′′ib(x, t)

)dx]

−1

L

∫ L

0

ICf (x, t) dx

(III.113)

ID (t) =d

dt

[W

∫ L

0

(x/L

) (Q′′nf (x, t) +Q′′if (x, t) +Q′′ib(x, t)

)dx]

+1

L

∫ L

0

ICf (x, t) dx

(III.114)

Using the quasi-static assumption detailed in section III.4.1, the space averageof the instantaneous channel current can be approximated by the static currentIDS expressed by (III.67). Comparison of the previous two equations with(III.93) and (III.92) then allows to formulate the definition of the source anddrain charges :

QS ,W∫ L

0

(1− x/L

) (Q′′nf (x, t) +Q′′if (x, t) +Q′′ib(x, t)

)dx (III.115)

QD ,W∫ L

0

(x/L

) (Q′′nf (x, t) +Q′′if (x, t) +Q′′ib(x, t)

)dx (III.116)

III.4.5 Drain and source charges

Applying the definitions developed in the previous sections, one can easily verifythat the sum of the source and drain charges is equal to the total charge storedin the channel and in the front and back interface states :

QD + QS = Qnf +Qif +Qib (III.117)

As all quantities on the right-hand side have already been evaluated in sec-tion III.4.2, it is sufficient to evaluate QD only, as QS can be deduced from theequation above.

In order to compute the drain-charge integral, it is split into the contributionfrom the linear region and the one from the saturation region :

QD = QD[0 ,L(eff )] +QD[L(eff ),L] (III.118)

Linear region The evaluation of QD in the linear region is performed by sub-stituting the expression for dx and x from section III.4.1 into equation (III.116).It is useful at this point to introduce new variables ξ and ξ0 which allow tosimplify the charge expressions :

ξ ,Q′′nif

κf C′′of

+ ξ0 and ξ0 ,FDS

η vn(sat) W κf C′′of

− φT (III.119)

III-35

Modelling fully depleted SOI MOSFET’s

This procedure yields :

QD[0 ,L(eff )] =κf C

′′of W

120L

(µeff W[Q′′nif

]P(eff )

S

FDS

)2

×−15 ξ0

(ξP(eff ) + ξP(eff )

)2+ 12 ξ3

P(eff ) + 24 ξ2P(eff ) ξS + 16 ξP(eff ) ξ

2S + 8 ξ3

S

− 5⟨Q′′if⟩P(eff )

S

[−12 ξ0

(ξP(eff ) + ξS

)+ 9 ξ2

P(eff ) + 10 ξP(eff ) ξS + 5 ξ2S

]+ 20

(⟨Q′′if⟩P(eff )

S

)2 [−3 ξ0 + 2 ξP(eff ) + ξS

]+W

L2(eff)

2L

⟨Q′′ib⟩P(eff )

S(III.120)

Saturation region As all charge densities have been assumed constant inthis region, the contribution of the saturation region to the drain charge iseasily evaluated as :

QD[L(eff ),L] = W

(L− L(eff)

) (L+ L(eff)

)2L

×Q′′nifP(eff ) +

⟨Q′′ib⟩P(eff )

S

(III.121)

III.4.6 Alternative formulation of the charge model

The formulation of the charge model described in the previous sections stemsfrom a black box approach of the MOSFET, where each terminal is consideredas a source of charging current. The model structure — topology — does notreveal the essential features of the underlying physics of the device. For exam-ple, the charge conservation must be imposed as an additional constraint onthe charge sources as with the combined equations (III.111) and (III.117). Thetranslation of this constraint into the model topology, as shown in figure III.9,fails to account for the fact that the main charging currents occur between thesource/drain terminal and the front gate.

The use of an adequate model topology may enhance the accuracy of circuitsimulation, in particular the evaluation of the capacitances to the back-gate.For this reason an alternative formulation of the charge model is proposedwhich accounts for the specific behaviour of the SOI MOSFET.

III-36

III.4 Dynamic currents

QS QD

IDSQGf

Source

Back Gate

Drain

Front Gate

Figure III.9: The conventional macroscopic charge model.

QGfS QGfDQGfGb

Source Drain

Front Gate

Back Gate

QGbS QGbDIDS

Figure III.10: The alternative physically-based circuit topology.

III-37

Modelling fully depleted SOI MOSFET’s

The model is readily deduced from the charge expressions developed above.

QGfS ,−1

κf

(QnifS +

Qof

2

)+

1− κb

κb

(QibS +

Qob

2

)−

1 +C′′bob

C′′ob

4 κfQb (III.122)

QGfD ,−1

κf

(QnifD +

Qof

2

)+

1− κb

κb

(QibS +

Qob

2

)−

1 +C′′bob

C′′ob

4 κfQb (III.123)

QGbS ,1− κf

κf

(QnifS +

Qof

2

)+−1

κb

(QibS +

Qob

2

)−

1 +C′′bof

C′′of

4 κbQb (III.124)

QGbD ,1− κf

κf

(QnifD +

Qof

2

)+−1

κb

(QibD +

Qob

2

)−

1 +C′′bof

C′′of

4 κbQb (III.125)

QGfGb ,W L

1/C′′of + 1/C′′b + 1/C′′ob

(VGf −∆W f + ∆W b − VGb

)+ C′′of

∣∣E‖sat

∣∣ l2CLM

(cosh(

∆L(eff)

lCLM)− 1

) (III.126)

where the following notations were used for charge integrals :

QnifS ,W∫ L

0

(1− x/L

)Q′′nif dx (III.127)

QibS ,W∫ L

0

(1− x/L

)Q′′ibdx (III.128)

QnifD ,W∫ L

0

(x/L

)Q′′nif dx (III.129)

QibD ,W∫ L

0

(x/L

)Q′′ibdx (III.130)

The front and back channel body coefficients are defined by :

κf , 1 +C′′bob

C′′of

and C′′bob,C′′ob C

′′b

C′′ob + C′′b(III.131)

κb , 1 +C′′bof

C′′ob

and C′′bof,C′′of C

′′b

C′′of + C′′b(III.132)

This charge model has been used for the implementation of the SOI MOSFETroutines into the harmonic balance simulator OSA. This model topology is alsoat the basis of the small signal distributed channel model developed in the nextsection.

III.5 Operation at microwave frequencies

All developments of section III.4 rely on the quasi-static assumption which wasintroduced in subsection III.4.1. This assumption reduces the applicability of

III-38

III.5 Operation at microwave frequencies

the model to signals which vary slowly with respect to the channel propagationdelay, so that, at this peculiar time-scale, a static distribution may be usedat all instants for the channel charge density. In microwave operation, thisquasi-static condition is generally not met. This can be easily verified using asimple evaluation of the channel propagation delay used by Tsividis in [III.6]for similar purposes. The order of magnitude of the channel propagation delay,O(τCf ), for a MOSFET at the onset of saturation is estimated on the basis ofthe time needed for a carrier to cross the whole channel :

O(τCf ) uL2

µVDS(III.133)

In the case of a 1.0 micrometer channel at 1.0V, the formula predicts an order ofmagnitude around 20 picoseconds, which is a non-negligible fraction of the 500picosecond period of a 2GHz sinusoid. The case of a MOSFET in saturation iseven rather favourable, due to the presence of the strong longitudinal field whichsweeps the carriers through the device at high speeds. The worst situation interms of channel delay is at VDS = 0.

In order to extend the applicability of the quasi-static current and chargeexpressions to operation at microwave frequencies, it has been proposed to splitthe channel into sufficiently small sections where the quasi-static conditionswould eventually be fulfilled. Tsividis reported an alternative approach basedon the continuity equation which allowed to obtain analytical expressions of thesmall-signal waveforms along the channel in the case of a bulk MOSFET. Usingthese waveforms, he proposed a small-signal equivalent circuit topology for theMOSFET in non-quasi-static operation. A similar approach is developed insubsection III.5.2 to obtain an analytical model of the worst-case situation,namely at VDS = 0. The draw-back of these analytical models, is that theyapply only to small signals. In order to obtain a model of sufficient generality— i.e., allowing large-signal excitations at any bias point — the first approachwill be used : In section III.5.3, the channel is split into discrete chunks, wherethe quasi-static current and charge expressions are applied. The analyticalmodel can then be used to evaluate the accuracy of the discretisation scheme,and decide in particular whether enough channel sections were introduced.

III.5.1 The non-quasi-static small-signal model topology

Using the current transport and the current-continuity equations, several au-thors propose analytical expressions for the small-signal waveforms propagatingalong the channel of bulk MOSFET’s. Using an iterative solution method ofthe same systems of equations, Bagheri and Tsividis, [III.23], developed ana-lytical expressions of all elements of the indefinite admittance matrix charac-terising the bulk MOSFET in non-quasi-static operation. Tsividis proposed inhis book [III.6] the equivalent circuit topology of the figure as implementationfor the NQS admittance matrix in a simulator. The capacitances are derived

III-39

Modelling fully depleted SOI MOSFET’s

Front Gate

Source

Drain

Back Gate

CGfDi RGfDi CGbDiRGbDi

CGfSi RGfSi CGbSiRGbSi

GDi

LDi

CGfGbi

Gmbi

1+j ω τ1

Gmfi

1+j ω τ1

Figure III.11: Non-quasi-static small-signal equivalent circuit for the intrinsicMOSFET.

from the conventional charge model as follows :

CGfSi , −dQGf

dVSCGfDi , −

dQGf

dVD(III.134)

CGbSi , −dQGb

dVSCGbDi , −

dQGb

dVD(III.135)

CGfGbi , −dQGf

dVGb(III.136)

The (trans-)conductances are given by :

Gmfi ,dID

dVGf(III.137)

Gmbi ,dID

dVGb(III.138)

GDi ,dID

dVD(III.139)

The resistors RGfSi , RGfDi , RGbSi and RGbDi as well as the inductor LDi modelthe NQS effects by introducing several new time-constants which account forthe delays in the channel response. These circuit elements are defined as :

RGfSi CGfSi = RGbSi CGbSi = τ1 − τ2 (III.140)

RGfDi CGfDi = RGbDi CGbDi = τ1 − τ3 (III.141)

LDi GDi = τ1 (III.142)

Tsividis, [III.6], reports expressions of the time-constants as a function of theapplied bias-voltages in the case of bulk MOSFET’s. These expressions can be

III-40

III.5 Operation at microwave frequencies

easily adapted to the SOI MOSFET :

τ1 =4

15

1

ω0

1 + 3 ν + ν2(1 + ν

)3 (III.143a)

τ2 =1

15

1

ω0

2 + 8 ν + 5 ν2(1 + ν

)2 (1 + 2 ν

) (III.143b)

τ3 =1

15

1

ω0

5 + 8 ν + 2 ν2(1 + ν

)2 (2 + ν

) (III.143c)

where ν and ω0 are given by :

ν , 1−VP(eff )

VP(sat)(III.144)

ω0 ,µ(VGf − VThf

)κf L2

(III.145)

III.5.2 The distributed channel model at VDS = 0

VC VC + dVC

Front Gate

Back Gate

dx · C′GfGb

dx · C′GfC

dx · C′GbC

dx ·R′Cf

Figure III.12: The distributed equivalent circuit of the channel at VDS = 0.

At zero drain/source bias, the surface potential and the inversion chargedensity are uniform across the whole device. The small-signal series resistanceR′Cf and the capacitances of an infinitesimal channel section to the front andback gates, C′GfC and C′GbC , are thus constant along the channel. As a result,the channel of a SOI MOSFET propagates small-signal waveforms applied atits ends as a distributed RC line when both gates are connected to the RFground. Classical transmission-line theory then provides simple expressions forthe propagation constant, γCf , the characteristic impedance, zCf , and finallythe admittance matrix of the common-gates SOI MOSFET at VDS = 0 , YCf .

III-41

Modelling fully depleted SOI MOSFET’s

Frequency[Hz]20

40

60

80

100

120

140

R(i, j)

[Ω]

108 109 1010

R(2 , 2)

R(1 , 2)

R(2 , 1)

R(1 , 1)

108 109 10100

0.1

0.2

0.3

0.4

-0.50

0.5

0.2

1

CGf

[pF]

VGf

[V]

Figure III.13: The distributed effects in the channel at VDS = 0 of acommon-source MOSFET : A series resistance at the gate terminal, resis-tive coupling between drain and gate, variation of R(i, j) , Re(Z(i, j)) and of

CGf ,[− Im(Z(1 , 1 ))ω

]−1versus frequency.

γCf ,√j ω R′Cf

(C′GfC + C′GbC

)(III.146)

zCf ,√

R′Cf

j ω(C′GfC + C′GbC

) (III.147)

YCf =1

zCf sinh(γCf L)

[cosh(γCf L) −1−1 cosh(γCf L)

](III.148)

The expressions for the capacitances per unit-length of channel are readilyobtained from the alternative charge model, considering a uniform distributionof charge :

C′GfC = W1

κf

dQ′′nf

dVC(III.149)

C′GbC = Wκf − 1

κf

dQ′′nf

dVC(III.150)

Using the transcendental equation of the inversion charge proposed by Parket al. in [III.11], the evaluation of the above expressions can be considerablysimplified :

dQ′′nf

dVC= −Q′′nf

(φT −

Q′′nf

κf C′′of

)−1

(III.151)

The series resistance per unit-length follows immediately from equation (III.62)of the transport model.

R′Cf , RCf /L = −W µQ′′nf (III.152)

III-42

III.5 Operation at microwave frequencies

In order to fully characterise the small-signal response of the SOI MOSFET,a 4 × 4 admittance matrix is required which relates the terminal currents tothe applied small-signal voltages as shown in (III.153) :

IDIGb

IGf

IS

= YFET ·

VD

VGb

VGf

VS

(III.153)

The sixteen admittance elements can be computed very easily if one considersthe following four independent excitation schemes :

1. Drain excitation, VD 6= 0, while all other terminals are connected to thesignal ground, VS = VGb = VGf = 0;

2. Source excitation, VS 6= 0, while VD = VGb = VGf = 0;

3. Common mode excitation of the gates, VGf = VGb 6= 0 while the sourceand drain are grounded, VS = VD = 0;

4. Asymmetric excitation of the gates, VGf = −κGbC/κGfC VGb 6= 0, whileVD = VS = 0. The peculiar excitation ensures that all points of the chan-nel remain level with the source and drain, so that the series small-signalcurrent is uniformly zero in the channel, which simplifies the calculations.

Calculating the small-signal currents at all ports, and rearranging the expres-sions in function of the terminal voltages then yields the small-signal admit-tance matrix of the MOSFET :

YFET =YCf (1 ,1 ) −κGbC

∑k YCf (1 , k)

−κGbC

∑k YCf (k , 1 ) κ2

GbC

∑k, l YCf (k , l) + ω

(κ2

GbC CGfC + CGfGb

)−κGfC

∑k YCf (k , 1 ) κGfC κGbC

∑k, l YCf (k , l) − ω

(κ2

GbC CGfC + CGfGb

)YCf (2 ,1 ) −κGbC

∑k YCf (2 , k)

−κGfC

∑k YCf (1 , k) YCf (1 , 2 )

κGfC κGbC

∑k, l YCf (k , l) − ω

(κ2

GbC CGfC + CGfGb

)−κGbC

∑k YCf (k , 1 )

κ2GfC

∑k, l YCf (k , l) + ω

(κ2

GfC CGbC + CGfGb

)−κGfC

∑k YCf (k , 1 )

−κGfC

∑k YCf (2 , k) YCf (2 , 2 )

(III.154)

where the following notations were used :

κGfC ,C′GfC

C′GfC + C′GbC

(III.155)

κGbC ,C′GbC

C′GfC + C′GbC

(III.156)

CGfC , LC′GfC (III.157)

CGbC , LC′GbC (III.158)

III-43

Modelling fully depleted SOI MOSFET’s

The capacitance CGfGb is the depletion capacitance of the structure and stemsdirectly from the alternative charge model.

CGfGb , −dQGfGb

dVGb(III.159)

This model has proven particularly useful for the wide-band extraction of themobility model parameters from S-parameters measurements as described inanother chapter.

III.5.3 A non-quasi-static large-signal channel model

QGfC (k) QGfGb

Source Drain

Front Gate

Back Gate

QGbC (k)

ICf (k)

k = 1 k = Nk = 0

Figure III.14: Topology of the discrete channel model.

In order to better account for the charging delays, the MOSFET structure isdivided into N chunks along the channel. All chunks have a fixed length equalto L/N . The endpoints of these channel sections are numbered from 0 at thesource to N at the drain. Each channel section is considered to be a transistorwith its own charges and current. The model topology is a generalisation of thealternative charge model presented in section III.4.6. At each channel point klocated at x = xk, two nonlinear charge “sources” are connected to the frontand back gate. These charges correspond to a weighted integral of the chargedensities around the channel point :

QGfC (k) = QGfD[xk−1 , xk ] +QGfS [xk , xk+1 ] (III.160)

QGbC (k) = QGbD[xk−1 , xk ] +QGbS [xk , xk+1 ] (III.161)

where QGfD[xk−1 , xk ] is the gate/drain charge of section k considered as tran-sistor with its source at xk−1 and its drain at xk. It is evaluated according tothe alternative charge model. Special cases arise at the drain and source of thecomplete SOI MOSFET structure :

QGfC (0 ) = QGfS [x0 , x1 ] (III.162)

QGbC (N ) = QGbD[xN−1 , xN ] (III.163)

III-44

III.5 Operation at microwave frequencies

The state of each channel point is characterised by by a voltage, VC (k), anda charging level of the interface states Q′′if (k) and Q′′ib(k). When N is chosen sothat the the last section on the drain-side of MOSFET structure is sufficientlylong to comprise the whole saturation region in all biasing configurations, thenonly this section must be capable of saturation and channel length modula-tion. All other sections will always function in the linear regime. As a result,the inversion charge density values Q′′nf (k) necessary for the evaluation of the

charges and the currents can be deduced directly from equation (III.37) for allchannel points except the drain-point, numbered N . The threshold voltage isevaluated at each channel point according to expression (III.55) with VDS be-ing the drain/source voltage applied to the whole MOSFET structure. Q′′nf (N )

is computed according to the unified model described in section III.3.4. Thecharges at points N − 1 and N must take the contribution of the saturationregion into account.

To obtain the response of the MOSFET to an input wave-form, the simu-lator into which the model is implemented, must determine all of the channelpoint voltages VC (k) so that the Kirchoff’s equations at all channel nodes areverified. These Kirchoff’s equations represent in effect a discrete version of thecontinuity equation, and implement a higher-order partitioning scheme thanthe Ward’s scheme. The accuracy gained for the high-frequency response ishowever traded for computation time. As N increases, the number of nonlin-ear current sources increases, and the resolution of the circuit equations slowsdown. Careful selection of N is necessary, to obtain accuracy at an afford-able price. By comparing the responses predicted by the analytical distributedchannel model and the discrete channel model at VDS = 0 — which is knownto be a worst case situation —, one can find that three channel sections seemto realise a good compromise.

Frequency[Hz]

CGf

[pF]

108 109 10100.1

0.15

0.2

0.25

0.3

0.35

Transmission line

Three sectionsFive sections

Single section

0

20

40

60

80

100

120

108 109 1010

140

R(i, j)

[Ω]

R(2 , 2)

R(2 , 1)

R(1 , 1)

Figure III.15: Comparing the analytical distributed channel model and thediscrete model with N = 1, 3, 5, at VGf = 1.0 V and VDS = 0.

III-45

Modelling fully depleted SOI MOSFET’s

III.6 Small-signal model for the extrinsic device

Up till now, the attention has been focussed exclusively on the intrinsic partof the device. The intrinsic model does however not suffice to describe thebehaviour of the MOSFET at high frequencies. It is now thus necessary toconcentrate on the extrinsic part, which is defined mainly by its complemen-tarity to the intrinsic part. All physical phenomena which were not accountedfor in the intrinsic model, become de facto part of the extrinsic model. Ac-cording to the description given in the introductory section III.1.4, the extrinsicmodel must account for : diffusion and contact resistances, overlap and fring-ing capacitances from the front gate to the diffusions, junction capacitance,substrate coupling effects, resistivity of the polysilicon gate, edge effects of theactive zone, etc. Several of these effects have even a determining influenceon the performance of the SOI MOSFET at microwave frequencies, as Jean-Pierre Raskin and Jian Chen demonstrated in their doctorate thesis, [III.24]and [III.25].

III.6.1 Diffusion and contact resistances

In MOSFET technology, the current leaving the channel must travel some dis-tance in the diffusion regions, in order to reach the nearest contact hole wherea connection to the metal layer is achieved. This short section of the currentpath is responsible for the almost all of the extrinsic resistance in series withthe transistor channel. Indeed, even heavily doped silicon offers only a limitedconductivity which combined with the limited film thickness, results in sheetresistivities on the order of several tens of Ω/. In comparison, one micrometerthick aluminium lines have a resistivity on the order of 0.03 Ω/. As demon-strated by Chen, [III.25], formation of a metal silicide on the diffusion regionallows not only to reduce the sheet resistivity down to 2.0 Ω/, but also toenhance the quality of the contacts to the metal layer. Raskin, [III.24], showedthat reduction of the extrinsic source resistance RSe is of primary importancefor the microwave performance of the common source MOSFET : RSe not onlyproduces an unwanted feedback which tends to reduce the power gain of theMOSFET, but also influences the noise performance detrimentally.

The contribution of the diffusion and contact resistance to the extrinsicseries resistances at the source or drain, is readily evaluated as :

RXe =Ldiff

Wrdiff +

1

Nctctrctct (III.164)

where W is the width of the active zone, Ldiff is the diffusion length measuredfrom the metallurgical junction to the middle of the contact area, rdiff is thediffusion sheet resistivity and rctct is the resistance of an individual contact.Expression (III.164) is a low-frequency approximation for the extrinsic seriesresistances RSe and RDe . It does not account for signal propagation effectsalong the drain and source feeding lines. Subsection III.6.3 will show underwhich conditions the low-frequency approximation holds for source and drain.

III-46

III.6 Small-signal model for the extrinsic device

III.6.2 Parasitic capacitances

Microwave performance of MOSFET’s is essentially achieved by down-scalingof the device geometry. This allows to rise the current gain cut-off frequencyof the intrinsic device at the expense of an increased influence of the parasiticcapacitance on the device response. Indeed, some parasitic capacitances tendto be scaling-independent, such as the lateral gate-diffusion capacitance, or aredifficult to scale properly, as the gate-diffusion overlap capacitance. Adequatemodelling of these capacitances is necessary at microwave frequencies as thecharging currents which they drain become very important and eventually willcontribute significantly to the degradation of the current gain. Substrate cou-pling capacitances need also to be properly accounted for, particularly at thelower end of the microwave spectrum were the SOI substrate eventually goesthrough dielectric transitions which imply a radical change in its behaviour.

Overlap and fringing capacitances of the polysilicon gate

The development of submicrometer MOSFET technologies has urged the needto understand and model the geometry-dependence of the gate parasitic ca-pacitances, CGfSe and CGfDeWang, [III.26], distinguishes among several com-ponents of the gate parasitic components based on their specific dependenceupon the geometrical parameters of the gate :

1. The overlap capacitance, covlp , depending on the gate oxide thickness andthe length of the overlap between the gate and the diffusion.

2. The lateral capacitance, clatrl , depending mainly on the polysilicon thick-ness, the gate oxide thickness and on the spacer material. It is associatedwith the electric field emerging from the sidewalls of the gate.

3. The inner fringing capacitance, cinner , which is associated with the elec-tric field emerging from the bottom of the gate and converging towardsthe metallurgical junction of the diffusions. This capacitance is related toexistence of a depletion region controlled by the gate and the diffusion. Itscontribution vanishes when the device is biased in strong accumulation.

4. The top side capacitance, ctop , which is associated with the electric fieldemerging from the top side of the gate. It depends upon the gate length,the polysilicon thickness and the gate oxide thickness.

Approximate expressions for the first three capacitance components were pub-lished by Shrivastava in [III.27]; Wang proposed an approximation for the topside capacitance in [III.26]. It is however questionable whether these expres-sions based on a crude partition of the configuration are capable of sufficientaccuracy in order to allow extraction of geometrical parameters by curve-fitting.Huang et al., [III.28] preferred to use two-dimensional device simulation for thispurpose.

Few authors account for the bias-dependence of cinner , and simply modelthe effect to which it is associated by connecting a constant capacitor betweenthe gate and the source or drain diffusion. This is justified in the case of

III-47

Modelling fully depleted SOI MOSFET’s

ctop

clatrl

covlp

cinner

Metal contact

Gate polysilicon

Buried oxyde

Substrate

Figure III.16: Field lines of the differential electric field resulting from a per-turbation of VGf in the case of a depleted device.

depletion, but in strong inversion the surface potential value ψsf is known tobe pinned at approximately VC + 2φF , so that one may anticipate that theinner fringing electric field will stop varying once saturation is reached. A morerealistic model is obtained if one considers the charge associated with the innerfringing field, Qinner :

Qinner [S ] = W cinner

(ψsfS − VS

)(III.165)

Qinner [D] = W cinner

(ψsfD − VS

)(III.166)

These charges simply add to the gate/source and gate/drain charges of thealternative charge model. This model is valid as long as the film body remainsdepleted : from depletion to inversion.

Substrate coupling capacitances

Many authors involved in SOI MOSFET modelling consider that the underlyingsubstrate is sufficiently conducting so as to maintain a uniform potential at theinterface with the buried oxide. This is certainly the case at sufficiently lowfrequency, when the carriers have plenty of time to rearrange themselves closeto the interfaces in order to stop the penetration of a normal electric fieldinto the substrate material. At higher frequency, the delays involved in themechanisms supplying the carriers — diffusion or generation/recombination —allow only a partial rearrangement of the carriers so that the electric field canpenetrate the substrate.

Raskin et al., [III.29], investigated the substrate coupling effects on SOIwafers. They validated a modelling approach for multi-layer substrates, basedon the translation of the dielectric properties of individual layers into parallelRC circuits and their interconnection according to the topology of the electric

III-48

III.6 Small-signal model for the extrinsic device

Gate polysilicon

S. and D. diffusions

Buried oxyde

Substrate

CDSe

CSe

CSGbe

RSGbe

Figure III.17: Field lines of the differential electric field resulting from a high-frequency perturbation of VD int the case of a depleted device.

field lines. This technique applied to the SOI MOSFET structure yields theequivalent circuit of figure III.18.

Drain

Back Gate

Source

CDe

CSe

CDSe

CDGbe

RDGbe

CSGbe

RSGbeCGbe

RGbe

Wafer back-plane

Figure III.18: Equivalent circuit model of the substrate coupling effects.

The physical correspondence of each equivalent circuit element is illustratedin figure III.17 : The capacitance CDSe accounts for the coupling betweensource and drain occurring exclusively through the air or the oxide surroundingthe diffusion and the metal. The capacitances CDe and CSe account for thefield lines crossing the buried oxide. The resistances and capacitances CXGbe

and RXGbe account for field lines in the substrate under the buried oxide.The coupling to the wafer back-plane is embodied by RGbe and CGbe . As thedistance involved in this latter coupling is at least two order of magnitude larger

III-49

Modelling fully depleted SOI MOSFET’s

than the channel length — the characteristic distance for the drain/sourcecoupling —, it is clear that at high frequencies the back gate is more influencedby the capacitive coupling to the source and drain than by the presence of aground contact at the wafer back-plane. The DC voltage at the interface ofthe substrate and the buried oxide is however well controlled by the back-planecontact. The frequency at which the SOI structure switches from the DC tothe RF behaviour depends on the substrate resistivity. For a 200Ω/cm p-typewafer, the transition occurs around 100 MHz.

III.6.3 Lateral signal distribution in the basic MOSFETcell

In MOS technology, it is common practice to have metal lines run in parallel tothe polysilicon gate and to connect them at regular intervals with the diffusionsalong the width of the transistor. This design minimises the source and drainseries resistance as well as the amount of overlap between the various electrodes,and hence the parasitic capacitance. In technologies with multiple metallisationlevels, variations are possible, such as interconnection of the source lines bya “bridge” on top of the gate and drain lines, allowing further reduction inthe gate and source resistance at the cost of an increase in some parasiticcapacitances.

Gate polysilicon

Source metal Drain metalDiffusion

W

OZ

OX

Figure III.19: Top view of the basic MOSFET cell in a single metallisationand single polysilicon layer technology, showing the parasitic impedance of thefeeding lines.

The striking feature of these designs is that at least two of the lines are fed attheir ends, requiring the signal to propagate along the width of the transistor.In the case of small signals, the structure of figure III.19 can be described verygenerally as a section of coupled transmission lines : The distributed shuntadmittance matrix of the system corresponds to a MOSFET device of unit-width, comprising the intrinsic device, the drain and source series resistancesand the shunt capacitive parasitics. The distributed series impedance matrixaccounts for the resistance of the signal lines as well as their self- and mutualinductances. The dominating series parasitic effect is the gate resistance. For

III-50

III.6 Small-signal model for the extrinsic device

a sheet resistivity of 4.0 Ω/ and a gate-width of 1.0 µm, the gate resistanceis 4.0 Ω/µm, while the inductances result in a reactance of 0.018 Ω/µm at 10.0GHz and the metal resistance amounts to 0.0037 Ω/µm, for 8.0 µm lines of 1.0µm thick aluminium.

The gate resistance

To evaluate the effect of the resistivity of the gate line, it seems quite reason-able — in view of the figures given above — to assume that the metal linesare equipotential. As indicated in subsection III.6.2 dealing with substratecoupling, at sufficiently high frequency the back gate is not tied anymore tothe ground, but behaves as a floating node. These considerations allow to re-duce the coupled line system to a single transmission line for which the voltageand current distributions can be readily evaluated using adequate boundaryconditions :

VGf (z) =VGf [in]

cosh(γgate W )cosh(γgate z) (III.167)

IGf (z) =zgate VGf [in]

cosh(γgate W )sinh(γgate z) (III.168)

where VGf [in] is the applied voltage at the input of the gate line; γgate and zgate

are given by :

γgate ,√

Z ′Gfe Y ′FET(1 , 1 ) (III.169)

zgate ,√

Z ′Gfe

Y ′FET(1 , 1 )

(III.170)

Z ′Gfe is the lineic series impedance of the gate, including both resistive andinductive effects. Y′FET is the lineic admittance matrix of the common sourceMOSFET structure incorporating the diffusion resistances and the capacitiveparasitics. Y ′FET(1 , 1 ) is the diagonal element corresponding to the gate termi-nal.

Using the voltage waveform of equation (III.167), expressions can be ob-tained for the hybrid immittance elements of the complete MOSFET cell :

VGf

IGf

∣∣∣∣VD =0

, H(1, 1) = zgate coth(γgate W ) (III.171a)

IDIGf

∣∣∣∣VD =0

, H(2, 1) =Y ′FET(2 , 1 ) zgate

γgate(III.171b)

VGf

VD

∣∣∣∣IGf =0

, H(1, 2) = −Y ′FET(1 , 2 )

Y ′FET(1 , 1 )

(III.171c)

IDVD

∣∣∣∣IGf =0

, H(2, 2) = −WY ′FET(2 , 2 ) Y ′FET(1 , 1 ) − Y ′FET(1 , 2 ) Y ′FET(2 , 1 )

Y ′FET(1 , 1 )

(III.171d)

III-51

Modelling fully depleted SOI MOSFET’s

These equations call for some comments. As expected, the impedance seen atthe gate, H(1, 1), is affected by propagation effects. The current gain, H(2, 1), isparadoxally not affected by these effects, as can be seen from equation (III.172b),which is the exact expansion of (III.171b). The voltage gain, the forwardtransadmittance and the maximum available gain are however well influencedby the propagation characteristics of the gate line.

Chen pointed out in his thesis, [III.25], that reducing the length of thegate line is an efficient way of improving the microwave performance of SOIMOSFET’s. Microwave transistors designed in the present work typically havegate line lengths corresponding to an attenuation of the voltage less than 5 %.In this case, |γgate W | 1.0 so that the hyperbolic cotangent can be closelyapproximated by the series development shown in (III.172a) :

H(1, 1) u zgate

[ 1

γgate W+γgate W

3+O((γgate W )2)

]=

1

Y ′FET(1 , 1 )W+

Z ′Gfe W

3

(III.172a)

H(2, 1) =Y ′FET(2 , 1 )

Y ′FET(1 , 1 )

(III.172b)

H(1, 2) = −Y ′FET(1 , 2 )

Y ′FET(1 , 1 )

(III.172c)

H(2, 2) = −WY ′FET(2 , 2 ) Y ′FET(1 , 1 ) − Y ′FET(1 , 2 ) Y ′FET(2 , 1 )

Y ′FET(1 , 1 )

(III.172d)

These equations and particularly expression (III.172a), show that the small-signal propagation effects along the gate can be modelled accurately by insert-ing a resistor RGfe in series with the gate terminal of the “ideal” admittancematrix YFET :

RGfe ,W

3rpoly (III.173)

YFET ,W Y′FET (III.174)

Inductances

As can be inferred from the previous section, a discrete equivalent circuit modelshould also suffice to describe the influence of the inductive effects on the signaldistribution in the basic MOSFET cell. The narrow spacing imply an importantmagnetic coupling between the conductors, so that an accurate model of theinductive effects on the cell would require six parameters : three mutual andthree self-inductances. Very few authors have published such models — withsome rare exceptions in the case of work on travelling-wave devices. The mainreason for this is that inductive effects emanating from the distribution linesin the basic MOSFET cell are generally overwhelmed by the contribution ofexternal inductances.

III-52

III.6 Small-signal model for the extrinsic device

This is easily illustrated with the following case-study. In a saturated de-vice, the majority of the gate current charges the capacitor CGfSi and flowsback along the source line. The series inductance per unit-length in the gatecan thus be evaluated as the difference between the self inductance and thegate/source mutual inductance, or half of the lineic inductance value obtainedfor two coplanar strips, L′CPS . Equation (III.172a) then allows to deduce thetotal series inductance of the gate :

LGf [0 ,W ]e =W

6L′CPS (III.175)

For MOSFET’s fabricated at the UCL, L′CPS = 0.55pH/µm and W = 24µm,so that LGf [0 ,W ]e amounts to 2.2 pH, which is only one tenth of the valueroutinely extracted from measurements of such transistors.

III.6.4 Dedicated model for the common-source configu-ration

In order to compensate for the limitation on the transistor width W imposedby the propagation characteristics of the basic MOSFET cell, several identicalcells are placed in parallel and interconnected to form the interdigitated combsstructure occupying the active zone indicated in figure III.20.

Gate Drain

Measurement planes

Active Zone Edges

Figure III.20: Layout of a common source MOSFET structure embedded in acoplanar waveguide.

III-53

Modelling fully depleted SOI MOSFET’s

The effect of the interconnection of Ncell basic cells on the equivalent circuitparameters can be readily evaluated by replacing the width parameter W bythe product Ncell ·W in all previous equations, with the exception of equationsinvolving inductances. The scaling rules for the inductances of the multiplecell structure are complicated by the mutual coupling between traces and bythe inductance of the cross-connections. One may however expect that theglobal inductance values in the multiple cell structure will be less than thecorresponding values for a single cell, so that the contribution of inductiveeffects from the active zone is finally quite small.

To be consistent with the measurement procedure described in a previouschapter, the model must be extended to include the contribution of all regionsenclosed within the reference planes. In particular, the effects of the metallines and tapers running from the reference planes to the active zone must beaccounted for. These short interconnections are modelled using the lumpedequivalent circuit of figure III.21. The topology of the shunt sub-circuit is in-herited directly from the substrate coupling model of Raskin, [III.24]. The in-ductance Lmet can be approximated using the lineic inductance for the coplanarwaveguide, L′CPW = 0.4 pH/µm, multiplied by an effective length dependingupon the layout geometry. Typically : Lmet u L′CPW × 60.0µm = 24.0 pH.

Cair

Cbox

Csubs Rsubs

Lmet Rmet

Figure III.21: Equivalent circuit for the coplanar waveguide taper structures.

The complete equivalent circuit for the as-measured common-source SOIMOSFET is shown in figure III.22. The intrinsic part corresponds to three mod-els described in section III.5. The substrate model is detailed in figure III.18.The dominant contribution to RSe and RDe comes from the diffusion resistanceas explained in subsection III.6.1. The value of RGfe is affected by distributioneffects described in subsection III.6.3. CGfSe and CGfDe comprise the overlap,the lateral and the top parasitic capacitances of the gate which were intro-duced in subsection III.6.2. The inductances LGfe and LDe are dominated bythe contribution from the lines and tapers. The source inductance LSe is at-tributed to the vertical path connecting the source of all basic cells to ground.The admittance YGfa groups the contributions of the shunt elements from theinput line and taper, together with the capacitances due to the crossings ofpolysilicon lines and the source interconnection metal. YDa is due to the lineand taper at the output. YGfDa corresponds to the capacitive coupling occur-

III-54

III.7 Model limitations

ring between the gate and drain lines outside of the active zone. The index “a”means adjacent — designating effects located just outside of the active zone.YGfa , YDa and YGfDa are thus by definition independent of W .

IntrinsicMOSFET

Substrate

Drain

Front Gate

Source

CGfDe

CGfSe

LGfe RGfe

RDe

LDe

LSe RSe

YGfa

YDa

YGfDa

Figure III.22: The complete equivalent circuit topology for the SOI MOSFET.

III.7 Model limitations

This section discusses the restrictions which apply for the simulation of fullydepleted SOI MOSFET’s using the model described in this chapter. A user-oriented perspective is adopted and all limitations are expressed in terms ofvalidity ranges constraining input parameters or variables.

III.7.1 Channel length

Three short-channel effects have been identified in section III.2.5 : Channel-length modulation, drain-induced barrier lowering and charge-sharing. Sec-tions III.2.5 and III.3.3 provide the means to account for these effects withinthe frame-work of the charge-sheet model, thus extending its applicability toshort-channel devices.

The channel-length modulation effect is introduced using the effective chan-nel length L(eff) evaluated according to the algorithm described in section III.3.4and based essentially on equation (III.88). The main parameter in this equation

III-55

Modelling fully depleted SOI MOSFET’s

is lCLM , the characteristic length, which contains all technological dependen-cies of equation (III.88). More precisely, in fixed biasing conditions, lCLM

determines the effective channel shortening, ∆L(eff) = L− L(eff), directly.

lCLM , tb

√C′′b

2 κf C′′of

(1 +

C′′bC′′b + C′′ob

)(III.176)

The ratio (lCLM/L) can hence be used as invariant characterising the severityof the channel-length modulation effect for various SOI MOSFET designs.

Drain-induced barrier lowering is modelled by a threshold voltage correctiongiven in equation (III.55). This correction is proportional to the applied drain-source voltage, VDS , and the proportionality constant κfD is given by :

κfD ,(

1 +C′′b

C′′b + C′′ob

) C′′b t2b

C′′of L2

=2 κf l

2CLM

L2(III.177)

where the ratio (lCLM/L) can be again identified as a measure of the severityof the short-channel effect.

Charge-sharing has not been included in the model because Colinge, [III.2],has shown that, in the case of 100 nm-thick films, charge-sharing only has aninfluence when L < 0.3µm, which well below the smallest feasible channellength in the UCL technology.

As already stated in section III.5.3, the discretisation scheme applied tothe channel combined with the constraint that only a single section may be insaturation, imposes a practical limit on the smallest channel length :

L > N max(∆L(sat)) (III.178)

In the case of the UCL technology, with its 100 nm-thick silicon film, a maxi-mum supply voltage of 3.0 V and three channel sections, the limit turns out tobe 0.36µm.

In this work, the model has been successfully used for MOSFET’s fabricatedat the UCL with channel lengths in the range of 1.5µm to 0.6µm. Using thelCLM/L invariant, these results can be extrapolated to the LETI technology,[III.30], where they correspond to channel lengths between 0.5µm and 0.2µm,thanks to the vertical down-scaling of the structure. As the charge-sharingeffect diminishes when the thickness decreases, one may expect that it willhave no significant influence for LETI devices even around 0.2µm.

III.7.2 Biasing conditions

There exist several limitations to the range of biasing conditions over whichthe characteristics predicted by the current and charge model are valid. Inthe case of the gate voltage, VGf , the limitation stems from the expressionsof the channel charge density, (III.36) or (III.37), which are only valid fromdepletion to strong inversion, excluding all negative gate voltages at whichpartial depletion or front-accumulation occur. For the UCL technology, therange is typically : −1.5 V < VGf .

III-56

III.7 Model limitations

The back-gate voltage is limited by the condition Q′′nb ≡ 0 imposed in sec-tion III.2.1. Accumulation and inversion of the back-channel must be avoided,so that VGb must be enclosed between the flat-band voltage across the buriedoxide and the threshold voltage for the inversion of the back-channel. Thetypical range for the UCL MOSFET’s is thus approximately : −10 V < VGb <+10 V.

The drain voltage is limited by the avalanche break-down phenomenonwhich is not accounted for in the model. Avalanching not only affects thecurrent-voltage characteristics but also increases the capacitive drain-gate cou-pling by the accumulation of holes at the bottom of the film. At the UCL, thebreakdown voltage lies higher than 3 V for 1.0µm channel lengths. Self-heatingalso limits the validity range for the drain-voltage, as the model assumes a fixedtemperature for the device. Experience has shown that self-heating becomesnon-negligible when the DC power consumption rises above 0.2 mW/µm ofchannel width.

III.7.3 Scaling rules

Scaling rules were described in section III.6. The fundamental scaling equationsare (III.173) and (III.174) which define the scaling along a single gate finger.Rules (III.173) and (III.174) apply only when the attenuation of the signalalong the gate is sufficiently low. An upper-bound to the active zone width,W , can be found if a maximal attenuation along the gate, ARC (max), is specifiedat some frequency :

W <√

2acosh(A−2

RC (max))√ω C′′of rpoly

(III.179)

In the UCL technology, a maximal attenuation of 0.5 dB at 40 GHz imposes anupper limit of 30µm on the active zone width.

The scaling rules for a single gate-finger are completed with rules for struc-tures comprising multiple fingers in subsection III.6.4. The scaling rule forthe number of gate-fingers, Ncell , is a plain proportionality rule. One may ex-pect that this rule remains valid as long as the lateral extent of the transistorstructure remains on the order of the ground to ground spacing of the feedingCPW’s.

The additional scaling rules mentioned in subsection III.6.4 also state thatall adjacent admittances are independent on the active zone width, W . Thisassumption results in a lower bound on W , because direct coupling betweenthe gate- and drain-feed becomes important at small W , typically around a fewµm.

III.7.4 Frequency

For the non-quasi-static small-signal model of section III.5.1, the frequencylimits of validity has been given by Tsividis, [III.6], and corresponds to thecharacteristic pulsation ω0 given in equation (III.145). For 1.0µm MOSFET’sin saturation, the limit lies above 40 GHz.

III-57

Modelling fully depleted SOI MOSFET’s

The distributed channel model of section III.5.2 is essentially broadband,so that the frequency limitation will be rather determined by the validity ofthe extrinsic and adjacent equivalent circuit models, which will be shown inchapter IV to be valid up to at least 20 GHz. Raskin, [III.24], has shown thatsimilar equivalent circuits did apply up to 40 GHz for SOI MOSFET’s.

The frequency limit of validity in the case of the multiple chunks model ofsection III.5.3 depends essentially on the number of channel partitions, N . Theworst-case situation has been identified in section III.5.3 as the zero drain-biascondition, allowing to evaluate the validity of the multiple chunks model bycomparison with the distributed channel model. The multiple chunks modelwill be valid as long as a single channel section is properly approximated bythe discrete equivalent circuit. This constraint can be expressed as :∣∣ L

NγCf

∣∣ < 1 (III.180)

where γCf is given by equation (III.146). Equation (III.180) shows that 3sections are sufficient to describe 1.0µm SOI MOSFET’s fabricated at theUCL up to 40 GHz.

III.8 Conclusion

Contributions of several authors were gathered in this chapter to produce astate-of-the-art model for the SOI MOSFET operating at microwave frequen-cies. The conventional charge-sheet model provided the framework onto whichshort-channel effects, dynamic interface states and distributed channel effectswere grafted. Unique features of the present work are :

1. The comprehensive treatment of non-quasi-static effects : The introduc-tion of multiple channel sections in the large-signal current and chargemodel; The formulation of a small-signal distributed channel model atVDS = 0, and particularly its use to evaluate the number of discretesections required to properly account for NQS effects.

2. The elaborate substrate model providing the adequate environment to theback-gate : Resistive coupling to the wafer back-plane at DC, capacitivecoupling to the diffusions at microwave frequencies.

3. The formulation of the “alternative” charge model. Its topology revealsthe structure of the underlying charge equations. This should enhancethe accuracy of numerically evaluated derivatives.

4. The combination of the unified inversion charge model from Inıguez, [III.10]with the modelling approach proposed by Veeraraghavan in [III.15] forthe short-channel effects and particularly the channel length modulation.

5. The introduction of the interface charges as state-variables controlled byspecific time-constants. This was necessary to allow a unified treatmentof both DC and high-frequency responses, particularly in sub-thresholdoperation.

III-58

REFERENCES

Frozen interface charge

Dynamic interface charge

0 0.5 1 1.5 2 2.5 30

100

200

300

400

5001

2

3

VDS

[V]

GDi−1[Ω]

VGf

[V]

-0.5 0 0.5 1 1.50

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

VGf

[V]

CGfi

[pF]

VDS = 0.0

Figure III.23: Influence of the interface charge on the output conductance GDi

and on the total gate capacitance CGfi =dQGf

dVGf.

The models developed here are compact, in the sense that they use a limitednumber of empirical parameters in addition to the technological data. Thiswas achieved by basing all developments on thorough insight in the underlyingphysical phenomena. A second important characteristic of the models is thatthe predicted curves are continuous and infinitely derivable over the whole biasrange.

The models described in this chapter have been successfully tested on SOIMOSFET’s fabricated mainly at the UCL with channel-lengths ranging from1.5µm to 0.5µm. Detailled comparisons of predicted and measured character-istics indicating the validity of the various models are presented in chapter IV.

References

[III.1] D. Flandre, Etude de Faisabilite d’une technologie CMOS sur Isolant(SOI) dans le Domaine des Circuits Digitaux. PhD thesis, Universitecatholique de Louvain, Laboratoire de Microelectronique, 1990.

[III.2] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI.Boston: Kluwer Academic Publ., 1991.

[III.3] Y. P. Tsividis and P. Suyama, “MOSFET modeling for analog cir-cuit CAD : Problems and prospects,” IEEE J. of Solid-State Circuits,vol. 29, pp. 210–216, Mar. 1994.

III-59

Modelling fully depleted SOI MOSFET’s

[III.4] B. Agrawal, V. K. De, J. M. Pimpbley, and J. D. Meindl, “Shortchannel models and scaling limits of SOI and bulk MOSFET’s,” IEEEJ. of Solid-State Circuits, vol. 29, pp. 122–125, Feb. 1994.

[III.5] J. R. Brews, “A charge-sheet model of the MOSFET,” Solid StateElectronics, vol. 21, pp. 345–355, 1978.

[III.6] Y. P. Tsividis, Operation and Modelling of the MOS Transistor. NewYork: Mc Graw-Hill, 1987.

[III.7] C. Mallikarjun and K. N. Bhat, “Numerical and charge sheet mod-els for thin-film SOI MOSFET’s,” IEEE Trans. on Electron Devices,vol. 37, pp. 2039–2051, Sept. 1990.

[III.8] A. Ortiz-Conde, F. J. Garcia-Sanchez, P. E. Schmidt, and A. SaNeto,“The foundation of a charge-sheet model for the thin-film MOSFET,”Solid State Electronics, vol. 31, no. 10, pp. 1497–1500, 1988.

[III.9] L. F. Ferreira, not accepted yet. PhD thesis, Universite catholique deLouvain, 1998.

[III.10] B. Inıguez, L. F. Ferreira, B. Gentinne, and D. Flandre, “A physically-based C∞-continuous fully-depleted SOI MOSFET model for analogapplications,” IEEE Trans. on Electron Devices, vol. 43, pp. 568–575,Apr. 1996.

[III.11] C.-K. Park, C.-Y. Lee, K. Lee, B.-J. Moon, Y. H. Byun, andM. Shur, “A unified current-voltage model for long-channel nMOS-FET’s,” IEEE Trans. on Electron Devices, vol. 38, pp. 399–406, Feb.1991.

[III.12] H.-K. Lim and J. G. Fossum, “Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFET’s,” IEEE Trans. on Electron Devices,vol. 30, pp. 1244–1251, Oct. 1983.

[III.13] C. Mallikarjun and K. N. Bhat, “Analytical expressions for subthresh-old charges and currents in thin-film SOI MOSFET’s,” IEE ElectronicsLetters, vol. 27, pp. 431–433, Feb. 1991.

[III.14] T. L. Tewksbury and H.-S. Lee, “Characterization, modelling and min-imization of transient threshold voltage shifts in MOSFET’s,” IEEEJ. of Solid-State Circuits, vol. 29, pp. 239–252, Mar. 1994.

[III.15] S. Veeraraghavan and J. G. Fossum, “A physical short-channel modelfor the thin-film SOI MOSFET applicable to device and circuit CAD,”IEEE Trans. on Electron Devices, vol. 35, pp. 1866–1875, Nov. 1988.

[III.16] C. G. Sodini, P.-K. Ko, and J. L. Moll, “The effect of high fieldson MOS device and circuit performance,” IEEE Trans. on ElectronDevices, vol. 31, pp. 1386–1392, Oct. 1984.

III-60

REFERENCES

[III.17] M. El-Banna and M. A. El-Nokali, “A simple analytical model forhot-carrier MOSFET’s,” IEEE Trans. on Electron Devices, vol. 36,pp. 979–986, May 1989.

[III.18] H.-C. Chow, W.-S. Feng, and J. B. Kuo, “An improved analyticalshort-channel MOSFET model valid in all regions of operation foranalog/digital circuit simulation,” IEEE Trans. on Computer AidedDesign, vol. 11, pp. 1522–1528, Dec. 1992.

[III.19] C. C. McAndrew, B. K. Bhattacharya, and O. Wing, “A single-pieceC∞-continuous MOSFET model including subthreshold conduction,”IEEE Trans. on Electron Devices, vol. 12, pp. 565–567, Oct. 1991.

[III.20] B. Inıguez, Analytical MOSFET Modelling with an Infinite Order ofContinuity. PhD thesis, Universitat de les Iles Balears, June 1996.

[III.21] J. G. Fossum, H. Jeong, and V. S., “Significance of the channel-chargepartition in the transient MOSFET model,” IEEE Trans. on ElectronDevices, vol. 33, pp. 1621–1623, Oct. 1986.

[III.22] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOStransistor capacitances,” IEEE J. of Solid-State Circuits, vol. 13,pp. 703–707, Oct. 1978.

[III.23] M. Bagheri and Y. P. Tsividis, “A small-signal DC-to-high-frequencynonquasistatic model for the four-termminal MOSFET valid in allregions of operation,” IEEE Trans. on Electron Devices, vol. 32,pp. 2383–2391, Nov. 1985.

[III.24] J.-P. Raskin, Modeling, Characterization and Optimization of MOS-FET’s and Passive Elements for the Synthesis of SOI MMIC’s. PhDthesis, Universite catholique de Louvain, Dec. 1997.

[III.25] J. Chen, Development of Metallization Processes on Thin-Film SOIfor Low-Voltage, Low-Power Microwave and High-Temperature Appli-cations. PhD thesis, Universite catholique de Louvain, Dec. 1997.

[III.26] C. H. Wang, “Identification and measurement of scaling-dependentparasitic capacitances of small-geometry MOSFET’s,” IEEE Trans.on Electron Devices, vol. 43, pp. 965–972, June 1996.

[III.27] R. Shrivastava and K. Fitzpatrick, “A simple model for the overlapcapacitance of a VLSI MOS device,” IEEE Trans. on Electron Devices,vol. 29, pp. 1870–1875, Dec. 1983.

[III.28] C.-L. Huang, J. V. Faricelli, D. A. Antoniadis, N. A. Khalil, and R. A.Rios, “An accurate gate length extraction method for sub-quarter mi-cron MOSFET’s,” IEEE Trans. on Electron Devices, vol. 43, pp. 958–963, June 1996.

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Modelling fully depleted SOI MOSFET’s

[III.29] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substratecrosstalk reduction using SOI technology,” IEEE Trans. on ElectronDevices, vol. 44, pp. 2252–2261, Dec. 1997.

[III.30] C. Raynaux, “Technological parameters of FD MOSFET’s fabricatedat LETI for the “SPACE” ESPRIT project.” Private Communication.

III-62

Chapter IV

Extraction ofSOI MOSFET

model parameters

IV.1 Introduction

The models developed in chapter III require in total about 60 parameters. Torender these models operational — that is : capable of accurate predictions —,it is necessary to determine the proper value of each parameter. The majorityof the model parameters is related to technological or physical characteristics,and can hence be readily estimated on the basis of available technological orphysical data. This data is however not always complete or can be subject tosignificant fluctuations, so that there is still a need for extraction techniquesworking on the measured characteristics of individual devices. Furthermore,a few model parameters are purely empirical, and can only be determined bycomparing model responses with measurements.

The purpose of this chapter is to provide evidence of the validity of themodels proposed in chapter III by confronting the predicted responses withmeasurements. The main objective of the present work being the developmentof bias-dependent high-frequency models for the SOI MOSFET, this chapterwill focus on the exploitation of high-frequency scattering parameters measure-ments. The core of the extraction procedure developed in the following pagesis the reliable identification of equivalent circuit parameters in agreement withthe physical interpretations given in chapter III. The most striking achieve-ment is probably the direct extraction of a mobility versus normal field curvefrom broadband high-frequency measurements, which corresponds very well to

IV-1

Extraction of SOI MOSFET model parameters

data published in the literature — see section IV.5.3.In comparison with the wealth of parameters traditionally used in SPICE

models, the number of parameters required for the unified analytical currentand charge model of chapter III seems quite reasonable. It is however suffi-ciently high to prohibit the extraction of parameters values in a single globaloptimisation. The extraction strategy developed below is rather a step-by-stepprocedure where the complexity of the model builds progressively up. At firsta simplified three-terminal model of the MOSFET is used. Starting with thedetermination of adjacent and extrinsic parasitic circuit elements, the extrac-tion proceeds inward with the identification of the series parasitics. Then thecomplete four-terminal model is introduced and the substrate coupling param-eters are identified. It will be shown that the approximations involved in thethree-terminal model do not affect the extracted values for the series parasiticelements, which thus may confidently be used in the four-terminal model. Fi-nally the internal parameters of the analytical current and charge model areidentified : inversion-charge parameters, transport model and saturation modelparameters.

In order to extract each parameter with a minimal uncertainty, care mustbe taken to select the biasing conditions at which the S-parameters are themost sensitive to the parameter in question. The optimal conditions for theextraction of the shunt parasitic circuit elements will be shown to be the reversebias, where the inversion channel is suppressed. For the series parasitic circuitelements, the optimal condition is saturation. For the extraction of internalparameters of the analytical current and charge model optimal bias ranges willalso be identified.

The detailed organisation of the present chapter is the following :

• At first, substrate resistivity is identified on the basis of transmissionline measurements in section IV.2. Substrate resistivity is indeed neededto estimate the conductances associated with parasitic substrate capaci-tances.

• Section IV.3 deals with the three-terminal small-signal equivalent circuitof the SOI MOSFET. Reliable optimiser-driven extraction of all equiva-lent circuit parameters is demonstrated, and an original direct extractionscheme is introduced allowing to determine all series extrinsic elementsin the presence of non-quasi-static effects.

• In section IV.4, the simplified three-terminal model is expanded intoa four-terminal small-signal equivalent circuit, accounting for substratecoupling effects. Optimisation is used to extract parameters values forthe 4-terminal circuit. Results are compared with those of the previoussection.

• Section IV.5 focuses on the extraction of the inversion charge and car-rier transport parameters for the intrinsic MOSFET model. Using thedistributed channel model, broadband two-port scattering parametersmeasurements are reduced to one equivalent DC capacitance and oneequivalent DC conductance. To illustrate the validity of the approach, a

IV-2

IV.2 Substrate resistivity

mobility versus normal electric field curve is reconstructed from measureddata .

• The whole extraction procedure is finalised in section IV.6, by the iden-tification of saturation parameters for the intrinsic current and chargemodel of the SOI MOSFET.

IV.2 Substrate resistivity

On silicon substrates the resistivity is essentially controlled by adjusting thedoping level. On a p-type substrate, a low resistivity of 20 Ω cm is achieved witha doping level on the order of 7.0 1014 cm−3, while a resistivity higher than 10kΩ cm implies an impurity concentration below 1012 cm−3. Such low impuritylevels are easily perturbed by a small contamination so that it is difficult to en-sure a precise or even uniform resistivity. The significant influence of substrateresistivity on the parasitic device capacitance in the case of high-resistivitySOI wafers urged the need to develop adequate characterisation techniques. Inparticular, the dopant concentration may also vary vertically within the wafersubstrate, so that an adequate characterisation technique should operate fromthe top of the wafer — not the back-side — in a configuration which is similarto the coplanar configuration of the basic MOSFET cell.

The scattering parameter calibration procedure described earlier yields asby-products the transmission line characteristics of a coplanar waveguide fabri-cated in the immediate vicinity of the transistors on the SOI wafer. The signifi-cant influence of the substrate resistivity on the transmission line characteristicssuggests several means of extracting substrate resistivity values : Either usingan electro-magnetic field simulator, or an adequate transmission line model,the resistivity of the substrate is adjusted until a satisfactory approximationis obtained for the evolution of the propagation constant γ and the character-istic impedance Zc in the measurement band. Another, more straightforwardapproach, is to deduce the resistivity from the time-constants governing thefrequency evolution of the distributed admittance for the waveguide. Identifi-cation of these time-constants relies on the extraction of an equivalent circuitfor Y ′πCPW as described in appendix A. It is shown in section A.3.1 that thesubstrate resistivity is related to the circuit parameters by :

ρsubs =C′subs

G′subs εSi(IV.1)

The estimation of the substrate resistivity using equation IV.1 has been foundto agree well with the values obtained by fitting the predictions from the modelof Huynen, [IV.1], to the measured characteristics.

IV.3 Three-terminal MOSFET model

GaAs MESFET’s or HEMT’s are usually presented as three-terminal devices.They are indeed fabricated on a semi-insulating substrate which is at least

IV-3

Extraction of SOI MOSFET model parameters

three orders of magnitude thicker than the depletion zone controlled by thegate, so that the influence of a potential applied to the wafer back-plane is trulynegligible. In the case of the SOI MOSFET, a low-frequency excitation appliedto the back of the wafer is transmitted integrally by the conductive siliconsubstrate to the bottom interface of the buried oxide — the back gate. TheSOI MOSFET then behaves as a four-terminal device, with a non-negligiblecontrol of the back gate on the small-signal performances as can be inferredfrom the device equations :

CGbSi

CGfSi=CGbDi

CGfDi=Gmbi

Gmfi= κf − 1 u

tof

tob(IV.2)

The ratio tof /tob is typically 0.075 for the UCL technology, and can go downto 0.011 in advanced processes — as for LETI.

Drain

Front Gate

Source

CGfDe

CGfSe

RGfe

RDe

RSe

YGfa

YDa

YGfDa CGfDi

CGfSi RGfSi

RGfDi

CDSe

GDi

LDi

ZDa

ZGfaGmfi e−ωτmfi

1+ ω τmfi

Figure IV.1: The 3-terminal SOI MOSFET model.

At microwave frequencies, above the dielectric relaxation frequencies, thesilicon substrate behaves rather as lossy dielectric material, so that the backgate potential is no longer controlled by the wafer back-plane but rather capac-itively by the source and drain diffusions. The SOI MOSFET then behaves asa three terminal device, and the common source small signal equivalent circuitconstructed from figures III.11, III.18 and III.20 can be simplified accordingly.All intrinsic circuit elements related to the back-gate are ignored, and the sub-strate coupling model is reduced to a single admittance connected betweenthe source and drain terminals. The resulting circuit topology is shown infigure IV.1. These simplifications modify of course the physical interpretation

IV-4

IV.3 Three-terminal MOSFET model

of some of the remaining equivalent circuit elements, but in a marginal pro-portion. For example, in depletion at VDS = 0, the suppression of CGfGbi isabsorbed by an increase of CGfSe . In strong inversion at VDS = 0, CGfGbi u 0so that its suppression from the equivalent circuit has no influence at all. Insaturation, CGbDi is known to be very small so that its suppression has no ef-fect. The transconductance Gmbi is however maximal, and its removal from theequivalent circuit will be compensated by an increase in GDi . Other elementssuch as Gmfi , CGfSi and CGfDi are almost not influenced by the simplifications.It will be shown in the next sections that the simplified circuit still allows toperform accurate extraction of technological parameters such as the channellength and the series resistances.

The equivalent circuit shown in figure IV.1 relies on the implicit assumptionthat the gate-line propagation effects are properly accounted for by the lumpedmodel. This imposes a limit on the active zone width W depending on the gateresistivity and capacitance. Below this limit, simple scaling rules apply whichcan be used to distinguish between the contributions of the various circuitelements. The equivalent circuit topology of figure IV.1 can be translated intothe following matricial equation :

[Yµ − Yα

]−1= Zσ + Y−1

π , Zσπ (IV.3)

where Yµ is the admittance matrix obtained directly from the measured S-parameters. Yα is the admittance matrix comprising the shunt adjacent el-ements. It does not depend on the active zone width W , and its expressionis :

Yα ,[

YGfa + YGfDa −YGfDa

−YGfDa YDa + YGfDa

](IV.4)

As indicated in section III.6.4, YGfa and YDa model mainly the shunt admit-tance of the metal taper sections at the input and output of the MOSFETstructure. The corresponding equivalent circuit topology is inspired from thedevelopments of appendix A. It is shown in figure IV.2.

GX3a CX3a

CX2a

CX1a

Figure IV.2: Equivalent circuit for the adjacent admittances YGfa and YDa .

The matrix Zσ groups the contributions of all series elements. The scaling

IV-5

Extraction of SOI MOSFET model parameters

rules detailed below have been introduced in section III.6 :

Zσ ,[

ZGfa +RSe +RGfe RSe

RSe ZDa +RSe +RDe

]=

[ZGfa +RGf0e 0

0 ZDa

]+W

[R′Gfe 0

0 0

]+

1

W

[R′Se R′Se

R′Se R′Se +R′De

](IV.5)

The impedances ZGfa and ZDa account for the series inductance and re-sistance of the input and output taper sections. It is shown in appendix Athat these parameters may vary significantly with frequency, particularly inthe case of a low resistivity substrate at frequencies around 1.0 GHz. In thiscase the equivalent circuit of figure IV.3 is recommended. On a high-resistivitysubstrate, this circuit may be simplified to a series inductance and resistancein the band between the dielectric relaxation frequencies and the onset of theskin effect. The absence of a series inductance in the source is a result of thespecific design of the MOSFET structure, as explained in section III.6.3.

LX1a

LX2a

LX3a

RX1a

RX2a

RX3a

Figure IV.3: Equivalent circuit for the adjacent impedances ZGfa and ZDa .

The matrix Yπ combines the shunt intrinsic and extrinsic elements, whichare all directly proportional to the active zone width, so that may write :

Yπ = W ·Y′π (IV.6a)

The general expressions for the elements of Y′π are :

Y ′π(1 , 1 ) = ω(C′GfSe + C′GfDe

)+

ω C′GfSi

1 + ω τGfSi+

ω C′GfDi

1 + ω τGfDi(IV.6b)

Y ′π(1 , 2 ) = − ω C′GfDe − ω CGfDi

1 + ω τGfDi(IV.6c)

Y ′π(2 , 1 ) = − ω C′GfDe +G′mfi exp(− ω τmfi)

1 + ω τmfi−

ω C′GfDi

1 + ω τGfDi(IV.6d)

Y ′π(2 , 2 ) = ω C′GfDe +G′Di

1 + ω τmfi+

ω C′GfDi

1 + ω τGfDi(IV.6e)

(IV.6f)

These are non-quasi-static expressions which constitute a valid model for allbiasing conditions. Simplified circuit topologies may be considered for specificbias ranges. In depletion, when VDS = 0 and VGf VThf , all intrinsic elements— index “i” — vanish. The resulting Y′π is purely capacitive and depends solely

IV-6

IV.3 Three-terminal MOSFET model

on the shunt extrinsic elements — index “e”. In saturation, when VGf VThf and VDS > (VGf − VThf ), the gate to drain capacitance C′GfDi becomesnegligible. Using equations (III.140) all time-constants can be related to asingle parameter :

τmfi =2

15τ0 (IV.7)

τGfSi =2

15τ0 (IV.8)

τGfDi =1

10τ0 (IV.9)

IV.3.1 Shunt parasitic elements

The denomination shunt parasitics groups all adjacent, index “a”, and extrin-sic, index“e”, elements which are connected in parallel with the intrinsic circuit.As indicated in the previous section, the intrinsic elements tend to vanish whenthe device is reverse-biased. This biasing condition is thus the most favourablefor the extraction of the shunt parasitics which are the sole parameters influenc-ing the device response. Accordingly, the determination of the shunt parasiticswill be based on S-parameters measurements of reverse-biased MOSFET’s.

The general purpose equivalent circuit topology of figure IV.1 is adaptedto the particular biasing condition by removing all intrinsic elements, so thatmatrix Yπ becomes purely capacitive and depends solely on the extrinsic capac-itances. The simplified equivalent circuit however still contains some redundantelements which can not be distinguished from each other on the sole basis ofthe frequency evolution of the device response. The adjacent shunt elementsexhibit an influence on the scattering parameters which is very closely similarto the influence of the extrinsic capacitances. Relying on the scaling rules itshould however be possible to make the distinction : The extrinsic shunt ele-ments have been shown to scale proportionally to the active zone width, W ,while the adjacent circuit elements where defined to be indepedent of W .

Raskin showed in his thesis [IV.2] that the parasitic adjacent and extrinsiccapacitances can be identified by performing a linear regression on the measuredsusceptance matrix of depleted devices of varying size. His demonstration doeshowever not give any insight in the possibility to apply a similar procedureto the measured conductance matrix in order to obtain the real part of theadjacent admittances. Using some simple equations and matrix algebra, it ispossible to show that a linear regression scheme will only work properly forthe capacitances, and that for the conductances a cubic regression would benecessary. Equation (IV.10) illustrates the dependencies on W .

Yµ(W ) = Yα + Yσπ(W ) (IV.10)

where Yσπ , Z−1σπ . The identification of Yα rests on the following approxima-

tion :

limW→0

Yσπ(W ) u 0 (IV.11)

IV-7

Extraction of SOI MOSFET model parameters

The above expression is approximate because it neglects the influence of a directcapacitive coupling between the metal tapers at the input and the output of theMOSFET structure. This coupling is truly negligible provided the active zonewidth is sufficient. It will however increase when W is reduced and eventuallybecome a dominant effect when W = 0. The approximation of equation (IV.11)nevertheless produces meaningfull results in the case of a regression based onsufficiently wide devices.

The admittance matrix Yσπ associated to the active zone can be expandedas follows :

Yσπ =[Zσ + Y−1

π

]−1

= Yπ

[I + Re(Zσ Yπ)︸ ︷︷ ︸

,A

+ Im(Zσ Yπ)︸ ︷︷ ︸,B

]−1 (IV.12)

Zσ and Yπ were defined above. Yπ is known to be directly proportional toW while the dependency of Zσ is slightly more involved as can be seen inequation (IV.5). Using simple matricial algebra, the real and imaginary part ofthe inverse matrix can be computed. Expression (IV.13) implicitly accounts forthe fact that the matrices A and B are both symmetric, being themselves theproduct of symmetric matrices. This expression shows that in all generality, theYσπ(i, j) are rational functions ofW . Both their numerator and the denominatorare polynomials of order higher than six.

Yσπ = Yπ

[A− B

] [A A + B B

]−1(IV.13)

Important simplifications are nevertheless possible. Matrix A can be expandedas(I− ω2 Lσ Cπ

)and matrix B as (ω Rσ Cπ). In the case of the MOSFET’s

considered here, the biggest LC product inside A is on the order of 10−24,while for B the highest RC product is about 10−12. Neglecting the contri-butions of the

(ω2LC

)- and (ωRC)-terms with respect 1.0 allows to simplify

equation (IV.13) to :

Yσπ u Yπ

[I− B

](IV.14)

This expression clearly shows that the imaginary part of Yσπ is very closelyproportional to W while the real part behaves more like a cubic polynomial inW . Expression (IV.14) is accurate within 5.0 % up to 20.0 GHz.

Performing a brute force regression in W for the conductances would thusrequire at least four “samples” — MOSFET’s with different active zone widths.This solution is rather unattractive as it doubles the work load compared to theextraction of the susceptances. Further more, the extraction of the adjacentadmittances over some frequency band would require a total of 24 × Nfreqreal coefficients, while the equivalent circuit description uses 22 parameters,independently of the number of measured frequency points, Nfreq. For thesereasons, an optimiser-based extraction method was found more appealing.

In order to reduce the number of potential optimisation parameters, someconstraints will be imposed on the general circuit topology described in sec-tion IV.3; Particularly on the adjacent immitances, as it is known that they

IV-8

IV.3 Three-terminal MOSFET model

account mainly for the characteristics of the input and output metal taperswhich are very closely related to the characteristics of the coplanar waveguidedescribed in appendix A. The constraint on the adjacent immitances, YGfa

and YDa is introduced by expressing explicitly their dependence upon the dis-tributed immitances of the CPW, as in equation (IV.15). As the metal tapersdiffer from the standard CPW section, some degrees of freedom are added :additional shunt capacitances are added at the gate and drain terminal, CGf0a

and CD0a ; the substrate conductance G′subs and the buried oxide capacitanceC′box from the CPW model are allowed to depart from the values extractedfrom the CPW characteristics.

YXa = ω CX0a + dXa × Y ′πCPW (IV.15)

ZXa = dXa × Z ′σCPW (IV.16)

The parameters dGfa and dDa must be considered as effective lengths whichmodel the specific geometrical dependency of the taper characteristics. Theyare used as optimisation parameters and their initial value is set equal to thephysical length of the tapers measured along their axis. The adjacent admit-tance YGfDa corresponds to a marginal effect — the stray capacitance betweenthe gate and drain lines outside of the active zone — so that a simple modelwill suffice :

YGfDa = ω CGfDa (IV.17)

The extraction is performed by fitting S(i, j), the equivalent circuit response,to the measurements, S(i, j), for the active zone widths inW ≡ Wmin, . . . , Wmaxand for the set of pulsations Ω ≡ ωmin , . . . , ωmax. The error is computed ina quadratic fashion ensuring a convergence in the mean.

minPE(P) (IV.18a)

E ,∑

Wk ∈Wωl ∈Ω

i, j ∈1, 2

∣∣S(i, j)(P, Wk, ωl)− S(i, j)(Wk, ωl )∣∣2 (IV.18b)

The parameter space for the optimisation is :

P ≡

p ,[C′GfSe , C

′GfDe , C

′DSe , dGfa , dDa , CGf0a , CD0a , CGfDa ,

G′subs , C′box , RGf0e , R

′Gfe , R

′De , R

′Se

]∈ R14|

0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.18c)

This extraction scheme was applied to a set of three n-channel MOSFET’swith the following active zone widths : 6.0 µm, 12.0 µm and 24 µm. All threeMOSFET’s had a nominal gate width of 1.0 µm, and consisted of 10 basiccells connected in parallel. These transistors were located close together on thesame wafer. Twenty frequency points were used, with a higher “density” below

IV-9

Extraction of SOI MOSFET model parameters

5.0 GHz. Figure IV.4 compares the measured scattering parameters with thecurves computed using the extracted parameters.

Table IV.1 summarises the optimisation results, mentionning initial andfinal values for the optimisation parameters. The values of the fixed parametersare mentioned in the second part of the table. The residual error was R =8.5 10−3. In conjunction with the sensitivities listed in table IV.1 it allows toidentify the parameters which have been reliably extracted. All parameterswhich have a sensitivity above 10−1 suffer an uncertainty smaller than 10.0 %on their final value. This means that in particular, all extracted adjacentand extrinsic parameters are known with a reasonable accuracy. The otherparameters will need to be extracted differently.

Parameter Final Value Initial Value Units SensitivityCGfDa 8.248 1.0 fF 2.0 10+2

CD0a 0.000 1.0 fF 1.0 10+2

CGf0a 25.672 5.0 fF 9.0 10+1

C′GfDe 2.5289 2.600 nF/m 2.0

C′GfSe 2.5723 2.600 nF/m 1.0

dGfa 64.26 60.0 µm 2.0 10−1

dDa 63.54 60.0 µm 2.0 10−1

C′DSe 0.7834 0.200 nF/m 1.5 10−1

G′subs 5.5335 1.058 f/m 8.0 10−2

R′Gfe 0.5665 0.4 MΩ/m 6.0 10−2

C′box 2.4733 0.7662 nF/m 5.0 10−3

R′De 0.1208 0.15 mΩ×m 4.0 10−3

R′Se 0.0504 0.15 mΩ×m 1.6 10−3

RGf0e 0.0005 2.0 Ω 1.5 10−4

C′air 0.0241 nF/m 10C′subs 0.1625 nF/m 10L′met1 390.15 nH/m 3.0 10−1

L′met2 40.888 nH/m 2.0 10−3

R′met1 12.056 kΩ/m 6.0 10−4

R′met2 1.935 kΩ/m 5.0 10−4

L′met3 487.59 nH/m 4.0 10−5

R′met3 3.080 kΩ/m 1.0 10−5

Table IV.1: Detailed results of the extraction in depletion at VGf = −1.0 Vand VDS = 0.0 V, using the 3-terminal model.

IV-10

IV.3 Three-terminal MOSFET model

Re(S11 )

0 2 4 6 8 10 12 14 16 18 20[GHz

]

6.0

12.0

24.0

W[µm]

−0.75

−0.25

−1.0

−0.5

0

0.25

0.5

0.75

1.0

Re(S22 )

0 2 4 6 8 10 12 14 16 18 20[GHz

]

6.012.0

24.0

W[µm]

−1.0

−0.25

0

0.25

0.5

0.75

1.0

−0.5

−0.75

Im(S22 )

0 2 4 6 8 10 12 14 16 18 20[GHz

]

6.012.024.0

W[µm]

−1.0

−0.25

−0.5

−0.75

0

0.25

0.5

0.75

1.0

Im(S21 )

0 2 4 6 8 10 12 14 16 18 20[GHz

]

6.012.0

24.0

W[µm]

−1.0

−0.25

0

0.25

0.5

0.75

1.0

−0.5

−0.75

Im(S11 )

0 2 4 6 8 10 12 14 16 18 20[GHz

]6.0

12.024.0

W[µm]

−1.0

−0.25

0

0.25

0.5

0.75

1.0

−0.5

−0.75

Re(S21 )

0 2 4 6 8 10 12 14 16 18 20[GHz

]

6.012.0

24.0

W[µm]

−1.0

−0.25

0

0.25

0.5

0.75

1.0

−0.5

−0.75

Figure IV.4: Comparison of the measured (dotted lines with rings) and thepredicted (straight lines with crosses) S-parameters after extraction of the 3-terminal circuit model at V Gf = −1.0V. The devices are 10 × (W/1.0µm)nMOSFET’s.

IV-11

Extraction of SOI MOSFET model parameters

IV.3.2 Channel length

L

∆Lovlp[S ] ∆Lovlp[D]

Lpoly

Figure IV.5: Cross-section of the SOI MOSFET showing the channel- andoverlap-lengths.

In conventional CMOS technology the channel length is determined bythe width of polysilicon gate strip and the amount of lateral diffusion of thesource and drain dopants below the gate oxide. In short channel MOSFET’sthe amount of lateral diffusion is critical, and special care is taken to reduceit, [IV.3]. The channel length has indeed a major influence on the deviceperformance, and accurate determination of its value is required. Several chan-nel length extraction techniques have been published. The first techniqueto appear in the literature was based on the channel-length dependency ofIDS , [IV.4, IV.5, IV.6]. Garcia Sanchez, [IV.7], and Guo, [IV.8] pointed outthat these IDS -based methods are inadequate for the extraction of the chan-nel length in sub-micron devices, as they use simplified current models whichdo not account for the normal field dependency and the velocity saturationof the inversion channel mobility. Fikry, [IV.9], tried to address these prob-lems. But the fundamental limitation of the IDS -based methods still remains,namely, they are not able to determine the absolute value of the channel lengthL directly.

L = Lpoly −∆Lovlp[S ] −∆Lovlp[D] = Lpoly −∆Lovlp (IV.19)

The IDS -based methods determine the total overlap length ∆Lovlp of the diffu-sions with respect to the polysilicon strip width Lpoly which is assumed to be

IV-12

IV.3 Three-terminal MOSFET model

equal to the corresponding layout dimension. However the lithography of thegate polysilicon is a critical process step in the case of short-channel devices, asthe gate width is quite close to the smallest manufacturable line-width, so thatdiscrepancies may be expected between Lpoly and its nominal value. Thesediscrepancies will finally result in errors on the extracted channel length.

The method advocated by Garcia Sanchez, [IV.7], and Guo, [IV.8] is basedon the measurement of the intrinsic gate capacitance and allows a direct ex-traction of the channel-length of bulk MOSFET’s. It is applied here to theSOI MOSFET. It has been shown in section III.35 that in strong inversion,when VGf > VThf , the inversion charge density Q′′nf can be approximated by−C′′of (VGf − VThf ). This allows to write simple expressions for the capaci-tors contributing to the intrinsic capacitance of the front gate in inversion atVDS = 0 :

CGfSi ≡ CGfDi u Ncell W LC′′of

2 κf(IV.20)

CGfGbi u 0 (IV.21)

These expressions show that the channel length can be deduced from themeasured intrinsic gate capacitance if the oxide capacitance per unit-widthis known.

L = κfCGfSi + CGfDi

Ncell W C′′of

for VGf VThf and VDS = 0 (IV.22)

In order to obtain the intrinsic gate capacitance, accurate identificationof the extrinsic gate capacitances is of primary importance. The bias pointat which the extrinsic capacitances are extracted must be carefully selected.For bulk MOSFET’s there is a consensus in the literature considering thatthe extraction of the extrinsic gate capacitances — defined as the sum of ctop ,clatrl and covlp , see section III.6.2 — should be performed in accumulation foran enhancement-mode device. The accumulation layer imposes a nearly fixedsurface potential underneath the gate oxide, so that the fringing capacitancescinner are “frozen” in a similar way as in inversion. Furthermore, the accumula-tion layer is isolated from the source and drain diffusions by the reverse-biasedjunctions, so that its capacitance to the gate charges exclusively through thebulk. The gate-source and gate-drain capacitances are then exactly equal tothe extrinsic gate capacitances.

For SOI MOSFET’s at high frequencies, the picture is somewhat different.By applying a sufficiently strong reverse-bias on the gate, it is indeed possibleto create a quasi-neutral region and eventually an accumulation layer. Thecarriers in the accumulation layer can however only be supplied by the leakagecurrent of the reverse-biased drain and source junctions, so that applying amicrowave signal on the gate will cause the redistribution of a constant chargeinside the silicon film and induce capacitive currents in the source, drain andback-gate. Furthermore, the back-gate behaves at microwave frequencies ratheras a floating node controlled capacitively by the source and drain than as agrounded node. It is thus not possible to isolate the contribution of CGfGbi from

IV-13

Extraction of SOI MOSFET model parameters

those of the extrinsic gate capacitances, CGfSe and CGfDe , in the frameworkof the 3-terminal model. As CGfGbi is zero in strong inversion and non-zerobelow threshold, an error will be induced on the extracted channel length. Inorder to get the best possible estimate of the gate parasitics, the shunt extrinsicelements are extracted at the reverse-bias corresponding to the minimum totalgate capacitance, typically around −1.0 V. The relative worst case error isexpected in this case to be lower as C′′b−f /C

′′of where :

1

C′′b−f

, 1

C′′of

+1

C′′b+

1

C′′ob

(IV.23)

For the technology at the UCL, the upper bound for the error evaluates to 6.0%. Due to the presence of the substrate capacitances in series with CGfGbi =Ncell W LC′′b−f the actual error will be significantly smaller.

To obtain CGfSi and CGfDi in strong inversion, the circuit of figure IV.1is fitted to measurements of MOSFET devices biased at 3.0 V. In order tosimplify the extraction process, RGfSi , RGfDi and LDi are set to zero. From thestrict point of view of the frequency behaviour of the circuit, RGfSi and RGfDi

are redundant with respect to the extrinsic resistances. As the time-constantsmodel of Tsividis — see equations (III.143) — breaks down at VDS = 0, nosimple relationship is available to lift the indetermination. As a result, theextracted values for RGfe , RSe and RDe will be affected by the NQS effects.This is not important, as only CGfSi and CGfDi are of interest here.

A typical extraction is presented below. The extraction was performed si-multaneously on three devices of varying W . This is not strictly necessary forthe extraction of CGfSi and CGfDi , but serves rather the purpose of validat-ing the scaling rules. The adjacent elements and shunt extrinsic parameterswere determined according to the procedure described in section IV.3.1. Initialvalues were computed from available technological data, assuming L = Lpoly .

minPE(P) (IV.24a)

E ,∑

Wk ∈Wωl ∈Ω

i, j ∈1, 2

∣∣S(i, j)(P, Wk, ωl)− S(i, j)(Wk, ωl )∣∣2 (IV.24b)

The parameter space for the optimisation is :

P ≡

p ,[C′GfSi , C

′GfDi , G

′Di , RGf0e , R

′Gfe , R

′De , R

′Se

]∈ R7|

0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.24c)

Figure IV.6 shows the adequation between the modelled and measured re-sponses after extraction. The residual errorR was 6.03 10−3. Sensitivity valueslisted in table IV.2 show that C′GfSi and C′GfDi were reliably extracted. Theseresult correspond to a channel length L of 0.612µm for a nominal gate widthLpoly of 1.0µm.

IV-14

IV.3 Three-terminal MOSFET model

Re(S22 )

[GHz

]

W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.0

24.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Im(S22 )

[GHz

]

W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.012.024.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Re(S21 )

[GHz

]

W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.024.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Im(S21 )

[GHz

]

W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.012.024.00

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Re(S11 )

[GHz

]

W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.0

24.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Im(S11 )

[GHz

]

W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.012.0

24.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Figure IV.6: Comparison of the measured (dotted lines with rings) and thepredicted (straight lines with crosses) S-parameters after extraction of the 3-terminal circuit model in inversion. The devices are 10× (W/1.0µm) nMOS-FET’s.

IV-15

Extraction of SOI MOSFET model parameters

Parameter Final Value Initial Value Units SensitivityG′Di 1.7669 1.0 kf/m 8.0 10−1

C′GfSi 3.23647 4.5 nF/m 2.7 10−1

C′GfDi 3.2250 4.5 nF/m 2.7 10−1

R′Se 0.08810 0.0504 mΩ×m 2.0 10−2

R′Gfe 0.538716 0.5665 MΩ/m 2.0 10−2

R′De 0.0521 0.1208 mΩ×m 7.5 10−3

RGf0e 0.00053 0.0005 Ω 5.0 10−7

Table IV.2: Detailed results of the extraction in strong inversion at VGf = 3.0 Vand VDS = 0.0 V, using the 3-terminal model.

IV.3.3 Series parasitic elements

This designation groups the extrinsic and adjacent elements connected in se-ries with the intrinsic part of the equivalent circuit. It has been shown insection IV.3.1 that, in depletion, the extraction of the series extrinsic elementswas not reliable, because of the insufficient sensitivity of the device responseto these parameters. In inversion it is impossible to distinguish the influenceof the intrinsic NQS resistances RGfSi and RGfDi from that of the extrinsicresistances. This impossibility is well known in MESFET modelling, wherethe “cold-FET” extraction method, [IV.10] is only able to determine the sum(RSe +RDe) from S-parameters, and requires additional information to sepa-rate RSe from RDe .

In saturation, the MOSFET becomes non-reciprocal — active — so thatadditional equations are available with respect to the case where VDS = 0.This specific feature will be exploited in the following subsections to performthe extraction of pure series resistances.

Optimiser-based extraction

The model used for the extraction of the series resistances is the non-quasi-static equivalent circuit depicted in figure IV.1. The shunt adjacent and ex-trinsic elements have been determined in section IV.3.1. The series adjacentelements predicted on the basis of the distributed CPW impedance Z ′σCPW andthe taper length extracted in section IV.3.1 will be used here in order to verifythe validity of the assertions concerning the device inductances : that the seriesgate and drain inductances are due essentially to the input tapers and that theseries source inductance is negligible.

In order to limit the number of optimisation variables, the expressions link-ing the NQS intrinsic elements RGfSi , RGfDi , LDi and τmfi to a single time-constant τ0, (IV.7) – (IV.9), are used explicitly, so that τ0 is the only NQSoptimisation parameter.

IV-16

IV.3 Three-terminal MOSFET model

minPE(P) (IV.25a)

E ,∑

Wk ∈Wωl ∈Ω

i, j ∈1, 2

∣∣S(i, j)(P, Wk, ωl)− S(i, j)(Wk, ωl )∣∣2 (IV.25b)

The parameter space for the optimisation is :

P ≡

p ,[C′GfSi , C

′GfDi , G

′mfi , G

′Di , τ0, RGf0e , R

′Gfe , R

′De , R

′Se

]∈ R9|

0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.25c)

Extractions at several bias points in saturation were performed in order toverify the bias-independancy of the extracted series resistances. All extractionswere operated on three devices simultaneously, allowing to check the validityof the scaling rules. Figure IV.7 shows the good match obtained betweenthe modelled and measured scattering parameters for the three MOSFET’s atVGfS = 2.0 V and VDS = 3.0 V. The residual error R was 2.5 10−2. A secondextraction was performed on the same devices at VGfS = 1.0 V and VDS = 2.0 V,with R = 2.6 10−2. Table IV.3 summarises the extraction results.

Parameter Final Value Initial Value Units SensitivityBias Pt 1 Bias Pt 2

G′mfi 0.6092 0.5060 0.671 kf/m 2.0

C′GfSi 4.8049 4.0295 4.0 nF/m 2.0 10−1

G′Di 71.08 51.974 60.0 f/m 6.0 10−2

τ0 13.49 15.72 6.0 ps 1.0 10−2

R′Gfe 0.5142 0.4942 0.5665 MΩ/m 3.5 10−2

R′Se 0.1151 0.1154 0.0881 mΩ×m 1.6 10−2

R′De 0.2929 0.3077 0.0521 mΩ×m 1.3 10−2

C′GfDi 0.2438 0.1550 0.4 nF/m 2.0 10−3

RGf0e 0.00053 0.00053 0.00053 Ω 4.0 10−7

Table IV.3: Detailed results of the extraction in saturation using the 3-terminalmodel. Bias point no. 1 is at VGfS = 2.0 V and VDS = 3.0 V. Bias point no. 2is at VGfS = 1.0 V and VDS = 2.0 V. Sensitivities were evaluated for bias pointno. 1.

Comparing the results of the two bias points, one may see that τ0 variesby more than 15.0 %, while the extrinsic resistances change less than 5.0 %.This allows to conclude that the gate, source and drain resistances have beenproperly identified.

IV-17

Extraction of SOI MOSFET model parameters

Parametric impedance curves method in the quasi-static approxima-tion

It has already been mentioned that the 3-terminal equivalent circuit can bedescribed by the following matricial equation :[

Yµ − Yα

]−1= Zσ + Y−1

π , Zσπ (IV.26)

where Yµ is the admittance matrix obtained directly from the measured scat-tering parameters; Yα is the admittance matrix describing the shunt adjacentpart of the circuit; Zσ is the impedance matrix including the series extrinsicand adjacent elements; Yπ is the admittance matrix accounting for the intrinsicand shunt extrinsic elements. Yα is assumed to be known, so that Zσπ can bedirectly evaluated on the basis of the measurements.

It will be shown in the subsequent developments that the specific shapeof equation IV.26 can be exploited to determine the series equivalent circuitparameters. Several restrictions must however be imposed on the 3-terminalmodel described in the introduction of IV.3 : The model of the adjacentimpedances ZGfa and ZDa must be reduced to the series inductances LGfa

and LDa . The quasi-static approximation is used for the intrinsic circuit, let-ting τ0 = 0 so that all NQS circuit parameters τmfi , RGfSi , RGfDi and LDi

vanish. It will be shown in subsection IV.3.3 how the restriction on the NQSparameters can be lifted.

Lee et al., [IV.11], have shown that in the quasi-static approximation, theelements of Zσπ have the following form :

Re(Zσπij ) = Re(Zσij ) +Aij

ω2 +Bfor i, j ∈

1, 2

(IV.27)

1

ωIm(Zσπij ) =

1

ωIm(Zσij )−

Eij

ω2 +B−

Fij

ω2(ω2 +B

)for i, j ∈

1, 2

(IV.28)

where B, the Aij , Eij and Fij are real and frequency independent coefficientsinvolving only the intrinsic and shunt extrinsic elements — see Raskin, [IV.2],or Raskin and Gillon, [IV.12]. F12 and F22 are always zero. All series resis-tances and inductances can thus be obtained from the asymptotic values takenby equations IV.27 and IV.28 at infinite frequency. In order to evaluate theseasymptotic values, the authors of [IV.11] use an optimiser to fit the expres-sions on the right-hand side of IV.27 and IV.28 individually to the evolutionsof measured data over the available frequency band. It is however possible totransform the determination of the asymptotic values into simple linear regres-sion problems.

In the case of the series resistors, this is done by considering the parametriccurves defined in a two dimensional plane by :[

x1(ω)x2(ω)

]=

[Re (Zσπij (ω))Re (Zσπkl(ω))

]where i, j 6= k, l (IV.29)

IV-18

IV.3 Three-terminal MOSFET model

[GHz

] [GHz

]

Im(S22 ) W[µm]

6.012.024.0

0 2 4 6 8 10 12 14 16 18 20

Re(S22 ) W[µm]

6.0

12.0

24.0

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

[GHz

] [GHz

]

Re(S11 ) W[µm]

6.0

12.0

24.0

0 2 4 6 8 10 12 14 16 18 20

Im(S11 ) W[µm]

6.012.0

24.0

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

[GHz

] [GHz

]

Re(S21 ) W[µm]

6.0

12.0

24.0

0 2 4 6 8 10 12 14 16 18 20

Im(S21 ) W[µm]

6.0

12.024.0

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Figure IV.7: Comparison of the measured (dotted lines with rings) and thepredicted (straight lines with crosses) S-parameters after extraction of the 3-terminal circuit model in saturation at VGf = 2.0 V and VDS = 3.0 V. Thedevices are 10× (W/1.0µm) nMOSFET’s.

IV-19

Extraction of SOI MOSFET model parameters

Im(Zσπ21 )/ω[pH]

Im(Zσπ22 )/ω[pH]

−1500 −1000 −500 0

Regression

Measurements

x20 = −9.0

dx2dx1

= 0.2

−0.2LDa = −9.0−300

−250

−200

−150

−100

−50

0Regression

Measurements

Re(Zσπ21 )[Ω]

Re(Zσπ11 )[Ω]

x20 = 17.7

dx2dx1

= 0.2

RGfe + (1− 0.2) RSe = 17.7

10

20

30

40

50

60

0 50 100 150 200

Figure IV.8: Parametric impedance curves for a 10 × (24.0µm/1.0µm) n-MOSFET at VGfS = 1.0 V and VDS = 2.0 V .

Using equation IV.27, it is straightforward to establish that these curves mustbe straight lines, and that their intercept at the origin [0, x20] and slope dx2

dx1is

given by :

x20 = Re(Zσkl )−Akl

AijRe(Zσij ) (IV.30)

dx2

dx1=Akl

Aij(IV.31)

Substituting the values of the intercept and the slope obtained from a linearregression on the measured data points into IV.30 and IV.31 yields a linearequation relating the series resistances. To determine all series resistances, it isnecessary to combine three linearly independent equations formed by varyingthe indices i, j, k, l. Such a set of equations can only be constructed whenZσπ21 and Zσπ12 are significantly different, which requires to bias the MOS-FET’s in saturation. The most reliable results are obtained from measurementsof saturated MOSFET’s and with the following pairs : [Re(Zσπ11 ),Re(Zσπ21 )],[Re(Zσπ12 ),Re(Zσπ21 )], [Re(Zσπ22 ),Re(Zσπ12 )]. Figure IV.8 illustrates thequality of the linear regressions performed on data measured from 500 MHz to40 GHz.

For the series inductances the situation is a little different, because of themore complicated frequency behaviour of the right hand side in IV.28, whenj = 1. As can be seen in figure IV.8, the pair [Im(Zσπ22 )/ω, Im(Zσπ12 )/ω]

IV-20

IV.3 Three-terminal MOSFET model

produces one useful equation based on the following relations :

x20 = −E12

A22LDa (IV.32)

dx2

dx1=E12

E22(IV.33)

A second equation can be obtained by considering the parametric curve definedin the tridimensional space by :x1(ω)

x2(ω)x3(ω)

=

Im (Zσπ21 (ω)) /ωIm (Zσπ12 (ω)) /ωIm (Zσπ11 (ω)) /ω

(IV.34)

Equation IV.28 imposes that this curve is contained in a plane, of which theintercept at the origin [0, 0, x30] and the slope coefficients dx3

dx1and dx3

dx2can be

determined from a linear regression on the measured data.

x30 = LGfa (IV.35)

dx3

dx1=F11

E21(IV.36)

dx3

dx2=E11

E12−E21 F11

E12 F21(IV.37)

The main advantage of the method based on the parametric curves withrespect to the optimisation of [IV.11], is that decreasing the device size doesnot compromise accuracy. Indeed, equations (IV.30), (IV.31), (IV.32), (IV.33),(IV.35), (IV.36), (IV.37), are not influenced by the device size, which cancels

out in the ratiosAijAkl

,EijEkl

,FijFkl

. The optimisation criteria used by Lee are, on thecontrary, based on equations IV.27 and IV.28 where the Aij , Eij and Fij termstend to mask the influence of the series elements in the case of small devices.Other important features of the present method are that it takes advantage ofthe asymmetry Zσπ to enhance accuracy, and also that the shared frequencydependence of the Zσπij is correctly and coherently accounted for during theextraction. This latter alleviates the need to discard data below a certainfrequency during the extraction of LGfa , [IV.11].

Extending the parametric method to the non-quasi-static case

The results of the direct extraction scheme shown in table IV.4 are affected bya bias dependent error due to the use of quasi-static analytical expressions as astarting-point for the developments. The striking correspondance between thelinear regression and the measured data points in figure IV.8 is paradoxal : aninappropriate — quasi-static — model leads to an adequate — experimentallyverified — formulation of the parametric impedance curves. The conclusionthat can be drawn from figure IV.8 is that the formalism of equations (IV.27)and (IV.28) is applicable to the non-quasi-static case. The effect of the NQS

IV-21

Extraction of SOI MOSFET model parameters

Parameter W Direct Optimisation Units6.0 2.88 Ω

RGfe 12.0 5.76 Ω24.0 10.31 11.52 Ω6.0 37.274 Ω

RSe 12.0 18.63 Ω24.0 9.36 9.317 Ω6.0 49.02 Ω

RDe 12.0 24.51 Ω24.0 12.26 Ω

Table IV.4: Comparing the results of the direct extraction scheme and theoptimisation, for n-MOSFET’s biased at VGf = 3.0 V and VDS = 0.0 V, usingthe 3-terminal model.

circuit parameters simply translates into a modification of the equation coeffi-cients :

Re(Zσπij ) = Re(Zσij ) + ∆Rσij +Aij + ∆Aijω2 +B + ∆B

for i, j ∈

1, 2 (IV.38)

1

ωIm(Zσπij ) =

1

ωIm(Zσij ) + ∆Lσij −

Eij + ∆Eijω2 +B + ∆B

−Fij + ∆Fij

ω2(ω2 +B + ∆B

)for i, j ∈

1, 2

(IV.39)

where ∆Rσij and ∆Lσij are the contribution of the NQS circuit parameters tothe asymptotic values of the Zσπij . If they are not properly accounted for — asin the QS extraction scheme of subsection IV.3.3 — these NQS contributionsinduce an error on the extracted series elements values.

The NQS contributions ∆Rσij and ∆Lσij could be easily evaluated if theadmittance matrix Yπ was known. Indeed, the NQS contributions could beobtained by considering the intercept and slope of the parametric curves derivedfrom Zπ , [Yπ]

−1in the same manner as explained in subsection IV.3.3 for

Zσπ . The problem is thus now to build correct estimates of Yπ on the basis ofthe results of the QS extraction scheme. In order to achieve this, simulationshave been performed to identify the intrinsic circuit parameters which could bereasonably well extracted by the QS scheme. Impedance data corresponding toZσπ was generated using the equivalent circuit of figure IV.1 for various devicesizes and bias points, [IV.12,IV.2]. The QS extraction scheme described belowwas then applied :

1. Extraction of the QS estimates of the extrinsic series elements using the

method of subsection IV.3.3. Construction of the QS estimate Zσ(0) ofZσ.

2. De-embedding of Zπ(0) from Zσπ using the QS estimate Zσ(0).

IV-22

IV.3 Three-terminal MOSFET model

Re(Zπ21 )[Ω]

Re(Zπ12 )[Ω]

ModelRegression

+

∆RGfe + (1− 0.132) ∆RSe = 2.85

0 50 100 150 200

0

10

20

30

x20 = 2.85

dx2dx1

= 0.132

Im(Zπ21 )/ω[pH]

Im(Zπ22 )/ω[pH]

ModelRegression

+

−300

−250

−200

−150

−100

−50

0

−1500 −1000 −500 0

−0.2 ∆LDa = −0.8

x20 = −0.8

dx2dx1

= 0.18

Figure IV.9: Parametric impedance curves in the non-quasi-static case.

3. Determination of the QS estimates of the intrinsic elements from[Zπ(0)

]−1

by inverting equation (IV.6) as shown by Berroth in [IV.13].

The simulations [IV.12,IV.2] showed that the QS estimates of CGfSi , Gmfi , GDi

and τmfi were accurate, well within 5.0% of the initial circuit parameter value.Only the estimate of RGfSi suffered a significant error, calling for a alternativesolution. One possibility is to use equations (IV.7) and (IV.8) to relate RGfSi

to τmfi and obtain a better estimate for the NQS resistance :

RGfSi (1) =τmfi (0)

CGfSi (0)

(IV.40)

Using the new estimate RGfSi (1), the updated matrix Zπ(1) is reconstructed,

and the NQS corrections ∆Rσij and ∆Lσij are evaluated by the parametriccurves method, illustrated in figure IV.9. This allows to correct the QS esti-mates of the series elements and to initiate a new extraction cycle which resultsin updated values for the intrinsic circuit elements. Figure IV.10 shows the ex-

tracted Gmfi (k+1)-curve in function of RGfSi (k). The correct RGfSi (k) results

is a constant Gmfi value over the whole measurement band, while under- oroverestimated values result in a down- or upward bending of the curve Gmfi .This feature can be used as a criterion to guide an iterative bisection processconverging to the correct RGfSi value :

1. Initiate the process with the QS extraction scheme.

2. Determine the updated estimate for RGfSi using equation (IV.40).

IV-23

Extraction of SOI MOSFET model parameters

3. Select an wide interval [RGfSi(1). . . RGfSi (1)] enclosing RGfSi (1).

4. Compute Zπ(k) using the latest RGfSi (k); Evaluate the NQS corrections

and apply them to obtain updated estimates of the series elements. Per-form a complete extraction cycle and determine the Gmfi -curve.

5. If the Gmfi -curve bends upward, then — bisection step — select a newinterval according to :

[RGfSi(k+1)

. . . RGfSi (k+1)] , [RGfSi (k) . . . RGfSi (k)] (IV.41)

If the Gmfi -curve bends downward, then select a new interval :

[RGfSi(k+1)

. . .RGfSi (K+1)] , [RGfSi(k). . . RGfSi (k)] (IV.42)

6. Select the new RGfSi estimate :

RGfSi (k+1) ,RGfSi

(k+1)+RGfSi (k+1)

2(IV.43)

7. Loop back to point 4 above and increment k. Repeat until the Gmfi -curveis sufficiently flat.

Gmfi[mf

]

[GHz

]

RGfSi

15

16

17

18

19

20

(Q.S.) 0.0

10.0

15.0

20.0

[Ω]

0 10 20 30 40

Figure IV.10: Extracted Gmfi curves for several RGfSi values.

This procedure has been found to yield consistent results with the optimiser-based parameter extraction method described in subsection IV.3.3. It is how-ever computationally much more efficient and better behaved in the sense that

IV-24

IV.4 Four-terminal MOSFET model

it avoids the pittfall of spurious solutions generated by local minima of theoptimisation criterion. The parametric impedance curves method is very wellsuited for implementation as a fully automatic routine — paving the way forthe systematic extraction of equivalent circuit parameters on a large numberof devices.

IV.4 Four-terminal MOSFET model

As mentioned in the introduction of section IV.3, the SOI MOSFET is inher-ently a four-terminal device. The simplified three-terminal model introducedin that section is only valid for high-frequency small-signal analyses. When itcomes to nonlinear broadband modelling, an elaborate model such as the onedevelopped in section III.6.4 is required. The purpose of the present sectionis to show how the extrinsic and adjacent parameters of the elaborate modelmay be extracted from small-signal measurements, and in particular, whichparameters were correctly extracted using the simplified model. The completesmall-signal equivalent circuit used in this section is presented in figure IV.11.It is dedicated for the common-source MOSFET which is the configuration inwhich nearly all measurements are done.

IV.4.1 Corrections to the shunt parasitic elements

As indicated in sections IV.3.1 and IV.3.2, the identification of the shunt para-sitic elements is performed in depletion at the gate voltage corresponding to aminimum of the global capacitance of the front gate, VDS being zero. In thesebiasing conditions, the equivalent circuit of figure IV.11 can be substantiallysimplified, as all intrinsic conductances and intrinsic capacitances vanish exceptCGfGbi , which is approximately equal to Ncell LW C′′b−f . The major modifi-cation with respect to the simplified model of section IV.3.1 is the addition ofan elaborate substrate coupling model. In agreement with the definition of theadjacent circuit elements, the extrinsic substrate coupling model accounts onlyfor scalable active-zone effects, so that by definition :

CGbDe = W C′GbDe RGbDe =R′GbDe

WCDe = W C′De (IV.44)

CGbSe = W C′GbSe RGbSe =R′GbSe

WCSe = W C′Se (IV.45)

CGbe = W C′Gbe RGbe =R′Gbe

W(IV.46)

This means in particular, that the adjacent circuit elements should remainunchanged with respect to the three-terminal model.

IV-25

Extra

ctio

nof

SO

IM

OS

FE

Tm

od

el

para

mete

rs

Drain

Gate

Source

CGfDe

CGfSe

RGfe

RDe

RSe

YGfa

YDa

YGfDa CGfDi

CGfSi RGfSi

RGfDi

CDSe

GDi

LDi

ZDa

ZGfa

Gmfi e−ωτmfi

1+ ω τmfi

CGbDi

CGbSiRGbSi

RGbDi

CGfGbi

Gmbi e−ωτmbi

1+ ω τmbi

CDe

CSe

CGbe

RGbe

CGbSe

CGbDe RGbDe

RGbSe

Figure IV.11: The 4-terminal SOI MOSFET model.

IV-2

6

IV.4 Four-terminal MOSFET model

Again, the extraction problem is formulated as an optimisation :

minPE(P) (IV.47a)

E ,∑

Wk ∈Wωl ∈Ω

i, j ∈1, 2

∣∣S(i, j)(P, Wk, ωl)− S(i, j)(Wk, ωl )∣∣2 (IV.47b)

where the parameter space for the optimisation is :

P ≡

p ,[C′GfSe , C

′GfDe , C

′DSe , C

′GbXe , R

′GbXe , dGfa , dDa

]∈ R7|

0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.47c)

The effective taper lengths dGfa and dDa are included in the set of optimisationparameters in order to verify whether their value is affected by the type of modelused during extraction. The other adjacent circuit parameters remain fixed atthe values found in section IV.3.1. The series extrinsic parameters are takenfrom table IV.3. Initial values for the substrate coupling model parameters canbe obtained from available technological data using the procedure described byRaskin in his thesis, [IV.2]. The number of potential optimisation parametersis further reduced by imposing the symmetry of the substrate coupling modelduring the optimisation :

C′GbSe ≡ C′GbXe ≡ C

′GbDe (IV.48)

R′GbSe ≡ R′GbXe ≡ R

′GbDe (IV.49)

where only R′GbXe and C′GbXe are considered as optimisation parameters.

This extraction procedure was applied to the same transistors as in sec-tion IV.3.1. The residual error was R = 3.4 10−3, about half of the valueobtained with the 3-terminal model. Figure IV.12 shows the good correspon-dence between the modelled and measured curves. Table IV.5 gives the Detailedresults.

It is noteworthy that dGfa remained virtually unchanged, while dDa wasmodified by about 5.0 %. The modification of dDa may be explained by theabsence of a resistor RDSe in parallel with CDSe in the extrinsic part of thesimplified model. This absence was compensated during the extraction of sec-tion IV.3.1 by an increase of dDa and a diminution of CD0a . It seems thus rea-sonable to conclude that the adjacent circuit elements can be properly extractedusing the simplified equivalent circuit — provided an extrinsic resistance RDSe

is used.

IV-27

Extraction of SOI MOSFET model parameters

[GHz

] [GHz

]

Im(S21 ) W

0 2 4 6 8 10 12 14 16 18 20

6.012.0

24.00

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Re(S21 ) W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.0

24.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

[GHz

] [GHz

]

Im(S11 ) W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.024.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Re(S11 ) W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.0

24.00

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

[GHz

] [GHz

]

Re(S22 ) W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.0

24.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Im(S22 ) W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.012.024.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Figure IV.12: Comparison of the measured (dotted lines with rings) and thepredicted (straight lines with crosses) S-parameters after extraction of the 4-terminal circuit model in depletion. The devices are 10 × (W/1.0µm) nMOS-FET’s.

IV-28

IV.4 Four-terminal MOSFET model

Parameter Final Value Initial Value Units SensitivityC′GfDe 2.3629 2.5289 nF/m 2.0 10−1

dGfa 64.48 64.26 µm 2.0 10−1

dDa 58.02 63.54 µm 2.0 10−1

C′GfSe 2.4323 2.5723 nF/m 8.5 10−2

C′DSe 0.7734 nF/m 1.5 10−2

C′GbXe 0.1516 nF/m 3.0 10−4

R′GbXe 82.64 mΩ ·m 3.5 10−4

C′Xe 0.8924 nF/m 4.5 10−4

C′GfGbi 0.45 nF/m 1.0

C′Gbe nF/m 1.0R′Gbe Ω×m 1.0

Table IV.5: Detailed results of the extraction in depletion at VGf = −1.0 Vand VDS = 0.0 V, using the 4-terminal model.

IV.4.2 Corrections to the series parasitic elements

The extraction of the series resistances and of the intrinsic circuit parametersfor the 4-terminal model can be accomplished in essentially the same way as forthe 3-terminal model. For saturated devices, the full complexity of the modelof figure IV.11 must be used; None of the circuit elements may be discarded.Considering that the number of intrinsic circuit elements has doubled withrespect to the 3-terminal model, one may realise that reduction of the numberof potential optimisation parameters has become even more important here. Inorder to render the extraction problem tractable, a call is made upon the deviceequations, which in the case of fully depleted SOI MOSFET’s allow to link theback- and front-gate circuit parameters as already shown in section IV.3 :

CGbSi

CGfSi=RGfSi

RGbSi= κf − 1 (IV.50)

CGbDi

CGfDi=RGfDi

RGbDi= κf − 1 (IV.51)

Gmbi

Gmfi= κf − 1 (IV.52)

This set of equations is very usefull, as it relates the weakly influent back-gate circuit parameters to their front-gate counterparts which have a dominantinfluence on the frequency response. Remembering the time-constant modelof Tsividis — equations (III.143) —, all NQSintrinsic circuit elements can berelated to a single time constant, τ0, (IV.7) – (IV.9). The extraction problem

IV-29

Extraction of SOI MOSFET model parameters

then takes the form :

minPE(P) (IV.53a)

E ,∑

Wk ∈Wωl ∈Ω

i, j ∈1, 2

∣∣S(i, j)(P, Wk, ωl)− S(i, j)(Wk, ωl )∣∣2 (IV.53b)

where the parameter space for the optimisation is :

P ≡

p ,[C′GfSi , C

′GfDi , G

′mfi , G

′Di , τ0, RGf0e , R

′Gfe , R

′De , R

′Se

]∈ R9|

0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.53c)

Values for the adjacent and extrinsic circuit elements are taken from sec-tion IV.4.1. The capacitance C′GfGbi kept constant at the value L/3C′′b−f .

This extraction procedure was applied to the same transistors as in sec-tion IV.3.1. The residual error R was 2.4 10−2, slightly better than previously.Table IV.6 allows to compare the extraction results with those obtained usingthe simplified model, listed in the initial values column. It is remarkable thatnone of the extrinsic series resistance changed significantly. Amongst the in-trinsic parameters, only G′Di changed notably. The value extracted for G′Di inthe framework of the 3-terminal model is indeed affected by the absence of atransconductance G′mbi in the circuit. These results confirm that the simpli-fied equivalent circuit allows to extract correct values for the extrinsic seriesresistances as well as the following intrinsic parameters : G′mfi , C′GfSi and τ0.

Parameter Final Value Initial Value Units SensitivityG′mfi 0.606 0.6092 kf/m 1.7

C′GfSi 4.9152 4.8049 nF/m 1.5 10−1

R′Se 0.1148 0.1151 mΩ×m 3.0 10−2

G′Di 54.212 71.084 f/m 2.0 10−2

R′Gfe 0.4946 0.5142 MΩ/m 2.0 10−2

τ0 14.305 13.49 ps 1.0 10−2

R′De 0.2934 0.2929 mΩ×m 8.5 10−3

C′GfDi 0.3163 0.14269 nF/m 3.0 10−3

RGf0e 0.00053 0.00053 Ω 3.0 10−7

Table IV.6: Detailed results of the extraction in saturation at VGf = 2.0 V andVDS = 3.0 V, using the 4-terminal model.

IV-30

IV.4 Four-terminal MOSFET model

[GHz

] [GHz

]

Im(S22 )

6.012.024.0

W[µm]

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

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6.0

12.0

24.0

W[µm]

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

[GHz

] [GHz

]

Re(S11 ) W[µm]

0 2 4 6 8 10 12 14 16 18 20

6.0

12.0

24.0

0

0.25

0.50

0.75

1.00

−1.00

−0.75

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6.012.0

24.0

W[µm]

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

[GHz

] [GHz

]

Re(S21 )

6.012.0

24.0

W[µm]

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Im(S21 )

6.0

12.024.0

W[µm]

0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.50

0.75

1.00

−1.00

−0.75

−0.50

−0.25

Figure IV.13: Comparison of the measured (dotted lines with rings) and thepredicted (straight lines with crosses) S-parameters after extraction of the 4-terminal circuit model in saturation at VGf = 2.0 V and VDS = 3.0 V. Thedevices are 10× (W/1.0µm) nMOSFET’s.

IV-31

Extraction of SOI MOSFET model parameters

IV.5 Intrinsic MOSFET in the linear operating

regime

The linear operating regime must be understood as the set of bias points atwhich the carriers in the channel do not attain their saturation velocity. Thiscorresponds roughly to the following condition : VGf − VThf > VDS . At lowdrain voltages, one may expect that velocity saturation will only have a limitedimpact on the device performance, so that an accurate knowledge of the pa-rameters modelling this effect is not required to obtain sensible predictions ofthe device responses. For moderately short channel lengths (L > 0.5µm), onemay even neglect the influence of velocity saturation on the small-signal char-acteristics at VDS = 0.0. This feature is particularly useful, as it considerablysimplifies the extraction of the transport and inversion-charge parameters.

IV.5.1 Determination of the C-V curve from broadbandmeasurements

It has been shown in section III.5.2 that, at VDS = 0, an analytical small-signalmodel can be obtained which rigorously accounts for the distributed channeleffects in the SOI MOSFET. The model is based on the expressions of theadmittance matrix YCf describing the distributed channel when both the frontand back gates are grounded :

YCf =1

zCf sinh(γCf L)

[cosh(γCf L) −1−1 cosh(γCf L)

](IV.54)

γCf ,1

L

√j ω RCf

(CGfC + CGbC

)(IV.55)

zCf ,√

RCf

j ω(CGfC + CGbC

) (IV.56)

where RCf = RDSi is the static resistance of the channel, while CGfC = CGfSi +CGfDi and CGbC = CGfSi + CGfDi are the static capacitances of the channelto the front and back gates. The merit of expression IV.54 is thus to linkthe high-frequency admittance matrix of the channel to three low-frequencychannel characteristics.

As already indicated, the back gate of the SOI MOSFET does not behaveas a grounded node at microwave frequencies, so that the more elaborate modelof equation III.154 is required in order to account for the substrate couplingeffects. The next subsection describes the extraction of the RCf -, CGfC - andCGbC -curves in the framework of the 4-terminal model using an optimiser. Thesubsection thereafter proposes a analytical method allowing to extract theRCf -and CGfC -curves directly from measurements.

IV-32

IV.5 Intrinsic MOSFET in the linear operating regime

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Re(S22 ) VGf[V]

3.02.01.0

0.50.2

−0.4−1.0

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Im(S22 ) VGf[V]

3.02.0

1.00.50.2−0.4−1.0

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Im(S11 ) VGf[V]

3.02.01.0

0.5

0.2

−0.4−1.0

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

3.02.01.00.50.2−0.4−1.0

Re(S11 ) VGf[V]

Figure IV.14: Comparing the measured (dotted lines with rings) and modelled(continuous lines with crosses) S-parameters after extraction of CGfC and GCf

on a 10×(24.0µm/2.0µm

)n-MOSFET.

Optimiser driven broadband curve-fitting

In order to extract the C-V curves from broadband S-parameters measurementsof the common-source MOSFET, the circuit of figure IV.11 is used. All extrinsicand adjacent elements must have been determined a priori — using the methodsdescribed earlier. The intrinsic part, grouping all elements with index “i” ishowever replaced by the admittance matrix YFET defined in equation IV.54.Explicit use is made of equation (IV.50) to avoid using CGbC as an optimisationvariable, as its influence on device response is expected to be marginal. Theextraction is then formulated as a set of optimisation problems, one for each

IV-33

Extraction of SOI MOSFET model parameters

bias-point :

minPk

E(Pk ) (IV.57a)

E ,∑ωl ∈Ω

i, j ∈1, 2

∣∣S(i, j)(Pk , ωl)− S(i, j)(VGf (k), ωl)∣∣2 (IV.57b)

where the parameter space for the optimisation is :

Pk ≡

p ,[CGfC (k), RCf (k)

]∈ R2 | 0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.57c)

VGf ,[VGf (1 ), . . . , VGf (n)

]is the vector of applied gate biases, while CGfC ,[

CGfC (1 ), . . . , CGfC (n)

]and RCf ,

[RCf (1 ), . . . , RCf (n)

]are the correspond-

ing vectors of extracted channel resistances and capacitances.

Figure IV.14 shows the good agreement between the model and the measure-ment, as obtained after a typical extraction process. It is remarkable that sucha good fit for the four scattering parameters is obtained over the whole measure-ment band by adjusting only two model parameters at every bias point ! Thisunderlines the validity of the distributed channel model. Figure IV.16 showsthe corresponding extraction results in the form of the total gate capacitanceCGf = CGfC + CGfSe + CGfDe .

Simplified analytical method

In the framework of the three terminal model, it is possible to extract CGfC

and RCfC directly from the measurements of the common-source MOSFETwithout any optimisation. Neglecting the back gate capacitances CGbC andCGfGb , the matrix YFET from equation IV.54 simplifies to YCf . Using the 3-terminal equivalent circuit of figure IV.1 together with its associated matricialequation (IV.3), it is possible to De-embed the admittance matrix Yπ fromthe measurements. The matrix Yπ accounts for both the shunt extrinsic andintrinsic elements of the common-source MOSFET. Stripping off the extrinsicshunt parasitics, one may write :

Yπ − ω

[CGfSe + CGfDe −CGfDe

−CGfDe CDSe + CGfDe

]=

1

zCf sinh(γCf L)

[2[cosh(γCf L)− 1

]−1[cosh(γCf L)− 1

]−1[cosh(γCf L)− 1

]cosh(γCf L)

](IV.58)

Equation (IV.58) combined with (IV.55) and (IV.56) allows to determine RCf

and CGfC directly. Figure IV.15 compares the result of the present directextraction technique and the optimisation described earlier. The curves forboth CGfC and GCf , 1/RCf correspond very well.

IV-34

IV.5 Intrinsic MOSFET in the linear operating regime

CGfC

[fF]

−2 0 2 4

GCf

[mf

]

−10

0

10

20

30

40

50

60

−20

0

20

40

60

80

100

120

140

160

−2 0 2 4

VGf

[V]

VGf

[V]

Figure IV.15: Comparing the results of the optimisation (crosses) and the directextraction (rings) for a 10×

(24.0µm/1.0µm

)n-MOSFET.

IV.5.2 Threshold voltage

In chapter III, the threshold voltage for moderate inversion, VThf (mod), wasdefined as :

VThf (mod) = Vfbf −Q′′b

2C′′of

−Q′′ifC′′of

+ κf

(VC + 2φF

)−C′′bob

C′′of

(VGb − Vfbb +

Q′′b2C′′ob

+Q′′ibC′′ob

)(IV.59)

This definition is however rather theoretical and does not indicate how to pro-ceed to obtain the threshold voltage from the measured C-V curve shown infigure IV.16. Booth et al, [IV.14], investigated several operational definitionsand compared them to theoretical definitions such as IV.59. They indicatedthat the point of steepest slope in the Gmfi versus VGf characteristic at low

drain voltage provided the best estimate of VThf (mod). This extremum ofdGmfi

dVGf

corresponds in fact to the maximal increase rate of the inversion charge, andcan equally well be evaluated by selecting the corresponding point of the CGf -curve. According to Flandre, [IV.15], the front gate flat-band voltage Vfbf canestimated as the gate voltage at which the accumulation charge starts to buildup. Combining threshold and flat-band voltage measurements with the sub-threshold slope measurements described by Colinge in [IV.16], it is possible todetermine the fixed oxide charge densities Nof and Nob the interface traps den-sities Nif , Nib and the depletion charge density in the film, Q′′b . Determination

IV-35

Extraction of SOI MOSFET model parameters

of these quantities is important, as they are most variable of all parameterspresent in expression (IV.59). Typical values are : Nof = 3.63 1011 cm−2,Nob = 2.45 1011 cm−2, Nif = 1.67 1011 cm−2 V−1, Nib = 1.0 1012 cm−2 V−1.Q′′b/q = 5.11−16 cm−3

−3 −2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3

100

162

225

288

350

412

475

538

600

[fF]

VGf

[V]

CGf

inversionaccumulation

VThfVfbf

Figure IV.16: Extracted total gate capacitance of a 10 ×(24.0µm/2.0µm

)n-

MOSFET.

IV.5.3 Mobility

In the case of a small-signal excitation at VDS = 0, the channel conductancecan be approximated by the following expression :

GCf =1

RCfuNcell W

LµQ′′nf (IV.60)

where Q′′nf is the inversion charge density, which is assumed to be constantalong the channel. At microwave frequencies, the interface traps are not ableto respond to the applied signals, so that the only contribution to the gate-to-channel capacitance CGfC is due to the inversion charge. This allows tocompute the inversion charge in function of the applied gate bias by integrationof CGfC , starting at a gate voltage VGf0 at which CGfC = 0 :

Q′′nf (VGf ) =κf

Ncell W L

∫ VGf

VGf0

CGfC (V )dV (IV.61)

IV-36

IV.5 Intrinsic MOSFET in the linear operating regime

E⊥eff

[cm2/

(V s)]

µ0 = 580.8[cm2/

(V s)]

χ = 0.0287[µm/V

]

100

200

300

400

500

600

700

0 5 10 15 20

[V/µm

]

µ

Figure IV.17: Extracted mobility versus normal electric field curve for a 10×(24.0µm/1.0µm

)n-MOSFET.

Knowing the inversion charge and the layout dimensions, it is now possi-ble to extract the mobility from the measured channel conductance curve us-ing IV.60. The channel mobility µ is known to degrade when the gate voltageis increased because the normal electric field presses the carriers harder ontothe gate oxide, causing more collisions and reducing their average speed. Thiseffect can be modelled by the simple expressions introduced in section III.3.1and shown below :

µ u µeff =µ0

1 + χ∣∣E⊥eff

∣∣ (IV.62)

E⊥eff , Esf −Q′′nf

2εSi=(ψsf − ψsb

tb−

Q′′b2εSi

)−Q′′nf

2εSi(IV.63)

Using equation (III.29) and (III.30), the surface potentials ψsf and ψsb canbe related to the inversion charge density Q′′nf . This allows to evaluate E⊥eff onthe basis of the measured gate-channel capacitance CGfC and equation (IV.61).The evolution of the extracted mobility is plotted on figure IV.17 in function ofthe normal electric field. The low-field mobility µ0 and the normal field coeffi-cient χ can be extracted by performing a linear regression on 1/µ(E⊥eff ). Theresults shown in the figure are in very good agreement with those published bySherony et al. in [IV.17]. This underlines both the validity of the distributedchannel model and the accuracy of the extracted series resistances. Overes-timated series resistances would cause an increase of the effective mobility at

IV-37

Extraction of SOI MOSFET model parameters

high gate voltages — corresponding to high E⊥eff — instead of the smoothE−1⊥eff decay. At low gate voltages, typically VGf u VThf , the evaluation of the

mobility according to (IV.60) is erroneous because Q′′nf can not be consideredconstant along the channel.

IV.5.4 Unified analytical model from depletion to inver-sion

The last subsections have demonstrated that the extraction of threshold voltageand mobility parameters from broadband S-parameters measurements is feasi-ble, provided that the distributed channel effects are properly accounted for inthe model. Accordingly, three channel sections are used here to perform theextraction of the empirical parameters used in the inversion charge expressionsof the unified analytical current and charge model presented in chapter III. Ithas indeed been shown in section III.5.3 that three subdivisions is a good com-promise between model complexity and accuracy of the predictions — evensomewhat conservative on the accuracy. The current and charge sources ofthe unified analytical model are embedded into the 4-terminal equivalent cir-cuit, replacing the small-signal elements of the intrinsic part. All adjacent andextrinsic elements are kept fixed at their previously extracted values. The op-timisation described below is performed over the set of measured bias pointsVlin , for which VDS = 0 and VGf varies from depletion to strong inversion.Only the empirical threshold voltage parameters and the mobility coefficientsare allowed to vary.

minPE(P) (IV.64a)

E ,∑

(VGf ,VD)∈Vlin

ωl ∈Ωi, j ∈1, 2

∣∣S(i, j)(P, VGf , VD , ωl)− S(i, j)(VGf , VD , ωl)∣∣2 (IV.64b)

where the parameter space for the optimisation is :

P ≡

p ,[µ0 , χ, φstg , φwk , θwk−stg

]∈ R5|

0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.64c)

Table IV.7 summarises the results of the extraction scheme applied to a10 ×

(24.0µm/1.0µm

)n-MOSFET fabricated at the UCL. Figure IV.18 com-

pares the measured and modelled S-parameters after extraction. The measuredand modelled curves in strong inversion and in depletion are all in reasonableagreement with each other. At VGf = 0, however, there is a non-negligibledifference between the two types of S11 -curves. It is not very well clear yetfor what reason the model is not able to properly reproduce the behaviourof the gate capacitance just below threshold. Possible explanations might bethe absence of corrections accounting for charge-sharing, the perfectible innerfringing capacitance model, or eventually inadequate evaluation of the DIBLcoefficient. Nevertheless, this discrepancy is rather marginal with respect tothe good fit which prevails at the majority of bias points.

IV-38

IV.5 Intrinsic MOSFET in the linear operating regime

Parameter Final Value Initial Value Unitsµ0 559.2 580.8 cm2/(V s)χ 0.02607 0.0287 µm/Vφstg 2.0803 2.0 φT

φwk −1.1215 −1.0 φT

θwk−stg 0.70354 0.9

Table IV.7: Detailed results of the extraction at VDS = 0.0 V, using the unifiedanalytical IQ-model with 3 sections, for a 10×

(24.0µm/1.0µm

)n-MOSFET.

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Im(S11 )

3.00.50.0

−0.5

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Re(S11 )

3.0

0.5

0.0

−0.5

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Re(S22 )

3.0

0.5

0.0

−0.5

2.0

1.0

[GHz

]0 2 4 6 8 10 12 14 16 18 20

0

0.25

0.5

0.75

1.0

−1.0

−0.75

−0.5

−0.25

Im(S22 )

3.0

0.5

0.0

−0.5

2.01.0

VGf[V] VGf[

V]

VGf[V] VGf[

V]

Figure IV.18: Comparing the measured (dotted lines with rings) and mod-elled (continuous lines with crosses) S-parameters after extraction of the unifiedmodel parameters for a 10×

(24.0µm/1.0µm

)n-MOSFET.

IV-39

Extraction of SOI MOSFET model parameters

IV.6 Intrinsic MOSFET in saturation

A MOSFET is said to operate in saturation when the electric field at the drainside of the channel drives the carriers so hard that they attain the saturationvelocity, vn(sat). It occurs in long-channel MOSFET’s when the channel is“pinched off”, in other words, when VDS > VGf − VThf . In the case of FET’swith very short channels — L < 0.2µm —, carriers may attain the satura-tion velocity in the channel even before pinch-off. This is typically the case inMESFET’s and HEMT’s, where it is commonly admitted that the length ofthe linear channel region is negligible with respect to the region where carrierstravel at the saturation velocity, [IV.18]. The converse is true for long-channelMOSFET’s, where the length of the saturation region is often neglected. TheSOI MOSFET’s considered in this work, have effective channel lengths rangingbetween 0.5µm and 1.5µm, so that none of the above simplifications apply.In normal biasing conditions, the length of the saturation region may attain0.15µm to 0.2µm, which constitutes a non-negligible fraction of the total chan-nel length. These considerations stress the importance of the channel lengthmodulation model, as well as the need to properly evaluate its parameters :vn(sat), the saturation velocity, η, the critical field coefficient, and θlin−sat theempirical parameter controlling the transition from the linear regime to satu-ration.

The extraction of these parameters is once again performed using the opti-miser. The corresponding optimisation problem is formulated below. The setof bias voltages considered during the optimisation, Vsat , extends from satu-ration into the linear region in order to adequately characterise the transition.

minPE(P) (IV.65a)

E ,∑

(VGf , VD)∈Vsat

ωl ∈Ωi, j ∈1, 2

∣∣S(i, j)(P, VGf , VD , ωl)− S(i, j)(VGf , VD , ωl )∣∣2 (IV.65b)

where the parameter space for the optimisation is :

P ≡

p ,[vn(sat), η, θlin−sat

]∈ R3| 0.1 · p(0) ≤ p ≤ 10 · p(0)

(IV.65c)

The extraction results obtained in the case of a 10 ×(24.0µm/1.0µm

)n-

MOSFET fabricated at the UCL are listed in table IV.8. The number of param-eters present in that table illustrates the compactness of the unified analyticalmodel : Few parameters need to be adjusted to nevertheless produce a sat-isfactory agreement between the modelled and measured S-parameters curvesshown in figures IV.19 and IV.20. The former shows the evolution of the fourscattering parameters for various gate voltages while the drain voltage is keptconstant. In the latter, the gate voltage is fixed and the drain bias is varied.

Figure IV.19 reveals a tendency of the model to overestimate the drain-source conductance that becomes worse when the drain voltage is increased.This can be noticed by looking at the low-frequency values of S22 , close to the

IV-40

IV.6 Intrinsic MOSFET in saturation

Parameter Final Value Initial Value Unitsvn(sat) 0.9153 1.0 105m/(V s)η 1.3765 1.8

θlin−sat 0.70354 4.0

Table IV.8: Detailed results of the extraction in saturation, using the unifiedanalytical IQ-model with 3 sections, for a 10×

(24.0µm/1.0µm

)n-MOSFET.

horizontal axis of the Smith chart. This effect is also clearly present in thelowest plot of figure IV.20. This has been interpreted as the manifestation ofself-heating effects, which are not accounted for in the model. Tenbroek et al.showed in their paper [IV.19] that the high-frequency drain-source conductancedecreases when the temperature rises. This is may explain why the predictionof the output conductance are systematically higher than the measurementsonce the dissipated power attains a few tens of milli-Watts.

The discrepancies between the modelled and measured S22 at the upperend of the band are probably related to inaccuracies in the substrate couplingmodel. Section IV.4.2 revealed indeed that the joint effect of the transconduc-tance Gmbi and of the capacitive coupling of the back gate to the diffusionsstrongly influences the apparent value of the drain-source conductance.

The modelled and measured curves of forward transmission S21 and inputreflection S11 are in very good agreement for all biases — except the pointat VGf = 2.0 and VDS = 3.0 where the self-heating during the measurementswas the worst. These results illustrate again the validity of the channel parti-tion scheme, which is responsible for the evaluation of the NQS effects in theunified analytical model. NQS effects indeed translate into a bias-dependentresistance in series with the gate-source capacitance and a phase-shift of thetransconductance, as shown in section IV.3.3. The close fit of S21 and S11 atall bias points suggests that both phenomena are properly predicted by thethree sections model.

IV-41

Extraction of SOI MOSFET model parameters

S21

S12

S11S22

VGf = 2.0 V VD = 2.0 V

S21

S12

S11S22

VGf = 3.0 V VD = 2.0 V

S21

S12

S11 S22

VGf = 1.0 V VD = 2.0 V

Figure IV.19: Comparing the measured (dotted lines with rings) and mod-elled (continuous lines with crosses) S-parameters after extraction of the unifiedmodel parameters for a 10×

(24.0µm/1.0µm

)n-MOSFET.

IV-42

IV.6 Intrinsic MOSFET in saturation

S21

S12

S11S22

VGf = 2.0 V VD = 2.0 V

S21 S12

S11

S22

VGf = 2.0 V VD = 1.0 V

S21

S12

S11

S22

VGf = 2.0 V VD = 3.0 V

Figure IV.20: Comparing the measured (dotted lines with rings) and mod-elled (continuous lines with crosses) S-parameters after extraction of the unifiedmodel parameters for a 10×

(24.0µm/1.0µm

)n-MOSFET.

IV-43

Extraction of SOI MOSFET model parameters

IV.7 Conclusion

A comprehensive extraction procedure has been developed along this chap-ter, allowing, on the fly, to validate all of the newly proposed models. TheNQS small-signal equivalent circuit was completely determined, and reliableidentification of all dominant parasitic elements was demonstrated. The mostimportant parameters of the unified analytical current and charge model wereextracted from on-wafer scattering parameters measurements performed at mi-crowave frequencies. Extracted values for physical parameters were found tobe in good agreement with results published in the literature. Adequate valuesfor the few empirical parameters were readily obtained. Important originalcontributions included in this chapter were :

1. A direct extraction scheme for the small-signal NQS equivalent circuit.

2. A direct extraction scheme for the gate-to-channel capacitance and thechannel conductance from broadband measurements on MOSFET’s atVDS = 0.

Experience has shown that direct extraction schemes are invaluable tools com-pared to optimiser-driven methods. They are much more computationally ef-ficient, may work unsupervised and are easily implemented as automatic rou-tines. The original direct extraction schemes proposed in this chapter are thusvery well suited for statistical modelling, opening up the possibility to extractthe equivalent circuit on a large population of devices.

The numerous comparisons of measured and predicted data allowed to verifythat, in particular :

1. The series resistances can be indifferently extracted in the framework ofthe 3- or of the 4-terminal model.

2. The proposed scaling rules for the small-signal model are valid in allpossible bias conditions, provided that the active zone width is neithertoo long or too short.

3. Three subdivisions suffice to properly account for the NQS effects usingthe unified analytical current and charge model.

The strengths and weaknesses of the unified analytical current and chargemodel were briefly discussed. Weaknesses are the absence of self-heating effectsand an unresolved problem in the evaluation of the gate capacitance just belowthreshold. The major strong point is the very limited number of parametersthat must be adjusted in order to produce reasonable predictions in all biasconditions up to 20 GHz.

References

[IV.1] I. Huynen, J.-P. Raskin, and D. Vanhoenacker, “An efficient varia-tional characterisation of multilayered planar lines combining thin andlow resistivity layers,” IEEE Trans. on Microwave Theory and Tech-niques, Submitted.

IV-44

REFERENCES

[IV.2] J.-P. Raskin, Modeling, Characterization and Optimization of MOS-FET’s and Passive Elements for the Synthesis of SOI MMIC’s. PhDthesis, Universite catholique de Louvain, Dec. 1997.

[IV.3] J. Chen, Development of Metallization Processes on Thin-Film SOIfor Low-Voltage, Low-Power Microwave and High-Temperature Appli-cations. PhD thesis, Universite catholique de Louvain, Dec. 1997.

[IV.4] J. J. Barnes, K. Shimohigashi, and R. W. Dutton, “Short-channelmosfet’s in the punchthrough current mode,” IEEE Trans. on ElectronDevices, vol. 3, pp. 953–959, Dec. 1979.

[IV.5] K. L. Peng and M. A. Afromowitz, “An improved method to deter-mine MOSFET channel length,” IEEE Electron Device Letters, vol. 3,pp. 360–362, Dec. 1982.

[IV.6] J. Whitfield, “A modification on “an improved method to determinethe MOSFET channel length,” IEEE Electron Device Letters, vol. 6,pp. 109–110, Mar. 1985.

[IV.7] F. J. Garcia Sanchez, A. Ortiz-Conde, M. Garcia Numez, and R. L.Anderson, “Extracting the series resistance and effective channellength of short-channel MOSFET’s at liquid nitrogen temperature,”Solid State Electronics, vol. 37, p. 1943, 1994.

[IV.8] J.-C. Gua, S. Shao-Shiun Chung, and C. Ching-Hsiang Hsu, “A newapproach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET’s,” IEEE Trans. onElectron Devices, vol. 41, pp. 1811–1817, Oct. 1994.

[IV.9] W. Fikry, G. Ghibaudo, H. H., C. S., and D. M., “A new methodto extract deep submicron MOSFET parameters,” in probably ECSAbstracts, undetermined date.

[IV.10] G. Dambrine, F. Heliodore, and E. Playez, “A new method for de-termining the FET small-signal equivalent circuit,” IEEE Trans. onMicrowave Theory and Techniques, vol. 36, pp. 1151–1159, July 1988.

[IV.11] S. Lee, H. K. Yu, C. S. Kim, J. G. Koo, and K. S. Nam, “A novelapproach to extracting small-signal model parameters of silicon MOS-FET’s,” IEEE Microwave and Guided Waves Letters, vol. 7, pp. 75–77,Mar. 1997.

[IV.12] J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge,“Accurate SOI MOSFET characterization at microwave frequenciesfor device performance optimisation and analogue modelling,” IEEETrans. on Electron Devices, May 1998. Accepted for publication.

[IV.13] M. Berroth and R. Bosch, “Broad-band determination of the FETsmall-signal equivalent circuit,” IEEE Trans. on Microwave Theoryand Techniques, vol. 38, pp. 891–895, July 1990.

IV-45

Extraction of SOI MOSFET model parameters

[IV.14] R. V. Booth, M. H. White, H.-S. Wong, and T. Krutsick, “The effectof channel implants on MOS transistor characterization,” IEEE Trans.on Electron Devices, 1987.

[IV.15] D. Flandre, Etude de Faisabilite d’une technologie CMOS sur Isolant(SOI) dans le Domaine des Circuits Digitaux. PhD thesis, Universitecatholique de Louvain, Laboratoire d’ Hyperfrequences, 1990.

[IV.16] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI.Boston: Kluwer Academic Publ., 1991.

[IV.17] M. J. Sherony, L. T. Su, J. E. Chung, and D. A. Antoniadis, “SOIMOSFET effective channel mobility,” IEEE Trans. on Electron De-vices, vol. 41, pp. 276–278, Feb. 1994.

[IV.18] J. H. Golio, Microwave MESFET’s and HEMT’s. Artec House, 1991.

[IV.19] B. M. Tenbroek, M. S. L. Lee, W. Redman-White, R. J. T. Bunyan,and M. J. Uren, “Self-heating effects in SOI MOSFET’s and theirmeasurement by small signal conductance techniques,” IEEE Trans.on Electron Devices, vol. 43, pp. 2240–2248, Dec. 1996.

IV-46

Chapter V

Microwave MOSFETdownconversion mixers

V.1 Introduction

There is presently a considerable research effort in the micro-electronic — andmicrowave — community towards the development of fully integrated transceiversfor mobile communications. Much work is being done around CMOS technol-ogy as it is low-cost and should allow to address the mass-market at lowerprices. The high-frequency parts of the system are the object of the an in-tense attention as technology evolved upwards from the radio-frequency rangeto the microwave range. Design solutions for the mixer stages have evolvedsubstantially in order to adapt to the specific requirements of microwave op-eration. Using the SOI MOSFET model developed in the previous chapter,the feasibility of microwave integrated mixers is investigated. Starting witha description of the basic building blocks to develop a thorough understand-ing of their operation, the chapter proceeds with a comparison of the majortypes of balanced mixer cells to finally select the resistive ring structureure andconstruct a complete down-conversion stage.

• Section V.2 introduces the two major types of mixers : Active and passivemixers. Single device mixers are analysed in order to identify specificfeatures for each type.

• Doubly balanced structures are presented in section V.3 as an efficientmeans to enhance the performance of integrated mixers. Measured char-acteristics of chopping and resistive SOI MOSFET mixers are compared

V-1

Microwave MOSFET downconversion mixers

with existing bulk implemetations showing the definite advantage of SOIin terms of low-voltage microwave performances.

• Section V.4 starts with a comparison of several down-converter architec-tures, showing the evolution towards single-chip integration. Solutionsfor the implementation of a low-IF receiver in SOI CMOS are presented.

The concept of device mismatch is used several times in the text below.The intended meaning is the one commonly admitted by IC design engineers :a disparity in the characteristics of nominally identical devices. This might besomewhat confusing for microwave engineers who use the term mismatch inrelation with the concept of impedance matching or tuning for optimal powertransfer or noise characteristics.

V.2 Single FET mixers

According to Maas, [V.1], and Philippe, [V.2], two major types of FET mixerscan be identified having each specific advantages and drawbacks :

1. Active mixers, also named transconductance mixers, where the mixingtransistors support a substantial DC bias current;

2. Passive mixers where the bias current is zero and where an eventual DCcurrent results only from self-mixing products.

In order to identify the properties of the active and passive operation modesfor mixers, simplified structures will be considered. A single FET is the basicbuilding block for mixers. Understanding its characteristics yields an immedi-ate insight into the strength and weaknesses of more elaborate mixing cells.Such elaborate cells attempt to enhance mixer performance by combining theresponses of identical devices in such a way that unwanted mixing productscancel out mutually. A meaningful comparison of balanced designs must in-clude an evaluation of their respective sensitivity to imperfect device matching— discrepancies in the behaviour of nominally identical devices. The moststraightforward manner to estimate the sensitivity to device matching is prob-ably to estimate the unwanted mixing products by simulating the basic buildingblock. The most important the unwanted products, the more stringent the re-quirement on matching will be. Simulation of the complete balanced structuredoes not reveal this information to the designer, unless some statistical investi-gation is made by introducing artificial discrepancies between devices. This ishowever much more computationally intensive than the simulation of the basicbuilding block. Furthermore, simpler circuits are naturally easier to interpret.

The following subsections concentrate thus on simplified single FET mixers.Simulation results are presented based on the SOI MOSFET model developedin chapter III with the parameters extracted in chapter IV.

V-2

V.2 Single FET mixers

V.2.1 Active mixers

The operating principle of active mixers is that the transconductance of thedevice is pumped by a large LO signal to achieve parametric conversion of theRF signal to the intermediate frequency.

IDS (t) = IDS(DC ) +Gmfi(t)VRF (t) (V.1)

In a conventional down-converter, the fundamental-frequency component ofthe transconductance is used for mixing. Maximising this frequency compo-nent of the transconductance optimises the gain, noise figure and minimisesintermodulation distortion. The fundamental LO-frequency transconductancecomponent is maximised when the transconductance waveform is a rectangularpulse train having a 50 % duty-cycle.

IF Filter

LO/RF Diplexer

LO

RF

IF

Source

Drain

Gate

Figure V.1: The gate-driven transconductance mixer. The diplexer combinesthe LO and RF signals providing impedance matching and mutual isolation tothe generators. The IF filter suppresses the strong LO component present inthe drain current.

Pumping of the transconductance Gmfi can be achieved by applying a largeLO signal in the following ways :

1. LO at the gate terminal of the device in saturation. This is, accordingto Maas, [V.1], the most favourable case, capable of the highest conver-sion gain. The gate is biased close to the threshold voltage so that thetransconductance waveform approximates a half-sinusoidal pulse train,which is as close to the optimum waveform as one can achieve in prac-tice.

2. LO at the source of the device in saturation, with the gate biased at thethreshold voltage. The presence of a load impedance — the LO generatorimpedance — in the source of the transistor reduces the fraction of theRF signal exciting the transistor, lowering the conversion gain.

3. LO applied at the drain of the transistor operating in triode regime. Thegate is biased well above threshold in order to keep the transistor at alltimes in the triode regime, independently of the LO signal. The trioderegime transconductance being smaller than in saturation, the conversiongain is naturally smaller.

V-3

Microwave MOSFET downconversion mixers

In all three cases the IF signal is collected at the drain. The RF signalis generally injected in the gate as this allows to obtain a power-conversiongain. Maas, [V.1], proposed the following expression for the conversion gain ofcase 1 :

Aconv ,PL(IF)

PG(RF)

uRe(ZL(IF)) Re(ZG(RF))

∣∣Gmfi (max)

∣∣28∣∣1 + ω(RF) CGfSi

(ZG(RF) +RGfe +RSe +RGfSi

)∣∣2(V.2)

where PL(IF) is the power delivered to the IF load; PG(RF) is the power availablefrom the RF source; ZG(RF) and ZL(IF) are the impedances loading the inputof the mixer at RF and its output at IF, respectively. Gmfi (max) is the peak

transconductance and the other parameters are circuit parameters defined inchapter III. The effect of the parasitic gate capacitances CGfSe and CGfDe hasbeen neglected.

Equation (V.2) implies that the conversion gain of the gate-driven activemixer can be made arbitrarily large by selecting a high value for RL(IF) ,Re(ZL(IF)). Limitations to the achievable conversion gain stem mainly fromthe fact that a high value for RL(IF) will generate amplifier-mode gain at the IFfrequency. Any out-of-band or noise signal present at the IF frequency on theRF node will be amplified and superimposed on the wanted IF signals. Practicalimplementations target a conversion gain around 0 dB, to avoid sacrificing tomuch of the noise figure due to amplifier-mode gain, [V.1].

Maintaining the transistor in saturation, or at least applying a substantialbias voltage on the drain has several effects. The elevation of temperatureinside the device due to DC power dissipation is responsible for the high levelof diffusion noise. Velocity saturation and channel-length modulation effects areresponsible for the high harmonic content of the drain current. On the otherhand, the presence of a strong DC longitudinal electric field in the channellimits the influence of NQS effects on the conversion gain. Carriers are indeedswept at maximum speed through the channel, allowing fast changes in theinversion charge density to occur in response to the LO stimulus.

Using equation (V.2) the influence of NQS effects on the conversion gain ofgate-driven single MOSFET mixers can be investigated. In a given technology,using the minimal available channel length, it is always possible to design amixer with a specified conversion gain Aconv(max) for a determined LO level,provided the RF and LO frequencies are sufficiently low. It therefore suffices tochoose a sufficient total device width, yielding the proper value of Gmfi (max).

Using the scaling rules, the evolution of the conversion gain in function of theRF frequency can be expressed by :

Aconv (ω(RF)) u Aconv(max) ×∣∣∣∣1 + ω(RF)

(√ 8 Aconv(max)

RL(IF)/RG(RF)ω−1

Ti + τGfe + τSe + τGfSi

)∣∣∣∣−2

(V.3a)

V-4

V.2 Single FET mixers

LO Frequency Conversion Gain 3rd Harmonic

PL(IF)

PG(RF)

PL(H3 )

P 2G(LO)

PG(RF)

GHz dB dB2.0 −17.1 −29.14.0 −18.0 −25.68.0 −20.0 −31.0

12.0 −22.8 −37.516.0 −25.8 −42.2

Table V.1: Detailed results of harmonic balance simulations of the single devicetransconductance mixer. The IF frequency is 10.0 MHz. The LO drive is a1.4 V peak-to-peak sinusoid. The mixer loads are 50.0 Ω resistors. The gate isbiased at 0.3 V, the drain at 2.0 V. The transistor is a 10× (24.0µm/1.0µm)nMOSFET.

where the following definitions apply :

ωTi ,G′mfi

C′GfSi

(V.3b)

τGfe , CGfSi RGfe (V.3c)

τSe , CGfSi RSe (V.3d)

The RF and IF load impedances were assumed to be real :

ZF(RF) = RG(RF) and ZL(IF) = RL(IF) (V.3e)

ωTi corresponds to the intrinsic current-gain cut-off frequency of the transistor.τGfe is fixed by the layout design and is kept to a minimum as the “CGfSi RGfe”product controls the attenuation of the gate signal along the gate finger — seesection III.6.3. τGfe is thus virtually independent of the total device widthand hence of Aconv(max). τSe is depends solely on the bias conditions and thetechnological parameters, not on the device width or the specified Aconv(max).τGfSi is the NQS charging delay of the gate-source capacitance.

Harmonic balance simulations were performed to assess the validity of equa-tion (V.3). The NQS analytical current and charge model with 3 channelsections was used to simulate a single device transconductance mixer withthe LO drive applied to the gate and loaded by 50 Ω resistors. The MOS-FET was the 10 × (24.0µm/1.0µm) n-channel device considered in the ex-tractions of chapter IV. The simulation results summarised in table V.1. Us-ing Aconv(max) = −16.0 dBm in equation (V.3), yields a 6.0 dB-frequency of12.0 GHz, which agrees well with the data of table V.1.

V-5

Microwave MOSFET downconversion mixers

IF Filter

LO Matching

LO

RF

IF

Source

Drain

Gate

RF Filter

Figure V.2: The resistive mixer.

V.2.2 Passive mixers

Passive mixers, often called resistive mixers, use the variation of the channelconductance to perform the parametric conversion of the RF signal to the IFfrequency. The MOSFET is biased in strong inversion at VDS = 0, and the LOis applied to the gate. The bias conditions are chosen so that operation in thelinear — triode — regime is ensured at all times, independently of the RF andLO signals. The RF signal is applied to one end of the channel and IF currentsare filtered indifferently from the same or the opposite end.

IDS (t) = GDi(t)VRF (t) (V.4)

The primary advantage of the resistive mixer is its very low-levels of in-termodulation distortion. Velocity saturation and channel length modulationwhich are the primary source of distortion in active mixers do not appear inresistive mixers. The absence of DC current implies that resistive mixers ex-hibit very low noise levels : As very little power is dissipated inside the devicethe channel is nearly at room temperature so that the level of diffusion noiseis low; Furthermore shot noise is also minimal in these conditions.

On the contrary to the active mixer, where the intrinsic gate-drain ca-pacitance is nearly zero, in the resistive mixer, the intrinsic source and draincapacitances CGfSi and CGfDi are equal. This means that, when the LO fre-quency is sufficiently high, an important LO leakage will occur across the CGfDi

capacitance. Balanced structures remedy to this problem, by creating virtualgrounds at the source and drain with respect to the differential LO signals. Adouble balanced resistive structure is presented in subsection V.3.2 below.

Another potential problem of the resistive mixer is the absence of a stronglongitudinal electric field in the channel. This means that the velocity of carriersis limited, so that one may fear a degradation of the conversion gain due toNQS effects. Harmonic balance simulations have been performed on a SOI n-MOSFET with a nominal channel length of 1.0µm and a total width of 240µm.The transistor was biased with 2.0 V at the gate. The loads of the mixer were50 Ω resistors. The results are summarised in table V.2. They show that the

V-6

V.2 Single FET mixers

LO Frequency Conversion Gain 3rd Harmonic

PL(IF)

PG(RF)

PL(H3 )

P 2G(LO)

PG(RF)

GHz dB dB2.0 −32.2 −48.04.0 −33.0 −52.88.0 −34.8 −68.2

12.0 −37.0 −57.616.0 −38.9 −52.6

Table V.2: Detailed results of harmonic balance simulations of the singledevice resistive mixer. The IF frequency is 10.0 MHz. The LO drive is a1.4 V peak-to-peak sinusoid. The gate is biased at 2.0 V. The transistor is a10× (24.0µm/1.0µm) nMOSFET.

conversion gain decreases at a rate of 8.0 dB/ decade which is not excessivelyhigh and even compares very well with the results of the active mixer. Onemay thus conclude that NQS effect do not degrade the conversion gain of thepassive mixer more than they do in the case of the active mixer.

The conversion gain of the resistive mixer is 15 dB lower than the conversiongain of the transconductance mixer based on the same transistor and loadedsimilarly. The level of third harmonic lies in the case of the resistive mixer 20 dBbelow the level reached in the transconductance mixer. It can be seen from theevolution of the level of the third harmonic in function of LO frequency thatthe resistive mixer is subject to stronger capacitive harmonic distortion thanthe transconductance mixer. The dip in the third harmonic around 4–6 GHzis due to a compensation between conductive and capacitive distortion. Abovethese frequencies capacitive distortion dominates.

V.2.3 The MOSFET switch

A single-MOSFET switch can be used as a mixer. Its operation principle isthat the RF current is sampled at the LO frequency, generating a IF signal onsome load. Such a mixer is a form of compromise between the active and thepassive mixer, widely used in balanced active mixer configurations.

The gate of the MOSFET is biased around the threshold voltage as in thecase of the active mixer. A sufficiently strong LO signal is applied to the gateso that the transistor is switched on and off during a LO cycle. The transistormust be designed large enough to ensure linear operation when it is turned onand to minimise its on-state resistance. A non-zero DC bias voltage is usuallyapplied to the drain in order to enhance the switching speed an minimise theswitching transient. The RF current is then fed in source and the IF signal iscollected at the drain.

Neglecting the influence of the drain-gate capacitance at the IF frequency,

V-7

Microwave MOSFET downconversion mixers

the relationship between the RF current and the IF voltage can be expressedaccording to Rofougaran, [V.3], as :

VL(IF) = π−1 ZL(IF)

1 + ωRF CGfSi

(RDSi + ZL(IF)

) IG(RF) (V.5)

As will be shown in section V.3.1 below, pratical implementations of this mixeruse a transconductance stage to feed the RF current to the switch.

The chopping mixer presented here share several advantages and drawbacksof active mixers. Its conversion gain can be adjusted at will by choosing propervalues for ZL(IF). The chopping mixer does not suffer from amplifier mode gainat the IF frequency, as any IF signal fed by the current source is transformed bythe switch into a signal at RF frequency on the IF node. The chopping mixerdoes well suffer from the high noise and distortion levels of active switches.

V.3 Balanced mixers

In order to enhance the performance of single device mixers, and particularly toattenuate detrimental effects, multiple identical devices can be used in balancedconfigurations fed by differential signals. These arrangements force unwantedmixing products to cancel out mutually while preserving the useful signal.Using differential signals on symmetrical structures, virtual grounds are createdwhich allow to enhance the isolation between the LO and the IF terminals.

Figure V.3: The printed circuit board for the characterisation of the packagedmixer chips. On the top the differential LO and RF signals. At bottom thedifferential IF signals.

V-8

V.3 Balanced mixers

Generation of differential signals is a key problem in the successful imple-mentation of integrated balanced mixers. Several solutions exist :

1. Passive generation of the differential signal using coupled planar induc-tors organised as a transformer with the secondary winding grounded atmidpoint.

2. Active generation using transistors, typically in an input amplifier.

3. Off-chip generation of the differential signals, using baluns or 180 deghybrid junctions.

This latter alternative has been applied for all mixer implementations in thepresent work. The reasons were that, at the time of design, inductors of suf-ficient quality were not available and very little was known about integratedCMOS microwave amplifiers. As the present chapter focusses on the character-istics of the mixing cells themselves, it was found more convenient to use highquality hybrid junctions for all measurements, so that all mixers would be fedby clean differential signals.

V.3.1 The Gilbert cell

This cell is named after B. Gilbert who proposed a balanced topology for bipolartansistor mixers where a common emitter pre-distortion stage was used toconpensate for the distortion of the actual balanced mixing stage, [V.4]. Hisdesign exploits specific features of the exponential transfer function of bipolartransistors. The distortion compensation feature does not apply to FET’s ingeneral, but balanced FET cells share the topology of the Gilbert cells properand are widely designated as Gilbert cells.

VIF+

VIF−

VLO−VLO+ VLO+

VRF+ VRF−

Transconductance stage

Switches Switches

VDD VDD

IF loads

Figure V.4: A balanced active MOSFET mixer : the Gilbert cell

V-9

Microwave MOSFET downconversion mixers

Several authors reported using switching MOSFET Gilbert cells for mo-bile communications applications, [V.5,V.6]. Very few solutions using balancedtransconductance MOSFET mixers have been proposed, [V.7,V.8]. Crols, [V.9],indicated that transconductance MOSFET mixers have in general a limitedlinearity which highly depend on device-uniformity — matching — and thathigh-frequency operation can only be achieved at the cost of high current con-sumption.

Figure V.5: Silicon die of the chopping mixer cell. The RF terminals are theupper two pads on the right. The LO terminals are the second and third fromthe right at the bottom. The IF terminals are on the left-hand side, at the top.The other bond pads are for DC biasing.

The feasability of SOI CMOS chopping mixers has been investigated. Thearchitecture proposed by Rofougaran, [V.3], was adapted to the SOI CMOStechnology of the UCL. The mixer cell topology was exactly the one depictedin figure V.4. An output buffer stage was added to allow stand-alone operationin the 50 Ω measurement environment. The cell was designed to have a 0 dBconversion gain at 10 dBm LO drive. For a LO and IF frequencies of 1.8 GHzand 5.0 MHz, respectively, SPICE simulations predicted a 55 mV amplitude ofoutput IF signal for a −10 dBm RF excitation. Measurement of the packagedmixers in these conditions revealed a 56 mV amplitude of the IF signal. Thesupply voltage was in both cases 4.0 V.

Power Supply IIP3V dBm(RF )

2.0 +25.42.5 +24.93.0 +16.53.5 +17.63.5 +17.9

Table V.3: Results of IIP3 measurements. The LO level was 10 dBm at 1.8 GHz.The IF frequency was 5.0 MHz. The third order intermodulation intercept pointIIP3 is characterised in terms of the RF power at the input.

The main purpose of the implementation was to verify the intermodulationproperties of the SOI CMOS chopping mixer. The intermodulation of two

V-10

V.3 Balanced mixers

neighbouring RF signals was characterised by measurement of the third orderintermodulation intercept point IIP3 at the IF frequency. The measurementswere repeated at various supply voltage levels.

The intermodulation results listed in table V.3 are encouraging. The in-put power levels corresponding to the third order intercept point are at least10 dBm higher than the results published by Rofougaran in [V.3] for a 3.0Vpower supply and a LO frequency of 1.0 GHz. The value given by Rofougarancombines however the intermodulation of the mixer and the low-noise ampli-fier. These measurement results again confirm that an SOI technology enablesCMOS designs to function at higher frequencies ...

V.3.2 The resistive ring

VIF+ VIF−

VLO−VLO+

VRF+

VRF−

Figure V.6: A balanced resitive mixer : the ring.

Song, [V.7], and Crols, [V.9], proposed to use balanced resistive bulk MOS-FET mixers to overcome the limitations of active mixers at high-frequencies.Crols mentioned very low distortion, low noise and zero power consumption asthe major advantages of resistive ring mixers. The use of the double balancedstructure shown in figure, allows to cancel the effect of common-mode DC bi-asing signals as well as the nonlinear dependence of GDi on the drain voltage.Crols pointed out that mismatches in the device characteristics have little effectas long as the LO is applied to the gates. Mismatches let indeed a quadraticterm function of the gate signal appear at the IF terminals. If the RF wasapplied to the gate, several parasitic signals would appear in the baseband dueto the quadratic detection. The squared LO signal results however only in aDC component which will not interfere with the baseband signals.

Crols achieved high-frequency performance with resistive rings by usingminimal transistor sizes for the MOSFET’s and a high value for VGf − VThf .This allowed to have a reasonably low channel resistance at the cost of little

V-11

Microwave MOSFET downconversion mixers

capacitance, maximising the bandwidth. Using minimal sizes is however notfavourable from the point of view of uniformity of device characteristics. Itis indeed better to use larger devices and to perform a space averaging of thecharacteristics by combining separate active regions to obtain the desired totalwidth. The simulations performed in section V.2.2 showed that the frequencyvariation of the conversion gain of a resistive mixer based on a SOI n-MOSFETwith a 1.0µm nominal channel length were even slightly better than for theactive mixer. NQS effects are not too severe and one could depart from minimaltransistor sizes to lower the VGf − VThf and render the design more robust toprocess variations.

Figure V.7: Silicon die of the resistive mixer cell. On the left, the LO terminals;On the top, the differential IF (left) and RF (right) terminals.

Resistive ring structures were designed to operate in the 50 Ω measurementenvironment, in order to allow characterisation of their intermodulation per-formance and to confirm their ability to function at high-frequencies. Resistivemixers fabricated at “Electronique Marin” were measured at 1.8GHz with aLO drive of +10 dBm. The maximum conversion was obtained at a gate biasaround 1.0 V and was −29.0 dB, relatively close in fact to the predictions fromcomputer simulations mentioned in subsection V.2.2. The simulations are how-ever intended for the UCL technology which uses silicides for the lowering ofseries resistances on the contrary to the technology at “Electronique Marin”.

DC gate bias IIP3V dBm(RF )

1.0 +40.11.5 +35.12.0 +41.2

Table V.4: Results of IIP3 measurements. The LO level was 10 dBm at 1.8 GHz.The IF frequency was 5.0 MHz. The third order intermodulation intercept pointIIP3 is characterised in terms of the RF power at the input.

The results summarised in table V.4 are in good agreement with what iscommonly expected for resistive mixers in the literature, [V.1,V.9]. The conver-

V-12

V.4 A low-IF down-conversion architecture

sion gain was not found to vary importantly over the measurement bandwidth,from 1.0 GHz to 2.0 GHz, confirming that SOI resistive mixing cells have a goodpotential for microwave applications. The exceptional linearity of the resistivecell is a distinctive advantage for the implementation of receivers in mobilecommunication systems. In the mobile environment, multi-path propagationor atmospheric perturbations can cause substantial signal fading, requiring thereceiver to have a large dynamic range. A high linearity of the mixer is impor-tant with this respect.

V.4 A low-IF down-conversion architecture

Crols performed an extensive comparison of existing down-conversion architec-tures in his thesis, [V.10]. The existing solutions, the conventional IF receiverand the zero-IF are analysed and an alternative solution is proposed, the low-IFarchitecture, which can be fully integrated on a single chip.

• In the conventional IF receiver a microwave preselection filter is used toavoid folding unwanted signals back on to the desired one during thedown conversion to IF. The IF frequency is dictated by the bandwidthof the preselection filter. Typical values are 10 to several hundred MHz.The rejection of the signal at the image frequency is performed at IF werenarrow filters can be realised in off-chip technology. The signal is thenfinally converted to the baseband and detected. This system architecturerequires thus at least three chips : a microwave chip, a IF filter chip andthe IF and baseband chip.

• In the zero-IF solution, [V.5], the RF signal is down-converted directlyto origin of the frequency axis, using a quadrature conversion scheme. Inthis scheme the baseband signal is represented by a pair of signals, thein-phase signal, I and the quadrature signal, Q. The wanted signal canthen be reconstructed by summing the I and Q signals. Substracting thesignals would yield the image. A simple low-pass filter is used to performthe channel selection after the down-conversion. This architecture canbe fully integrated on a single chip but it is highly sensitive to parasiticbaseband signals like DC offset voltages, second order distortion productsand self-mixing products, [V.11].

• In the low-IF solution, [V.10], the RF signal is translated directly to alow IF frequency using the quadrature down-conversion scheme. Low-frequency signal processing — most likely digital processing — can thenbe used to retrieve the wanted signal from the I and Q representation.This architecture resolves the problem of sensitivity to parasitic DC sig-nals. Its overall performance is however dependent up on the accuracy ofthe phase relationships between the quadrature LO and RF signals. Thequadrature generation circuits are thus key components of the design.According to Crols, [V.11], phase errors must lie below 0.5.

V-13

Microwave MOSFET downconversion mixers

The architecture of the low-IF solution is presented in figure V.8. This so-lution has been chosen for implementation in the UCL technology as a demon-strator. It allows proper evaluation of the downconverter on its own, on thecontrary to the zero-IF solution which must be coupled to baseband signalprocessing in order to cancel the unwanted DC parasitic responses.

The two most important sub-assemblies have been implemented separatelyto test their individual performance : The basic IF cell, consisting of a singlemixer, the low-pass filter and the IF amplifier, and the passive quadraturegeneration filter.

RF

LO

QLOILO

IRF

QRF

IIF

QIF

IF Amplifier

IF Amplifier

90

900

0

Mixers

∑

∑

Low-pass Filter

Low-pass Filter

+

−

+

+

Figure V.8: The low-IF downconverter architecture

V-14

V.4 A low-IF down-conversion architecture

V.4.1 Basic IF cell

A basic IF cell has been designed for stand-alone operation. The design usesthe resistive ring mixer, based on minimal size n-MOSFET’s having a channellength of 1.0µm and a total width of 6.0µm.

Special care was taken for the implementation of the capacitor CLP respon-sible for the filtering of the unwanted high frequency mixing products. Theresonance frequency of CLP must significantly higher than the first harmonicof the LO frequency. Furthermore, the parasitic series resistance must be keptvery low, typically below a few Ω.

The amplifier is an operational transconductance amplifier designed ac-cording to the method of [V.12] by J.-P. Eggermont. It was implemented ina fully differential topology with active common-mode suppression. The feed-back around the OTA was designed to ensure a 10 MHz IF bandwidth and anoverall conversion gain for the cell of 20 dB at a 10 dBm LO drive.

RF

LO

IFResistive Ring CLP

RF

CF

OTA

Figure V.9: The IF test-cell design

Measurements of the mixer cell at 1.8 GHz under a LO drive of 12 dBm anda DC power supply of 4.0 V revealed a conversion gain of only 7.0 dB. A furtheranalysis showed that the common-mode suppression feedback was interferingwith the differential mode because of a mismatch in the feedback resistors.

V.4.2 Quadrature generation

Crols proposed in [V.10] an enhanced version of the traditional R-C quadraturegenerator. It is the passive polyphase filter shown in figure V.10. All resistorhave the same resistance R and all capacitors the same capacitance C. Thefilter rejects in-phase signals presented to the input and let quadrature signalspass through with a 6.0 dB attenuation. It can be configured as a quadraturegenerator simply by grounding the input quadrature terminals, Qi+ and Qi−.The center frequency is given simply by fc = RC/(2π).

The main advantage of the polyphase filter is that it is less sensitive toprocess variations and that it allows to obtain an accurate 90 phase differenceover a wide band : a ±0.3 variation in a 100 MHz band around 1.8 GHz.

V-15

Microwave MOSFET downconversion mixers

Io+ Io−

Qo−

Qo+

Qi+

Qi−

Ii+ Ii−

R C

Figure V.10: The passive polyphase quadrature generator filter.

The practical implementation of the structure was hampered by the low re-sistivity of the polysilicon layer used to make resistors at the UCL. The parasiticcapacitance of the 500 Ω resistors used in the design attained a very importantfraction of the value required for C. A new layout design was developped wichallowed to incorporate the parasitic capacitances of the resistors into the theuseful capacitance. The quadrature generator were fabricated but have notbeen characterised yet.

Io+

Io−

Qo−

Qo+

Qi+

Qi−

Ground

Polysilicon Resistors

Metal-Polysilicon Capacitors

Figure V.11: The layout of the passive quadrature generator.

V-16

V.5 Conclusion

V.4.3 Evaluation chip

The complete evaluation chip was fabricated, but the chips have not beenencapsulated yet, so that no measurements are available at present.

Figure V.12: Silicon die of the quadrature down-conversion mixer, with fromleft to right : the LO and IF quadrature generators, the mixers block, the twolow-pass filters (capacitors), feedback resistors, the two IF-amplifiers

V.5 Conclusion

The feasability of microwave SOI MOSFET mixers has been tested and demon-strated. Resistive SOI MOSFET mixers were shown to enjoy the low-distortionand large dynamic range which is typical of resistive ring mixers. Harmonicbalance simulation performed with the newly developped analytical currentand charge model revealed that NQS effect do not significantly degrade theconversion gain of resistive mixers fabricated in a 1.0µm SOI CMOS technol-ogy — at least not to prohibit the use of resistive rings with LO frequenciesas high as 10 GHz. This is probably the most outstanding original result pre-sented in this chapter. A complete downconverter has been fabricated andmore measurement results are still to come.

V-17

Microwave MOSFET downconversion mixers

References

[V.1] L. E. Larson, ed., RF and Microwave Circuit Design for Wireless Com-munications, ch. Mixers for Wireless applications. London: ArtechHouse, 1996.

[V.2] R. Goyal, ed., High-frequency Analog Integrated Circuit Design,ch. Mixers. New York: John Wiley & Sons, 1995.

[V.3] A. Rofougaran, J. Y.-C. Chang, M. Rofougaran, and A. A. Abidi, “A 1GHz CMOS RF front-end IC for a direct conversion wireless receiver,”IEEE J. of Solid-State Circuits, vol. 31, pp. 880–889, July 1996.

[V.4] B. Gilbert, “A high-performance monolithic multiplier using activefeedback,” IEEE J. of Solid-State Circuits, vol. 9, pp. 364–373, Dec.1974.

[V.5] A. A. Abidi, “Direct-conversion radio transceivers for digital communi-cations,” IEEE J. of Solid-State Circuits, vol. 30, pp. 1309–1410, Dec.1995.

[V.6] A. N. Karanicolas, “A 2.7 V 900 MHz CMOS LNA and mixer,” in 1996IEEE Int. Solid-State Circuits Conference, Digest of Technical Papers,Feb. 1996.

[V.7] B.-S. Song, “CMOS RF circuits for data communications applications,”IEEE J. of Solid-State Circuits, vol. 21, pp. 310–317, Apr. 1986.

[V.8] H.-J. Song and C.-K. Kim, “A MOS four-quadrant analog multiplierusing simple two-input squaring circuits source followers,” IEEE J. ofSolid-State Circuits, vol. 25, pp. 841–848, Mar. 1990.

[V.9] J. Crols and M. S. J. Steyaert, “A 1.5 GHz highly linear cmos downcon-version mixer,” IEEE J. of Solid-State Circuits, vol. 30, pp. 736–741,July 1995.

[V.10] J. Crols, Full integration of wireless transceveir systems. PhD thesis,Katholieke Universiteit Leuven, Leuven, Belgium, 1996.

[V.11] J. Crols and M. S. J. Steyaert, “A single-chip 900 MHz CMOS receiverfront-end with a high performance low-IF topology,” IEEE J. of Solid-State Circuits, vol. 30, pp. 1483–1492, Dec. 1995.

[V.12] F. Silveira, D. Flandre, and P. G. Jespers, “A gm/ID based method-ology for the design of CMOS analog circuits and its applications tothe synthesis of a silicon-on-insulator micropower OTA,” IEEE J. ofSolid-State Circuits, vol. 31, pp. 1314–1318, Sept. 1996.

V-18

Conclusion

This work presented a comprehensive and innovative approach to the modellingof SOI MOSFET’s at microwave frequencies.

An accurate small-signal characterisation procedure was setup on the basisof scattering parameters measurements. In-situ calibration was introduced asan efficient de-embedding technique, allowing to circumvent the limitations ofthe widely used immittance correction technique. The importance of properdetermination of the reference impedance of S-parameters on-wafer calibra-tions was revealed, and two original determination methods were proposed :The load measurement method, which proceeds by comparison of the DC andRF characteristics of a resistor, and the calibration comparison method, whichextracts information about the impedance transform from the T-matrices re-lating two successive calibrations. The load measurement method was appliedfor validation purposes to the determination of the characteristic impedance ofa coplanar waveguide section : The results turned out to agree very well withboth computer simulations and experimental determinations of the character-istic impedance, evaluated in the quasi-TEM approximation. In practice, theapplication of the calibration comparison method proved to be more compli-cated than that of the load measurement, so that the latter method has beenpreferred. Combined with the rigorous TRL calibration technique, the newreference impedance determination method contributed to achieve reliable on-wafer measurements of admittance and impedance parameters up to 40 GHz,with simple calibration structures implemented in a standard 1.0µm CMOSprocess.

A large signal current and charge model was developed for the SOI n-channelMOSFET with the specific needs of analogue microwave circuit design in mind.Special attention was devoted to channel propagation delays, to short channeleffects and to the dispersive behaviour of the interface traps. Multiple channelsections were introduced to simulate channel propagation delays. It was shownthat, in the case of 1.0µm SOI MOSFET’s, three channel sections are sufficientto account properly for these non-quasi-static effects up to 40 GHz. A semi-analytical model of the saturation region has been used to evaluate the effective

1

Conclusion

channel length shortening in saturation. Drain-induced barrier lowering, thesecond significant short-channel effect affecting UCL SOI MOSFET’s, has beenmodelled by a threshold voltage correction. These enhancements allowed to ex-tend the validity of the charge-sheet model to submicrometer devices. Specificstate variables controlled by a first order differential equation were introducedin order to mimmic the dispersive behaviour of the interface traps, enabling theunified treatment of DC and RF characteristics. To ensure the continuity ofall bias-dependent characteristics across several operating regimes, the modelrelies on two infinitely derivable interpolation functions : one for the predictionof the inversion charge from depletion to strong inversion, a second for the tran-sition from the linear regime into saturation. The curent and charge model wascoded in C and integrated into the OSA software for harmonic balance circuit-simulation and optimisation. The implementation proved sufficiently efficientto allow on-line small-signal simulation and optimisation. Two-tone harmonicbalance simulations using fifteen discrete frequencies were conducted off-line,and lasted typically less than one hour on a Sun SPARK station.

Dedicated small-signal models for the intrinsic SOI MOS device were alsopresented : An adaptation to SOI of the high-frequency small-signal modelproposed by Tsividis for bulk MOSFET’s, and an original distributed channelmodel for SOI MOSFET’s at VDS = 0. Finally, an elaborate small-signal equiv-alent circuit model was devised for parasitic effects such as substrate coupling,capacitive gate-diffusions coupling, series resistances and residual interconnec-tion lengths at the input and output of the device. This extrinsic small-signalmodel constitutes an indispensable complement to the intrinic models — eitherthe analytical current and charge model or the dedicated small-signal models— for the prediction of the microwave behaviour of the MOSFET.

The proposed models were confronted to measurements. Several new S-parameters based extraction techniques were developed, allowing to identifymodel parameters in a way which proved coherent with established physicalinterpretations. This was specifically the case for the series resistances, theparasitic gate capacitances, the threshold voltage, the channel length and thetransport model parameters. The available extraction techniques were com-bined in a comprehensive procedure allowing the progressive identification ofthe majority of model parameters; Only a few well-controlled technological pa-rameters were assumed to be known a-priori. At the beginning of the extractionprocedure, a simplified three-terminal small-signal model of the MOSFET isused. Starting with the determination of adjacent and extrinsic parasitic cir-cuit elements, the extraction proceeds inward with the identification of theseries parasitics. Then the complete four-terminal model is introduced and thesubstrate coupling parameters are identified. Finally, the current and chargemodel is substituted to the intrinsic part of the small-signal equivalent cir-cuit, and its internal parameters are identified : inversion-charge parameters,transport model and saturation model parameters. All extractions involved inthis procedure were formulated as optimisation problems. In order to extracteach parameter with minimal uncertainty, biasing conditions for the extrac-tions were carefully selected for an optimal sensitivity of the measurements tothe parameter in question.

2

Two original direct extraction schemes were proposed : one for the identifi-cation of the non-quasi-static small-signal equivalent circuit in saturation andanother one for the determination of the channel capacitance and conductancefrom broadband S-parameters measurements. These direct extraction methodsenjoy a number of distinctive advantages with respect to their optimiser-drivencounterparts : Initial values are not required, spurious solutions — comparableto local minima in the case of optimisation — do not exist. Furthermore, directextraction schemes are computationally efficient and can be easily implementedas automatic routines.

The extensive comparisons of model predictions with measurements pro-vided confidence in the validity of the modelling approach. The analyticalcurrent and charge model was then used to analyse the performance of mi-crowave mixer designs. The feasibility of resistive SOI MOSFET mixers at2.0 GHz was established and confirmed by measurements performed on basicmixing cells. Simulations even showed that the conversion gain of resistive mix-ers fabricated in a 1.0µm SOI technology did not degrade significantly above2.0 GHz, even up to 10 GHz. This conclusion seems to depart from the widelyadmitted opinion that NQS effects would force to use deep sub-micron channellengths to implement mixers in MOS technologies above a few GHz. The anal-ysis performed here showed on the contrary that some margin is available tochoose larger channel length allowing to enhance the robustness of the circuitto process variations — typically, a very critical aspect of analogue designs.

This latter result is a good illustration of the benefits resulting from themodelling approach elaborated during this doctorate research. The key featuresof this approach are :

1. An accurate de-embedding method, based on rigorous calibration tech-niques.

2. Physical modelling.

3. Reliable identification of parameters using direct extraction schemes orselective optimisation.

3

Appendix A

Coplanar waveguideson SOI

A.1 Introduction

Coplanar waveguides are a key-component for the on-wafer characterisationof SOI structures. Being truly planar, they are the natural choice for low-cost fabrication processes. CPW’s avoid the complication of precise thicknesscontrol and of through-hole etching which are both mandatory for a micro-striptechnology. CPW’s have furthermore the distinctive advantage to be scalableprovided the substrate thickness is sufficient. The CPW topology allows therealisation of simple and efficient transitions to coaxial waveguides, a featurethat fostered the development of on-wafer probes.

The practical realisation of CPW’s suffers however of several draw-backs.The ideal CPW structure is unbounded, on the contrary to the micro-stripstructure which occupies a half-plane. In particular, an ideal CPW shouldbe self-supporting while a MS may rest on a ground-plane or heat-sink. Toadapt the CPW to conventional packaging or handling technologies, a metallicback-plane may be used. The resulting structure is “over-moded”, in the sensethat several propagation modes coexist : the wanted coplanar mode and theunwanted micro-strip-like mode, which may convert to a surface wave, causingleakage. Another disadvantage of the CPW structure stems from its symmetry.The CPW can be analysed as a coupled slots system, in which the desiredmode is the odd mode. As soon as the symmetry is perturbed — differentloads on each slot — a mode conversion will occur transferring power fromthe odd mode to the unwanted even mode. Solutions used to tackle the modeconversion problems are presented in section A.2.

A-1

Coplanar waveguides on SOI

(a) (b)

(c) (d)

OX

OY

⊗OZ

Figure A.1: Electric field lines for the propagation modes of the CPW struc-ture : (a) CPW mode; (b) Parasitic slot mode; (c) Parasitic MS mode; (d)Surface wave, propagating along OX . (a–c) propagate along OZ.

CPW sections have been used intensively in the present work as basic struc-tures for the calibration of the vector network analyser. The calibration pro-cedure described earlier yields both the propagation constant γ and the char-acteristic impedance Zc of the CPW’s as by-products. These parameters fullycharacterise the behaviour of the measured CPW structures and contain usefulinformation about the supporting substrate. A macroscopic model has been de-veloped which properly accounts for the frequency evolution of the transmissionline characteristics. This model eventually allows to relate these characteristicsto physical parameters and to perform extractions. The model is presented insection A.3 and the extraction procedure in section A.4.

A.2 Parasitic mode suppression

The parasitic modes described in the introduction may influence the perfor-mance of a CPW section in essentially two ways :

1. Leakage, which is the continuous conversion of power from the CPW-mode to a parasitic mode. When the phase velocities of the modes differ,the parasitic mode diverges from the axis of the CPW, so that a substan-tial fraction of the power is lost.

2. Conversion at discontinuities. Conversion to surface waves causes lossesand eventually unwanted coupling between otherwise isolated circuits.Conversion to parasitic modes of the CPW structure leads to a racingcondition where destructive and constructive interferences modify thefrequency response at the other end of the line.

Both phenomena may be quite harmful for the calibration process. Surface-waves radiated from a discontinuity or leaking from a section of line will travel

A-2

A.2 Parasitic mode suppression

on the SOI substrate until l they are reflected by an obstacle. The reflectedsignal may then interfere with the wanted signal. This interference will de-pend upon the surroundings of the measured structure, rendering the basic as-sumption of consistent error boxes inapplicable. In the presence of significantinterference from parasitic modes of the CPW structure, the TRL approachdescribed earlier breaks down : It is indeed based on the diagonal shape of the2×2 transmission matrix in the case of a waveguide propagating a single mode.

Jackson published a study of the mode conversion at discontinuities inconductor-backed CPW’s, [A.1]. The author showed that the CPW open struc-ture can cause very significant conversion losses : Up to 20% of the incidentpower converted to the parasitic micro-strip mode. The CPW short was shownto behave much better : Less than 0.4% conversion to the micro-strip mode.Jackson pointed out that these conversion losses could be significantly reducedby inserting a low-dielectric-constant material between the original substrateand the ground plane. Liu and Itoh, [A.2], showed that insertion of a low-dielectric constant spacer between the substrate and the ground plane caneven suppress leakage, if the thickness of the spacer is sufficient.

SOI Wafer

PTFE Spacer

Metal Ring

PTFE Material

Solder Pad

Figure A.2: Teflon spacer for the suppression of parasitic modes.

When measuring either passive or active devices on SOI, the DC potentialapplied to the wafer back-plane must be controlled. This potential not onlyinfluences the threshold voltage of MOSFET’s, but also the depth of the deple-tion region under the buried oxide. Insertion of a dielectric spacer in betweenthe SOI wafer and the supporting metal chuck must be somehow reconciledwith the necessity to set the back-plane potential. The solution adopted isshown in the figure. A 0.5 mm thick Duroid spacer is used, with a metal ringallowing to contact the bottom of the SOI wafer. The spacer material is PTFEwith a relative dielectric constant of 2.33.

A-3

Coplanar waveguides on SOI

A.3 Macroscopic model for CPW’s on SOI

The macroscopic model is based on the analogy between the waveguide the-ory outlined in a previous chapter and conventional transmission line theory.Brews, [A.3] proposed to define a distributed equivalent circuit for the waveg-uide using equations from transmission line theory :

Z ′σ = γ · Zc (A.1)

Y ′π = γ/Zc (A.2)

Marks, [A.4], derived the following explicit expressions of Z ′σ and Y ′π in termsof the modal fields directly from the Maxwell’s equations :

C ′π ,Im(Y ′π)

ω=

1∣∣Vc

∣∣2 [∫Sε∣∣−→et

∣∣2 dS − ∫Sµ∣∣hz

∣∣2 dS] (A.3)

L′σ ,Im(Z ′σ)

ω=

1∣∣Ic∣∣2[∫Sµ∣∣−→ht

∣∣2 dS − ∫Sε∣∣ez

∣∣2 dS] (A.4)

G ′π , Re(Y ′π) =ω∣∣Vc

∣∣2 [∫Sε∣∣−→et

∣∣2 dS +

∫Sµ∣∣hz

∣∣2 dS] (A.5)

R ′σ , Re(Z ′σ) =ω∣∣Ic∣∣2[∫Sµ∣∣−→ht

∣∣2 dS +

∫Sε∣∣ez

∣∣2 dS] (A.6)

where ε , ε+ε and µ , µ+µ. S is the waveguide cross-section, extending upto the point where all fields vanish. These expressions are fairly general : Theyapply both to open or closed structures, consisting of eventually lossy materials.Metal conductivity is not accounted for explicitly but instead absorbed in ε.

The parameters C ′π, L′σ, G ′π and R ′σ depend on the same normalisation thatdetermines the magnitude of the characteristic impedance Zc. Marks statesin [A.4] that, for instance, when Vc is chosen to be the voltage between twoactive conductors in a lossless TEM line, then C ′π and L′σ are the conventionalcapacitance and inductance per unit-length. Furthermore, certain combina-tions of these parameters, notably G ′π/ (ω C ′π), R ′σ/ (ω L′σ), (R ′σ C ′π), (R ′σ G ′π),(L′σ C ′π) and (L′σ G ′π) are normalisation independent. This latter feature is ofparticular importance, as it opens the possibility to extract physical parame-ters directly from adequate combinations of the distributed transmission lineparameters.

The formal definitions of C ′π , L′σ, G ′π and R ′σ in equations (A.3) to (A.6)do not imply that these parameters are independent of frequency. In the caseof SOI CPW’s all of the distributed line parameters vary substantially in theband from 40.0 MHz to 40.0 GHz. It is the purpose of the next subsections todevelop physically based equivalent circuit topologies which properly accountfor the frequency behaviour of Z ′σ and Y ′π .

A.3.1 Distributed shunt admittance

The field distribution of the fundamental CPW mode is quasi-TEM whichis known to be a particular case of the TM modes, [A.5]. This amounts to

A-4

A.3 Macroscopic model for CPW’s on SOI

say that the longitudinal magnetic field component hz is zero, so that theevaluation of Y ′π = G ′π + ω C ′π according to equations (A.3) and (A.5) reducesto the contribution of the quasi-static term — the −→et integral.

Si SiO2

C′subs

R′subs

C′box

C′air

Wcntr Wslt Wgnd

tfld

tmet

tbox

tsubs

Figure A.3: Cross-section of a SOI CPW structure showing electric field lines.

A glance at the electric field distribution in the SOI CPW structure shownin figure A.3.1 reveals that electric field lines can be split into three categories :

1. Field lines crossing the field oxide and penetrating into the air region ontop of the wafer.

2. Field lines contained exclusively in the oxide region enclosing the conduc-tors.

3. Field lines crossing the buried oxide and penetrating into the silicon sub-strate.

R′subs C′subs

C′box

C′air

Figure A.4: Equivalent circuit model for the distributed admittance of a CPWon SOI.

Neglecting the dielectric losses which may exist in the SiO2 layer, the con-tribution of the field lines in the oxide and in the air to the lineic admittancemay be modelled as a capacitor C′air . The contribution of the electric field lines

A-5

Coplanar waveguides on SOI

penetrating into the substrate is modelled as the series connection of a capac-itor C′box for the buried oxide layer with C′subs and R′subs for the underlyingsilicon.

107 108 109 1010 10110.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequency [Hz]

C ′π[fF/µm

]1.0

107 108 109 1010 10110

2

4

6

8

10

Frequency [GHz]

G ′π[µf/µm

]

Figure A.5: Comparison of the measured (dotted line) and modelled (contin-uous line) distributed admittance curves after parameter extraction on a SOICPW.

Values for the capacitances may be approximated using formulas availablefor the canonical CPW topology : C′0 is the capacitance of the CPW structurein the absence of any dielectric material. C′box is evaluated using the parallelplate approximation. For the evaluation of C′subs the thickness of the oxidelayers is set to zero in order to fall back to a standard CPW topology.

C′0 =C′CPW

(Wcntr , Wslt , Wgnd | tfld ≡ 0, tbox ≡ 0, tsubs ≡ 0

)(A.7)

C′air =C′CPW

(Wcntr , Wslt , Wgnd (tfld + tbox ), tmet | tsubs ≡ 0

)− 1/2 C′0

(A.8)

C′box =εSi02

tbox

Wcntr Wgnd

Wcntr +Wgnd(A.9)

C′subs =C′CPW

(Wcntr , Wslt , Wgnd , tsubs | tfld ≡ 0, tbox ≡ 0

)− 1/2 C′0

(A.10)

where C′CPW (·) is the functional corresponding to the evaluation of the dis-tributed capacitance of the canonical CPW — see figure A.1 (a). R′subs can bededuced from C′subs and the substrate resistivity using the following equation :

A-6

A.3 Macroscopic model for CPW’s on SOI

C′subs R′subs =

C′subs

G′subs

=εSi

ρsubs(A.11)

A.3.2 Distributed series impedance

Here too, the contributions of various regions to Z ′σ = R ′σ +ω L′σ are estimatedon the basis of equations (A.4) and (A.6). As indicated earlier, the CPW

mode is of the TM-type, so that contributions from both−→ht and ez must be

taken into account. For the distributed resistance the magnetic are totallynegligible (µ u 0) so that only contributions from conductive regions count —dielectric losses in the oxide are very small and will also be neglected. Theseconsiderations allow to write :

R ′σ =1∣∣Ic∣∣2[∫Smet

σ∣∣ez

∣∣2 dS +

∫Ssubs

σ∣∣ez

∣∣2 dS], R ′σ[Smet ]

+ R ′σ[Ssubs ]

(A.12)

where Smet is the metal cross-section and Ssubs is the substrate region. Thisequation reveals that the frequency evolution of R ′σ is determined by at leastby two independent phenomena : The skin effect in the metallisation and thedielectric transitions of the SOI structure. These two effects will also influenceL′σ, but the dependency is not as obvious :

L′σ =1∣∣Ic∣∣2[∫Smet

(µ∣∣−→ht

∣∣2 − ε ∣∣ez

∣∣2) dS +

∫Scmet

(µ∣∣−→ht

∣∣2 − ε ∣∣ez

∣∣2)dS], L′σ[Smet ]

+ L′σ[Scmet ]

(A.13)

where Scmet = S \ Smet .

The skin effect is related to the finite penetration of electric and magneticfields into metallic material at high frequencies. In the case of plane metallicconductors, an analytical treatment is feasible starting from Maxwell’s equa-tions, [A.5,A.6]. Ramo et al. derived in their book [A.6] an expression for theinternal impedance of a metal sheet of infinite extent :

zmet =1 +

σ δmetcotanh(

1 +

δmettmet) (A.14)

δmet =

√2

√ω µ σ

(A.15)

zmet is an impedance “per square” that must be divided by an effective width toobtain a value of the conductor impedance accounting for the current crowding

A-7

Coplanar waveguides on SOI

at the edges of the slots :

Z ′σ[Smet ]=

zmetWeff

(A.16)

Weff = 16(Wcntr + 2Wslt

)K(s)

(1− s2

)×2

s

[π + log(

4 πWslt

tmet

1− s

1 + s)]

+ 2[π + log(

4 π (Wcntr + 2Wslt )

tmet

1− s

1 + s)] (A.17)

where s is the normalised slot width : s ,Wslt/(Wcntr +2Wslt). The expressionfor the effective width was deduced from the current densities obtained byconformal mapping in the case of ground conductors of infinite extent, [A.7].At low frequencies equation A.14 can be approximated by a series expansionso that (A.16) simplifies to :

Z ′σ[Smet ]u

1 +

σ δmetWeff

×[ 1

(1 + ) tmet/δmet+

(1 + )2 tmet/δmet

3− O((tmet/δmet)

2)]

=1

tmet Weff σ+ ω

µ tmet

3Weff− ω

32 . . .

(A.18)

In the case of a 1.0µm thick sheet of aluminium this approximation is accurateup to 6.0 GHz within 5.0%. At this frequency the skin depth is on the order ofthe metal thickness. Above this frequency the internal metal resistance startsto increase, while the internal inductance decreases.

At the time of writing no simplified technique has been established to eval-uate Z ′σ[Scmet ]

accurately. The contribution of ez is the main difficulty. The−→ht

term corresponds indeed to a quasi-static evaluation of the distributed induc-tance, so that equation (A.13) allows to write :

Z ′σ[Scmet ]≤ L′CPW (A.19)

where L′CPW is the lineic inductance value obtained for the canonical CPWstructure, considering a loss-less silicon substrate and no skin effect.

Comparing the measured evolution of L′σ(ω) with the predictions for L′σ[Smet ](ω)

suggests that the skin effect in the metal is not solely responsible for the fre-quency evolution of L′σ. The skin effect model predicts a frequency of 6.0GHz for the onset of frequency variations, while the measured curves clearlyshow variations occurring before 1.0 GHz. These frequency values correspondapproximately to the dielectric transition frequencies of the substrate. Fur-thermore, the maximal predicted internal inductance value is almost one orderof magnitude too small to account for the measured changes in L′σ. Finally,comparing the frequency evolution of the measured resistance and inductance

A-8

A.3 Macroscopic model for CPW’s on SOI

0.4

0.45

0.5

0.55

L′σ[pH/µm

]0.6

107 108 109 1010 1011

Frequency [Hz]

2

3

4

5

6

7

R ′σmΩ/µm

107 108 109 1010 1011

Frequency [Hz]

Figure A.6: Comparison of the measured (dotted line) and modelled (contin-uous line) distributed impedance curves after parameter extraction on a SOICPW.

curves additional evidence of the substrate influence is obtained :

R ′σ(6 .0 GHz) − R ′σ[Smet ]

L′σ(6 .0 GHz) − L′σ[Smet ]− L′CPW

uσsubs

εSi(A.20)

where the “ · ” indicates estimations based on the skin effect model describedin the present section; The “ (6.0 GHz) ” subscripts indicate measured valuesat 6.0 GHz.

L′met1

L′met2

L′met3

R′met1

R′met2

R′met3

Figure A.7: Equivalent circuit model for the distributed impedance of a CPWon SOI.

Based on the insight gained from the preceding analysis, the empirical modelof figure A.3.2 is proposed. It allows at least to fit the measured data satisfac-torily. Considering the circuit response at high frequency and assuming thatthe variation of inductance is due solely to the skin effect, one easily finds thatL′met1 = Z ′σ[Scmet ]

.

A-9

Coplanar waveguides on SOI

A.4 Parameter extraction for the circuit mod-

els

The previous section introduced the equivalent circuit models for the dis-tributed immitances discussing physical aspects and proposing a method toestimate the parameters. The present section briefly describes the procedurewhich has been developed to extract circuit parameter values. It is an opti-misation procedure which adjusts the parameter values to ensure a close fitbetween the model response and the measured curves. The optimisation strat-egy proposed by Bandler et al, in [A.8] is used in combination with initialvalues obtained from the developments of section A.3. The main feature of theoptimisation strategy of Bandler et al. is that it is well behaved, avoiding tointroduce random errors on parameters with marginal influence. To differen-tiate model responses from measurements or estimated values from actual —eventually unknown — values, the former will be indicated with “ · ”.

A.4.1 Distributed shunt admittance circuit parameters

Initial values for the capacitances are from the expressions in section A.3.1.As the substrate resistivity is usually unknown a first estimate for the R′subs isobtained from :

R′subs

(0)= Re(Y ′π(ω))

for ω at the upper end of the band(A.21)

The circuit response is then fitted to the measured Y ′π curve by minimising thefollowing error criterion, where P is the parameter space and Ω is the set ofmeasured frequencies :

minP

∑ωk ∈Ω

∣∣Y ′π(P, ωk )− Y ′π(ωk )∣∣2 (A.22a)

P ≡ p = [C′air , C′box , C

′subs , R

′subs , ] ∈ R4 |

0.1 · p(0) ≤ p ≤ 10 · p(0)(A.22b)

Ω ≡ ωmin , . . . , ωmax (A.22c)

The result is shown in figure A.3.1.

A.4.2 Distributed shunt impedance circuit parameters

The procedure used here is slightly different. As no expressions are availableto obtain initial values for the circuit elements, except for L′met1 , a step-wiseprocedure is adopted. The optimisation framework is described by :

minP

∑ωk ∈Ω

∣∣Z ′σ(P, ωk )− Z ′σ(ωk )∣∣2 (A.23)

A-10

A.5 Conclusion

1. A simplifed circuit consisting solely of L′met1 and R′met1 is considered.Optimisation is performed at the highest measurement frequency :

P ≡ p = [L′met1 , R′met1 ] ∈ R2 | 0.1 · p(0) ≤ p ≤ 10 · p(0)

Ω ≡ ωmax

2. Elements L′met2 and R′met2 are added, and optimisation is performed inthe band starting at a corner frequency located just beyond the sharpdrop of the inductance curve, at the beginning of the flat region. Thevalues obtained for L′met1 and R′met1 are used as initial estimates forL′met2 and R′met2 .

P ≡ p = [L′met1 , L′met2 , R

′met1 , R

′met2 , ] ∈ R4 |

0.1 · p(0) ≤ p ≤ 10 · p(0)

Ω ≡ ωc, . . . , ωmax

3. Finally whole band is considered an all parameters are adjusted. Thevalues obtained for L′met2 and R′met2 are used as initial estimates forL′met3 and R′met3 .

P ≡ p = [L′met1 , L′met2 , L

′met3 , R

′met1 , R

′met2 , R

′met3 ] ∈ R6 |

0.1 · p(0) ≤ p ≤ 10 · p(0)

Ω ≡ ωmin , . . . , ωmax

The result is shown in figure A.3.2.

A.5 Conclusion

This appendix provided an in-depth treatment of coplanar waveguides on SOIsubstrates. A physical justification has been found for the frequency evolutionof the measured distributed immitance curves. A macroscopic model has beendeveloped in the form of equivalent circuits. Simple expressions have beenderived for all distributed admittance parameters, while an original analysishas been made indicating the dominant role of substrate parameters on thefrequency evolution of the distributed impedance. This should foster the de-velopment of expressions for the corresponding circuit parameters. Finally, asuccessful parameter extraction procedure has been presented, validating themodel topology.

The results of this appendix demonstrate the relevance of the waveguidecircuit topology from [A.4] in general, and the accuracy of the calibration pro-cedure developed in the present work.

References

[A.1] R. W. Jackson, “Mode conversion at discontinuities in finite-widthconductor-backed coplanar waveguide,” IEEE Trans. on MicrowaveTheory and Techniques, vol. 37, pp. 1582–1589, Oct. 1989.

A-11

Coplanar waveguides on SOI

[A.2] Y. Liu and T. Itoh, “Leakage phenomena in multilayered conductor-backed coplanar waveguides,” IEEE Microwave and Guided Waves Let-ters, vol. 3, pp. 426–427, Nov. 1993.

[A.3] J. R. Brews, “Transmission line models for lossy waveguide interconnec-tions on VLSI,” IEEE Trans. on Electron Devices, vol. 33, pp. 1356–1365, Oct. 1986.

[A.4] R. B. Marks and D. F. Williams, “A general waveguide circuit theory,”J. Res. of the Natl Inst. Stand. and Technol., vol. 97, pp. 533–562, Sep–Oct 1992.

[A.5] A. Vander Vorst and D. Vanhoenacker, Bases de l’ingenierie micro-onde.Bruxelles: De Boeck Universite, 1996.

[A.6] S. Ramo, J. R. Whinnery, and T. Van Duzer, Fields and Waves inCommunications Electronics. New York, London, Sidney: John Wiley& Sons, 1965.

[A.7] R. K. Hoffmann, Handbook of Microwave Integrated Circuits. Norwood,MA: Artech House, 1987.

[A.8] J. Bandler and Q.-J. Zhang, “An automatic decomposition approach tooptimization of large microwave systems,” IEEE Trans. on MicrowaveTheory and Techniques, vol. 35, pp. 1231–1239, Dec. 1987.

A-12

Appendix B

Optimiser-drivenparameter extraction

The parameter extraction problem is often formulated as an optimisation where

model parameters [p1, . . . , pn] are adjusted until the modelled responses Hi(xk)coincides with the measured samples Hi(xk). The xk being the sampling points.The distance between the modelled and measured responses is evaluated usingan appropriate norm :

1. The L1-norm is the sum of the absolute values of the error vectors com-ponents. It

L1

H(·) − H(·)

,∑i, k

∣∣∣Hi(xk)− Hi(xk)∣∣∣ (B.1)

2. The L2-norm is the typical Euclidean norm. It ensures a convergence inthe mean which is a desirable feature in the presence of “noise”.

L2

H(·)− H(·)

,∑i, k

∣∣∣Hi(xk)− Hi(xk)∣∣∣2 (B.2)

3. The Huber-norm, LHu, introduced by Bandler et al. in [B.1], is a com-promise between L1 and L2. It treats the components of the error vectoraccording to L1 above a certain threshold and according to L2 below.This ensures a certain immunity to catastrophic errors while maintainingan adequate behaviour in the presence of noise. The threshold must beadjusted in function of the “noise-level”.

B-1

Optimiser-driven parameter extraction

The formulation of the typical extraction problem is then :

minPE(P) (B.3a)

E , L2

H(P, ·)− H(P, ·)

(B.3b)

where E is the “error criterion” and P is the parameter space. In order to avoiddivergence to unrealistic parameter values, the parameter space is restricted toa range extending one decade above and below the initial value p(0). Unrealisticdivergence of parameters values appears either when the model is inappropriate,or, more often, when trying to adjust weakly influent parameters in the presenceof noise. Specifying bounds enhances the detection of these pathologic cases.

P ≡

p ,[p1, . . . , pn

]∈ Rn| 0.1 · p(0) ≤ p ≤ 10 · p(0)

(B.4)

In order to obtain meaningful results with an optimiser-based extractionscheme, it is important to suppress any redundancy amongst the optimisationparameters as well as to avoid adjusting weakly influent parameters — or atleast avoid to place confidence in the final values of such parameters. Through-out this chapter the optimisation strategy proposed by Bandler in [B.2] is used.It is based on the elaboration of a sensitivity dictionary which allows to iden-tify the most influent parameters and eventually to split the global optimisationinto subproblems when some responses are controlled by independent groups ofparameters. For each subproblem, the optimisation is performed by adjustingonly the most influent parameters. Once a local optimum is reached, these pa-rameters are kept constant and some of the remaining less influent parametersare chosen to be adjusted during the next optimisation run. This process iscontinued until all parameters have been adjusted, so that a fairly good ap-proximation to the global solution is attained. Then a final optimisation isperformed and all parameters are allowed to vary. The main advantages of thisoptimisation strategy are : that the optimisation is well-behaved, avoiding tointroduce random errors on parameters with marginal influence; that compu-tation time is reduced because the intermediate optimisation problems involveless variables.

After the completion of the optimisation process it is always interesting tobe able to estimate the uncertainties affecting the extracted values. During theoptimisation, the error criterion E rarely converges to 0, but rather to somefinite value R, the residual error. This residue proceeds from two types ofmeasurement errors :

1. Random fluctuations around the mean value of the curves. This type oferror produces a residue in the evaluation of the quadratic error criterionbut does not affect the extracted parameters values. This is a specificfeature of quadratic error norms.

2. Errors which introduce an offset in the mean value of the curves. Thistype produces a residue and tweaks the extracted parameters values.

The uncertainty margin UP for an extracted parameter P may be estimatedon the basis of the fraction of the total residue which corresponds to the second

B-2

REFERENCES

type of errors, RM :

UP ,∣∣∣∣∣P − PP

∣∣∣∣∣ =RM

SP(B.5)

where P stands for the exact value of the parameter while P is its estimate.SP is the sensitivity of the error norm E to a variation in parameter P :

SP ,∣∣∣∣E(P + ∆P )− E(P )

∆P/P

∣∣∣∣ (B.6)

However, only the global residue R is available, not its fraction RM , so that itis only possible to specify an upper bound on the uncertainty for the extractedparameters values :

UP ≤R

SP(B.7)

References

[B.1] J. W. Bandler, S. H. Chen, R. M. Biernacki, L. Gao, K. Madsen, andH. Yu, “Huber optimisation of circuits : A robust approach,” IEEETrans. on Microwave Theory and Techniques, vol. 41, pp. 2279–2287,Dec. 1993.

[B.2] J. Bandler and Q.-J. Zhang, “An automatic decomposition approach tooptimization of large microwave systems,” IEEE Trans. on MicrowaveTheory and Techniques, vol. 35, pp. 1231–1239, Dec. 1987.

B-3