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11

Physical IP Solutions

Bryan Lawrence

Solutions Marketing

222

Library platformsStandard cellsEmbedded memoryI/O functionality

Physical IP Product Focus

High-speed interfacesSerial PHYs DDR

MemoryMemory

MemoryMemory

MemoryMemory

Standard CellsStandard Cells

I/O CellsI/O Cells

Pervasive SoC IP

DDRDDRSerial PHYsSerial PHYs

333

ARM Artisan® Physical IP Platforms

Analog/Mixed SignalPLLs, DLLs

Specialt y I/Os

GPIOInline/Staggered

ROMVia or Diffusion

1/2-PortRegister File

Single/Dual PortSRAM

AdvantageStandard Cell

Analog/Mixed SignalPLL, VREG, OSC,

Specialt y I/Os


ROMVia or Diffusion



MetroStandard Cell

DDR/DDR2/GDDR3

XAUI

Serial-ATA

PCI-Express


Specialt y I/Os


ROMVia or Diffusion



SAGE-X™Standard Cell

Mainst ream Pl atform

Power ManagementKit

Power ManagementKit

Perfo rmance Platfo rm Den sity Optimiz ed Platfo rm High-Speed PHY s

444

Library Platforms Power Performance Area

area

~100%

power

1/2

area

80%

power

1/5

performance

System requirement

area

power

performance

Systemrequirement

performance

System requirement

555

Advantage Overview

Performance-optimized physical IP products for nanometer designs

Memories provide 40% speed improvement and 50% power improvement over ‘Classic’architectures

Standard cells provide up to 25% speed improvement over ‘Classic’ architecture

Lower die costsFlex-Repair™ redundancy for yield

DFM for improved yield

Ring-less power routing to reduce area

Targeted at high-performance designReplaces ‘Classic’ architecture at 90nm and below

Available for 130nm, 90nm and 65nm processes


Specialt y I/Os


ROMVia or Diffusion



AdvantageStandard Cell

Power ManagementKit

Perfo rmance Platfo rm

666

Advantage Platform Standard Cell Libraries

15129/10# Tracks high

Highest PerformanceHigh PerformanceSpeed and

density optimized

Target designs

M1 onlyM1 onlyM1 onlyMetal usage

separateseparateseparateWell taps

1.51.251Area

1.41.251Power

1.41.251Speed

Advantage- CE Advantage-HSAdvantage

Wide selection of standard cell libraries enables optimal design performance…Use different libraries in different blocks

777

Metro Overview

Density and power-optimized physical IP productsEnables designs with up to 80% lower power than traditional products

Using voltage islands and dynamic voltage/frequency scaling

Dynamic and static power management

Enables multi-voltage SoC designs and complements ARM Intelligent Energy Manager (IEM)

Compatible with latest releases of EDA vendor ‘power-optimized’ flows

Increased design productivity

Targets battery-powered applicationsArea efficient

Moderate performance

Improved yieldAvailable for 180nm, 130nm,

90nm and 65nm processes

Analog/Mixed SignalPLL, VREG, OSC,

Specialt y I/Os


ROMVia or Diffusion



MetroStandard Cell

Power ManagementKit

Den sity Optimiz ed Platfo rm

888

Metro Standard Cell Features & BenefitsDynamic power reduction techniques

Clock-gating cells enable clock-based power managementCareful attention to P:N ratio and stage ratios to limit switching currentsDistribution of drive strengths minimizes over-designShorter cell height minimizes power at moderate speed while providing high density

Leakage Power reduction techniquesCell GDS supports mix and match of different Vt in adjacent cellsWell contacts outside cell enable leakage reduction through wellbiasingTiming views (.l ib) with State-dependent leakage power for best estimation of power dissipation.

999

1 R Port128bits - 2MbitsROM

1 R Port, 1 W Port16bits - 16KbitsTwo-Port Register File

1 R/W Port64bits - 32KbitsSingle-Port Register File

2 R/W Ports128bits - 256KbitsDual-Port SRAM

1 R/W Port256bits - 512KbitsSingle-Port SRAM

PortsRangeGenerator

Memory

101010

Memory

Design-for-Manufacturability (DFM) compliant design and characterization techniques

Smaller die area Lower die cost

ArtiGrid ‘Ov er-the-cell’ power routing

Leakage power controlPower down modes:standby, retention and shutdown

Dynamic power controlLow-v oltage functionality and characterization

Shorter development timeLower die cost

Integrated BIST Muxes

Soft Error Repair RTL

Extra timing margin adjustment

Improv ed yield Lower die costFlex-Repair redundancy

BenefitFeature

111111

Available in both Metro and Advantage platformsVoltage level shifter and isolation cells

Up and down shifting with optional enable signal

MT-CMOS power gates Power control of voltage islandsvia switchable voltage railsusing header- (shown) orfooter-switch cells

Retention flip-flops Maintain FF state after power down for leakage reduction

ARM Power Management Kit

VDD2

VDD1

VDD1

VDD1

VDD2

VDD2

Global VDDGlobal VSS

Note: P ictur e shows a conc eptual implementation

Enables implementation of advanced power management system architectures

121212

Power Optimized Designs Enabled

Power gating and power down modesin memories

Retention fl ip flops

Power gating of standard cells

Multi VT support in standard cells

Leakage Power Control

Extended operating range of standardcells and memories DVFS support

Voltage level shifters

Clock gating standard cells

Dynamic Power Control

AdvantageMetro

131313

I/O Products Complete the Platform

General Purpose I/O

Specialty I/O

ProcessGeometry250 nm 180nm 130 nm 90 nm 65 nm

Sp

eed

Input only I/O; 2 – 24 mA drive Multiple slew ratesOutput only LVTTL, Schmitt trigger inputs Oscil lators, Analog pads

SSTL I, II HSTL I, II LVDS

SSTL_18 USB 1.1

141414

Extensive EDA SupportStandard EDA Packages

Comprehensive coverage

Consistent deliverables

Verilog and VHDL/Vital

Synthesis/timing/power

Place-and-route abstracts

Schematic symbols

GDSII files and LVS netlists

EDAPlusExtended support

Signal integrityNoise

PowerDFT

Downloadable From the Web

151515

ARM Supports Leading Manufacturers

JazzJazz TowerTower SMICHHNECHeJian

SMICHHNECHeJian

HynixDongbuAnam

HynixDongbuAnam

Chartered1st Silicon

Silterra

Chartered1st Silicon

Silterra

TSMCUMCVanguard

TSMCUMCVanguard

IDMIDMFoundryFoundry

InfineonInfineonSTSTIBMIBMAtmel

AMDLSI LogicNational

AtmelAMD

LSI LogicNational

NECSanyoSeiko EpsonSharpSony

NECSanyoSeiko EpsonSharpSony

161616

ARM Physical IPUser Community

World’s LeadingIC Manufacturers

2,000+ Companies,Estimated 10,000

Design Teams

Connecting Manufacturers with Designers

171717

ARM Access Library ProgramInnovative business model enables easy access to products for customers using “pure-play” foundries

Access library program

Foundry licenses platform products from ARM

Platform products developed by ARM and distributed on ARM website

License agreement between ARM and design customer

License fees paid by foundry

Royalties paid by foundry

181818

Access Library Program

FoundryFoundry

LicenseLicense$$

Product Product LicenseLicense

Fabless ICFabless ICCompaniesCompanies IDMsIDMs PartnersPartners

IP ProductsIP ProductsOptional SupportOptional Support

FoundryFoundry

SOC DesignSOC DesignTeamsTeams

Fabless ICFabless ICCompaniesCompanies

IDMsIDMs PartnersPartners

FoundryFoundry

SOC DesignSOC Design

TeamsTeams

Completed DesignsCompleted DesignsProduction OrdersProduction Orders

Fabless ICFabless ICCompaniesCompanies

IDMsIDMs PartnersPartners

Wafer ProductionWafer Production

FoundryFoundry

RoyaltyRoyalty$$

SOC DesignSOC Design

TeamsTeams

191919

Access Program Product Availability Choices

Silterra

HeJian

HHNEC

MagnaChip

Vanguard

250nm 180-150nm

2

130-110nm

Dongbu

1st Silicon

Tower

SMIC

UMC

33TSMC

11IBM

11Chartered

65nm90-80nm

1 Metro for 9FLP/10LP, Advantage for 9SF/10SF(HS); products for 10LP/10SF under development

2 Metro for L130e, Classic for other 130, Advantage for L90SP

3 Advantage for CLN 90G/G-OD/GT available; CLN65G under development

202020

Velocity High-Speed Interfaces


High-speed interfacesSerial PHYs

DDR

MemoryMemory

MemoryMemory

MemoryMemory


I/O CellsI/O Cells

Pervasive SoC IP

DDRDDRSerial PHYsSerial PHYsSerial PHYs

212121

Graphics

Router/Switch

CPU

Hard DiskDriv e

SystemController

I/OController Local I/O

MemoryController

MemorySubsystem

Gb Ethernet

Add-inCards

Serdes Backplane

PCIe

SATA

DDR

PCIe

XAUI


222222

Serial Link: New System Economics

0.18um115K/mm**2

106 I/Os @ 40u pitch

Active Area

Unused AreaI/O Area

• Smaller die size

• Smaller package size

• Fewer package pins

• Less power

• Scalable bandwidth

Taking the Path to Higher Performance and Lower Cost

0.13um230K/mm**2


Serial I/OSerial I/O

0.13um230K/mm**2


Parallel I/OParallel I/O

High-Speed Serial Interfaces Offer Many Advantages

232323

Engineered to save you time and moneySuperior jitter performance, small size and low power

Scalable, advanced platform architecture to meet future higher bandwidth requirements

Extensive programmable features offer integration flexibility

Built-in test for improved manufacturability

In Development

65nm Series

PCI Express

XAUI/1-3.2Gbps Backplane

1-6.4Gbps Backplane

Serial ATA

DDR 1/2

GDDR3

90nm Series130nm Series


242424

ESD

SerDes Core

PCS Layer

TX/RX Lane

Small Size and Low Power

Low-power features

< 65mW/lane average

Most of the circuitry, including driver, run off 1.0V/1.2V

Extensive power down controls for precise control

< 250µm

ApplicationDependent

< 600µm

Smallest size in the industry< 0.20mm2 per lane

Area includes ESD, BIST with pattern generators and receivers in each lane

252525

Broad Lane Configuration Support

16 Lane PHY16 Lane PHY

8 Lane PHY8 Lane PHY 4 Lane PHY4 Lane PHY 2 Lane PHY2 Lane PHY

1 Lane PHY1 Lane PHYFlexible configurations ready for instantiation

Standard configurations of 1, 2, 4, 8 and 16 lanes

Standard bump pitches of 175µm, 200µm, 225µm

262626

Extensive Manufacturing Test Support

-

FIFOFIFO

RX

FromPackage

ToPackage

AC

RC

LK

Loo

pbac

k

Par

alle

l Lo

opb

ack

Ser

ial

Loop

bac

k

Lin

e Lo

opb

ack

JTAG

TXSerializer

RXCDR

RX

TX

RXDe-Serializer

Serial Control Register (SCR)

Scan built in to all digital

JTAG support DC and AC

Analog test bus

High-speed analog BIST

CDR/Phase Interpolator test

ARM has designed a comprehensive built in self test capability that enables a standard tester to be used in production

272727

Designed for Easy ImplementationExcellent noise immunity and signal integrity

Fully differential circuitry in transmitter, receiver, PLL

On-chip regulator for VCO power supply minimizes effects of power supply noise

Built-in “seawall” isolation to protect macro from substrate noise

Few external components requiredOn-chip AC coupling capacitors, only 1 external resistor required

Comprehensive documentation availableUser guide, integration guide, testing guide

Test plan and characterization report

282828

Velocity High-Speed Interfaces Proven In Silicon

Superior jitter performance

Translates into an extremely resilient design

Will deliver extremely low bit error rates

Extra design margin

Cheaper package, connectors, PCBs

Extremely low jitter2.5Gbps

3.125Gbps

6.25Gbps

292929

Flexible Velocity PHY Test and Demo Board

All ARM Velocity PHYS are silicon proven

Boards available for

evaluation on a loan basis

303030



High-speed interfacesSerial PHYs DDR

MemoryMemory

MemoryMemory

MemoryMemory


I/O CellsI/O Cells

Pervasive SoC IP

Serial PHYsSerial PHYsDDRDDRDDR

313131

Flexible DDR SolutionFlexible implementation to optimize solution area, power, performance

Switchable architecture allows DDRI, DDRII, GDDR3

Up to 1.8Gb/s(GDDR3) data throughput

Backwards compatible with DDR (2.5V I/O drive) using lower drive strengths

Contains dynamic calibrator for on-die termination and pull-up/pull-down driver network for PVT variations

Slav eDLL

Slav eDLL

Master – Delay Locked Loop (DLL)

Phase Locked Loop (PLL)

I/O Pads

Off Chip Interface IO pads repeat 8 times

I/O Pads

323232

I/O Placement Flexibility

Go around the chip corner

Match supply / decap pad frequency to actual needs. (varies widely with package type)

Power group

I/O group

333333

DDR Solutions for 130nm and 90nm

ARM PL340(also support sMobile-DDR)

DDR1/2

DDR1/2

GDDR31800Mbs DLL

800Mbs DLL

533MHz PLL

800MHz PLL

800Mbs DLL

533MHz PLL

Controller Analog I/Os

Soft IP Hard IP

DDR II1.8V

GDDR III1.8V

DDR I2.5V

Up To 800Mb/s

Up To 1.6Gb/s

SDRAM

SDRAM/RLDRAM

SDRAM/RLDRAM

Up To 400Mb/s

Standard/App

ARM PL341(Q2, 2006)

3rd Party

343434

SummaryPhysical IP is a key part of the ARM product portfolio

Optimized physical IP enables new benefits:Unique power, performance and area solutions

Faster time to market through use ofIP that works together easily

Manufacturing flexibility

Best commercial terms for SoC production

Leading foundry and EDA support

Low risk solutionsSilicon and system validated

Extensive offering, capabilities and experienceSingle source for processors, high-speed interfaces, memory interfaces, specialty I/Os, analog, standard cells, standard I/Os, and memories

R&D team, support, silicon, lab

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