PIC Processor DesignPIC Processor DesignCPE 428/528CPE 428/528April 29, 2002April 29, 2002Dr. MilenkovicDr. Milenkovic

Presented by:

David Fatzer

Le Pitts

William Cruger

Donn Hall

IntroductionIntroduction

Project Description– Build a Soft Core for a PIC18 Series

MicrocontrollerMotivation

– Desire to Gain Further Understanding of Microprocessor Architecture

– Apply VHDL Techniques to a Real-World Situation

PlatformPlatform

FPGA – Spartan II– 600 Complex Logic Blocks (20x30)– 100,000 Gates– 10 Configurable 4K bit block RAMs– Dedicated carry logic for high-speed

arithmetic

Spartan II Demo BoardSpartan II Demo Board

2-Digit LCDRS-232 PortUser LED’sUser Switches2.5 and 3.3 Volt RegulatorsJTAG PortOscillator, 30MHz – 50MHz

Demo Board ModificationsDemo Board Modifications

3.6864 MHz OscillatorLCD Module Display 4 Lines x 20

Characters5V Power Source for LCD

Development ToolsDevelopment Tools

Model Technology – ModelSim– VHDL Composition– Pre-Synthesis Testing

Xilinx ISE WebPack– VHDL Synthesis– VHDL Implementation

MicroChip MPLAB Assembler– ROM test code

PIC DescriptionPIC Description

Microcontrol Unit16-bit Wide Instruction Width8-bit Wide Data BusTwo-Stage PipelineSingle Cycle Execution versus

Microchip’s Four Cycle Execution

PIC ComponentsPIC Components

ROMRegister FileData Processing UnitInstruction Fetch UnitInstruction Decode UnitReset ControllerInput/Output Latches

ROMROM

Provides Storage– OP-Codes– Data Constants– Strings for Test and Application Code

Includes 256 x 16-bit WordsUtilizes On-Chip Block RAM

Register FileRegister File

Provides the Following– Storage and Decoding for One Bank of a

128 8-bit General Purpose Register– Decoding for Special Function Registers– Five Condition Code Registers

Utilizes 4096-bit on Chip Block RAM

Data Processing Unit (DPU)Data Processing Unit (DPU)

Handles all Data Processing FunctionsComponents

– Arithmetic Logic Unit (ALU)– Multiplier– Rotate Unit (RU)– Bit Operation Unit (BOU)– Working Register (WREG/Accumulator)

Data Processing Unit (DPU)Data Processing Unit (DPU)

Register File Rotator

UnitMultiplier

MuxA MuxB

ALU

Bit Unit

WREG

Literal Bus

FileWriteBus

FileReadBus

WRegBus

DPU – Arithmetic Logic UnitDPU – Arithmetic Logic Unit

Two 8-bit Inputs One 8-bit Output Four Operations - AND, OR, XOR, ADD Pre-Conditioners

– PASS – Do Nothing to the Input– INVERT – Invert the Input– Force0 – Force the Input to all Zeroes– Force1 – Force the Input to all Ones

Generates Condition Codes

DPU – Arithmetic Logic Unit DPU – Arithmetic Logic Unit

InputA

AND/OR/XOR/ADD

Pass/Invert/Force1/Force0

Pass/Invert/Force1/Force0

Pass/Invert/Force0/Force1

ConditionCode

Generator

InputB

LatchedCarryIn

ALUout

ConditionCodes

CarryOut

8 8

8 8

8

DPU – Arithmetic Logic UnitDPU – Arithmetic Logic Unit

ALU Condition CodesCondition Code Implementation

Negative 1 when AluResult(7) = 1

Zero 1 when AluResult(7..0) = all 0s

Carry 1 when AluCarry(7) = 1

Overflow 1 when AluCarry(7) != AluCarry(6)

DigitCarry Not yet implemented

DPU – MultiplierDPU – Multiplier

Single Cycle Using Combinatorial Array Multiplier

Two 8-bit Unsigned InputsOne 16-bit Unsigned Output Stored in

Two 8-bit Special Function Registers

DPU – Rotate UnitDPU – Rotate Unit

Performs Single Position Rotate and Nibble Swapping

Combinatorial Implementation

DPU – Rotate UnitDPU – Rotate Unit

Rotate Unit OperationsRotateUnitFunctionCode Effect on Stack Pointer

RLCF Rotate Left through Carry

RLNCF Rotate Left

RRCF Rotate Right through Carry

RRNCF Rotate Right

SWAP Swap Nibbles

DPU – Bit Operation UnitDPU – Bit Operation Unit Provides Mask for Bit-Oriented Operations Bit Operation Decoding

Instruction Word Bits[11..9] Bit Operation Unit Output Bits[7..0]

000 00000001

001 00000010

010 00000100

011 00001000

100 00010000

101 00100000

110 01000000

111 10000000

DPU – Working RegisterDPU – Working Register

Provides a Temporary Storage Register That Serves as an Accumulator

For All Data Processing instructions, Bit 9 Determines whether the Result of the Operation is Stored in Working Register or the Register File

Instruction Fetch Unit (IFU)Instruction Fetch Unit (IFU)

Updates Program CounterManages Hardware Return StackUpdates Instruction RegisterManages Table Pointer

IFU – Block DiagramIFU – Block Diagram

TablePointer

OperationInstructionRegister

ProgramAddress

ROM

TablePointer

Mux

PCOperation

PC

Stack

ProgramData

CurrentInstruction

16

16

21 21

NextInstruction

21

IFU – Program CounterIFU – Program Counter

21-bits (2MB Address Space)Asynchronous ResetUpdated on Rising Edge of ClockProgramCounterOpcode Determines

Function

IFU – Program CounterIFU – Program Counter

Program Counter OpcodesProgramCounterOpcode Effect on PC

NextInstruction Increment to next address (+1)

BranchRelativeOffset8 Add 8-bit signed offset (-127 to +128)

BranchRelativeOffset11 Add 11-bit signed offset (-1024 to +1023)

BranchAbsolute Force new 21-bit value (GOTO)

RestoreFromTopOfStack Use top of return stack value (RETURN)

DontFetch Do not change (+0)

InterruptHighPriority Force to high priority interrupt vector (address 8)

InterruptLowPriority Force to low priority interrupt vector (address 18)

IFU – Return StackIFU – Return Stack

21-bit Wide by 16 DeepStores Return AddressesImplemented Using Block RAM

IFU – Return StackIFU – Return Stack

Stack Pointer Operations

StackOpcode Effect on Stack Pointer

StackNOP Do not change (+0)

StackPUSH Add 1 then store (pre-increment)

StackPOP Retreive then subtract 1 (post-decrement)

IFU – Instruction RegisterIFU – Instruction Register

Latches Instructions from Program Data Bus

Two-Stage Pipeline– Fetch Next Instruction– Decode & Execute Current Instruction

IFU – Instruction RegisterIFU – Instruction Register

Instruction Register Operations

InstructionRegisterOpcode Effect on Instruction Register

LatchNextInstruction Latch new instruction

ForceNOP Force instruction register to all 0’s (NOP)

IFU – Table Pointer InstructionIFU – Table Pointer Instruction

Facilitates Movement of Data to and from the ROM

21-bits Wide to Address 2MB of ROMTable Latch Register

– Bridge for Program and Data Buses

IFU – Table Pointer InstructionIFU – Table Pointer Instruction

Table Address AssignmentsInstructionRegister(1:0)

Operation onTable Pointer

Table PointerNext Value

Table Address

00 No change Table Pointer Table Pointer

01 Post-Increment Table Pointer + 1 Table Pointer

10 Post-Decrement Table Pointer - 1 Table Pointer

11 Pre-Increment Table Pointer + 1 Table PointerNext Value

IFU – Table Pointer InstructionIFU – Table Pointer Instruction

Table Function Op-Codes

TableFunctionOpCode Operation on Table Latch (TABLAT)

TableFunctionNOP No change

TableFunctionRead Contents of TableAddress are written to TABLAT

TableFunctionWrite Contents of TABLAT written to ROM at TableAddress

IFU – Table Pointer InstructionIFU – Table Pointer Instruction

Key Signals– Program Address

Address Bus to ROM Normally Follows Program Counter Follows Table Address For

Table Pointer Instructions

– Program Data Data Bus From the ROM High-Impedance Except on TableFunctionWrite

– TableFunctionWrite Used to Program Flash

Instruction Decoder - IDInstruction Decoder - ID

Three Distinct Stages of Design– Instruction Disassembler

Identifies Instruction from Opcode

– Define Global Decode Signals– Assign Global Decode Signals

Must Include all Global Signals in Each Instruction to Avoid Latches

ID – Instruction DisassemblerID – Instruction DisassemblerInstruction Decoder Grouping

Group #InstructionBits(15..12)

Assembly Instruction

0000 NOP, MOVLB, RESET, RETFIE, RETURN, CLRWDT, DAW, POP, PUSH, SLEEP, TBLRD, TBLWT, DECF, SUBLW, IORLW, XORLW, ANDLW, RETLW, MULLW, MOVLW, ADDLW

0001 IORWF, ANDWF, XORWF, COMF

0010 ADDWF, ADDWFC, DECFSZ, INCF

0011 INCFSZ, RLCF, RRCF, SWAPF

0100 DCFSNZ, INFSNZ, RLNCF, RRNCF

0101 SUBFWB, SUBFW, SUBWFB, MOVF

0110 CPFSEG, CPFSGT, CPFSLT, CLRF,SETF, MOVWF, NEGF, TSTFSZ

0111 BTG

1000 BSF

1001 BCF

1010 BTFSS

1011 BTFSC

1100 MOVFF

1101 BRA, RCALL

1110 BC, BN, BNC, BNN, BNOV, BNC, BOV, BZ, GOTO, CALL, LFSR

1111 NOP (Second half of two-word instruction)

ID – Global Decode SignalsID – Global Decode SignalsSignal Name Signal Function

MuxASelect Selects either register file or literal value for ALU input A

MuxBSelect Selects either W-Register or Bit-Op value for ALU input B

RotateUnitEnable Enables Rotate Unit

RotateUnitFunctionCode Selects RU function (Rotate Left, Right, with/without carry)

ALUEnable Enables ALU

ALUFunctionCode ALU function code (AND, OR, XOR ADD)

ALUBusACondCode ALU input a conditioner (Pass, Invert, Force0s, Force1s)

ALUBusBCondCode ALU input B conditioner (Pass, Invert, Force0s, Force1s)

ALUCarryCondCode ALU carry input conditioner (Pass, Invert, Force0, Force1)

BitOpEnable Enables Bit-Op unit

BitOpPosition Selects Bit-OP position ( 1,2,4,8,16,32,64,128 )

UpdateConditionCodes Set to 1 to enable change in corresponding condition code

WRegWriteEnable Enables writes from WriteBus to WREG on next rising edge

FileWriteEnable Enables writes from WriteBus to Register File on next rising edge

ProgramCounterOpCode Tells how to prepare Program Counter for next cycle

InstructionRegisterOpcode Tells how to prepare Instruction Register for next cycle

StackOpCode Stack function code. (Push, Pop, Nop)

MultiplierEnable Enables single-cycle combinatorial multiplier

ClearWatchdogTimer Set to 1 by CLRWDT instruction to clear watchdog timer

SoftwareReset Set by RESET instruction to reset unit

BSRWriteEnable Set to enable updates to Bank Select Register

DAWEnable Enables Decimal Adjust Accumulator Unit

TableFunctionOpCode Table-pointer function code. (Read, Write, NOP)

SleepMode Set by SLEEP instruction to freeze clock until next external reset

Reset Controller - RCReset Controller - RC

Provides Global Reset Signal to PICReset Sources

– External Reset– Software Reset– Stack Error– Watchdog Timeout

Watchdog Timer Module

RC - Watchdog Timer ModuleRC - Watchdog Timer Module

17-Stage Ripple Counter36ms Timeout Based On 3.6864 MHzAsynchronous Clear

– Reset– Clear from CLRWDT Instruction

Input/Output LatchesInput/Output Latches

Provides Three 8-bit Bi-Directional Ports for Parallel Communications

Two of the Three Ports are for Communication with the LCD Module

Implementation ResultsImplementation Results

Implementation ResultsImplementation Results

Device Utilization - 74%Clock Cycle – 21.125MHz

– Multiplier Determines Critical Datapath

Design ProcessDesign ProcessAssembly Program

Assembler

Converter (.HEX to ASCII)

Load ROM (Copy/Paste)ModelSim Simulation/Verification

VHDL Model

Synthesis

Future ConsiderationFuture Consideration

Core for Future System-On-Chip Designs

Further Exhaustive TestingExternal Flash Memory ImplementationHigh-Level Language Applications ASIC Synthesis

Questions?Questions?