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PIC18 MICROCONTROLLER{ I }{ Interrupts}Mohamad Fauzi Zakaria

http://fkee.uthm.edu.my/mfauzi

Interrupts vs Polling2

Interrupts vs. Polling

Interrupt method: The microcontroller stops whatever it is doing upon receiving an interrupt signal and serves the device. The upon receiving an interrupt signal and serves the device. The program associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler. ( ) p

Polling method: The microcontroller continuously monitors the status of a given device; when the status condition is met it status of a given device; when the status condition is met, it performs the service.

The advantage of interrupts: microcontroller can serve many devices which each device can get the attention based on the priority. Interrupts are used to avoid tying down the microcontroller.

The polling method cannot assign priority because it checks all The polling method cannot assign priority because it checks all devices in a round-robin fashion.

I t t S i R ti3

Interrupt Service Routine

For every interrupt, there must be an interrupt service routine (ISR), or i t t h dl interrupt handler.

The microcontroller gets the address of ISR form interrupt vector table. g p

In the PlC18, there are only two locations for the interrupt vector table, locations 0008h (High Priority Interrupt) and 0018h (Low Priority locations 0008h (High Priority Interrupt) and 0018h (Low Priority Interrupt).

Sources of Interrupts (most widely used)

Timers (0 – 3) PORTB-Change Interrupt( ) g p

External INT0 (RB0), INT1 (RB1), and INT2 (RB2)

Two interrupts of Serial Comm. (USART)

ADC CCP

I t t R i t4

Interrupt Registers

There are ten registers which are used to control interrupt operation. These registers are:

INTCON, INTCON2, and INTCON3: INTERRUPT CONTROL , ,REGISTER

PIR1 and PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG)PIR1 and PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER

PIE1 and PIE2: PERIPHERAL INTERRUPT ENABLE REGISTERPIE1 and PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER

IPR1 and IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER RCON: RESET CONTROL REGISTERRCON: RESET CONTROL REGISTER

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Enabling and disabling an interrupt16

Enabling and disabling an interrupt

Upon reset, all interrupts are disabled (masked)

Th i t t t b bl d ( k d) b ft i d f th The interrupts must be enabled (unmasked) by software in order for the microcontroller to respond to them. INTCON Register

PICI8 interrupt programming in C17

PICI8 interrupt programming in C

C18 does not place an ISR at the interrupt #pragma code high_vector =0x0008 // High-priority interrupt addrISR at the interrupt vector table automatically.

void high_vector(void) {

_asm

Use Assembly language instr ction GOTO at the

GOTO my_isr_endasm

} instruction GOTO at the interrupt vector to transfer control to the

}#pragma code // End of code

#pragma interrupt my isr //interrupt is reserved keywordISR.

p g p y_ p yvoid my_isr (void) //used for high-priority interrupt{

//C18 places RETFIE here automatically due to//C18 places RETFIE here automatically due to//interrupt keyword

}

P i Ti I t t18

Programming Timer Interrupts

Interrupt Flag Bit Register Enable Bit Register

Timer0 TMR0IF INTCON TMR0IE INTCONTimer0 TMR0IF INTCON TMR0IE INTCON

Timer1 TMR1IF PIR1 TMR1IE PIE1

Timer2 TMR2IF PIR1 TMR2IE PIE1Timer2 TMR2IF PIR1 TMR2IE PIE1

Timer3 TMR3IF PIR3 TMR3IE PIE2

E t l H d I t t19

External Hardware Interrupts

Interrupt Flag Bit Register Enable Bit Register

INT0 (RB0) INT0IF INTCON INT0IE INTCONINT0 (RB0) INT0IF INTCON INT0IE INTCON

INT1 (RB1) INT1IF INTCON3 INT1IE INTCON3

INT2 (RB2) INT2IF INTCON3 INT2IE INTCON3INT2 (RB2) INT2IF INTCON3 INT2IE INTCON3

Negative edge-triggered interrupts20

Negative edge-triggered interrupts

Upon power-on reset, INT0, INT1, and INT2 are in positive (rising) edge-triggered interrupts triggered interrupts.

To make any of them a negative (falling) edge-triggered interrupt, we must program the INTEDGx (where x can be 0 1 or 2) in INTCON2 register program the INTEDGx (where x can be 0, 1, or 2) in INTCON2 register.

PORTB-Change Interrupt21

PORTB-Change Interrupt

The PORTB (RB4 -RB7) can cause an interrupt when any cause an interrupt when any changes are detected on any one of them.

Widely used in KEYPAD InterfacingInterfacing

C i22

Comparison

INT0 INT2 PORTB ChINT0 – INT2 PORTB-Change

Has independent pin Uses all four pins and considered as a single interrupt pinsingle interrupt pin.

Has its own interrupt flag A single flag for the PORTB-Change interruptinterrupt

Each interrupt pins can be configured to negative or positive edge

All pins could cause an interrupt if occur status changing from H-L or L-H. g p g g g

Interrupt Priority23

Interrupt Priority

Upon power-on reset, all interrupts are automatically designated as high priority and will go to address 00008H. This is done to make the PlC18 compatible with the earlier generation of PlC microcontrollers such as PlC16xxx. We can make the PlC18 a two level priority system by way of programming the We can make the PlC18 a two-level priority system by way of programming the IPEN (interrupt priority enable) bit in the RCON register.

Interrupt Priority Selection24

Interrupt Priority Selection

To make the PlC18 a two-level priority system, we must first set the IPEN bit to HIGH. Then, we can assign a low priority to any of the interrupts by programming the bits called IP (interrupt priority).

Register in IPR1Register in IPR1

Interrupt Priority Selection25

Interrupt Priority Selection

All the PlC18 interrupts can be assigned a low or high priority level, except the external hardware interrupt of INTO. To set the priority, we have to make IPEN =1.Then, set two bits of GIEH (also referred as GIE) and GIEL in INTCON:

GIEH 1 Th GIEH bit i th GIE hi h d i i tiGIEH = 1. The GIEH bit is the same as GIE which used in previous section.GIEL = 1. This will enable all the interrupts whose IP = 0 (low priority).

Low and High – priority Interrupt

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programming in C

Interrupt ROM Location C18 keywordInterrupt ROM Location C18 keyword

High-priority 0x0008 (Default) interrupt

Low priority 0x0018 (Selected with IP bit) interruptlowLow-priority 0x0018 (Selected with IP bit) interruptlow

Example:

//used for high-priority#pragma interrupt test1

//used for low-priority#pragma interruptlow test2

Example:

#pragma interrupt test1void test1 (void){}

#pragma interruptlow test2void test2 (void){}} }

3 Condition for Interrupt Inside an Interrupt27

3 Condition for Interrupt Inside an Interrupt

1. When a high-priority interrupt is vectored into address 0x0008, the GIE bit is disabled (GIEH = 0), thereby blocking another (high or low-priority) interrupt from coming in. During the return from ISR, the GIE (GIE = 1) enabled automatically, which allows others interrupts to come in again. If we want to allow another high-priority interrupt to come in during the execution of the current ISR, we must make GIE = 1 at p g ,the beginning in the current ISR.

2. When a low-priority interrupt is vectored into address 0x0018, the GIEL bit is disabled (GIEL = 0), thereby blocking another low-priority interrupt from coming in. During the return from ISR, the GIEL (GIEL=1) enabled automatically, which allows low-priority interrupts to come in again Notice that the low-priority interrupt cannot low priority interrupts to come in again. Notice that the low priority interrupt cannot block a high-priority interrupt from coming in during the execution of the current low-priority ISR because GIEH is still set to high (GIEH=1).

3. When two or more interrupts have the same priority level, they are serviced according to the sequence of the program them in the interrupt vector table.