pic18f8722 family data sheet · 2019. 10. 12. · pic18f8722 family

© 2008 Microchip Technology Inc. DS39646C

PIC18F8722 FamilyData Sheet

64/80-Pin, 1-Mbit,Enhanced Flash Microcontrollers

with 10-Bit A/D and nanoWatt Technology

DS39646C-page ii © 2008 Microchip Technology Inc.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

© 2008 Microchip Technology Inc. DS39646C-page 1

PIC18F8722 FAMILY

Power Management Features:• Run: CPU On, Peripherals On• Idle: CPU Off, Peripherals On• Sleep: CPU Off, Peripherals Off• Ultra Low 50 nA Input Leakage• Run mode Currents Down to 25 μA Typical• Idle mode Currents Down to 6.8 μA Typical• Sleep mode Current Down to 120 nA Typical• Timer1 Oscillator: 900 nA, 32 kHz, 2V• Watchdog Timer: 1.6 μA, 2V Typical• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:• Four Crystal modes, up to 40 MHz• 4x Phase Lock Loop (PLL) – Available for Crystal

and Internal Oscillators• Internal Oscillator Block:

- Fast wake from Sleep and Idle, 1 μs typical- Provides a complete range of clock speeds

from 31 kHz to 32 MHz when used with PLL- User-tunable to compensate for frequency drift

• Secondary oscillator using Timer1 @ 32 kHz• Fail-Safe Clock Monitor:

- Allows for safe shutdown if peripheral clock stops

Peripheral Highlights:• High-Current Sink/Source 25 mA/25 mA• Three Programmable External Interrupts• Four Input Change Interrupts• Enhanced Capture/Compare/PWM (ECCP)

module (40/44-pin devices only):- One, two or four PWM outputs- Programmable dead time- Auto-shutdown and auto-restart

Peripheral Highlights (Continued):• Up to 2 Capture/Compare/PWM (CCP) modules,

one with Auto-Shutdown (28-pin devices)• Master Synchronous Serial Port (MSSP) module

Supporting 3-Wire SPI (all 4 modes) and I2C™ Master and Slave modes

• Enhanced Addressable USART module:- Supports RS-485, RS-232 and LIN/J2602- RS-232 operation using internal oscillator

block (no external crystal required)• 10-Bit, up to 13-Channel Analog-to-Digital (A/D)

Converter module:- Conversion available during Sleep

• Dual Analog Comparators with Input Multiplexing• Programmable 16-Level High/Low-Voltage

Detection (HLVD) module

Special Microcontroller Features:• C Compiler Optimized Architecture• 100,000 Erase/Write Cycle Enhanced Flash

Program Memory Typical• 1,000,000 Erase/Write Cycle Data EEPROM

Memory Typical• Flash/Data EEPROM Retention: 100 Years Typical• Self-Programmable under Software Control• Priority Levels for Interrupts• 8 x 8 Single-Cycle Hardware Multiplier• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s• Single-Supply 5V In-Circuit Serial Programming™

(ICSP™) via Two Pins• In-Circuit Debug (ICD) via Two Pins• Wide Operating Voltage Range: 2.0V to 5.5V• Programmable Brown-out Reset (BOR) with

Software Enable Option

Device

Program Memory Data Memory

I/O10-BitA/D (ch)

CCP/ECCP(PWM)

MSSP

EUSA

RT

Com

para

tors

Tim

ers

8/16

-Bit

Exte

rnal

Bus

Flash(bytes)

# Single-WordInstructions

SRAM(bytes)

EEPROM(bytes) SPI

MasterI2C™

PIC18F6527 48K 24576 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 NPIC18F6622 64K 32768 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 NPIC18F6627 96K 49152 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 NPIC18F6722 128K 65536 3936 1024 54 12 2/3 2 Y Y 2 2 2/3 NPIC18F8527 48K 24576 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 YPIC18F8622 64K 32768 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 YPIC18F8627 96K 49152 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 YPIC18F8722 128K 65536 3936 1024 70 16 2/3 2 Y Y 2 2 2/3 Y

64/80-Pin, 1-Mbit, Enhanced Flash Microcontrollers with10-Bit A/D and nanoWatt Technology

PIC18F8722 FAMILY

DS39646C-page 2 © 2008 Microchip Technology Inc.

Pin Diagrams

Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit.

1234567891011121314

383736353433

50 49

17 18 19 20 21 22 23 24 25 26

RE

2/C

S/P

2BR

E3/

P3C

RE

4/P

3BR

E5/

P1C

RE

6/P

1BR

E7/

EC

CP

2(1)

/P2A

(1)

RD

0/P

SP

0V

DD

VS

S

RD

1/P

SP

1R

D2/

PS

P2

RD

3/P

SP

3R

D4/

PS

P4/

SDO

2R

D5/

PS

P5/

SDI2

/SD

A2

RD

6/P

SP

6/SC

K2/

SC

L2R

D7/

PS

P7/

SS2

RE1/WR/P2CRE0/RD/P2D

RG0/ECCP3/P3ARG1/TX2/CK2RG2/RX2/DT2

RG3/CCP4/P3DRG5/MCLR/VPPRG4/CCP5/P1D

VSSVDD

RF7/SS1RF6/AN11

RF5/AN10/CVREFRF4/AN9RF3/AN8

RF2/AN7/C1OUT

RB0/INT0RB1/INT1RB2/INT2RB3/INT3RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCVSSOSC2/CLKO/RA6OSC1/CLKI/RA7VDDRB7/KBI3/PGD

RC4/SDI1/SDA1RC3/SCK1/SCL1RC2/ECCP1/P1A

RF0

/AN

5R

F1/A

N6/

C2O

UT

AVD

D

AVS

S

RA

3/AN

3/VR

EF+

RA

2/A

N2/

VRE

F-R

A1/

AN

1R

A0/

AN

0V

SS

VD

D

RA

4/T0

CK

IR

A5/

AN

4/H

LVD

IN

RC

1/T1

OSI

/EC

CP

2(1)

/P2A

(1)

RC

0/T1

OS

O/T

13C

KI

RC

7/R

X1/D

T1R

C6/

TX1/

CK

1

RC5/SDO1

1516

31

4039

27 28 29 30 32

4847464544434241

54 53 52 5158 57 56 5560 5964 63 62 61

64-Pin TQFP

PIC18F6527PIC18F6622PIC18F6627PIC18F6722


PIC18F8722 FAMILYPin Diagrams (Continued)

PIC18F8527

345678910111213141516

4847464544434241

4039

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

RE

2/AD

10/C

S/P

2BR

E3/

AD11

/P3C

(2)

RE

4/AD

12/P

3B(2

)

RE

5/AD

13/P

1C(2

)

RE

6/AD

14/P

1B(2

)

RE

7/AD

15/E

CC

P2(

1)/P

2A(1

)

RD

0/A

D0/

PS

P0

VD

D

VS

S

RD

1/A

D1/

PS

P1

RD

2/A

D2/

PS

P2

RD

3/A

D3/

PS

P3

RD

4/A

D4/

PS

P4/

SD

O2

RD

5/A

D5/

PS

P5/

SD

I2/S

DA

2R

D6/

AD

6/P

SP

6/S

CK

2/S

CL2

RD

7/A

D7/

PS

P7/

SS

2

RE1/AD9/WR/P2CRE0/AD8/RD/P2DRG0/ECCP3/P3A

RG1/TX2/CK2RG2/RX2/DT2

RG3/CCP4/P3DRG5/MCLR/VPPRG4/CCP5/P1D

VSSVDD

RF7/SS1

RB0/INT0RB1/INT1RB2/INT2RB3/INT3/ECCP2(1)/P2A(1)

RB4/KBI0RB5/KBI1/PGMRB6/KBI2/PGCVSSOSC2/CLKO/RA6OSC1/CLKI/RA7VDDRB7/KBI3/PGD

RC4/SDI1/SDA1RC3/SCK1/SCL1RC2/ECCP1/P1A

RF0

/AN

5R

F1/A

N6/

C2O

UT

AVD

D

AVS

S

RA

3/A

N3/

VRE

F+R

A2/

AN

2/VR

EF-

RA

1/A

N1

RA

0/A

N0

V SS

VD

D

RA

4/T0

CK

IR

A5/

AN

4/H

LVD

IN

RC

1/T1

OS

I/EC

CP

2(1)

/P2A

(1)

RC

0/T1

OS

O/T

13C

KI

RC

7/R

X1/

DT1

RC

6/TX

1/C

K1

RC5/SDO1

RJ0

/ALE

RJ1

/OE

RH

1/A

17R

H0/

A16

12

RH2/A18RH3/A19

1718

RH7/AN15/P1B(2)

RH6/AN14/P1C(2)

RH

5/A

N13

/P3B

(2)

RH

4/A

N12

/P3C

(2)

RJ5

/CE

RJ4

/BA

0

37

RJ7/UBRJ6/LB

5049

RJ2/WRLRJ3/WRH

1920

33 34 35 36 38

5857565554535251

6059

68 67 66 6572 71 70 6974 7378 77 76 757980

80-Pin TQFP

Note 1: The ECCP2/P2A pin placement is determined by the CCP2MX Configuration bit and Processor mode settings.2: P1B, P1C, P3B and P3C pin placement is determined by the ECCPMX Configuration bit.

RF5/AN10/CVREFRF4/AN9RF3/AN8

RF2/AN7/C1OUT

RF6/AN11

PIC18F8622PIC18F8627PIC18F8722

PIC18F8722 FAMILY


Table of Contents1.0 Device Overview .......................................................................................................................................................................... 72.0 Oscillator Configurations ............................................................................................................................................................ 313.0 Power-Managed Modes ............................................................................................................................................................. 414.0 Reset .......................................................................................................................................................................................... 495.0 Memory Organization ................................................................................................................................................................. 636.0 Flash Program Memory.............................................................................................................................................................. 877.0 External Memory Bus ................................................................................................................................................................. 978.0 Data EEPROM Memory ........................................................................................................................................................... 1119.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 11710.0 Interrupts .................................................................................................................................................................................. 11911.0 I/O Ports ................................................................................................................................................................................... 13512.0 Timer0 Module ......................................................................................................................................................................... 16113.0 Timer1 Module ......................................................................................................................................................................... 16514.0 Timer2 Module ......................................................................................................................................................................... 17115.0 Timer3 Module ......................................................................................................................................................................... 17316.0 Timer4 Module ......................................................................................................................................................................... 17717.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 17918.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 18719.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 20520.0 Enhanced Universal Synchronous Receiver Transmitter (EUSART) ....................................................................................... 24721.0 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 27122.0 Comparator Module.................................................................................................................................................................. 28123.0 Comparator Voltage Reference Module................................................................................................................................... 28724.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 29125.0 Special Features of the CPU.................................................................................................................................................... 29726.0 Instruction Set Summary .......................................................................................................................................................... 32127.0 Development Support............................................................................................................................................................... 37128.0 Electrical Characteristics .......................................................................................................................................................... 37529.0 Packaging Information.............................................................................................................................................................. 419Appendix A: Revision History............................................................................................................................................................. 425Appendix B: Device Differences......................................................................................................................................................... 425Appendix C: Conversion Considerations ........................................................................................................................................... 426Appendix D: Migration From Baseline to Enhanced Devices............................................................................................................. 426Appendix E: Migration From Mid-Range to Enhanced Devices ......................................................................................................... 427Appendix F: Migration From High-End to Enhanced Devices............................................................................................................ 427Index .................................................................................................................................................................................................. 429The Microchip Web Site ..................................................................................................................................................................... 441Customer Change Notification Service .............................................................................................................................................. 441Customer Support .............................................................................................................................................................................. 441Reader Response .............................................................................................................................................................................. 442PIC18F8722 Family Product Identification System............................................................................................................................ 443


PIC18F8722 FAMILY

TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

Most Current Data SheetTo obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.comYou can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

Customer Notification SystemRegister on our web site at www.microchip.com to receive the most current information on all of our products.

PIC18F8722 FAMILY


NOTES:


PIC18F8722 FAMILY1.0 DEVICE OVERVIEWThis document contains device specific information forthe following devices:

This family offers the advantages of all PIC18 micro-controllers – namely, high computational performance atan economical price – with the addition of high-endurance, Enhanced Flash program memory. On top ofthese features, the PIC18F8722 family introducesdesign enhancements that make these microcontrollersa logical choice for many high-performance, powersensitive applications.

1.1 New Core Features 1.1.1 nanoWatt TECHNOLOGYAll of the devices in the PIC18F8722 family incorporatea range of features that can significantly reduce powerconsumption during operation. Key items include:

• Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be significantly reduced.

• Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further.

• On-the-fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design.

• Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 28.0 “Electrical Characteristics” for values.

1.1.2 EXPANDED MEMORYThe PIC18F8722 family provides ample room forapplication code and includes members with 48, 64,96 or 128 Kbytes of code space.

• Data RAM and Data EEPROM: The PIC18F8722 family also provides plenty of room for application data. The devices have 3936 bytes of data RAM, as well as 1024 bytes of data EEPROM, for long term retention of nonvolatile data.

• Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles, up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years.

1.1.3 MULTIPLE OSCILLATOR OPTIONS AND FEATURES

All of the devices in the PIC18F8722 family offer tendifferent oscillator options, allowing users a wide rangeof choices in developing application hardware. Theseinclude:

• Four Crystal modes, using crystals or ceramic resonators

• Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O)

• Two External RC Oscillator modes with the same pin options as the External Clock modes

• An internal oscillator block which provides an 8 MHz clock and an INTRC source (approxi-mately 31 kHz), as well as a range of 6 user selectable clock frequencies, between 125 kHz to 4 MHz, for a total of 8 clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/O.

• A Phase Lock Loop (PLL) frequency multiplier, available to both the high-speed crystal and inter-nal oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz – all without using an external crystal or clock circuit.

• PIC18F6527 • PIC18LF6527• PIC18F6622 • PIC18LF6622• PIC18F6627 • PIC18LF6627• PIC18F6722 • PIC18LF6722• PIC18F8527 • PIC18LF8527• PIC18F8622 • PIC18LF8622• PIC18F8627 • PIC18LF8627• PIC18F8722 • PIC18LF8722

PIC18F8722 FAMILY


Besides its availability as a clock source, the internaloscillator block provides a stable reference source thatgives the family additional features for robust operation:

• Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown.

• Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.

1.1.4 EXTERNAL MEMORY INTERFACEIn the unlikely event that 128 Kbytes of programmemory is inadequate for an application, thePIC18F8527/8622/8627/8722 members of the familyalso implement an external memory interface. Thisallows the controller’s internal program counter toaddress a memory space of up to 2 Mbytes,permitting a level of data access that few 8-bit devicescan claim.

With the addition of new operating modes, the externalmemory interface offers many new options, including:

• Operating the microcontroller entirely from external memory

• Using combinations of on-chip and external memory, up to the 2-Mbyte limit

• Using external Flash memory for reprogrammable application code or large data tables

• Using external RAM devices for storing large amounts of variable data

1.1.5 EASY MIGRATIONRegardless of the memory size, all devices share thesame rich set of peripherals, allowing for a smoothmigration path as applications grow and evolve.

The consistent pinout scheme used throughout theentire family also aids in migrating to the next largerdevice. This is true when moving between the 64-pinmembers, between the 80-pin members, or evenjumping from 64-pin to 80-pin devices.

1.2 Other Special Features• Communications: The PIC18F8722 family

incorporates a range of serial communication peripherals, including 2 independent Enhanced USARTs and 2 Master SSP modules capable of both SPI and I2C (Master and Slave) modes of operation. Also, one of the general purpose I/O ports can be reconfigured as an 8-bit Parallel Slave Port for direct processor-to-processor communications.

• CCP Modules: All devices in the family incorporate two Capture/Compare/PWM (CCP) modules and three Enhanced CCP (ECCP) modules to maximize flexibility in control applications. Up to four different time bases may be used to perform several different operations at once. Each of the three ECCP modules offer up to four PWM outputs, allowing for a total of 12 PWMs. The ECCPs also offer many beneficial features, including polarity selection, Programmable Dead-Time, Auto-Shutdown and Restart and Half-Bridge and Full-Bridge Output modes.

• Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected boot block at the top of program memory, it becomes possible to create an application that can update itself in the field.

• Extended Instruction Set: The PIC18F8722 family introduces an optional extension to the PIC18 instruction set, which adds 8 new instruc-tions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C.

• 10-bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead.

• Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 28.0 “Electrical Characteristics” for time-out periods.


PIC18F8722 FAMILY1.3 Details on Individual Family

MembersDevices in the PIC18F8722 family are available in64-pin and 80-pin packages. Block diagrams for thetwo groups are shown in Figure 1-1 and Figure 1-2.

The devices are differentiated from each other in fiveways:

1. Flash program memory (48 Kbytes forPIC18F6527/8527 devices, 64 Kbytes forPIC18F6622/8622 devices, 96 Kbytes forPIC18F6627/8627 devices and 128 Kbytes forPIC18F6722/8722).

2. A/D channels (12 for 64-pin devices, 16 for80-pin devices).

3. I/O ports (7 bidirectional ports on 64-pin devices,9 bidirectional ports on 80-pin devices).

4. External Memory Bus, configurable for 8 and16-bit operation, is available on PIC18F8527/8622/8627/8722 devices.

All other features for devices in this family are identical.These are summarized in Table 1-2 and Table 1-2.

The pinouts for all devices are listed in Table 1-3 andTable 1-4.

Like all Microchip PIC18 devices, members of thePIC18F8722 family are available as both standard andlow-voltage devices. Standard devices with EnhancedFlash memory, designated with an “F” in the partnumber (such as PIC18F6627), accommodate anoperating VDD range of 4.2V to 5.5V. Low-voltageparts, designated by “LF” (such as PIC18LF6627),function over an extended VDD range of 2.0V to 5.5V.

TABLE 1-1: DEVICE FEATURES (PIC18F6527/6622/6627/6722) Features PIC18F6527 PIC18F6622 PIC18F6627 PIC18F6722

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHzProgram Memory (Bytes) 48K 64K 96K 128KProgram Memory (Instructions) 24576 32768 49152 65536Data Memory (Bytes) 3936 3936 3936 3936Data EEPROM Memory (Bytes) 1024 1024 1024 1024Interrupt Sources 28 28 28 28I/O Ports Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, G Ports A, B, C, D, E, F, GTimers 5 5 5 5Capture/Compare/PWM Modules

2 2 2 2

Enhanced Capture/Compare/PWM Modules

3 3 3 3

Enhanced USART 2 2 2 2Serial Communications MSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTParallel Communications (PSP) Yes Yes Yes Yes10-bit Analog-to-Digital Module 12 Input Channels 12 Input Channels 12 Input Channels 12 Input ChannelsResets (and Delays) POR, BOR,

RESET Instruction, Stack Full, Stack

Underflow (PWRT, OST), MCLR (optional), WDT

POR, BOR, RESET Instruction,

Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT





Programmable High/Low-Voltage Detect

Yes Yes Yes Yes

Programmable Brown-out Reset

Yes Yes Yes Yes

Instruction Set 75 Instructions; 83 with Extended

Instruction Set enabled

75 Instructions; 83 with Extended





Instruction Set enabledPackages 64-pin TQFP 64-pin TQFP 64-pin TQFP 64-pin TQFP

PIC18F8722 FAMILY


TABLE 1-2: DEVICE FEATURES (PIC18F8527/8622/8627/8722) Features PIC18F8527 PIC18F8622 PIC18F8627 PIC18F8722

Operating Frequency DC – 40 MHz DC – 40 MHz DC – 40 MHz DC – 40 MHzProgram Memory (Bytes) 48K 64K 96K 128KProgram Memory (Instructions) 24576 32768 49152 65536Data Memory (Bytes) 3936 3936 3936 3936Data EEPROM Memory (Bytes) 1024 1024 1024 1024Interrupt Sources 29 29 29 29I/O Ports Ports A, B, C, D, E,

F, G, H, JPorts A, B, C, D, E,



F, G, H, JTimers 5 5 5 5Capture/Compare/PWM Modules

2 2 2 2

Enhanced Capture/Compare/PWM Modules

3 3 3 3

Enhanced USART 2 2 2 2Serial Communications MSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTMSSP,

Enhanced USARTParallel Communications (PSP)

Yes Yes Yes Yes

10-bit Analog-to-Digital Module 16 Input Channels 16 Input Channels 16 Input Channels 16 Input ChannelsResets (and Delays) POR, BOR,

RESET Instruction, Stack Full, Stack

Underflow (PWRT, OST), MCLR (optional), WDT







Programmable High/Low-Voltage Detect

Yes Yes Yes Yes

Programmable Brown-out Reset

Yes Yes Yes Yes

Instruction Set 75 Instructions; 83 with Extended







Instruction Set enabledPackages 80-pin TQFP 80-pin TQFP 80-pin TQFP 80-pin TQFP


PIC18F8722 FAMILY

FIGURE 1-1: PIC18F6527/6622/6627/6722 (64-PIN) BLOCK DIAGRAM

InstructionDecode and

Control

PORTAData Latch

Data Memory(3.9 Kbytes)

Address Latch

Data Address12

AccessBSR FSR0FSR1FSR2

inc/declogic

Address

4 12 4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

Address LatchProgram Memory

(48/64/96/128

Data Latch

20

8

8

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

3

PCLATU

PCU

Note 1: See Table 1-3 for I/O port pin descriptions.2: RG5 is only available when MCLR functionality is disabled.3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as

digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0HLVD

ECCP1

BOR ADC10-bit

W

Instruction Bus

STKPTR Bank

8

State MachineControl Signals

Decode

8

8

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

OSC1(3)

OSC2(3)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

Precision

ReferenceBand Gap

VSS

MCLR(2)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

EUSART2ECCP2

ROM Latch

ECCP3 MSSP2CCP4 CCP5

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7(1)

RC0:RC7(1)

RD0:RD7(1)

RE0:RE7(1)

RF0:RF7(1)

RG0:RG5(1)

PORTB

RB0:RB7(1)

Timer4

Kbytes)

PIC18F8722 FAMILY


FIGURE 1-2: PIC18F8527/8622/8627/8722 (80-PIN) BLOCK DIAGRAM

PRODLPRODH

8 x 8 Multiply

8

BITOP88

ALU

8

83

W8

8

8Power-up

Timer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

OSC1(3)

OSC2(3)

VDD,

Brown-outReset

InternalOscillator

Fail-SafeClock Monitor

Precision

ReferenceBand Gap

VSS

MCLR(2)

Block

INTRCOscillator

8 MHzOscillator

Single-SupplyProgramming

In-CircuitDebugger

T1OSI

T1OSO

InstructionDecode &

Control

Data Latch

Data Memory(3.9 Kbytes)

Address Latch

Data Address12

AccessBSR FSR0FSR1FSR2

inc/declogic

Address

4 12 4

PCH PCL

PCLATH

8

31-Level Stack

Program Counter

Address LatchProgram Memory

(48/64/96/128

Data Latch

20

Table Pointer

inc/dec logic

21

8

Data Bus

Table Latch8

IR

12

ROM Latch

PCLATU

PCU

Instruction Bus

STKPTR Bank

State MachineControl Signals

Decode

Sys

tem

Bus

Inte

rface

AD15:AD0, A19:A16(Multiplexed with PORTD,PORTE and PORTH)

PORTA

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7(1)

RC0:RC7(1)

RD0:RD7(1)

RE0:RE7(1)

RF0:RF7(1)

RG0:RG5(1)

PORTB

RB0:RB7(1)

PORTH

RH0:RH7(1)

PORTJ

RJ0:RJ7(1)

EUSART1

Comparators

MSSP1

Timer2Timer1 Timer3Timer0HLVD

ECCP1

BOR ADC10-bit

EUSART2ECCP2 ECCP3 MSSP2CCP4 CCP5

Timer4

Note 1: See Table 1-4 for I/O port pin descriptions.2: RG5 is only available when MCLR functionality is disabled.3: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as

digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information.

Kbytes)


PIC18F8722 FAMILY

TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS

Pin NamePin Number Pin

TypeBufferType DescriptionTQFP

RG5/MCLR/VPPRG5MCLR

VPP

7II

P

STST

Master Clear (input) or programming voltage (input).Digital input.Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

39I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise.External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

40O

O

I/O

—

—

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes theinstruction cycle rate. General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™ = I2C/SMBus input buffer

Note 1: Default assignment for ECCP2 when Configuration bit, CCP2MX, is set.2: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared.

PIC18F8722 FAMILY


PORTA is a bidirectional I/O port.

RA0/AN0RA0AN0

24I/OI

TTLAnalog

Digital I/O.Analog input 0.

RA1/AN1RA1AN1

23I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

22I/OII

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

21I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

28I/OI

STST

Digital I/O.Timer0 external clock input.

RA5/AN4/HLVDINRA5AN4HLVDIN

27I/OII

TTLAnalogAnalog

Digital I/O.Analog input 4. High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

TABLE 1-3: PIC18F6527/6622/6627/6722 PINOUT I/O DESCRIPTIONS (CONTINUED)






PIC18F8722 FAMILY

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0RB0INT0FLT0

48I/OII

TTLSTST

Digital I/O.External interrupt 0.PWM Fault input for ECCPx.

RB1/INT1RB1INT1

47I/OI

TTLST

Digital I/O.External interrupt 1.

RB2/INT2RB2INT2

46I/OI

TTLST


RB3/INT3RB3INT3

45I/OI

TTLST


RB4/KBI0RB4KBI0

44I/OI

TTLTTL

Digital I/O.Interrupt-on-change pin.

RB5/KBI1/PGMRB5KBI1PGM

43I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

42I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

37I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.






PIC18F8722 FAMILY


PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKIRC0T1OSOT13CKI

30I/OOI

ST—ST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSI/ECCP2/P2ARC1T1OSIECCP2(1)

P2A(1)

29I/OI

I/O

O

STCMOS

ST

—

Digital I/O.Timer1 oscillator input.Enhanced Capture 2 input/Compare 2 output/PWM 2 output.ECCP2 PWM output A.

RC2/ECCP1/P1ARC2ECCP1

P1A

33I/OI/O

O

STST

—

Digital I/O.Enhanced Capture 1 input/Compare 1 output/PWM 1 output.ECCP1 PWM output A.

RC3/SCK1/SCL1RC3SCK1SCL1

34I/OI/OI/O

STSTST

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C™ mode.

RC4/SDI1/SDA1RC4SDI1SDA1

35I/OI

I/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDO1RC5SDO1

36I/OO

ST—

Digital I/O.SPI data out.

RC6/TX1/CK1RC6TX1CK1

31I/OOI/O

ST—ST

Digital I/O.EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1).

RC7/RX1/DT1RC7RX1DT1

32I/OI

I/O

STSTST

Digital I/O.EUSART1 asynchronous receive.EUSART1 synchronous data (see related TX1/CK1).







PIC18F8722 FAMILY

PORTD is a bidirectional I/O port.

RD0/PSP0RD0PSP0

58I/OI/O

STTTL

Digital I/O.Parallel Slave Port data.

RD1/PSP1RD1PSP1

55I/OI/O

STTTL


RD2/PSP2RD2PSP2

54I/OI/O

STTTL


RD3/PSP3RD3PSP3

53I/OI/O

STTTL


RD4/PSP4/SDO2RD4PSP4SDO2

52I/OI/OO

STTTL—

Digital I/O.Parallel Slave Port data.SPI data out.

RD5/PSP5/SDI2/SDA2RD5PSP5SDI2SDA2

51I/OI/OI

I/O

STTTLST

I2C/SMB

Digital I/O.Parallel Slave Port data.SPI data in.I2C™ data I/O.

RD6/PSP6/SCK2/SCL2RD6PSP6SCK2SCL2

50I/OI/OI/OI/O

STTTLST

I2C/SMB

Digital I/O.Parallel Slave Port data.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RD7/PSP7/SS2RD7PSP7SS2

49I/OI/OI

STTTLTTL

Digital I/O.Parallel Slave Port data.SPI slave select input.






PIC18F8722 FAMILY


PORTE is a bidirectional I/O port.

RE0/RD/P2DRE0RDP2D

2I/OIO

STTTL—

Digital I/O.Read control for Parallel Slave Port.ECCP2 PWM output D.

RE1/WR/P2CRE1WRP2C

1I/OIO

STTTL—

Digital I/O.Write control for Parallel Slave Port.ECCP2 PWM output C.

RE2/CS/P2BRE2CSP2B

64I/OIO

STTTL—

Digital I/O.Chip select control for Parallel Slave Port.ECCP2 PWM output B.

RE3/P3CRE3P3C

63I/OO

ST—

Digital I/O.ECCP3 PWM output C.

RE4/P3BRE4P3B

62I/OO

ST—

Digital I/O.ECCP3 PWM output B.

RE5/P1CRE5P1C

61I/OO

ST—

Digital I/O.ECCP1 PWM output C.

RE6/P1BRE6P1B

60I/OO

ST—

Digital I/O.ECCP1 PWM output B.

RE7/ECCP2/P2ARE7ECCP2(2)

P2A(2)

59I/OI/O

O

STST

—








PIC18F8722 FAMILY

PORTF is a bidirectional I/O port.

RF0/AN5RF0AN5

18I/OI

STAnalog


RF1/AN6/C2OUTRF1AN6C2OUT

17I/OIO

STAnalog

—

Digital I/O.Analog input 6.Comparator 2 output.


16I/OIO

STAnalog

—


RF3/AN8RF3AN8

15I/OI

STAnalog


RF4/AN9RF4AN9

14I/OI

STAnalog


RF5/AN10/CVREFRF5AN10CVREF

13I/OIO

STAnalogAnalog

Digital I/O.Analog input 10. Comparator reference voltage output.

RF6/AN11RF6AN11

12I/OI

STAnalog


RF7/SS1RF7SS1

11I/OI

STTTL

Digital I/O.SPI slave select input.






PIC18F8722 FAMILY


PORTG is a bidirectional I/O port.

RG0/ECCP3/P3ARG0ECCP3

P3A

3I/OI/O

O

STST

—


RG1/TX2/CK2RG1TX2CK2

4I/OOI/O

ST—ST


RG2/RX2/DT2RG2RX2DT2

5I/OI

I/O

STSTST


RG3/CCP4/P3DRG3CCP4P3D

6I/OI/OO

STST—

Digital I/O.Capture 4 input/Compare 4 output/PWM 4 output.ECCP3 PWM output D.


8I/OI/OO

STST—


RG5 See RG5/MCLR/VPP pin.VSS 9, 25, 41, 56 P — Ground reference for logic and I/O pins.VDD 10, 26, 38, 57 P — Positive supply for logic and I/O pins.AVSS 20 P — Ground reference for analog modules.AVDD 19 P — Positive supply for analog modules.







PIC18F8722 FAMILY

TABLE 1-4: PIC18F8527/8622/8627/8722 PINOUT I/O DESCRIPTIONS



RG5/MCLR/VPPRG5MCLR

VPP

9II

P

STST

Master Clear (input) or programming voltage (input).Digital input.Master Clear (Reset) input. This pin is an active-low Reset to the device.Programming voltage input.

OSC1/CLKI/RA7OSC1

CLKI

RA7

49I

I

I/O

ST

CMOS

TTL

Oscillator crystal or external clock input.Oscillator crystal input or external clock source input. ST buffer when configured in RC mode, CMOS otherwise.External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.)General purpose I/O pin.

OSC2/CLKO/RA6OSC2

CLKO

RA6

50O

O

I/O

—

—

TTL

Oscillator crystal or clock output.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes theinstruction cycle rate. General purpose I/O pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog= Analog input I = Input O = Output P = Power I2C™/SMB = I2C/SMBus input buffer

Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except Microcontroller mode).

2: Default assignment for ECCP2 in all operating modes (CCP2MX is set). 3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).

PIC18F8722 FAMILY


PORTA is a bidirectional I/O port.

RA0/AN0RA0AN0

30I/OI

TTLAnalog


RA1/AN1RA1AN1

29I/OI

TTLAnalog


RA2/AN2/VREF-RA2AN2VREF-

28I/OII

TTLAnalogAnalog

Digital I/O.Analog input 2.A/D reference voltage (low) input.

RA3/AN3/VREF+RA3AN3VREF+

27I/OII

TTLAnalogAnalog

Digital I/O.Analog input 3.A/D reference voltage (high) input.

RA4/T0CKIRA4T0CKI

34I/OI

ST/ODST

Digital I/O. Open-drain when configured as output.Timer0 external clock input.

RA5/AN4/HLVDINRA5AN4HLVDIN

33I/OII

TTLAnalogAnalog

Digital I/O.Analog input 4. High/Low-Voltage Detect input.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.








PIC18F8722 FAMILY

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs.

RB0/INT0/FLT0RB0INT0FLT0

58I/OII

TTLSTST

Digital I/O.External interrupt 0.PWM Fault input for ECCPx.

RB1/INT1RB1INT1

57I/OI

TTLST


RB2/INT2RB2INT2

56I/OI

TTLST


RB3/INT3/ECCP2/P2ARB3INT3ECCP2(1)

P2A(1)

55I/OIO

O

TTLST—

—

Digital I/O.External interrupt 3.Enhanced Capture 2 input/Compare 2 output/PWM 2 output.ECCP2 PWM output A.

RB4/KBI0RB4KBI0

54I/OI

TTLTTL

Digital I/O.Interrupt-on-change pin.

RB5/KBI1/PGMRB5KBI1PGM

53I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin.Low-Voltage ICSP™ Programming enable pin.

RB6/KBI2/PGCRB6KBI2PGC

52I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP™ programming clock pin.

RB7/KBI3/PGDRB7KBI3PGD

47I/OI

I/O

TTLTTLST

Digital I/O.Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin.







PIC18F8722 FAMILY


PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKIRC0T1OSOT13CKI

36I/OOI

ST—ST

Digital I/O.Timer1 oscillator output. Timer1/Timer3 external clock input.

RC1/T1OSI/ECCP2/P2ARC1T1OSIECCP2(2)

P2A(2)

35I/OI

I/O

O

STCMOS

ST

—

Digital I/O.Timer1 oscillator input.Enhanced Capture 2 input/Compare 2 output/PWM 2 output.ECCP2 PWM output A.

RC2/ECCP1/P1ARC2ECCP1

P1A

43I/OI/O

O

STST

—


RC3/SCK1/SCL1RC3SCK1SCL1

44I/OI/OI/O

STSTST

Digital I/O.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C™ mode.

RC4/SDI1/SDA1RC4SDI1SDA1

45I/OI

I/O

STSTST

Digital I/O.SPI data in.I2C data I/O.

RC5/SDO1RC5SDO1

46I/OO

ST—

Digital I/O.SPI data out.

RC6/TX1/CK1RC6TX1CK1

37I/OO

I/O

ST—ST


RC7/RX1/DT1RC7RX1DT1

38I/OI

I/O

STSTST









PIC18F8722 FAMILY

PORTD is a bidirectional I/O port.

RD0/AD0/PSP0RD0AD0PSP0

72I/OI/OI/O

STTTLTTL

Digital I/O.External memory address/data 0.Parallel Slave Port data.


69I/OI/OI/O

STTTLTTL



68I/OI/OI/O

STTTLTTL



67I/OI/OI/O

STTTLTTL


RD4/AD4/PSP4/SDO2RD4AD4PSP4SDO2

66I/OI/OI/OO

STTTLTTL—

Digital I/O.External memory address/data 4.Parallel Slave Port data.SPI data out.

RD5/AD5/PSP5/SDI2/SDA2

RD5AD5PSP5SDI2SDA2

65

I/OI/OI/OI

I/O

STTTLTTLST

I2C/SMB

Digital I/O.External memory address/data 5.Parallel Slave Port data.SPI data in.I2C™ data I/O.

RD6/AD6/PSP6/SCK2/SCL2

RD6AD6PSP6SCK2SCL2

64

I/OI/OI/OI/OI/O

STTTLTTLST

I2C/SMB

Digital I/O.External memory address/data 6.Parallel Slave Port data.Synchronous serial clock input/output for SPI mode.Synchronous serial clock input/output for I2C mode.

RD7/AD7/PSP7/SS2RD7AD7PSP7SS2

63I/OI/OI/OI

STTTLTTLTTL

Digital I/O.External memory address/data 7.Parallel Slave Port data.SPI slave select input.







PIC18F8722 FAMILY


PORTE is a bidirectional I/O port.

RE0/AD8/RD/P2DRE0AD8RDP2D

4I/OI/OIO

STTTLTTL—

Digital I/O.External memory address/data 8.Read control for Parallel Slave Port.ECCP2 PWM output D.

RE1/AD9/WR/P2CRE1AD9WRP2C

3I/OI/OIO

STTTLTTL—

Digital I/O.External memory address/data 9.Write control for Parallel Slave Port.ECCP2 PWM output C.

RE2/AD10/CS/P2BRE2AD10CSP2B

78I/OI/OIO

STTTLTTL—

Digital I/O.External memory address/data 10.Chip select control for Parallel Slave Port.ECCP2 PWM output B.

RE3/AD11/P3CRE3AD11P3C(4)

77I/OI/OO

STTTL—

Digital I/O.External memory address/data 11.ECCP3 PWM output C.

RE4/AD12/P3BRE4AD12P3B(4)

76I/OI/OO

STTTL—

Digital I/O.External memory address/data 12.ECCP3 PWM output B.

RE5/AD13/P1CRE5AD13P1C(4)

75I/OI/OO

STTTL—

Digital I/O.External memory address/data 13.ECCP1 PWM output C.

RE6/AD14/P1BRE6AD14P1B(4)

74I/OI/OO

STTTL—

Digital I/O.External memory address/data 14.ECCP1 PWM output B.

RE7/AD15/ECCP2/P2ARE7AD15ECCP2(3)

P2A(3)

73I/OI/OI/O

O

STTTLST

—

Digital I/O.External memory address/data 15.Enhanced Capture 2 input/Compare 2 output/PWM 2 output.ECCP2 PWM output A.








PIC18F8722 FAMILY

PORTF is a bidirectional I/O port.

RF0/AN5RF0AN5

24I/OI

STAnalog



23I/OIO

STAnalog

—



18I/OIO

STAnalog

—


RF3/AN8RF3AN8

17I/OI

STAnalog


RF4/AN9RF4AN9

16I/OI

STAnalog


RF5/AN10/CVREFRF5AN10CVREF

15I/OIO

STAnalogAnalog

Digital I/O.Analog input 10. Comparator reference voltage output.

RF6/AN11RF6AN11

14I/OI

STAnalog


RF7/SS1RF7SS1

13I/OI

STTTL

Digital I/O.SPI slave select input.







PIC18F8722 FAMILY


PORTG is a bidirectional I/O port.

RG0/ECCP3/P3ARG0ECCP3

P3A

5I/OI/O

O

STST

—


RG1/TX2/CK2RG1TX2CK2

6I/OO

I/O

ST—ST


RG2/RX2/DT2RG2RX2DT2

7I/OI

I/O

STSTST



8I/OI/OO

STST—



10I/OI/OO

STST—


RG5 See RG5/MCLR/VPP pin.








PIC18F8722 FAMILY

PORTH is a bidirectional I/O port.

RH0/A16RH0A16

79I/OI/O

STTTL

Digital I/O.External memory address/data 16.

RH1/A17RH1A17

80I/OI/O

STTTL


RH2/A18RH2A18

1I/OI/O

STTTL


RH3/A19RH3A19

2I/OI/O

STTTL


RH4/AN12/P3CRH4AN12P3C(5)

22I/OIO

STAnalog

—

Digital I/O.Analog input 12.ECCP3 PWM output C.

RH5/AN13/P3BRH5AN13P3B(5)

21I/OIO

STAnalog

—

Digital I/O.Analog input 13.ECCP3 PWM output B.

RH6/AN14/P1CRH6AN14P1C(5)

20I/OIO

STAnalog

—

Digital I/O.Analog input 14.ECCP1 PWM output C.

RH7/AN15/P1BRH7AN15P1B(5)

19I/OIO

STAnalog

—

Digital I/O.Analog input 15.ECCP1 PWM output B.







PIC18F8722 FAMILY


PORTJ is a bidirectional I/O port.

RJ0/ALERJ0ALE

62I/OO

ST—

Digital I/O.External memory address latch enable.

RJ1/OERJ1OE

61I/OO

ST—

Digital I/O.External memory output enable.

RJ2/WRLRJ2WRL

60I/OO

ST—

Digital I/O.External memory write low control.

RJ3/WRHRJ3WRH

59I/OO

ST—

Digital I/O.External memory write high control.

RJ4/BA0RJ4BA0

39I/OO

ST—

Digital I/O.External memory byte address 0 control.

RJ5/CERJ4CE

40I/OO

ST—

Digital I/OExternal memory chip enable control.

RJ6/LBRJ6LB

41I/OO

ST—

Digital I/O.External memory low byte control.

RJ7/UBRJ7UB

42I/OO

ST—

Digital I/O.External memory high byte control.

VSS 11, 31, 51, 70 P — Ground reference for logic and I/O pins.VDD 12, 32, 48, 71 P — Positive supply for logic and I/O pins.AVSS 26 P — Ground reference for analog modules.AVDD 25 P — Positive supply for analog modules.








PIC18F8722 FAMILY

2.0 OSCILLATOR CONFIGURATIONS

2.1 Oscillator TypesThe PIC18F8722 family of devices can be operated inten different oscillator modes. The user can program theConfiguration bits, FOSC, in ConfigurationRegister 1H to select one of these ten modes:

1. LP Low-Power Crystal2. XT Crystal/Resonator3. HS High-Speed Crystal/Resonator4. HSPLL High-Speed Crystal/Resonator

with PLL enabled5. RC External Resistor/Capacitor with

FOSC/4 output on RA66. RCIO External Resistor/Capacitor with I/O

on RA67. INTIO1 Internal Oscillator with FOSC/4 output

on RA6 and I/O on RA78. INTIO2 Internal Oscillator with I/O on RA6

and RA79. EC External Clock with FOSC/4 output10. ECIO External Clock with I/O on RA6

2.2 Crystal Oscillator/Ceramic Resonators

In XT, LP, HS or HSPLL Oscillator modes, a crystal orceramic resonator is connected to the OSC1 andOSC2 pins to establish oscillation. Figure 2-1 showsthe pin connections.

The oscillator design requires the use of a parallel cutcrystal.

FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)

TABLE 2-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS

Note: Use of a series cut crystal may give afrequency out of the crystal manufacturer’sspecifications.

Typical Capacitor Values Used:

Mode Freq OSC1 OSC2

XT 3.58 MHz 22 pF 22 pFCapacitor values are for design guidance only. Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application. Referto the following application notes for oscillator specificinformation:

• AN588 – PIC® Microcontroller Oscillator Design Guide

• AN826 – Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices

• AN849 – Basic PIC® Oscillator Design• AN943 – Practical PIC® Oscillator Analysis and

Design• AN949 – Making Your Oscillator Work

See the notes following Table 2-2 for additionalinformation.

Note: When using resonators with frequenciesabove 3.5 MHz, the use of HS mode,rather than XT mode, is recommended.HS mode may be used at any VDD forwhich the controller is rated. If HS isselected, it is possible that the gain of theoscillator will overdrive the resonator.Therefore, a series resistor may be placedbetween the OSC2 pin and the resonator.As a good starting point, therecommended value of RS is 330Ω.

Note 1: See Table 2-1 and Table 2-2 for initial values ofC1 and C2.

2: A series resistor (RS) may be required for ATstrip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

To

Logic

PIC18FXXXXRS(2)

Internal

PIC18F8722 FAMILY


TABLE 2-2: CAPACITOR SELECTION FOR QUARTZ CRYSTALS

An external clock source may also be connected to theOSC1 pin in the HS mode, as shown in Figure 2-2.When operated in this mode, parameters D033 andD043 apply.

FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)

2.3 External Clock InputThe EC and ECIO Oscillator modes require an externalclock source to be connected to the OSC1 pin. There isno oscillator start-up time required after a Power-onReset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-3 shows the pin connections for the ECOscillator mode.

FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,except that the OSC2 pin becomes an additionalgeneral purpose I/O pin. The I/O pin becomes bit 6 ofPORTA (RA6). Figure 2-4 shows the pin connectionsfor the ECIO Oscillator mode. When operated in thismode, parameters D033A and D043A apply.

FIGURE 2-4: EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)

Osc Type Crystal Freq

Typical Capacitor Values Tested:

C1 C2

LP 32 kHz 22 pF 22 pFXT 1 MHz

4 MHz22 pF22 pF

22 pF22 pF

HS 4 MHz10 MHz20 MHz25 MHz

22 pF22 pF22 pF22 pF

22 pF22 pF22 pF22 pF

Capacitor values are for design guidance only. Different capacitor values may be required to produceacceptable oscillator operation. The user should testthe performance of the oscillator over the expectedVDD and temperature range for the application. Referto the following application notes for oscillator specificinformation:

• AN588 – PIC® Microcontroller Oscillator Design Guide

• AN826 – Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices

• AN849 – Basic PIC® Oscillator Design• AN943 – Practical PIC® Oscillator Analysis and

Design• AN949 – Making Your Oscillator Work

See the notes following this table for additionalinformation.

Note 1: Higher capacitance increases the stabilityof the oscillator but also increases thestart-up time.

2: When operating below 3V VDD, or whenusing certain ceramic resonators at anyvoltage, it may be necessary to use theHS mode or switch to a crystal oscillator.

3: Since each resonator/crystal has its owncharacteristics, the user should consultthe resonator/crystal manufacturer forappropriate values of externalcomponents.

4: Rs may be required to avoid overdrivingcrystals with low drive level specification.

5: Always verify oscillator performance overthe VDD and temperature range that isexpected for the application.

OSC1

OSC2Open

Clock fromExt. System PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKOFOSC/4


OSC1/CLKI

I/O (OSC2)RA6



PIC18F8722 FAMILY2.4 RC OscillatorFor timing insensitive applications, the RC and RCIOOscillator modes offer additional cost savings. Theactual oscillator frequency is a function of severalfactors:

• supply voltage• values of the external resistor (REXT) and

capacitor (CEXT)• operating temperature

Given the same device, operating voltage and tempera-ture and component values, there will also be unit-to-unitfrequency variations. These are due to factors such as:

• normal manufacturing variation• difference in lead frame capacitance between

package types (especially for low CEXT values) • variations within the tolerance of limits of REXT

and CEXT

In the RC Oscillator mode, the oscillator frequencydivided by 4 is available on the OSC2 pin. This signalmay be used for test purposes or to synchronize otherlogic. Figure 2-5 shows how the R/C combination isconnected.

FIGURE 2-5: RC OSCILLATOR MODE

The RCIO Oscillator mode (Figure 2-6) functions likethe RC mode, except that the OSC2 pin becomes anadditional general purpose I/O pin. The I/O pinbecomes bit 6 of PORTA (RA6).

FIGURE 2-6: RCIO OSCILLATOR MODE

2.5 PLL Frequency MultiplierA Phase Locked Loop (PLL) circuit is provided as anoption for users who wish to use a lower frequencyoscillator circuit or to clock the device up to its highestrated frequency from a crystal oscillator. This may beuseful for customers who are concerned with EMI dueto high-frequency crystals or users who require higherclock speeds from an internal oscillator.

2.5.1 HSPLL OSCILLATOR MODEThe HSPLL mode makes use of the HS mode oscillatorfor frequencies up to 10 MHz. A PLL then multiplies theoscillator output frequency by 4 to produce an internalclock frequency up to 40 MHz. The PLLEN bit is notavailable when this mode is configured as the primaryclock source.

The PLL is only available to the crystal oscillator whenthe FOSC Configuration bits are programmed forHSPLL mode (= 0110).

FIGURE 2-7: HSPLL BLOCK DIAGRAM

2.5.2 PLL AND INTOSCThe PLL is also available to the internal oscillator blockwhen the internal oscillator block is configured as theprimary clock source. In this configuration, the PLL isenabled in software and generates a clock output of upto 32 MHz. The operation of INTOSC with the PLL isdescribed in Section 2.6.4 “PLL in INTOSC Modes”.

OSC2/CLKO

CEXT

REXT

PIC18FXXXX

OSC1

FOSC/4

InternalClock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ20 pF ≤ CEXT ≤ 300 pF

CEXT

REXT

PIC18FXXXX

OSC1 InternalClock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ20 pF ≤ CEXT ≤ 300 pF

I/O (OSC2)RA6

MU

X

VCO

LoopFilter

CrystalOsc

OSC2

OSC1

PLL Enable

FINFOUT

SYSCLK

PhaseComparator

HS Oscillator Enable

÷4

(from Configuration Register 1H)

HS Mode

PIC18F8722 FAMILY


2.6 Internal Oscillator BlockThe PIC18F8722 family of devices includes an internaloscillator block which generates two different clocksignals; either can be used as the microcontroller’sclock source. This may eliminate the need for externaloscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,which can be used to directly drive the device clock. Italso drives a postscaler, which can provide a range ofclock frequencies from 31 kHz to 4 MHz. The INTOSCoutput is enabled when a clock frequency from 125 kHzto 8 MHz is selected. The INTOSC output can also beenabled when 31 kHz is selected, depending on theINTSRC bit (OSCTUNE).

The other clock source is the internal RC oscillator(INTRC), which provides a nominal 31 kHz output.INTRC is enabled if it is selected as the device clocksource; it is also enabled automatically when any of thefollowing are enabled:

• Power-up Timer• Fail-Safe Clock Monitor• Watchdog Timer• Two-Speed Start-up

These features are discussed in greater detail inSection 25.0 “Special Features of the CPU”.The clock source frequency (INTOSC direct, INTRCdirect or INTOSC postscaler) is selected by configuringthe IRCF bits of the OSCCON register (page 39).

2.6.1 INTIO MODESUsing the internal oscillator as the clock source elimi-nates the need for up to two external oscillator pins,which can then be used for digital I/O. Two distinctconfigurations are available:

• In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 (see Figure 2-8) for digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6 (see Figure 2-9), both for digital input and output.

FIGURE 2-8: INTIO1 OSCILLATOR MODE

FIGURE 2-9: INTIO2 OSCILLATOR MODE

2.6.2 INTOSC OUTPUT FREQUENCYThe internal oscillator block is calibrated at the factoryto produce an INTOSC output frequency of 8 MHz.

The INTRC oscillator operates independently of theINTOSC source. Any changes in INTOSC acrossvoltage and temperature are not necessarily reflectedby changes in INTRC or vice versa.

2.6.3 OSCTUNE REGISTERThe INTOSC output has been calibrated at thefactory but can be adjusted in the user’s application.This is done by writing to TUN(OSCTUNE) in the OSCTUNE register(Register ).

When the OSCTUNE register is modified, the INTOSCfrequency will begin shifting to the new frequency. TheINTOSC clock will stabilize within 1 ms. Code execu-tion continues during this shift. There is no indicationthat the shift has occurred. The INTRC is not affectedby OSCTUNE.

The OSCTUNE register also implements the INTSRC(OSCTUNE) and PLLEN (OSCTUNE) bits,which control certain features of the internal oscillatorblock. The INTSRC bit allows users to select whichinternal oscillator provides the clock source when the31 kHz frequency option is selected. This is covered ingreater detail in Section 2.7.1 “Oscillator ControlRegister”. The PLLEN bit controls the operation of the PhaseLocked Loop (PLL) in internal oscillator modes (seeFigure 2-10).

FIGURE 2-10: INTOSC AND PLL BLOCK DIAGRAM

PIC18FXXXXOSC2FOSC/4

I/O (OSC1)RA7

PIC18FXXXXI/O (OSC2)RA6

I/O (OSC1)RA7

MU

X

VCO

LoopFilter

OSC2

PLLEN

FINFOUT

SYSCLK

PhaseComparator

8 or 4 MHz

÷4

(OSCTUNE)

MU

X

RA6

CLKO

INTOSC


PIC18F8722 FAMILY2.6.4 PLL IN INTOSC MODESThe 4x Phase Locked Loop (PLL) can be used with theinternal oscillator block to produce faster device clockspeeds than are normally possible with the internaloscillator sources. When enabled, the PLL produces aclock speed of 16 MHz or 32 MHz.

Unlike HSPLL mode, the PLL is controlled throughsoftware. The control bit, PLLEN (OSCTUNE), isused to enable or disable its operation.

The PLL is available when the device is configured touse the internal oscillator block as its primary clocksource (FOSC = 1001 or 1000). Additionally, thePLL will only function when the selected output fre-quency is either 4 MHz or 8 MHz (OSCCON = 111or 110). If both of these conditions are not met, the PLLis disabled and the PLLEN bit remains clear (writes areignored).

2.6.5 INTOSC FREQUENCY DRIFTThe factory calibrates the internal oscillator blockoutput (INTOSC) for 8 MHz. However, this frequencymay drift as VDD or temperature changes and canaffect the controller operation in a variety of ways. It ispossible to adjust the INTOSC frequency by modifyingthe value in the OSCTUNE register. Depending on thedevice, this may have no effect on the INTRC clocksource frequency.

Tuning the INTOSC source requires knowing when tomake the adjustment, in which direction it should bemade and in some cases, how large a change isneeded. Three compensation techniques are discussedin Section 2.6.5.1 “Compensating with theEUSART”, Section 2.6.5.2 “Compensating with theTimers” and Section 2.6.5.3 “Compensating with theCCP Module in Capture Mode” but other techniquesmay be used.

REGISTER 2-1: OSCTUNE: OSCILLATOR TUNING REGISTER

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTSRC PLLEN(1) — TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)0 = 31 kHz device clock derived directly from INTRC internal oscillator

bit 6 PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1)

1 = PLL enabled for INTOSC (4 MHz and 8 MHz only)0 = PLL disabled

bit 5 Unimplemented: Read as ‘0’bit 4-0 TUN: Frequency Tuning bits

01111 = Maximum frequency• •• •00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency.11111 • •• •10000 = Minimum frequency

Note 1: Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as ‘0’. See Section 2.6.4 “PLL in INTOSC Modes” for details.

PIC18F8722 FAMILY


2.6.5.1 Compensating with the EUSART An adjustment may be required when the EUSARTbegins to generate framing errors or receives data witherrors while in Asynchronous mode. Framing errorsindicate that the device clock frequency is too high. Toadjust for this, decrement the value in OSCTUNE toreduce the clock frequency. On the other hand, errorsin data may suggest that the clock speed is too low. Tocompensate, increment OSCTUNE to increase theclock frequency.

2.6.5.2 Compensating with the TimersThis technique compares device clock speed to somereference clock. Two timers may be used; one timer isclocked by the peripheral clock, while the other isclocked by a fixed reference source, such as theTimer1 oscillator.

Both timers are cleared, but the timer clocked by thereference generates interrupts. When an interruptoccurs, the internally clocked timer is read and bothtimers are cleared. If the internally clocked timer valueis much greater than expected, then the internaloscillator block is running too fast. To adjust for this,decrement the OSCTUNE register.

2.6.5.3 Compensating with the CCP Module in Capture Mode

A CCP module can use free running Timer1 (orTimer3), clocked by the internal oscillator block and anexternal event with a known period (i.e., AC powerfrequency). The time of the first event is captured in theCCPRxH:CCPRxL registers and is recorded for uselater. When the second event cause

pic18f8722 family data sheet · 2019. 10. 12. · pic18f8722 family

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