pic

1

Chapter 1.0: Introduction

1.1 Application of research

Power factor is the ratio between the KW and the KVA drawn by an electrical load

where the KW is the actual load power and the KVA is the apparent load power. It is a

measure of how effectively the current is being converted into useful work output and

more particularly is a good indicator of the effect of the load current on the efficiency of

the supply system.

When an electric load has a PF. lower than 1, the apparent power delivered to the load

is greater than the real power that the load consumes. Only the real power is capable of

doing work, but the apparent power determines the amount of current that flows into the

load, for a given load voltage.

All current will causes losses in the supply and distribution system. A load with a power

factor of 1.0 provides most efficient loading of the supply and a load with a power

factor of 0.5 will result in much higher losses in the supply system.

A poor power factor can be the result of a significant phase difference between the

voltage and current at the load terminals. Poor load current phase angle is generally the

result of an inductive load such as an induction motor, power transformer, lighting

ballasts, welder or induction furnace.

2

1.2 Objective of this thesis

An improved power factor AC output is the main target of this project. This project

focuses on the design and implementation of power factor correction using PIC micro-

controller chip, determine the power factor of the loaded power system, generate proper

action to calculate and to pin point adequate capacitor to redeem appropriate power lost

under the project design using MikroC program and finally test or simulate the design

with PIC chip stand individual without interface of personal computer.

1.3 Structure of thesis

This thesis is divided into main six chapters that are literature background, role of

capacitor, different approach of power factor correction, System Design,

implementation & results, future direction and conclusion. The literature background

(chapter 2) discuss about the fundamentals knowledge of power factor and its

applications. While the role of capacitor (chapter 3) is one main component that used to

correct power factor, its relation with power factor and application background are

mainly explain in this chapter.

In meantime, few types of power factor correction methodologies under difference

circumstances are outlined for the present power factor correction methods used in

various approaches (chapter 4). Then next chapter (chapter 5) is the system design of

this project; this section explains the process of how the overall design works using PIC

micro-controller chip. After the explanation of the working principle of the system

design, the testing results and ways of implementation will be analyzed and discussed in

3

chapter 6. Finally, in chapter 7, this thesis ends with conclusion as well as

recommendations for future research.

4

Chapter 2.0: Literature Background

2.1 Power Relation with power factor

It is known that reactive loads such as inductors and capacitors dissipate zero power, yet

the fact that they drop voltage and draw current gives the deceptive impression that they

actually do dissipate power. This "phantom power" is called reactive power, and it is

measured in a unit called Volt-Amps-Reactive (VAR), rather than watts. The

mathematical symbol for reactive power is the capital letter Q. The actual amount of

power being used, or dissipated, in a circuit is called true power, and it is measured in

watts (symbolized by the capital letter P). The combination of reactive power and true

power is called apparent power, and it is the product of a circuit's voltage and current,

without reference to phase angle. Apparent power is measured in the unit of Volt-Amps

(VA) and is symbolized by the capital letter S.

There are several power equations relating the three types of power to resistance,

reactance, and impedance (all using scalar quantities), E here refers as voltage in single-

phase:

θcos×= EIP (real part)

θsin×= EIQ (imaginary part)

jQPQPEIS +=+== 22

⎥⎦

⎤⎢⎣

⎡⎟⎠⎞

⎜⎝⎛==

×== −

PQ

EIEI

SPPF 1tancoscoscos θθ

5

Where, P = Real Power (unit in Watt),

Q = Reactive Power (unit in VAR) and

S = Apparent power (unit in VA)

PF = power factor

For three-phase system, the power equation mostly measure in kilo-unit or Mega-unit,

where ph denotes as phase and L denotes as line. Before attempting to determine the

power factor in three-phase system, there are mainly two ways of loads connection

appears in three-phase power system: wye (or star) connection and delta connection,

that needs to be aware of. (H. Saadat, 1999)

In wye-connection load, (Y)

phL

PhL

IIVV

=

°∠= 303

As for in delta connection, (∆)

°−∠=

=

303 phL

phL

II

VV

And the relationship of wye and delta connection in impedance is as follow.

3∆=

ZZY

6

Thus the power relationship would be

( )∑=

=

×=Nj

jpjph pj

IVN

P1

*3 or ( )∑=

=

×=Nj

jLjL Lj

IVN

P1

*3 with cos θ;

( )∑=

=N

jpjpj IV

NQ

1

*3 or ( )∑ ∗= pjLj IVN

Q 3 with sin θ;

( ) ( )2

1

1

22

1

1

2 113 ⎥⎦

⎤⎢⎣

⎡×⎥

⎦

⎤⎢⎣

⎡×= ∑∑

==

N

jpj

N

jpj I

NV

NS or

( ) ( )2

1

1

22

1

1

2 113 ⎥⎦

⎤⎢⎣

⎡×⎥

⎦

⎤⎢⎣

⎡×= ∑∑

==

N

jpj

N

jLj I

NV

NS

⎥⎦

⎤⎢⎣

⎡==== −

)()(tancoscos 1

kWPkVARQ

kVAkW

SPPF θ

The power equations shown in previous section are in balanced condition. Apparently, a

pure balanced condition is rarely existed but mostly able to draw near to acceptable

range. One of the main reason the results to unbalance are earthed system elements that

leads to current flowing in earthed neutral and earth ground itself is a gigantic

grounding terminal that easily create faulty for electronic circuit if without proper

prevention and taking safety caution.

The equations for unbalanced condition use a, b and c for different loads notation; in

other words, instantaneous power is formed by summation of instantaneous values of

Va, Vb, and Vc multiply with of instantaneous values of current Ia, Ib and Ic.

ccbbaa IVIVIVP ++=

Where, 0=++ cba III

7

Therefore the power expression would be,

Using ( )baC III +−=

( )bacbbaa IIVIVIVP +++=

Or ( ) ( ) bcbaca IVVIVVP ×−+×−=

On using caac VVV −= and cbbc VVV −=

bbcaac IVIVP +=

Therefore with respect of time-series, the expression of real power and reactive power is

as shown below.

( )⎭⎬⎫

⎩⎨⎧

+×= ∑=

=

Nj

jbcjacj bjaj

IVIVN

P1

**1Re

( )⎭⎬⎫

⎩⎨⎧

+×= ∑=

=

∗∗Nj

jbjbcjajacj IVIV

NQ

1

1Im

The apparent power and the power factor calculation would be the same as balanced

condition.

8

2.2 Why power factor correction

As slight explained in the introduction, the existing of reactive power does not included

in the electric bill yet this probably causes dissipation power lost at the load, which

results to an increment of electricity bill charge. Penalty charge is just one of the feature

concerned mostly by electricity user, however there are more other problem occurs if

power factor is low.

• Penalty charge in electric bill;

• Extra losses in feeder cables;

• Significant voltage drop

• reduction of effective capacity of cables

• Reduction in power available at the transformer

• Significant voltage drop at the secondary of the transformer

• Significant losses in transformer

2.2.1 Reasons cause lower power factor

All current will causes losses in the supply and distribution system. A load with a power

factor of 1.0 results in the most efficient loading of the supply and a load with a power

factor of 0.5 will result in much higher losses in the supply system.

A poor power factor can be the result of either a significant phase difference between

the voltage and current at the load terminals, or it can be due to a high harmonic content

or distorted/discontinuous current waveform.

System that has inductors like motors and electronic devices will produce inductive

reactance and thus generate lagging reactive power. The main reason is the current

9

flows within power system. No matter how a power system designed, current will

surely causes loss in both supply and distributed loads. Load with power factor of 1.0

has best efficient of power usage upon the load itself and this can only appear in pure

resistive circuit. A poor power factor appears due to the significant phase difference

between voltages and currents at load terminals are large, which thus gives power factor

value lower than unity (=1).

Unfortunately this is not the only reason that power factor drop. High harmonic or

distorted/discontinuous current waveform will also cause low power factor; however

this is not mainly designed but it will be discussed in chapter 4, which about various

approaches attempt to different kind of power factor failures. System that contains

motor, power transformer, lighting ballasts, welder or induction furnace are the main

reasons that result phase shift in sinusoidal load current. While system that possess

rectifier, variable speed drive, switched mode power supply, discharge lighting or other

electronic load creates harmonics and have high possibility cause current signal to be

distorted or discreet. Simple capacitor bank cannot fix the such problem, a change in

equipment design or expensive harmonic filters are needed to perform further

improvement.

10

2.3 Power factor correction Process

This can be discussed with an example [quote]. Since single-phase is considered one of

the phase in three-phase system when connected in wye-connection, hence the

following calculation procedures would use single-phase scene as base.

Aj

jI

AI

8420100200

02100

0200

2

1

−=+

°∠=

°∠=°∠

=

( )

var1600800)84(0200

var0400020200

22

11

jWjVIS

jWjVIS

+=+×°∠==

+=−×°∠==∗

∗

Total apparent power and current are

A

VSI

VAjjQPS

°−∠=°∠

°−∠==

°∠=+=+=

∗

∗

13.53100200

13.53200013.53200016001200

The power factor vat the source is

( ) 6.013.53cos =°=PF lagging

The main target is to get nearer power factor to unity hence the following action being

done.

I IC

I1 I2

100Ω

10Ω

j20Ω

200V C

11

Total real power remains the same, P = 1200 W with new power factor choose to be

cross to unity, say 0.95 lagging

°== − 19.18)95.0(cos 1newθ

( ) var4.39419.18tan1200tan =°×== newnew PQ θ

var6.12054.3941600 =−=CQ

( )Ω−=== ∗ 18.33

6.1205200 22

jjS

VZ

CC

FC µπ

93.9518.33502

1=

××=

Since there is no exactly 95.93µF, a near capacitor value like 90µF can be chosen with

a slight lower of PF value.

This example pre-determined a desired power factor of 0.95 so getting a nearest PF can

also choose capacitor value of 100µF with PF value is approximately 0.96 (or 96%) but

if a system designed to get as close to unity, it is better to pick a lower capacitor value

to avoid excessive of leading current flow into the line bus. Since unity power factor

gives rise to the greatest utilization of the plant. Electric utilities measure reactive power

used by high demand customers and charge higher rates accordingly.

12

Chapter 3.0: Role of Capacitor

Frequency is standardized at constant 50 Hz, or 60 Hz in other countries; power factor

correction is veiled as a solution to such fixed network frequency, the only key solution

is by addition of capacitor in shunt to the load. Capacitors are commonly used within a

lot of power system, especially electronic constructed circuitry. Though common it is, it

is consequently least understood by majority as one most beneficial component for

power system.

• Release of system capacity

• Reduction of kVAR generation requirements

• Reduction of system loss

• Regulation or improvement in voltage

These benefits require only small amount of investment and maintenance compare to a

lot of power system components. Budgeting expenses itself already a solid reason for

why capacitors are most welcome in many power system.

In three-phase power system, capacitors normally installed within an isolating non-

conductor metal box, which called capacitor bank; they are either fixed or switched.

Fixed banks are connected permanently to the primary conductors through fused

switches. Switched banks are tied to the primary system through automated switches,

allowing them to be put on line and taken off line as needed. Distribution power system

usually connects capacitor in parallel (also called shunt) rather connecting in series.

13

The function of shunt power capacitor is to provide leading (capacitive) kVARs to an

electrical system when and where needed. Lagging (inductive) kVARs appear when

there are inductors (coils) exist within electrical (e.g. motor) or electronic (personal

computer) equipments, as the amount grows, the increment of inductive kVARs will

increase as well, thus the demand of capacitive kVARs to compensate is pretty much

required in order to reduce unnecessary lost. (TVPPA, Distribution Design Guideline)

The actual capacitor in farads of a capacitor bank can be calculated using the following

equation:

22 RVfVARC×

=π

(3-1)

where, VAR = capacitor unit VAR rating

C = capacitor (farads)

f = frequency (cycles/second)

VR = capacitor unit rated voltage

3.1 Relationship of capacitor with power factor

Capacitor is the main component that supplies capacitive reactance, which is negative

reactive power. Since the power factor is the ratio of real power and apparent power,

where apparent power has the relation with reactive power and real power as shown in

the power triangle in figure 3-1. As majority power system has inductive loads thus

normally only lagging power factor occurs hence capacitors are used to compensate by

14

producing leading current to the load to reduce the lagging current, thereby shrink the

phase angle distance between the real power and apparent power.

Figure 3-1: Power triangle

Table 3-1 list a number of common loads appears in general industrial systems and their

typical power factor.

Load Typical Power Factor Incandescent lamps 1.0 Florescent lamps 0.95 – 0.97 Synchronous motors 1.0 to 0.80 leading Squirrel cage motors High speed 0.75 – 0.90 Low speed 0.85 –0.92 Wound rotor 0.80 – 0.90 Induction motors Fractional HP 0.55 – 0.75 1 – 10 HP 0.75 – 0.85 Arc furnace 0.65 – 0.70 Power Converter 0.50 – 0.90

Table 3-1: Typical power factors of end use equipment

3.1.1 Connection Type

In general, power capacitors shall be wye-connected on the three-phase distribution

feeder. Grounding the neutral is essential for the fuses to operate in case of any event of

capacitor fault. For a small ungrounded wye-connected capacitor bank, faulty capacitor

15

would not blow the fuse to isolate faulty capacitor. Any event of this could lead to an

explosion to the capacitor bank.

However, Isolating the neutral of the wye of a capacitor bank has the advantage of

reducing harmonics. (Quote) The method can only be an alternative when grounding the

neutral would cause operating difficulty for a particular installation. In case of

insulation failure inside the unit, phase-to-ground fault can still occurs to an ungrounded

wye capacitor bank even with its enclosure properly grounded.

The most effective solution is to insert reactors in series with each capacitor group

connected between the phase wire and the neutral of a three-phase bank. This method is

used to mitigate any resonant circuit, while reduction of induction triple harmonic

frequency current can be made.

3.2 Determine Size of Capacitor Banks

Standard capacitor sizes are 50, 100, 150, 200, 300 and 400 kVAR. Since three-phase

installations are pretty much the same as single phase installation, which single-phase is

just one of the phase among three phase connection. Of course, the formula for both

phases will be different. Since capacitors can be connected more than one per phase in

order to increase the bank size, it is recommended to select two or at most three

capacitor unit sizes to avoid stocking the sizes. (TVPPA Group, Distribution design

Guidelines)

16

ILAG

Time

Loss reduction = 0%

ILAG MAX

Rective current without capacitor

Loss reduction = 89%

ILAG MAX

Icap

Cap off at ILead Max = (1/3)Icap

Cap off at ILead Max = (2/3)Icap

Reactive current with capacitor (Maximum loss reduction)

Figure 3-2: Reactive current with capacitor (maximum loss reduction)

(TVPPA, Distribute design guidelines)

How much amount of capacitance to install within a bank is considered sufficient? In a

fixed capacitor installation, one should at first determine desired power factor value

before attempting to design one. By installing fixed capacitor can approximately

improve the power factor around 94% to 96%. Higher power factor may only be

acquired with switched capacitor banks.

When using switched capacitor to correct the power factor of a circuit, the switch

control is set to close the bank onto the line when the load kVARs equal two-thirds of

the bank’s rated kVAR. This scheme is tend to reduce loss by driving the line leading

17

with first turn on before it is turn off, this is referred as the “two-thirds rule.” Taking a

daily load cycle as shown in figure 3-2 as example.

Compare with fixed capacitor bank, switching capacitor bank is generally more

expensive thus it is essential to take accounting of the cost of installation so that its time

value worth for the investment.

3.3 Possible Problems Occur in Capacitor Bank

Despite the benefits provided by capacitor bank, there are several possible undesired

events occur in the process of using capacitor bank, which mostly happen when

capacitor performs charge and discharge process.

3.3.1 Switching Counter Strike

In three-phase bank of capacitor connected in wye with neutral grounded, the initial

voltage is practically zero since capacitor on load side of the switch holds the same

instantaneous voltage as existed on the supply side. Since capacitive current leads

voltage by 90°, voltage of capacitor peak and circuit at same value, voltage across the

switch contacts tend to be twice the peak value compare with the fundamental on half

cycle period which capacitor at its moment of full charged and the supply voltage in

meantime reached its peak of opposite value, as shown in figure

18

Figure 3-3: Voltage across switch contacts during the first half cycle.

(TVPPA, Distribution Design Circuit)

For the moment across switch gap, the capacitor voltage will overshoot when attempted

change in voltage in order voltage across the capacitor interrupted leaving three times

its steady state value. Same behavior happens in first current zero as its arc again may

be interrupted leaving three times normal peak voltage on the capacitor. After one-half

cycle, another four times will appear at switch contact as shown in figure 3-4. These

two time periods of overshoot behaviors are the counter striking back to the circuit,

therefore sufficiently separation between contacts or else a counter strike across switch

gaps will occurs. Proper steps like choice of switching devices and component like

diode that only allow one way current flow to protect controlling circuit from counter

striking.

T1T0 T2 T3

2EC across switch

contacts

Capacitor Voltage To = Beginning of switching opening; T1 = First current zero; T2 = ½ cycle after first current zero; T3 = switch completely opened.

Voltage

Current

19

Figure 3-4: A strike caused by difference of capacitor voltage and line voltage.

(TVPPA, Distribution Design Guideline)

3.3.2 Harmonic Problem

Increment of power electronic devices had drawn attention of high concern with

harmonics level. Capacitors individual does not cause harmonic current; however, the

rising of frequency when capacitive impedance drop will results harmonics generation

and affecting the magnitude of voltages and currents within the buses, especially when

capacitor banks connected in grounded wye to earth.

It is advised that capacitor bank should be placed at somewhere with proper distance

based on pre-defined desire power factor, rated voltage, etc with the actual system.

Another method is use ungrounded wye connection, this will prevent harmonic

4 EC switch contacts after counter strike

Bus voltage

Voltage

C

Counter Strike

20

produces but careful study of capacitor switches to prevent switching counter attack and

capacitor bank short circuit protection.

For small capacitor bank, connecting in delta formation also have the same effect but

make sure proper discharge function must be installed, like connecting resistors in

between line-to-line of the three-phase delta-connected capacitor; nevertheless, the

switching effect problem must still be cautioned.

21

Chapter 4.0: Different Approaches of PFC

In the precious chapter, the method that directly used of capacitor to correct power

factor as discussed in section 2.3 only applicable when current waveform was nearly

perfect sine wave. There are nowadays many power systems contains complicated

power electronic components or drives systems, such as converters, inverters, variable

drives system, etc; these types of power systems would mostly distort current waveform

or produce discreet signal output. Therefore this chapter will briefly converse about

different type of approaches apply in power factor correction for various type of

electrical power systems.

This chapter mainly categorized into two major types of power factor collecting circuit

methodologies. The first category is called the passive power factor correction, which

usually more reliable, inexpensive and typically improves power factor value up to a

maximum of 80%; while the second category that generally more effective and able to

achieve over 95% of corrected power factor is called the active power factor correction

method, this types generally integrated with switch-mode power supply. (Power factor,

LM Photonics Ltd.)

4.1 Passive PFC

Passive power factor correction is quite common in many distribution power system, it

mainly use capacitive filter (or fixed capacitors) to generate leading reactive current to

correct poor power factor. The initial setting of the AC input voltage will determine the

22

amount of capacitive filter needed for the power system and all this being done

manually. This type of power factor correction is practically sufficient enough for

system that had planned not to be altered much at the input for long time; and certainly

it is comparatively cheap compare to active PFC, which would be discussed in section

4.2. Generally, the desired power factor value is pre-calculated and selects sufficient

capacitors to perform constant power factor correction. However, passive PFC may be

affected when environmental vibration occurs and it cannot fully utilise the energy

potential of the AC line. [1]

Certainly that passive PFC can only apply to general power system that acquires pure

sinusoidal voltage and current waveforms. For sophisticate power electronic systems

that easily affected by harmonic distortion, active PFC is a better choice for long term

investment.

4.2 Active PFC

Active power factor is more preferable since it capable in providing more efficient

power frequency by diminishing total harmonics and phase different in between input

current and input voltage. Majority of active power factor are circuits built integrate

with the switched mode power supply, using IC and other active elements like diode

and FET. Follow ahead of this sector are introduction of few types of active PFC.

The effect of harmonic distortion makes many advanced systems suffer with lower

power factor as by normal mean of power factor correction method cannot solve the

problem as current might not even have the shape of sine wave. A diagram in figure 4-1

23

shows what exactly happen to the distorted current compares with perfect sinusoidal

current waveform.

Figure 4-1: Voltage and current waveform behavior

I represents the fundamental current out of phase in sine wave in an angle difference, θ;

while I’ is the actual current waveform. In other word, passive PFC circuit only capable

to correct poor power factor when only I exist in the power system, but if instead I’

occur then the corrected power factor using passive PFC circuit would not be precise;

losses and weak performance still remain yet power factor might read as 0.9 but instead

it is actually lower to 0.6. As a result, active PFC is developed to overcome the above

circumstances.

4.2.1 Basic converter topology switch mode PFC

The following are six types of single-phase switching converter-based active power

factor correction circuits: Buck, boost, buck-boost, flyback, cuk and sepic.

24

Figure 4-2: Converter types of PFC

(a) Buck, (b) Boost, (c) Buck-Boost, (d) Flyback, (e) Cuk and (f) Sepic

The buck converter type circuit in figure 4-2(a) able to take in discontinuous current and

supply continuous current. Despite it can supply lower voltage from the input voltage, it

cannot convert a higher voltage when needed; harmonic current distortion would occur

if input voltage is lower than certain range, plus the input current intake is

discontinuous, thus it does not suit to AC/DC converting system. As for the boost

converter circuit in figure 4-2 (b), the working principle is just the opposite of buck

converter PFC circuit. The intake current is continuous while the output is

discontinuous. Since the input voltage can directly control the switching, it is practically

able to obtain near unity power factor. Of course, it can only produce constantly high

25

voltage output. This type of PFC converter is the most popular topology used in switch

mode power factor collection circuit.

Next is the buck-boost converter topology in figure 4-2 (c). This type of converter

allows stepping up or down voltage input, the polarity is opposite compare with the

output voltage. Unfortunately the current supply to the circuit is discontinuous and peak

current tend to bypass switching component, thus create harmonic, a harmonic filter is

needed. The fly-back type isolates both input and output terminal and the circuit

operation works under discreet current manner to control the switching hence normally

when used for system that aim for higher power factor and low harmonic distortion

would tend to install filters to increase switching speed, yet may reduce the overall

efficiency and require additional EMI filter. This type of switch mode PFC is suitable

for high voltage but low power system, which generally used for assisting high power

converter.

As shown in figure 4-2 (e), the circuit structure of cuk topology pretty much the same

behaviour as buck-boost topology, only lesser components. The sepic is the simplified

version of buck-boost with two switching control and continuous input current that able

to correct power factor to near unity. Each of these six types of converters PFC circuits

has their own advantages and disadvantages, taking concern of discontinuous

conduction mode (DCM), the distinguish power factor correction performance are

outlined in table 4-1.

26

Basic Converters Input current waveform Effect of DCM power factor correction

Buck

Less effective

Boost

Good

Buck-Boost

Best

Fly-back

Best

Cuk and Sepic

Less effective

Table 4-1: Converter base switch-mode PFC circuits attributes

27

4.2.2 Dither, Half-Bridge and Full-Bridge type PFC circuits

Figure 4-3: Dual and more switching mode PFC circuits

(a) Dither circuit, (b) half-bridge circuit, and (c) full-bridge circuit.

The converter based switch mode PFC in section 4.2.1 can only allow one way flow and

low power system. This section will introduce three types of bidirectional control

switch mode PFC circuits, there are dither, half-bridge and full bridge circuits.

The dither topology shown in figure 4-3 (a) uses two switches to perform switching

operation, where S1 and D1 take charge in correcting positive half cycle of waveform,

while S2 and D2 working on the negative portion. Such circuit commonly placed before

28

an electronic circuit for power factor improvement. The only problem exists in this

circuit is when voltage crossing zero, harmonic appears as the voltage difference

between the switching are too small thus results the current waveform cannot maintain

perfect sine wave at that particular portion.

The half-bridge circuit in figure 4-3 (b) also has two control switches with two

capacitors. Similar with the dither topology, S1 and D1 perform correction at the

positive half cycle while S2 and D2 responsible for the negative half. Due to this circuit

has only one semiconductor component, the amount of power lost is relatively small,

plus it has two supportive capacitors so it is very suitable for supplying high voltage and

bidirectional source design.

As for the full-bridge circuit in figure 4-3 (c), there are altogether four control switches

that allows complete control of the waveform with the same working principle as the

previous two circuits. S2, S3 working as D1, D4 for positive half cycle, and S1, S4 as D2,

D3 for negative half cycle. Since the full-bridge topology constructs with extra two

control switches hence it is naturally cost higher and complicated to build one but in

return, its ability to reduce total harmonic distortion down to the lowest extend and no

distorted current appears at zero crossing like what happen in the dither topology. This

is because in full-bridge topology has wider potential difference at zero-crossing hence

the current able to catch up with the proper sine wave shaping.

A comparison summary of the nine switch-modes is displayed in table 4-2.

29

Converter Type Circuit Structures Characteristic Single switch mode Buck

Boost Buck-boost

Fly-back Cuk

Sepic

1. Easy control 2. Current flow only one way 3. Only suitable with low power system

Double switches mode

Dither boost Half-bridge

1. Power can be transferred bidirectional however Capacitive Voltage might appear unstable.

2. Suitable for medium and low power supply system

Four switching mode

Full-bridge 1. Complicated, high cost 2. Dual direction transfer 3. Typically suits for high power

transmission. Table 4-2: Summary of nine converters PFC circuits general characteristics.

4.2.3 PFC control in switch-mode converter topology

Though out the basic analysis of power converter topology type of PFC, it is well

understood that the converter circuit such as boost converter, which able to perform

conversion upon continuous current, has less electromagnetic interference, voltage

control switching so that waveform able to maintain according to the original sinusoidal

waveform, hence its power factor manage to reach near unity. Typically boost converter

type PFC is quite famous with its simple design construction and far superior in

correcting power factor for small voltage. Therefore using boost converter topology as

base for explanation for the type of PFC control undertaking in general power converter

based PFC circuits.

The main target to carry out power factor correction is divided into continuous

conduction mode (CCM) and discontinuous conduction mode (DCM). If a design able

to control both modes simultaneously, the efficiency might boost to certain extreme.

However DCM is not commonly applied to many systems and meanwhile CCM has the

30

following benefits that determine its superiority compared to DCM, which thus DCM is

normally omitted when designing one:

1. Able to obtain higher power factor value and lower EMI.

2. Able to use smaller output capacitor and high power density.

3. Also able to be used in high power system.

31

Chapter 5.0: System Design and Structure

5.1 Main equipment Description

Programmable Interface Circuit chip, short form named PIC chip; it is the Microchip

Technologies’ series of micro controller. In other word, PIC is a type inexpensive

single-chip computer that confines integrated circuit within it. Basically, it looks like a

standard personal computer, which contains a CPU (central processing unit), RAM

(Random-access memory), ROM (Read-only memory), I/O (input/output) lines, serial

and parallel ports, timer, internal oscillator, and even built-in peripherals such as A/D

(analogue-to-digital) and D/A (Digital-to-analogue) converters, sample/holder (S/H);

more advanced features can be found in the latest series of PIC chip. The PIC used in

this project is PIC16F777, which contains comparator function.

Such chip is programmed via a PIC programmer board (K8048) interfaces with personal

computer using MikroC programmer and WinPIC programmer both freeware. The

MikroC programming software is a programming software recognized by Microchip

Cooperate.

32

Figure 5-2: K8048 Programmer Board

5.2 Circuit Designs

The design aims to monitor phase angle continuously and in the event of phase angle

deviation, a correction action is initialized to compensate for this difference by

continuous changing variable capacitors value via switching process. The overall

system requires the only one PIC chip, few power electronic components and a bank of

capacitors. Figure 5-2 shows the hardware block diagram layout of the overall system.

33

Figure 5-2: Overview of design system

5.2.1 Sensors

The alternative voltage and current signals are both sensed and scared down using

sensors, while the current is converted into an equivalent voltage representation. The

sensing devices used to detect the voltage signal are a LV 25-P and LA 55-P. LV 25-P

is a type of voltage transducer that able to read both DC and AC signal by converting

the captured signal into smaller scale with ratio of 2500:1000; while LA 55-P is a

current transducer that scares down input signal with ratio of 1:1000. These two devices

can only be used if ± 12V…15V is supplied. The devices appearances are displayed in

figure 5-3.

It is essential to take caution that PIC chip can only take in certain range of input

voltage, either the range of 0 to 5V with current limiting to 20mA, or higher range of

voltage reading with condition that current limited within range of micro (µ) unit. In

other word, the total power dissipated within the PIC chip must not exceed 1W. The

power dissipation is calculated using the following formula.

Main C

omputation Procedure

Sensors Determine phase angle and command proper action for correction

Zero-Crossing Detector

V I

Switching D

rivers

……

…

Capacitor B

ank

Power Factor

improved

AD

C

S/H system

PIC16F777 Chip

34

( ) ( )[ ] ( )∑∑∑ ×+×−+−×= OLOLOHOHDDOHDDDDdiss IVIVVIIVP

Figure 5-3: Voltage and Current Sensors

5.2.2 Zero crossing detector

The sensed signals transfer into zero-crossing detecting procedure. Originally, zero

crossing can be detected using a specific design circuit; a simple zero-crossing detector

circuit sample is shown in figure 5-4. However such design cannot apply when input

voltage is too low, the output pulses tend to be distorted; a simulated result shows in

figure 5-5 and figure 5-6 that describe the drawback of this circuit. This is merely

simulation, the actual output also being tested and discovered that the output waveform

was even distorted.

Figure 5-4: Typical sample of zero-crossing detector circuit

35

When input voltage = 110V.

Figure 5-5: Output pulses when input AC supply voltage high enough

When input voltage = 5V

Figure 5-6: Output pulses when AC supply voltage is low

36

Figure 5-7: PIC chip interface zero-crossing detector

The approached were constructed into actual circuit in figure B-4 of appendix B and

proven the circuit are relatively hard to work fine practically. Such problem can be

solved directly by inserting the input voltage and current signal into the PIC chip with

proper component used to prevent damage to the microchip.

It is mentioned that as far as PIC chip is within 1W power dissipation, high alternating

input voltage are acceptable by the chip input pins. For that, a high external resistor

must be placed before the pin in order to ensure very low current supply into it. A

typical input AC voltage, 50 Hz, sine wave will definitely cross from 0 to 2V; therefore

a threshold around 1V will allow zero-crossing detection accuracy around 32µs. The

external resistor, say 5MΩ with 110V applied to the pin will limit the current to 38µA,

such limited current is definitely within the safety margin of the PIC chip requirement.

Further more, in order to make sure the chip’s safety, a diode is connected between the

pin and the resistor to clip out negative portion of the sinusoidal AC input, this is

because most of PIC chip pins can only accept input voltage of -0.3V to (VDD + 0.3V)

with respect to VSS.

37

Figure 5-8: Zero-crossing detecting waveform using PIC interface

(a) Input AC signal; (b) Input AC signal across diode; (c) Extract digital square wave input signal with comparator then invert it; (d) Using interrupt to capture the very moment when signal rise.

The above was external installation of the zero-crossing detecting process, the internal

working process of the chip is mainly control using software programmed into it. By

using an existing unique function in PIC16F777 – the comparator; it is a module that

able to perform threshold comparison by either using certain fraction the on-chip

voltage – VDD or supply an external voltage as voltage reference, hence a square wave

output is then generated according to the reference threshold voltage. When a rise signal

38

is detected, the software creates an interrupt and directly store into the RAM for later

phase angle calculation, the capture of interrupt work like a pulse generated at the very

moment when the waveform cross below the threshold voltage. Even though the overall

process will certainly have some delay within the system however it will be small and

would not affect much upon the actual reading. An expecting zero-crossing signal

detecting output is shown in figure 5-8.

5.2.3 ADC and shunt capacitor bank

Conversion of analogue to digital is done within the PIC chip. Such process is done

automatically as PIC chip can only produce digital outputs; the intelligence of the

microchip provides a cinch to PIC programming user, who wants to deliver digital

pulses at output pin. The main task for this section is proper allocation of the output

signal to trigger sufficient shunt capacitors to compensate with leading VAR so that to

improve the connected power system with loads. The overall working principle is

discussed in the flow chart in section 5.3.3

5.3 Design Flow Chart

The designed programs that operate internally in PIC chip are presenting in flow chart

presentation with detail explanations to gain in depth view for this project.

5.3.1 Zero-crossing Detecting Module

As reference in figure 5-8, it was the expecting output pulses of what the following

module should get. Actually the input signal can be rectified into full wave rectified

output using a four diodes bridge circuit but in order to simplify the work for capturing

39

signals between voltage and current since there is possibility that voltage half cycle

might cross zero point before current signal does, it is preferable to block the negative

portion of the sinusoidal signals.

Figure 5-9: Flow chart for zero crossing detector

40

The self-designed zero crossing detector gives priority to detect voltage signal with a

slight delay at beginning so that to ensure the first signal capture would have higher

possibility to detect at crossing zero position instead of somewhere in the middle of

rising edge. With comparator function in the PIC16F777 chip, setting a threshold

voltage of approximate 0.4V using the following equation to extract certain ratio of VDD

as reference voltage as a representation of the threshold voltage.

vefDD CVCVR=×

24

Where, CVR = Comparator reference supply voltage

Cref = Comparator reference voltage (threshold voltage)

Taking CVR = 0010, which equivalent to 2 of decimal as CVR. (2/24) × 5 = 0.41677 V.

Once the threshold voltage is set, the comparator will continuously trace input voltage

and current signals on and on, two trains of pulses with respect to timer are stored into

RAM stacks. Whenever a pulse were created and stored, a flag would trigger so that to

keep track with general clock timer. The voltage flag will continue shooting until the

current flag is detected and stored into RAM as well, then both flags would reset and

begin another round of detection.

41

5.3.2 Phase Angle Computation Module

Figure 5-10: Flow chart for phase angle computation module

After the process of locating the zero crossing positions, determine the phase angle

difference under pure sinusoidal current is now possible. Figure 5-10 is the flow chart

diagram of the phase angle computation.

42

The zero-crossing module sends stored signals into this function module, using general

clock as the main division of two timers. The flags captured in previous mode stored up

records of flag running in term of times. Prior setting of frequency for this system is

8MHz. So the total time interval is

msf

T 125.010811

6 =×

==

Say time difference recorded is 0.025ms, hence the phase angle difference would be

610005.0 ×=−= timevoltagetimecurrentdifferenceTime

02.010125.010005.0

6

6

=××

=elapsedTime

°=°×= 4.1436004.0anglePhase (lagging)

Hence, the power factor, %86.969686.0)1.14cos(cos ==°== θpf

Since most system are lagging in general, thus if current time found to be lower than

voltage, it will reset the system and start all over again.

43

5.3.3 Capacitor bank switching control module

Figure 5-11: Flow chart for Capacitor bank control module

As the power factor has been determine, applied with appropriate mathematic

calculation, the amount of capacitor required to aim for higher power factor output can

44

be found. The mathematic calculating process shall be discussed in the next chapter

with actual reading

The capacitor bank control module is used to decide how many stages of capacitors

should be activated. For a mathematic computed capacitor value, the system will start

comparing that value with the bank stage by stage starting from the lower and smallest

capacitor value. The first detect is if the system is turned on or not, if nothing connected

to the PFC system, this module will order all capacitors to be disconnected and

discharged via the resistors installed in the circuit. Such process done by using the max

capacitor value in the bank deduct the wanted capacitor value, the system will turn all

drivers off if found that the capacitor bank value is the same of the leftover capacitor

value after deduction, then it is confirmed there are no inductive reactance occurs in the

power system or system is remained off.

The way to find out how much capacitor is actually needed for the power system

through the working process of this module, is deduct starting capacitor stages if the

capacitor value is lower than the maximum amount; such process continue until the

required capacitive value of the bank match or close to the wanting value as computed.

An extra feature is to detect how many stage are actually installed into the system, the

remaining available capacitors will continue perform the same process with extra

detection for remaining capacitor in the bank. Note that the minimum installation for

this module is at least three stages.

45

Chapter 6.0: Implementation & Results

6.1 Implementation procedures and target results

The idea is to connect to two types of power system – single-phase and three-phase,

with existence of inductive reactance one at a time in order to test how accurate and

efficient the designed circuit ability to correct the power factor. The level of

improvement and faults would be recorded. For an ideal expectation, the designed

circuit should be able to detect the initial power factor correctly with near zero

uncertainty for each type of assigned power system, which here used a single-phase

power generator with inductor loads and an AC motor. The first testing stage was tested

with fixed inputs.

The next step was to determine the system sensitivity through generate various kind of

inputs. For both single-phase and three-phases power systems, each was tuned up and

down of its input voltage value with reasonable range or varied the loads

simultaneously within a period of time so that to test how sensitive the designed circuit

capable to detect the power factor of the system. With each two major experiment, the

final goal was automatic correcting power factor after extracted power factor and other

necessary parameters information; the improved power factor value would be jobbed

down; since collecting power factor involves capacitor switching and the how much

power factor being improved depends on the amount of capacitor in use hence pre-

calculation is needed for testing purposes.

46

Figure 6-1: Test setting for zero-crossing detector

6.2 Implemented results and discussions

The system design implementation and testing were being divided into three major

parts: Test on zero-crossing detector, test on fixed input system and finally test on a

various inputs system. Since the power factor reading test is different for both single-

phase and three-phase, thus individual testing was carried out in two different sections.

Follow by then is correcting the power factor and this process also distributed in the last

two sub-chapters.

6.2.1 Test on zero-crossing detector module

Figure 6-1 shows the structural configuration to run a test upon the zero-crossing

detector module. Using a model, INSTEK GFG-8020H signal generator to supply a

frequency of 50 Hz and 5V into the PIC microchip at PIN number 2 then set an external

reference voltage using power supply to provides constant DC voltage into PIN number

5, observed the output signal via oscilloscope (model TDS 1012). It should be cautioned

not to over tunning the input voltage more that 5V.

Input voltage signal

Reference voltage

Signal output to oscilloscope

(1) (2) (3)

47

All groundings were connected together with VSS. Meanwhile, the oscilloscope first

channel probe were attached to the input voltage signal port (1) before diode and the

channel two attached to port (1) after diode to find out if the sinusoidal signal were

really clipped the negative portions, then attached to port (3) to monitor the output

waveforms.

Figure 6-2 shows the testing results observed through the oscilloscope. In figure 6-2 (a),

the channel 1 displayed a complete sinusoidal signal while channel 2 was outcome of

input voltage after bypassed the diode before entering into pin port (1), the diode

clipped the negative portion of the sine waveform so that to prevent PIC take in

excessive negative voltage; at the same time, it itself drained some voltage hence

channel 2 waveform was slightly lower. Make sure a shunt resistor of any value must be

connected after the diode and link to ground, this will prevent harmonic appears.

Before obtained the output waveform in figure 6-2 (b), it should be aware that pin 6,

which is RA4 is an open drain output that pull down output signal, thus a pull up

resistor is needed by connecting it to VDD then able come out with desired output. The

DC power supply was connected to port (2) and supplied a reference voltage as

threshold voltage, which is lower than 5V. The reference voltage supplied into port (2)

were 3.74V hence the bandwidth of the square wave rising pulse train was very small.

In order to locate precise zero-crossing point, the threshold voltage were reduced until

reaching approximately 0.524 V before null, the rising edges and falling edges were

almost perfectly drop on every zero points, this are clearly displayed in figure 6-2 (c).

48

Output waveform in figure 6-2 (c) was actually sufficient enough to apply into the

program coding to run the rest of the experiments. However this may not be a satisfied

result compare with the simulated result in figure 5-5, so a slight modification in the

programming code was done using the capture module setting as follow to capture

every finite moment of rising edges and falling edges, a train of perfect zero-crossing

pulses are demonstrated via oscilloscope as shown in figure 6-2 (d).

PIE1 = 0b00000101; // Enable CCP1 & TMR1 overflow interrupt

PIE2 = 0b01000001; // Enable CCP2

CCP1CON = 0b00000101; // Detect every rising edge for voltage

CCP2CON = 0b00000101; // Detect every rising edge for current

Figure 6-3 displays the actual circuit wiring while running the zero-crossing detecting

test after the results demonstrated.

Figure 6-2 (a): Voltage output after diode at the input port.

Output voltage

Input voltage

49

Figure 6.2 (b): Output voltage with VREF = 3.74V

Figure 6.2 (c): Output voltage with VREF = 0.524V

VREF = 3.74V

Output voltage

VREF = 0.524V

Output voltage

50

Figure 6-2 (d): Output voltage after apply capture mode with VREF = 0.5247

Figure 6-3: Actual circuit wiring, the labeling determine the position of results

VREF = 0.524V

Output voltage pulse

(a)

(b) – (d)

51

6.2.2 Test on phase angle detection

This was attempted using an existing induction motor based device – home table fan.

The table fan was connected with an oscilloscope for monitoring the waveforms, a

sensors box (both current transducer and voltage transducer are built inside), and DC

power supply to provide threshold voltage to the PIC. A typical picture is shown in

figure B-6 of appendix B.

The power factor measured for the table fan were quite high, around 0.99234, even

increased its load to the level 3 of its fan rotation. Hence calibration was needed to

obtain a clear view upon the phase changes. During the testing process, the designed

sensor used to test was having a major problem to determine the output. This was

because the converting ratio for the current sensor is 1:1000; while the current exist in

the table were only 0.03A, which after converted would be 30µA. Bypassing with some

resistors and converted into voltage value was not even exceed 0.04 V, such voltage

level would definitely cannot even passed through the diode, which has voltage drop of

0.7V.

The solution was using an operational amplifier - model UA741CP to boost up the input

so that it can be view on screen. A clear picture is shown in figure 6-4 of how the circuit

were connected. The operational amplifier not only serves to amplify the current input

but also can work as a system calibrator. This was a great help for future developing of

the system as the clearly shown the delay occurred in the designed system hence proper

calibration can be done to make the system more perfect.

52

Figure 6-4: Circuit constructed to test phase angle.

The test was simple after solving the problem of low input reading, simply pressed the

button from 0 ~ 3 to observe the changes in phase difference. The LEDs were used to

run a prior test for the next section. The leftmost LED was just used to find out if the

system was running. The red LED was with highest PF – button 1 then follow by button

2 and button 3; the oscilloscope also presented the results as displayed in figure 6-5(a)-

(d). The reason was to run experiment that phase angle can direct affecting the output

without concerning the reactive power. The digital time step differences for PIC to

identify the button were calculated using the following equation:

ns

timeindifferencephasemeasuredsteptime500

= (6 – 1)

Op-Amp

Diode

LEDs correspond to fan buttons

Current input

Voltage input

Voltage (left) and current (right) outputs

53

Figure 6-5 (a): When no button (or button 0) was pressed

Figure 6-5 (b) When button number 1 was pressed

Voltage output

Current output = 0V

Current output

Voltage output

54

Figure 6-5 (c): When button 2 was pressed.

Figure 6-5 (d): When button 3 was pressed.

Current output

Voltage output

Current output

Voltage output

55

Figure 6-4: Block diagram of power factor corretion testing process

6.2.3 Test on fixed input AC power system

6.2.3.1 Single-phase system test procedure

The single-phase fixed input AC power system test is by using an AC voltage regulator

supply unit and applies some loads onto it – resistors and inductor. The frequency of the

supply unit is 50Hz, which directly extracts from normal electrical socket. A typical

testing module was built according to the block diagram as shown in figure 6-4, with

supportive measuring tools to check and to verify the testing outputs with respect to the

PIC chip. The single-phase voltage generator can supply up to 240VAC, but it is a type

that can only be regulated manually by twisting the knob, where percentage values are

labelled on it. The same device will then be used for various inputs test as well.

The first test was supplying a fixed input voltage around 100VAC with different loads.

The main parameters that required determining are: measured phase angles, actual

power factor values, corrected power factor values, number of capacitors triggered.

PIC16F777 phase angle measuring

Single-phase power supply unit

+ Inductive loads

PIC16F777 pf c control process

Capacitor bank

Lab measuring tools

Represents comparison and checking readings

56

Record and tabulate the retrieved parameters into tables and plotting graph to view the

system efficiency.

In this section of testing was with the program to execute power factor correction

process. Unlike the second phase program, the first phase using timer1 as register to

store temporary data. There is a critical situation must a PIC programmer be aware of,

although timer1 is being used as a temporary storage register but it is still a timer that

will continuously running increment until it reaches its limit and overflow, consequently

reset. If programmer ignore this, there are chances that the program being restarted

before finish. Some calculation is needed to avoid the above consequences.

The settling frequency in the PIC oscillator = 8MHz

Only quarter will be used, thus FOSC = 66

1024108

×=× = 2 MHz

For timer1 is a 16-bits register, so 65536216 =

Hence total available time for timer1 to run 1 cycle is

ms768.32sec035768.0102

655366 ==

×

So long the program can accomplish its job that required timer1 before it reset, else the

result retrieved would definitely wrong.

6.2.3.2 Three-phase system test procedure

A three-phase induction motor through an electrical test bed would be a suitable testing

apparatus. It is assumed that unbalance condition is very minute hence the phase angle

differences are technically the same in each line, hence the PFC system would only read

57

a single line current and a line voltage out of the three lines then work out appropriate

calculation to perform suitable power factor correction process. Such assumption were

made because the modules used within microchip, as well as the programmed code

were only capable to take in two inputs for zero-crossing detection and comparison,

hence the parameters to be tested will be the same as single phase, only that the

calculation would be different than the single phase calculation.

6.2.3.3 Overall tested result for fixed input

Although calibration was made during testing with phase angle detection in section

6.2.2 in order to ensure the system run smooth in the rest of testing, however such

attempt still unable to guarantee a nice output; calibration is still needed. Figure B-7 of

appendix B was photo taken for running the test of this section.

Due to insufficient of time proceeding detail testing, the testing stage was done through

observation of LED. The first attempt was supplying 101 VAC to the load of 210 Ω

resistor from the resistive loading bank and 0.67H from the inductive loading bank,

series connection. The calculation below determines the power factor value:

Given HL

RVin

67.0210

0100

=Ω=

°∠=

( )49.210210

67.0502210jj

jXRZ LTotal

+=×××+=

+=π

°−∠=°∠

°∠=

+°∠

== 06.453397.006.4533.297

010049.210210

0101jZ

VIT

%63.707063.006.45cos ===∴PF

58

Supposing the amount of LED lit should be five pieces but the instead it was only three.

Adjustment were made by increasing the threshold of the operational amplifier, also

slight tuning at the PIC threshold voltage. Finally, it was managed to secure up to five

LED but the threshold for operational amplifier seem to be at its limit because if further

increase will lose the signal; hence it was discovered that LED number five kept on

blinking with approximately 4 to 6 seconds each.

A second trial was using two parallel resistors and 4 parallel inductors connected in

series with the source.

%40.89894.0618.26cos

618.268599.06225.52105

1016225.52105

6225.5249.210//49.210//49.210//49.210105210//210

===

−∠=+

==

+=+===

Ω==

PFjZ

VI

jLRZjjjjjL

R

T

T

With calibration done, two LED were lit but the third were slightly blinking as 0.89 PF

is almost 0.90. As a result, the system running considered quite satisfied; it was regret

that unable to construct the capacitor switching. The idea was suppose to drive a

MOSFET directly from the output pins then into the relay to draw connection with the

capacitor banks link with the electric bus.

Since the same application can be assumed applicable in three-phase system wye-

system, hence with the least amount of time in hand, it was suspect it can work quite

well the three-phase system as well.

59

6.2.4 Test on various inputs

This test main concern is the sensitivity of the designed system. The testing process is to

test how fast the system can react when power supply behaves like an emergency power

supply. In other word, the power supply would vary its input in ascending order or

descending order or triggering up and down; certainly this would be done manually.

This part was task for the second phase of the programmed code and testing with the

same appliances used in section 6.2.2.

Unfortunately the desired output cannot be implementing as PIC chip cannot cope with

the changes made. Whenever there were changes made, the power factor reading lost

somewhere, it was suspected that few looping functions within the code were messed

when different voltage inputs supplied. Due to limitation of time, amendment seems

impossible. The second reason, PIC16F777 has no EEPROM to keep history on track;

the timer1 in section 6.2.2 can only perform counting one at a time, if an unpredicted

change appeared just in the middle while detecting phase angle is processing; it will get

a wrong reading or become never ending loop, as a result system completely crashed.

With EEPROM, data storage can perform precise comparison and by averaging the past

results to get power factor to a nearer and reasonable range if system is unstable.

6.3 Review of goals

The tests on fixed voltage input with different loads were considered 60% success

provided the condition that pre-calculation of desired power factor value and supplies

enough shunt capacitors of same value. So far the system only designed of capable to

run switching on maximum 8 stages of capacitors.

60

The various voltage inputs test was not able to accomplish its task however it can be

improved with PIC chip that have EEPROM. If necessary, an external crystal can be

used to rise the clocking frequency thus able to perform a lot of arithmetic calculation,

as well as avoid bus congestion.

61

Chapter 7.0: Future Direction and Conclusion

The testing process did not run test on power converter based systems or synchronous

motor due to required huge amount of expense may need to further enhance the system

to such feature, financial is a critical issue upon further enhancement. Besides, as

discuss in chapter 3 and chapter 4, systems that contain serious harmonic current or ill

non-sinusoidal current would mostly exist in power system with a lot of active

elements.

The final result was not quite the desired output but the idea of making one workable

simple PIC-based power factor correction with the developed system is absolutely

possible.

7.1 Future Direction

In chapter 4 mentioned about power factor correction can be constructed with many and

better approach; as this project did not focus on power system with distorted current or

non-linear waveform system, it is a good idea to further study and getting in depth

knowledge to achieve a better type of power factor corrector using the PIC. The idea of

using converter in for the active power factor circuit was because it can regenerate the

current waveform by amplifier and smoothen it through converter system; such action

with detail understand might can be done with software calibration as well as using PIC

chip to perform suitable control along the circuit. In the present technology, PIC mostly

used as switching control for mainly switched-mode distribution power system,

62

however the increment of green energy had turn the focal point towards renewable

energy and until present era, renewable energy still facing serious problem with poor

power quality, which low power factor is one of the main reasons.

As a result, many firms spent a lot of investment to solve the problem. PIC chip is a

good example of financial solution as one single chip can nearly do everything plus it

only consume very low voltage supply.

63

References

H. Saadat, “Power System Analysis”, Mc Graw Hill, US, 1999. TVPPA group, “Distribution Design Guidelines, Chapter 8 – Capacitors”, pp 256-295,

Booth & Associates Inc., Alexander Publications. ‘FAQ: What is power factor’ 2006. Retrieved 04 July 2006, from

http://www.endpcnoise.com/cgi-bin/e/faqpfc.html

J. M. Bourgeois, ‘Circuit for power factor correction with regards to mains filtering’,

STMicroelectronics, Italy. Retrieved August 23rd, 2006 from http://www.st.com/stonline/products/literature/an/3727.htm

M. Chin 2005, ‘ Power Fundamentals & Recommendations’, pp 5-7, SPCR. Retrieved

September 1st, 2006 from http://www.silentpcreview.com/article28-page5.html ‘K8048 Velleman Board Datasheet’. Retrieved March 10th, 2006, from

http://dev.kewl.org/k8048/k8048/ ‘Power Factor’, LM Photonics Ltd. Retrieved September 8th, 2006 from

http://www.lmphotonics.com/pwrfact.htm ‘Lesson in Electric Circuits – Volume 11, Power Factor ’, Chapter 11. Retrieved May

18th, 2006 from http://www.ibiblio.org/obp/electricCircuits/AC/AC_11.html ‘AN220 – Watt-Hour Meter using PIC16C923 and CS5460’. Retrieved June 5th, 2006

from http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function

‘AN939 – Designing Energy Meter with PIC16F873A’ Retrieved July 25th, 2006 from

http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function

‘AN521 – Interfacing to AC Power lines’. Retrieved August 27th, 2006 from

http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=1469&filter1=function

64

Appendix A

Program Code

unsigned int Iph;

int ph_diff;

unsigned short x1, x2;

void main ()

OSCCON = 0b01110000; // Use 8MHz

ADCON1 &= 0b11110000; // Clear PCFG0~3 Pins

ADCON1 |= 0b00001011; // RA0-RA3 analogue, RA4-RA7 digitals

T1CON = 0b00000001; // Simply enable TMR1, Prescale 1:1

TRISA = 0b11001111; // set RA4 & RA5 as output, the rest are input

TRISD = 0b00000000; // Set portD as output for ensure chip working

TRISB = 0b00000000; // set portB as output for 2ndary comparator output

// --- zero crossing detector --- //

CMCON = 0b00110101; // select mode 101, invert all input

// --- Power factor computation -- //

65

x1 = 0;

x2 = 0;

if (CMCON.C1OUT == 1 && x1 == 0)

TMR1L = 0; // reset TMR1

TMR1H = 0;

x1 = 1;

x2 = 1;

if (CMCON.C2OUT == 1 && x2 == 1)

Iph = TMR1L;

Iph = TMR1H << 8;

ph_diff = Iph - 0x0000; // compute phase difference

x2 = 0;

if (CMCON.C1OUT == 0 && x2 = 0) //restart all

x1 = 0

66

// --- Capacitors Stage Triggering --- //

// phase different calculation with respect to time

// time phase difference = [(angle / 180 deg) / 50 freq ] * 2.0e6

if (ph_diff <= 4043) // pf >= 0.95

PORTB.F1 = 1; // LED RB1 lit to determine no need correction

else if (ph_diff >= 4043 && ph_diff <= 5743) // 0.95 > pf > 0.90

PORTB.F2 = 1; // stage 1 capacitor trigger










67










else if (ph_diff >= 11806) // pf < 0.6







else PORTD.F1 = 1; // indicate pf exceed below 0.6

while (1)

68

PORTD.F0 = ~PORTD.F0; // Ensure MCU working

delay_ms(1000); */

69

Appendix B

PIC16F777 microchip

Figure B-1: PIC16F777 Microcontroller chip

70

MikroC version 6.0 program overview

Figure B-2: MikroC microchip programming software

71

WinPIC software (DL4YHF's PIC Programmer for Windows)

Figure B-3: Win PIC programmer microchip interface software

72

Test on Zero-crossing Circuit (Built circuit and result)

Figure B-4: Zero-crossing circuit hardware structure

Figure B-5: Output waveforms of above circuit

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Environment of phase angle testing progress

Figure B-6: Picture taken when testing phase angle using induction motor (table fan)

Environment of single phase power factor testing progress

Figure B-7: Testing for single phase variable loads

Single-phase voltage regulator

PIC circuit

Sensors

74

Appendix C

Sample of actual PFC 3-phase connection diagram

Figure C-1: 3-Phase system cable connection (TCS Perunding Ltd. Co.)

pic

Documents

power relationship

true power

power transformer

appropriate power

power factorit

power equations

phantom power

apparent load power