pipe-islped2004-slides

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Power-Optimal Pipelining inDeep Submicron Technology

Seongmoo Heo and Krste AsanoviComputer Architecture Group, MIT CSAIL

ISLPED 20048/10/2004


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Traditional Pipelining

Goal: Maximum performance

Clk

Clk-Q SetupPropagation Delay

Clk

Clk

Vdd


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Pipelining as a Low-Power Tool

Clk


Time Slack

Goal: Low-Power, Fixed Throughput

Time Slack

Vdd

Clk

Clk


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Clk


Time Slack

Goal: Low-Power, Fixed Throughput

Time Slack

Vdd

Clk

Clk

Traded for Power(supply voltage scaling)


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Delay

Power

Pipelining

Time slack

Flip-flopPowerOverhead

* Clock frequency fixed


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Delay

Power

Supplyvoltagescaling

Power Saving

* Clock frequency fixed


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Power-Optimal Pipelining Power reduction from pipelining limited by power

overhead of increased number of flip-flops Power-Optimal Pipelining


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Power-Optimal Pipelining

Delay

Power

Too shallow pipelining

Power reduction from pipelining limited by poweroverhead of increased number of flip-flops Power-Optimal Pipelining


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Delay

Power

Too deep pipelining




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Delay

Power

OptimalPower Saving

Too deep pipelining


Optimalpipelining



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Contribution Pipelining is an old idea. Research focus has been on performance impact of

pipelining. Idea of using pipelining [Chandrakasan 92] to lower

power has not been fully explored in deep submicron

technology.

Analysis and circuit-level simulation of Power-OptimalPipelining for different regimes of Vth, activity factor,

clock gating


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1. Impact of pipelining on power component

2. Impact of pipelining on total power (with/withoutclock-gating)

Bottom-to-Top Approach

Total

Power(clock-gated)

Power

Timeactive activeinactive

SwitchingPower

Component

LeakagePower

Component

IdlePower

Component


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1. Impact of pipelining on power component

2. Impact of pipelining on total power (with/withoutclock-gating)

Bottom-to-Top Approach

Total

Power(not clock-gated)

SwitchingPower

Component

LeakagePower

Component

IdlePower

Component

Power

Timeactive inactive active

*Idle power =power consumedwhen circuit is idleand not clock-gated


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Target digital system: Fixed throughput,Highly parallel computation, Logic-dominant

Test bencho BPTM (Berkeley Predictive Technology Model)

70nm process:

o LVT(0.17/-0.2), MVT(0.19/-0.22), HVT(0.21/-0.24)o Hspice simulation at 100C, Clock = 2 GHz

Methodology

Baseline

N FO4 inverters (N= 2 ~ 24)

One Pipeline Stage

TG flip-flops TG flip-flops


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Pipelining and Switching Power:Analytical Trend

O(N2)

O(1/N)

Number of FO4 per stage, N

Switching Power

OptimalSaving

Optimal FO4

Quadratic reductionof logic switching power

Flip-flop overhead

Vdd2 N2


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O(1/N)

Leakage Power

O(N ) (1


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Pipelining and Idle Power:Analytical Trend

Clock-gating is not always possibleo Increased control complexityo insufficient setup time of clock enable signal

Leakage Power + Flip-flop Switching Powero Between leakage power scaling and flip-flop

switching power scaling depending on leakage level


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Pipelining and Idle Power:Analytical Trend

O(1/N)

Number of FO4 per stage, N

e Power O(N ) (1


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Simulation Results:Power Components

PowerComponents

SwitchingPower

LeakagePower

Idle Power

Right hand

side curve

O(N2) O(N )

(1


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Optimal Power Saving

Optimal FO4 = 6

ClockGating

NoClockGating

Optimal FO4 = 6~8

activity factor activity factor

relative powerrelative power

*2 GHz*Flip-flop delaynot included inoptimal FO4


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IdlePower

SwitchingPower

Switching

Power

LeakagePower




Optimal FO4 = 6 Optimal FO4 = 6~8

ClockGating

NoClockGating


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Optimal FO4 = 6 Optimal FO4 = 6~8

LVT

ClockGating

NoClockGating


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Discussion

LVT can be fast and power-efficiento enables lower Vdd

Flip-flop delay more important than flip-floppower for power-optimal pipelining


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Limitation of This Work

Effect onoptimal logicdepth

Effect onoptimal powersaving

Super-linear growth of flip-flops

Additional memory

Reduced glitches

Parasitic wire capacitance


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Conclusion

Pipelining is an effective low-power toolwhen used to support voltage scaling indigital system implementing highly parallelcomputation.

Optimal Logic Depth: 6-8 FO4o ~ 8-10 FO4 including flip-flop delay

Optimal Power Saving: 55 80%o It depends on Vth, AF, Clock-Gating

Insights:

o Pipelining is more effective with High AF Pipelining is most effective at saving switching power

o Pipelining is more effective with lower Vth Except for when leakage power is dominant.

o Pipelining is more effective with clock-gating reduced flip-flop overhead.


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Acknowledgments

Thanks to SCALE group members andanonymous reviewers

Funded by NSF CAREER award CCR-

0093354, NSF ITR award CCR-0219545, anda donation from Intel Corporation.


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