pipecheck hands-on mcm... · 2019. 7. 3. · simplesc: an sc microarchitecture •partially...
TRANSCRIPT
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PipeCheck Hands-On
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Overview▪Will take you through modelling simple uarches in µSpec
▪ simpleSC: An SC microarchitecture
• Partially completed uarch specification in VM, you will fill in remainder
▪ Initially, will look at verifying individual litmus test programs
▪ Later, will look at verifying across all programs (an infinite space!)
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The simpleSC Microarchitecture
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
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The simpleSC Microarchitecture
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 13-stage
in-order
pipelines
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The simpleSC Microarchitecture
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Loads
access
Mem in
Execute
stage
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The simpleSC Microarchitecture
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Stores sent
to Memory
during
Writeback
Stores sent
to Memory
during
Writeback
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The simpleSC Microarchitecture
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Stores sent
to Memory
during
Writeback
Stores sent
to Memory
during
Writeback
1. Start VirtualBox VM
2. Open a Terminal
3. Partially completed SC uarch in/home/check/pipecheck_tutorial/uarches/SC_fillable.uarch
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µSpec: A DSL for Specifying Microarchitectures▪ Language has capabilities similar to first-order logic (FOL)
• forall, exists, AND (/\), OR (\/), NOT (~), implication (=>)
• Has a number of built-in predicates which take memory operations as input
− e.g. ProgramOrder i j where i and j are loads/stores
− Other predicates include SamePhysicalAddress, SameData, IsAnyRead, …• See “Check Quick Start” handout for a more extensive list
• Predicates can also reference nodes and edges
− e.g. EdgeExists ((i1, Fetch), (i2, Fetch))
− This predicate is true iff an edge exists between i1 and i2’s Fetch stages
• All µhb edges are transitive (so µSpec is not a subset of FOL)
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µSpec: A DSL for Specifying Microarchitectures▪Microarchitecture spec has three components:
• Stage identifier definitions
• Macro definitions (optional)
• Axiom definitions
▪Macros allow:
• decomposition of axioms into smaller parts
• reuse of uspec fragments
▪Axioms are each a partial ordering on the events in an execution
▪ Job of PipeCheck is to ensure that these axioms correctly work together to uphold ISA-level MCM requirements for a litmus test
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Memory Hierarchy
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Stores and loads go through
the pipeline stages in order
Memory Hierarchy
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The Instr_Path Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Stores go through the
pipeline stages and reach
memory in order
Memory Hierarchy
Axiom “Instr_Path":forall microops "i",AddEdges [((i, Fetch), (i, Execute), "path");
((i, Execute), (i, Writeback), "path")].
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The Instr_Path Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Stores go through the
pipeline stages and reach
memory in order
Memory Hierarchy
Axiom “Instr_Path":forall microops "i",AddEdges [((i, Fetch), (i, Execute), "path");
((i, Execute), (i, Writeback), "path")].
Axiom
name
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The Instr_Path Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Stores go through the
pipeline stages and reach
memory in order
Memory Hierarchy
Axiom “Instr_Path":forall microops "i",AddEdges [((i, Fetch), (i, Execute), "path");
((i, Execute), (i, Writeback), "path")].
Microop: A single load/store op.
May correspond to an ISA instr,
or part of an ISA instr.
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The Instr_Path Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Stores go through the
pipeline stages and reach
memory in order
Memory Hierarchy
Axiom “Instr_Path":forall microops "i",AddEdges [((i, Fetch), (i, Execute), "path");
((i, Execute), (i, Writeback), "path")].
For all load/store ops…
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The Instr_Path Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writeback
Execute
Fetch
Core 0
Stores go through the
pipeline stages and reach
memory in order
Memory Hierarchy
Axiom “Instr_Path":forall microops "i",AddEdges [((i, Fetch), (i, Execute), "path");
((i, Execute), (i, Writeback), "path")].
Add edges from Fetch to Execute, and
Execute to Writeback
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Specifying µSpec Nodes▪A node represents a particular event in a particular instruction’s
execution
▪ Format for nodes is: (instr, stage/event_name)
▪Thus, (i, Fetch) represents the fetch stage of instruction i…
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Edges added according to Instr_Pathaxiom
Initially, Mem[x] = 0
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Fetchi1
Fetchi2
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1All instructions on the
same core go through
Fetch in program
order
Fetchi1
Fetchi2
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The PO_Fetch Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1All instructions on the
same core go through
Fetch in program order
FetchAxiom "PO_Fetch":forall microops "i1",forall microops "i2",SameCore i1 i2 /\ ProgramOrder i1 i2 =>AddEdge ((i1, Fetch), (i2, Fetch), "PO", "blue").
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The PO_Fetch Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1All instructions on the
same core go through
Fetch in program order
FetchAxiom "PO_Fetch":forall microops "i1",forall microops "i2",SameCore i1 i2 /\ ProgramOrder i1 i2 =>AddEdge ((i1, Fetch), (i2, Fetch), "PO", "blue").
Use of predicates to check that instrs are
on the same core and in program order
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The PO_Fetch Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1All instructions on the
same core go through
Fetch in program order
FetchAxiom "PO_Fetch":forall microops "i1",forall microops "i2",SameCore i1 i2 /\ ProgramOrder i1 i2 =>AddEdge ((i1, Fetch), (i2, Fetch), "PO", "blue").
Add edge from Fetch stage of earlier
instruction to Fetch stage of later instruction
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Initially, Mem[x] = 0
![Page 25: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/25.jpg)
µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Edges Added Using PO_Fetch axiom
Initially, Mem[x] = 0
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Executei1
Fetchi1
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Executei1
Fetchi1
Executei2
Fetchi2
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Fetch in order,
they will go through
Execute in the same
order
Executei1
Fetchi1
Executei2
Fetchi2
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The Execute_Stage_Is_In_order Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If two instructions on the
same core go through
Fetch in order, they will
go through Execute in the
same order
Execute
FetchAxiom "Execute_stage_is_in_order":forall microops "i1",forall microops "i2",SameCore i1 i2 /\EdgeExists ((i1, Fetch), (i2, Fetch), "") =>AddEdge ((i1, Execute), (i2, Execute), "PPO").
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The Execute_Stage_Is_In_order Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If two instructions on the
same core go through
Fetch in order, they will
go through Execute in the
same order
Execute
FetchAxiom "Execute_stage_is_in_order":forall microops "i1",forall microops "i2",SameCore i1 i2 /\EdgeExists ((i1, Fetch), (i2, Fetch), "") =>AddEdge ((i1, Execute), (i2, Execute), "PPO").
If instructions on same core
go through Fetch in order…
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The Execute_Stage_Is_In_order Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If two instructions on the
same core go through
Fetch in order, they will
go through Execute in the
same order
Execute
FetchAxiom "Execute_stage_is_in_order":forall microops "i1",forall microops "i2",SameCore i1 i2 /\EdgeExists ((i1, Fetch), (i2, Fetch), "") =>AddEdge ((i1, Execute), (i2, Execute), "PPO").
…then they go through
Execute in the same order.
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Fetchi1
Writebacki1
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Fetchi1
Writebacki1
Fetchi2
Writebacki2
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Fetch in order,
they will go through
Writeback in the same
order
Fetchi1
Writebacki1
Fetchi2
Writebacki2
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The Writeback_Stage_Is_In_Order Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If two instructions on the
same core go through
Fetch in order, they will
go through Writeback in
the same order
Fetch
Writeback
Axiom "Writeback_stage_is_in_order":forall microops "i1",forall microops "i2",________ i1 i2 /\EdgeExists ((i1, _____), (i2, _____), "") =>AddEdge ((i1, _________), (i2, _________), "PPO").
If two instructions on the same core go through Fetch in
order, they will go through Writeback in the same order
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The Writeback_Stage_Is_In_Order Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If two instructions on the
same core go through
Fetch in order, they will
go through Writeback in
the same order
Fetch
Writeback
Axiom "Writeback_stage_is_in_order":forall microops "i1",forall microops "i2",________ i1 i2 /\EdgeExists ((i1, _____), (i2, _____), "") =>AddEdge ((i1, _________), (i2, _________), "PPO").
Axiom "Writeback_stage_is_in_order":forall microops "i1",forall microops "i2",SameCore i1 i2 /\EdgeExists ((i1, Fetch), (i2, Fetch), "") =>AddEdge ((i1, Writeback), (i2, Writeback), "PPO").
If two instructions on the same core go through Fetch in
order, they will go through Writeback in the same order
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Initially, Mem[x] = 0
![Page 38: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/38.jpg)
µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Initially, Mem[x] = 0
![Page 39: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/39.jpg)
µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Edges fromExecute_stage_is
_in_order & Writeback_stage
_is_in_orderaxioms
Initially, Mem[x] = 0
![Page 40: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/40.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
Writebacki1 Writebacki2
![Page 41: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/41.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
All writes to the same address must be
totally ordered at memory.
(coherence order)
Writebacki1 Writebacki2
![Page 42: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/42.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
All writes to the same address must be
totally ordered at memory.
(coherence order)
Writebacki1 Writebacki2
i1: Store y=1 i2: Store y=2
![Page 43: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/43.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
All writes to the same address must be
totally ordered at memory.
(coherence order)
Writebacki1 Writebacki2
i1: Store y=1 i2: Store y=2
OR
Coherence order:
![Page 44: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/44.jpg)
The WriteSerialization Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Writeback in
order, they must reach
the Memory Hierarchy
in the same order
Writebacki1
Writebacki2
Memory Hierarchy
Axiom "WriteSerialization":forall microops "i1",forall microops "i2",( ~(SameMicroop i1 i2) /\ IsAnyWrite i1/\ IsAnyWrite i2 /\ SamePhysicalAddress i1 i2) =>(EdgeExists ((i1, Writeback), (i2, Writeback)) \/EdgeExists ((i2, Writeback), (i1, Writeback))).
![Page 45: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/45.jpg)
The WriteSerialization Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Writeback in
order, they must reach
the Memory Hierarchy
in the same order
Writebacki1
Writebacki2
Memory Hierarchy
Axiom "WriteSerialization":forall microops "i1",forall microops "i2",( ~(SameMicroop i1 i2) /\ IsAnyWrite i1/\ IsAnyWrite i2 /\ SamePhysicalAddress i1 i2) =>(EdgeExists ((i1, Writeback), (i2, Writeback)) \/EdgeExists ((i2, Writeback), (i1, Writeback))).
Two different writes to the
same address
![Page 46: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/46.jpg)
The WriteSerialization Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Writeback in
order, they must reach
the Memory Hierarchy
in the same order
Writebacki1
Writebacki2
Memory Hierarchy
Axiom "WriteSerialization":forall microops "i1",forall microops "i2",( ~(SameMicroop i1 i2) /\ IsAnyWrite i1/\ IsAnyWrite i2 /\ SamePhysicalAddress i1 i2) =>(EdgeExists ((i1, Writeback), (i2, Writeback)) \/EdgeExists ((i2, Writeback), (i1, Writeback))).
Either i1 is before i2 in
coherence order, OR vice-versa.
![Page 47: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/47.jpg)
µhb Graphs for co-mp Using Axioms
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
WriteSerialization axiom
![Page 48: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/48.jpg)
µhb Graphs for co-mp Using Axioms
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
WriteSerialization axiom
Two solutions;
Each enumerated separately(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4) (i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
![Page 49: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/49.jpg)
µhb Graphs for co-mp Using Axioms
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
WriteSerialization axiom
Two solutions;
Each enumerated separately(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4) (i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
![Page 50: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/50.jpg)
µhb Graphs for co-mp Using Axioms
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
WriteSerialization axiom
Two solutions;
Each enumerated separately
We will focus on left
graph going forward
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4) (i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
![Page 51: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/51.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
Writebacki1 Writebacki2
i1: Store y=1 i2: Store y=2OR
Coherence order:
![Page 52: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/52.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
Writebacki1 Writebacki2
i1: Store y=1 i2: Store y=2OR
Coherence order:
Test requires
y_final = 2
![Page 53: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/53.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
If a litmus test requires that an address has the value
of a certain write at the end of the test, that write must
be the last to reach memory.
Writebacki1 Writebacki2
i1: Store y=1 i2: Store y=2OR
Coherence order:
Test requires
y_final = 2
![Page 54: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/54.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
If a litmus test requires that an address has the value
of a certain write at the end of the test, that write must
be the last to reach memory.
Writebacki1 Writebacki2
i1: Store y=1 i2: Store y=2
Coherence order:
Test requires
y_final = 2
Enforced by test
EnforceFinalWrite axiom in the µSpec
![Page 55: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/55.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebacki1 Executei2
Memory Hierarchy
Executei1
![Page 56: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/56.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebacki1 Executei2
Memory Hierarchy
Executei1
A write must complete
its writeback before
loads/stores on the
same core that are
fetched after the write.
(otherwise the write could
be reordered with later
writes or later reads)
![Page 57: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/57.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebacki1 Executei2
Memory Hierarchy
Executei1
A write must complete
its writeback before
loads/stores on the
same core that are
fetched after the write.
(otherwise the write could
be reordered with later
writes or later reads)
![Page 58: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/58.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebacki1 Executei2
Memory Hierarchy
Executei1
A write must complete
its writeback before
loads/stores on the
same core that are
fetched after the write.
(otherwise the write could
be reordered with later
writes or later reads)
![Page 59: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/59.jpg)
The EnforceWritePPO Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Writeback in
order, they must reach
the Memory Hierarchy
in the same order
Writebacki1
Writebacki2
Memory Hierarchy
Axiom "EnforceWritePPO":forall microop "w",forall microop "i",(__________ w /\ ________ w i/\ EdgeExists((w, Fetch), (i, Fetch), "")) =>
AddEdge ((w, _________), (i, _______)).
A write must complete its writeback before execution of
loads/stores on the same core that are fetched after the
write.
![Page 60: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/60.jpg)
The EnforceWritePPO Axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
If two instructions on
the same core go
through Writeback in
order, they must reach
the Memory Hierarchy
in the same order
Writebacki1
Writebacki2
Memory Hierarchy
Axiom "EnforceWritePPO":forall microop "w",forall microop "i",(__________ w /\ ________ w i/\ EdgeExists((w, Fetch), (i, Fetch), "")) =>
AddEdge ((w, _________), (i, _______)).
A write must complete its writeback before execution of
loads/stores on the same core that are fetched after the
write.
Axiom "EnforceWritePPO":forall microop "w",forall microop "i",(IsAnyWrite w /\ SameCore w i/\ EdgeExists((w, Fetch), (i, Fetch), "")) =>
AddEdge ((w, Writeback), (i, Execute)).
![Page 61: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/61.jpg)
µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Initially, Mem[x] = 0
![Page 62: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/62.jpg)
µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Edge added by EnforceWrite
PPO axiom
Initially, Mem[x] = 0
![Page 63: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/63.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebacki1
Execute
Y = 0
![Page 64: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/64.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
Execute
Y = 0
![Page 65: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/65.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
i: Load y=0
Execute
Y = 0
![Page 66: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/66.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 1
![Page 67: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/67.jpg)
The BeforeAllWrites Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 0Y = 1
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).
![Page 68: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/68.jpg)
The BeforeAllWrites Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 0Y = 1
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).
Macro: This is a µSpec fragment
that can be instantiated as part
of a larger axiom
![Page 69: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/69.jpg)
The BeforeAllWrites Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 0Y = 1
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).
Check that the load reads
the data from the initial
state of the litmus test
![Page 70: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/70.jpg)
The BeforeAllWrites Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 0Y = 1
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).
If a load reads the initial value of a memory location, it
must execute before any write to that addr completes its
writeback.
![Page 71: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/71.jpg)
The BeforeAllWrites Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 0Y = 1
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, Execute), (w, Writeback))).
![Page 72: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/72.jpg)
The BeforeAllWrites Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1If a load reads the initial value
of a memory location, it must
execute before any write to
that location reaches Mem.
Writebacki1
w: Store y=1 i: Load y=0
Execute
Y = 0Y = 1
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, _______), (w, _________))).
DefineMacro "BeforeAllWrites":DataFromInitialStateAtPA i /\forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i/\ ~SameMicroop i w) =>AddEdge ((i, Execute), (w, Writeback))).
Enforce that the load
executes before all writes
to its address in the test
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
Writebacki1
Execute
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
A load must execute either
before or after any write to its
address completes writeback.
Writebacki1
Execute
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
A load must execute either
before or after any write to its
address completes writeback.
Writebacki1
w: Store y=val1 i: Load y=val2
Execute
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
A load must execute either
before or after any write to its
address completes writeback.
Writebacki1
w: Store y=val1 i: Load y=val2
Execute
OR
![Page 77: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/77.jpg)
The Before_Or_After_Every_SameAddrWrite Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
A load must execute either
before or after any write to its
address reaches memory.
Writebacki1
w: Store y=val1 i: Load y=val2
Execute
OR
DefineMacro "Before_Or_After_Every_SameAddrWrite":forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i) =>(AddEdge ((w, Writeback)), (i, Execute)) \/AddEdge ((i, Execute), (w, Writeback)))).
![Page 78: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/78.jpg)
The Before_Or_After_Every_SameAddrWrite Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Memory Hierarchy
A load must execute either
before or after any write to its
address reaches memory.
Writebacki1
w: Store y=val1 i: Load y=val2
Execute
OR
DefineMacro "Before_Or_After_Every_SameAddrWrite":forall microop "w", ((IsAnyWrite w /\ SamePhysicalAddress w i) =>(AddEdge ((w, Writeback)), (i, Execute)) \/AddEdge ((i, Execute), (w, Writeback)))).
Either w completes writeback
before i executes, or vice-versa.
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
Execute
Y = 0
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
Execute
A load must read from the latest write to that address to reach
memory.
Y = 0
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
Execute
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0
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Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1
Execute
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 1
![Page 83: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/83.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 1
![Page 84: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/84.jpg)
Finding Axioms
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 2
Writebackw’
w’: St y=2
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The No_SameAddrWrites_Btwn_Src_And_Read Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ ___________________ w i /\ ________ w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ ___________________ i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
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The No_SameAddrWrites_Btwn_Src_And_Read Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ ___________________ w i /\ ________ w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ ___________________ i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ SamePhysicalAddress w i /\ SameData w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ SamePhysicalAddress i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
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The No_SameAddrWrites_Btwn_Src_And_Read Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ ___________________ w i /\ ________ w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ ___________________ i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ SamePhysicalAddress w i /\ SameData w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ SamePhysicalAddress i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
Read i executes after its source
write w reaches memory…
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The No_SameAddrWrites_Btwn_Src_And_Read Macro
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ ___________________ w i /\ ________ w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ ___________________ i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
DefineMacro "No_SameAddrWrites_Btwn_Src_And_Read":exists microop "w", (IsAnyWrite w /\ SamePhysicalAddress w i /\ SameData w i/\ AddEdge ((w, Writeback), (i, Execute)) /\~(exists microop "w'",IsAnyWrite w' /\ SamePhysicalAddress i w’ /\~SameMicroop w w’ /\ EdgesExist [((w, Writeback), (w’, Writeback));
((w’, Writeback), (i, Execute))])).
…and there are no writes w’ to
that addr between the source
write w and the read i.
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Putting the Macros together: the Read_Values axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
Axiom "Read_Values":forall microops "i",IsAnyRead i =>(ExpandMacro BeforeAllWrites \/(ExpandMacro No_SameAddrWrites_Btwn_Src_And_Read/\ExpandMacro Before_Or_After_Every_SameAddrWrite
)).
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Putting the Macros together: the Read_Values axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
Axiom "Read_Values":forall microops "i",IsAnyRead i =>(ExpandMacro BeforeAllWrites \/(ExpandMacro No_SameAddrWrites_Btwn_Src_And_Read/\ExpandMacro Before_Or_After_Every_SameAddrWrite
)).
For all reads i (same identifier
used in the macros)…
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Putting the Macros together: the Read_Values axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
Axiom "Read_Values":forall microops "i",IsAnyRead i =>(ExpandMacro BeforeAllWrites \/(ExpandMacro No_SameAddrWrites_Btwn_Src_And_Read/\ExpandMacro Before_Or_After_Every_SameAddrWrite
)).
…either the read executes
before all writes (expand
macro defined earlier)…
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Putting the Macros together: the Read_Values axiom
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
Axiom "Read_Values":forall microops "i",IsAnyRead i =>(ExpandMacro BeforeAllWrites \/(ExpandMacro No_SameAddrWrites_Btwn_Src_And_Read/\ExpandMacro Before_Or_After_Every_SameAddrWrite
)).
…or the read reads from
the latest write to that
address
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
Initially, Mem[x] = 0
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
• i3 must be sourced from the write i2
• No intervening writes; constraint satisfied
Initially, Mem[x] = 0
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
• i4 must be sourced from i1
• But i2 intervenes! => Constraint unsatisfiable
Initially, Mem[x] = 0
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µhb Graphs for co-mp Using AxiomsEach column represents an instruction flowing
through the pipeline
(i1) (i2)
Fetch
Execute
Writeback
(i3) (i4)
Thread 0 Thread 1
i1: Store [x] 1i2: Store [x] 2
i3: r1 = Load [x]i4: r2 = Load [x]
SC Forbids: r1=2, r2=1, Mem[x] = 2
• i4 must be sourced from i1
• But i2 intervenes! => Constraint unsatisfiable
Initially, Mem[x] = 0
Cannot find an acyclic graph that satisfies all constraints =>
Forbidden Execution of co-mp is NOT observable on µarch!
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Test your completed SC uarch!
Memory Hierarchy
Writeback
Execute
Fetch
Core 0
Writeback
Execute
Fetch
Core 1
Writebackw
w: St y=1 i: Load y=1
Execute
A load must read from the latest write to that address to reach
memory.
Alternatively:
1) The load must execute after the write it reads from
2) No writes to that address between the source write and the read
Y = 0Y = 1Y = 2
Writebackw’
w’: St y=2
# Assuming you are in ~/pipecheck_tutorial/uarches/$ check -i ../tests/SC_tests/co-mp.test -m SC_fillable.uarch
# If your uarch is valid, the above will create co-mp.pdf in your# current directory (open pdfs from command line with evince)# To run the solution version of the SC uarch on this test:# (Note: this will overwrite the co-mp.pdf in your current folder)$ check -i ../tests/SC_tests/co-mp.test -m SC.uarch –d solutions/
# If you get an error (cannot parse uarch, ps2pdf crashes, etc),# examine your syntax or ask for help.# If the outcome is observable (“BUG”), compare the graphs# generated by the solution uarch to those of your uarch.
# To compare the uarches themselves:$ diff SC_fillable.uarch solutions/SC.uarch
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Run the entire suite of SC litmus tests!# Assuming you are in ~/pipecheck_tutorial/uarches/$ run_tests –v 2 -t ../tests/SC_tests/ -m SC_fillable.uarch
# The above will generate *.gv files in ~/pipecheck_tutorial/out/# for all SC tests, and output overall statistics at the end. If # the count for “Buggy” is non-zero, your uarch is faulty. Look for the tests that output “BUG” to find out which tests fail.
# You can use gen_graph to convert gv files into PDFs:$ gen_graph –i <test_gv_file>
# Compare your uarch with the solution SC uarch using diff to find # discrepancies:$ diff SC_fillable.uarch solutions/SC.uarch
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PipeCheck Verification Time
0.01
0.1
1
safe
029 ss
lrf
i001 m
prf
i002
rfi0
04sa
fe0
10sa
fe0
30sa
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test
and
set lb
safe
033
safe
036
safe
004
safe
006
rfi0
07 n5
test
and
set2
iwp
23
b sbsa
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17p
od
wr0
00
amd
5rf
i008
safe
018 wrc
co-m
psa
fe0
02sa
fe0
31sa
fe0
09sa
fe0
05m
p+f
ence
ssa
fe0
20m
p+s
tale
ldrf
i000
safe
007
test
and
set3
safe
003 n
6sa
fe0
14sa
fe0
12rf
i016
rfi0
12sa
fe0
32rw
c-u
nfe
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dsa
fe0
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p2
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safe
001
safe
026
safe
000 n
8sa
fe0
08sa
fe0
34rf
i013
safe
027
rwc-
fen
ced
rfi0
17 iriw
iwp
24
safe
021
rfi0
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safe
015
safe
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28rf
i015
po
dw
r00
1sa
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d3
n7
rfi0
06 n1
co-i
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safe
024
rfi0
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23sa
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i009
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10 n3
iwp
27
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(s)
FiveStage (No SB) FiveStage (w/ SB) gem5 O3 OpenSPARC T2
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Covered the basics of what PipeCheck can do…
▪But there’s more!
▪PipeCheck can handle heterogeneous pipelines:
![Page 101: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/101.jpg)
Covered the basics of what PipeCheck can do…
▪…and microarchitectural optimizations…
Left: Speculative Load Reordering
Right: Speculative Fence Retirement
![Page 102: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/102.jpg)
Covered the basics of what PipeCheck can do…
▪…and the methodology is extensible to other ordering types, including…
CCICheck: Coherence orderings that affect consistency (with ViCL abstraction)
COATCheck: Addr Translation/Virtual Memory orderings that affect consistency
![Page 103: PipeCheck Hands-On MCM... · 2019. 7. 3. · simpleSC: An SC microarchitecture •Partially completed uarch specification in VM, you will fill in remainder Initially, will look at](https://reader033.vdocument.in/reader033/viewer/2022060601/6054dbb2dba3dc726c4d3ffa/html5/thumbnails/103.jpg)
PipeCheck Summary
▪ Fast, automated per-program verification
▪Check implementation against ISA spec
▪Decompose RTL verification into smaller per-axiom sub-problems
• More on that after the coffee break with RTLCheck!
▪Open-Sourced:
https://github.com/daniellustig/coatcheck
Repo from this tutorial:
https://github.com/ymanerka/pipecheck_tutorial