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    TABLE OF CONTENTS

    1. ABSTRACT

    2. BLOCK DIAGRAM

    3. CIRCUIT DIAGRAM

    4. COMPONENTS TO BE USED

    5. DATA SHEET

    6. APPLICATIONS

    7. CONCLUSION

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    Purpose.

    MOTION DETECTION USING PIR

    ABSTRACT

    This is a system based on PIR motion detector module. If the motion detection module detects anymotion in the room or where it placed, it sends an out put to the micro controller which controls the

    whole system. When micro controller receives an input from motion detection module, it sends an

    out put to the relay driver section. When the relay was ON the light became on.

    If there is no motion was happened the light remains OFF.

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    Purpose.

    The main sections of this system are:

    PIR MOTION DETECTION MODULE

    Micro controller

    Relay

    Appliance to be controlled.

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    Purpose.

    Basic block diagram

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    Purpose.

    WORKING

    When the PIR motion detection module detects any motion in the room, it sends an out putto the micro controller which controls the whole system. When micro controller receives an input, it

    sends an out put to the relay driver section. The relay driver section drives the relay ON. When the

    relay was ON the light became on.

    If there is no motion was happened the light remains OFF.

    Circuit diagram

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    Purpose.

    PIR motion detection module

    Compact and complete, easy to use Pyroelectric Infrared (PIR) Sensor Module for human

    body detection. Incorporating Fresnel lens and motion detection circuit. High sensitivity and low

    noise. Output is a standard 5V active low output signal. Module provides an optimized circuit that

    will detect motion up to 6 meters away and can be used in burglar alarms and access control systems.

    Inexpensive and easy to use, it's ideal for alarm systems, motion-activated lighting, holiday props,

    and robotics applications.

    The Output can be connected to microcontroller pin directly to monitor signal or a connected

    to transistor to drive DC loads like a bell, buzzer, siren, relay, opto-coupler (e.g. PC817, MOC3021),

    etc. The PIR sensor and Fresnel lens are fitted onto the PCB. This enables the board to be mounted

    inside a case with the detecting lens protruding outwards.

    Features

    Complete with PIR, Motion Detection IC and Fresnel Lens

    Simple 3 connections

    Dual Element Sensor with Low Noise and High Sensitivity

    Supply Voltage: 5V DC

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    Purpose. Standard Active Low Output pin for connecting to microcontroller directly

    Detecting range up to 6 meters

    LED indication

    Module Dimensions: 25mm Length, 32mmWidth, 25mm Height

    Applications

    Motion-activated nightlight

    Alarm systems

    Robotics & Holiday animated props

    Theory of Operation

    Pyroelectric devices, such as the PIR sensor, have elements made of a crystalline material

    that generates an electric charge when exposed to infrared radiation. The changes in the amount of

    infrared striking the element change the voltages generated, which are measured by an on-board

    amplifier. The device contains a special filter called a Fresnel lens, which focuses the infrared

    signals onto the element. As the ambient infrared signals change rapidly, the on-board amplifier trips

    the output to indicate motion. The PIR (Passive Infra-Red) Sensor is a pyroelectric device that

    detects motion by measuring changes in the infrared (heat) levels emitted by surrounding objects.

    This motion can be detected by checking for a sudden change in the surrounding IR patterns. When

    motion is detected the PIR sensor outputs a high signal on its output pin. This logic signal can be

    read by a microcontroller or used to drive a transistor to switch a higher current load.

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    Purpose.Warm up time

    The PIR Sensor requires a warm-up time in order to function properly. This is due to thesettling time involved in learning its environment. This could be anywhere from 1-2 Minutes. After

    this warm up time, sensor will be ready to use.

    Pin Definitions

    Using the Sensor

    Connect regulated DC power supply of 5 Volts. Black wire is Ground, Next middle wire is

    Brown which is output and Red wire is positive supply. These wires are also marked on

    PCB.

    After powering up, allow startup delay time of 2 minutes before using the sensor. The sensor

    output might become LOW once or twice during this period since it has to learn about its

    environment. After 2 minutes, your sensor is ready for use.

    Preset in sensor is for delay time adjustment, Factory setting is 2 seconds. It means when a

    motion is detected, the sensor will keep output LOW at least for 2 seconds. It is normally not

    required to adjust this setting. Just in case you need to adjust the delay time, Make note of

    factory setting position, in case you have to revert back to original setting.

    To test sensor you only need power the sensor by connect two wires +5V and GND. You

    can leave the output wire as it is. When LED is off the output is at 5V, means no motion

    detected.

    Walk in front of sensor and the LED will lit up and output becomes 0V. The output is active

    low and can be given directly to microcontroller for interfacing applications.

    Range of Operation

    The PIR Sensor has a range of approximately 20 feet(6 meters). This can vary with

    environmental conditions. The sensor is designed to adjust to slowly changing conditions that would

    happen normally as the day progresses and the environmental conditions change, but responds by

    making its output high when sudden changes occur, such as when there is motion.

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    Purpose.FIGURE 1 RANGE OF SENSOR

    This device is designed for indoor use. Operation outside or in extreme temperatures may

    affect stability negatively. Due to the high sensitivity of PIR sensor device, it is not recommended to

    use the module in the following or similar condition.

    In rapid environmental changes & strong shock or vibration

    In a place where there are obstructing material (eg. glass) through which IR cannot pass within

    detection area.

    Exposed to direct sun light or direct wind from a heater or air condition

    PIC16F877A

    Features

    High Performance RISC CPU:

    Only 35 single-word instructions to learn

    All single-cycle instructions except for program branches, which are two-cycle

    Operating speed: DC 20 MHz clock input DC 200 ns instruction cycle

    Up to 8K x 14 words of Flash Program Memory, Up to 368 x 8 bytes of Data Memory (RAM),

    Up to 256 x 8 bytes of EEPROM Data Memory

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    Purpose. Pinout compatible to other 28-pin or 40/44-pin PIC16CXXX and PIC16FXXX

    microcontrollers

    Pin Configuration

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    Purpose.

    2.0 ARCHITECTURAL OVERVIEW

    The high performance of the PIC16F62X family can be attributed to a number of architectural

    features commonly found in RISC microprocessors. To begin with, the PIC16F62X uses a

    Harvard architecture, in which, program and data are accessed from separate memories using

    separate buses. This improves bandwidth over traditional Von Neumann architecture where

    program and data are fetched from the same memory. Separating program and data memory

    further allows instructions to be sized differently than 8-bit wide data word. Instruction opcodes

    are 14-bits wide making it possible to have all single-word instructions. A 14-bit wide program

    memory access bus fetches a 14-bit instruction in a single cycle. A two-stage pipeline overlaps

    fetch and execution of instructions. Consequently, all instructions (35) execute in a single cycle

    (200 ns @ 20 MHz) except for program branches. The Table below lists program memory

    (FLASH, Data and EEPROM).

    The PIC16F62X can directly or indirectly address its register files or data memory. All Special

    Function registers, including the program counter, are mapped in the data memory. The

    PIC16F62X have an orthogonal (symmetrical) instruction set that makes it possible to carry out

    any operation, on any register, using any Addressing mode. This symmetrical nature, and lack of

    special optimal situations make programming with the PIC16F62X simple yet efficient. In

    addition, the learning curve is reduced significantly. The PIC16F62X devices contain an 8-bit

    ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic

    and Boolean functions between data in the working register and any register file.

    The ALU is 8-bit wide and capable of addition, subtraction, shift and logical operations. Unless

    otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand

    instructions,

    typically one operand is the working register (W register). The other operand is a file register or an

    immediate constant. In single operand instructions, the operand is either the W register or a file

    register. The W register is an 8-bit working register used for ALU operations. It is not an

    addressable register. Depending on the instruction executed, the ALU may affect the values of the

    Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate

    as a Borrow and Digit Borrow out bit, respectively, bit in subtraction. See the SUBLW and

    SUBWF instructions for examples.

    A simplified block diagram is shown in Figure 2-1, and a description of the device pins in Table 2-

    1. Two types of data memory are provided on the PIC16F62X devices. Non-volatile EEPROM data

    memory is provided for long term storage of data such as calibration values, lookup table data, and

    any other data which may require periodic updating in the field. This data is not lost when power is

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    Purpose.removed. The other data memory provided is regular RAM data memory. Regular RAM data

    memory is provided for temporary storage of data during normal operation. It is lost when power is

    removed.

    A Brief Overview of the Serial Communications Process

    Computer serial ports transmit and receive data bit by bit. During transmission, the serial

    device driver program on the computer CPU takes each byte from the main computer memory

    (typically 8 KB in size) and places it onto the data bus along with the serial port I/O address. The byte

    then travels through the data bus and is stored in the serial port hardware buffer. When the serial port

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    Purpose.is ready to transmit data, it fetches the data from this hardware buffer, places it in its shift register, and

    transmits each bit over the communication line.

    The following figure shows this process:

    The shift register is one byte long. From the shift register, the serial port transmits data bit by

    bit. When the last bit in the shift register is transmitted, the serial port must request the next byte from

    the CPU via an interrupt request (IRQ). However, the CPU is usually busy when the serial port needs

    the byte, so the serial port must interrupt the CPU. The CPU may not respond to this interrupt

    immediately, which may lead to a delay in bit transmission. To solve this problem, the serial port has

    a hardware buffer; while the serial port transmits bits from its shift register, the hardware buffer

    actually sends the IRQ to the CPU to request the next byte. The advantage of this process is that when

    the serial port takes the final bit from its shift register and is ready to transmit the next byte, it does not

    need to send an IRQ to the CPU. Rather, the next byte is readily available in the buffer. This buffer is

    a FIFO buffer and is called a Universal Asynchronous Receiver Transmitter (UART). Early UARTversions had a 1-byte buffer, but recent versions such as 16550 and 16750 have up to a 64-byte buffer.

    The larger buffer means interrupt requests occur less often, and the CPU can respond to IRQs more

    efficiently and devote more time to other tasks.

    Receiving data is similar to transmission. The serial port receives the data bit by bit and places

    it in the shift register. When a byte is received, it is transmitted into the UART. With modern UARTs

    and their larger buffers, the serial port continues placing the bytes. When the buffer holds 1, 4, 8, or

    14 bytes, the port sends an IRQ to the CPU to pick up the bytes. The port does not wait until the

    buffer contains 16 bytes, because the CPU may not respond immediately due to the interrupt request

    process overload involved (due to identifying the type of request, I/O address, etc.). While the CPU

    responds to the IRQ, if more than 2 bytes are received, the new byte may overwrite the byte in the

    buffer. This creates aHardware Overrun Error.

    Universal Asynchronous Receiver Transmitter (UART)

    A UART is a 40-pin serial chip on the PC motherboard. During transmission, the UART

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    Purpose.converts the bytes from the PC parallel bus to the serial bit stream. During receiving, the UART builds

    the serial bits into a parallel byte and either sends the parallel byte to the CPU or places it in its buffer.

    The UART does not do anything with the data; it just receives it and sends it. Early UARTs had 1-byte buffers; therefore, after receiving or building every byte, they needed to send an IRQ to either

    send or pick up the next byte. This process is acceptable with low transfer speeds. But at high speeds,

    the CPU must service the request so often that it either cannot give sufficient time to other processes

    or cannot service the IRQ in a timely manner. In the latter case, the new byte may come before the old

    byte has been received, thus causing a Hardware Overrun Error. Modern UARTs such as the 16550

    and 16750 (also called FIFO UARTs) have up to a 64-byte buffer. They also have adjustable trigger

    levels of 1, 4, 8, or 14, meaning they can send an IRQ after collecting 1, 4, 8, or 14 bytes.

    Hardware Overrun Errors

    In serial communication, data bits received at the serial port are bundled into a byte and

    transmitted into the serial port hardware buffer. From the buffer, the byte is sent into the CPU. If a

    new byte arrives before the byte in the buffer is moved into the CPU, a Hardware Overrun Error

    occurs.

    A Hardware Overrun Error may happen for several reasons:

    The serial port hardware buffer is not large enough. For example, early UART chips can store

    only 1 byte. After each byte is received, the serial port sends an IRQ to the CPU to pick up the

    next byte. Therefore, the CPU must respond very quickly, or a new byte may arrive and cause

    an overrun error. The new UART chips have up to a 64-byte buffer (16 bytes in the 16550A

    and 64 bytes in the 16750), so the buffer can store more bytes before the serial port sends an

    IRQ to the CPU. Therefore, the CPU has sufficient time to respond to the interrupt requestand act on it. These new UARTs also have adjustable trigger levels of 1, 4, 8, and 14,

    meaning they can send interrupt requests to the CPU on receiving 1, 4, 8, or 14 bytes.

    Some other process might have disabled the interrupt.

    In Windows, the CPU must take care of many processes and may not respond to fast IRQs

    from the serial port. Also, if there is high-priority IRQs from other processes, the CPU may

    ignore the serial port IRQ.

    USART

    Using the USART in Asynchronous Mode

    USART -- Main Functions

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    Purpose. Universal Synchronous Asynchronous Receiver Transmitter

    Can be synchronous or asynchronous

    Can receive and transmit Full duplex asynchronous operation

    Most common use

    RS-232 communications to a PC serial port

    Note: Needs driver for level shifting

    USART stands for Universal Synchronous Asynchronous Receiver Transmitter. It is

    sometimes called the Serial Communications Interface or SCI. Synchronous operation uses a clock

    and data line while there is no separate clock accompanying the data for Asynchronous transmission.

    Since there is no clock signal in asynchronous operation, one pin can be used for transmission andanother pin can be used for reception. Both transmission and reception can occur at the same time

    this is known as full duplex operation. Transmission and reception can be independently enabled.

    However, when the serial port is enabled, the USART will control both pins and one cannot be used

    for general purpose I/O when the other is being used for transmission or reception.

    The USART is most commonly used in the asynchronous mode. In this presentation we will

    deal exclusively with asynchronous operation. The most common use of the USART in asynchronous

    mode is to communicate to a PC serial port using the RS-232 protocol. Please note that a driver is

    required to interface to RS-232 voltage levels and the PICmicro MCU should not be directly

    connected to RS-232 signals.

    The USART can both transmit and receive, and we will now briefly look at how this is

    implemented in the USART.

    USART -- Block Diagram

    The USART can be configured to transmit eight or nine data bits by the TX9 bit in the

    TXSTA register. If nine bits are to be transmitted, the ninth data bit must be placed in the TX9D bit of

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    Purpose.the TXSTA register before writing the other eight bits to the TXREG register. Once data has been

    written to TXREG, the eight or nine bits are moved into the transmit shift register. From there they are

    clocked out onto the TX pin preceded by a start bit and followed by a stop bit. The use of a separatetransmit shift register allows new data to be written to the TXREG register while the previous data is

    still being transmitted. This allows the maximum throughput to be achieved.

    USART -- Block Diagram

    The USART can be configured to receive eight or nine bits by the RX9 bit in the RCSTA

    register. After the detection of a start bit, eight or nine bits of serial data are shifted from the RX pin

    into the receive shift register one bit at a time. After the last bit has been shifted in, the stop bit is

    checked and the data is moved into the buffer which passes the data through to the RCREG register if

    it is empty. The buffer and RCREG register therefore form a two element FIFO. If nine bit reception

    is enabled, the ninth bit is passed into the RX9D bit in the RCSTA register in the same way as the

    other eight bits of data are passed into the RCREG register. The use of a separate receive shift register

    and a FIFO buffer allows time for the software running on the PIC micro MCU to read out the

    received data before an overrun error occurs. It is possible to have received two bytes and be busy

    receiving a third byte before the data in the RCREG register is read.

    USART Signals

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    Purpose.

    The USART outputs and inputs logic level signals on the TX and RX pins of the PICmicro

    MCU. The signal is high when no transmission or reception is in progress and goes low when the

    transmission starts. This low going transition is used by the receiver to synchronize to the incoming

    data. The signal stays low for the duration of the start bit and is followed by the data bits, least

    significant bit first. In the case of an eight-bit transfer, there are eight data bits and the last data bit is

    followed by the stop bit which is high. The transmission therefore ends with the pin high. After the

    stop bit has completed, the start bit of the next transmission can occur as shown by the dotted lines.

    There are several things to note about this waveform, which represents the signal on the TX or

    RX pins of the microcontroller. The start bit is a zero and the stop bit is a one. The data is sent least

    significant bit first so the bit pattern looks backwards in comparison to the way it appears when

    written as a binary number. The data is not inverted even though RS-232 uses negative voltages to

    represent a logic one. Generally, when using the USART for RS-232 communications, the signals

    must be inverted and level shifted through a transceiver chip of some sort.

    USART Signals

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    Purpose.

    In the case of a nine bit asynchronous transmission, the ninth bit occurs after the eighth data

    bit and is followed by the stop bit. Having the ninth bit in this position makes it easy to implement

    RS-232 data formats that require parity or two stop bits. Even parity can be implemented in software

    by changing the ninth data bit to make the total number of ones in the data an even number. Similarly,

    odd parity can be implemented by making the total number of ones in the data an odd number. If two

    stop bits are required for an eight bit transmission, this can be achieved by setting the ninth data bit toone. The ninth bit then acts as the first stop bit and the normal stop bit becomes the second stop bit.

    Another advantage of having a ninth data bit is that it can be used as an address indicator. This is

    commonly implemented on the RS-485 protocol. Each device on a serial bus is assigned a specific

    address and monitors the data for transmissions with the ninth bit set. When the ninth bit is set, the

    software on the PICmicro compares the received data to its own address. If the addresses match, the

    software can enable reception of the data that follows the address, but if the addresses do not match,

    the data that follows is ignored. On some PICmicro devices the USART has hardware built in to

    check the address bit and can ignore transmissions that do not have this bit set. These USARTs are

    referred to as addressable USARTs.

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    Purpose.

    The signals on the USART pins of the microcontroller use logic levels. This means that for a

    five volt supply, the signals will be close to five volts when they are high and close to ground when

    they are low. When communicating with other logic devices, these signals can be used directly. In

    many applications, particularly with asynchronous communications, transmission standards such asRS-232 and RS-485 require different voltage levels to be used. For example, RS-232 uses a voltage

    below minus five volts to represent a logic one and a voltage above five volts to represent a logic zero.

    For RS-232, an interface chip such as Microchips TC232 device is recommended to convert the

    signals to the required levels.

    USART Registers

    There are several registers used to control the USART. The SPBRG register allows the baud

    rate to be set. The TXSTA and RCSTA registers are used to control transmission and reception but

    there are some overlapping functions and both registers are always used. The TXREG and RCREG

    registers are used write data to be transmitted and to read the received data. The PIR1 and PIE1

    registers contain the interrupt flag bits and enable bits to allow the USART to generate interrupts.

    Interrupts are often used when the PICmicro is busy executing code and data needs to be transmitted

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    Purpose.or received in the background. The interrupt flags are not only used for interrupts but can also be read

    during normal operation to determine whether data has been received or can be transmitted.

    USART -- Baud Rate

    The rate at which data is transmitted or received must be always be set using the baud rate

    generator unless the USART is being used in synchronous slave mode. The baud rate is set by writing

    to the SPBRG register. The SYNC bit selects between synchronous and asynchronous modes, and

    these modes have different baud rates for a particular value in the SPBRG register. For asynchronous

    mode, the SYNC bit must be cleared and the BRGH bit is used to select between high and low speed

    options for greater flexibility in setting the baud rate.

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    Purpose.

    The top two formulas show how the baud rate is set by the value in the SPBRG register and

    the BRGH bit. More important for the user, however, is to be able to calculate the value to place in the

    SPBRG register to achieve a desired baud rate. The bottom two formulas can be used to do this. The

    SPBRG register can have a value of zero to 255 and must always be an integer value. When these

    formulas yield a value for SPBRG that is not an integer, there will be a difference between the desired

    baud rate and the rate that can actually be achieved. By calculating the actual baud rate using the

    nearest integer value of SPBRG, the error can be determined. Whether this error is acceptable usually

    depends on the application.

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    Purpose.

    As an example of a baud rate calculation, consider the case of a microcontroller operating at4MHz that is required to communicate at 9600 baud with a serial port on a PC. The USART would

    then be used in asynchronous mode.

    When BRGH is set to zero, the ideal value of SPBRG is calculated as 5.51. Since this differs

    from the closest integer value of six by approximately nine percent, this will cause a corresponding

    error in the baud rate. When BRGH is set to one, the ideal value of SPBRG is calculated as 25.04.

    This is very close to the integer value of 25 which must be used. Setting SPBRG to 25 will give a

    baud rate of 9615 which is within two tenths of a percent of the desired baud rate.

    Note that to get an accurate and stable baud rate, an accurate and stable oscillator is required.

    A crystal or ceramic resonator usually works well but an RC oscillator is seldom accurate enough for

    reliable asynchronous communications. It is not advisable to use an RC oscillator when doing RS-232

    communications to a PC, for example.

    This is an example of how to write code to set up the baud rate. The correct bank must be

    selected to access the SPBRG register. The required data, decimal 25 in this example, is moved into

    the working register which is then moved into the SPBRG register. Finally, the BRGH bit in the

    TXSTA register is set. In many cases the BRGH bit will be set when writing to the TXSTA register to

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    Purpose.set up other features of the USART which will be discussed later. This example uses the BANKSEL

    directive to select the correct bank. It is not a PICmicro instruction but will cause the assembler or

    linker to generate the appropriate instructions to change the bank. Please see the MPASM UsersGuide for more information.

    USART -- TXSTA Register

    The TXSTA register is mainly used to control transmissions but does have other functions.

    For example, the SYNC bit selects between synchronous and asynchronous modes for both

    transmission and reception. The CSRC bit has no effect in asynchronous mode. The TX9 bit enables

    nine bit transmission. If this bit is set, the TX9D bit in the TXSTA register will be transmitted in

    addition to the eight bits of data that was written to the TXREG register. The TXEN bit enables

    transmissions. Once this bit has been set, writes to the TXREG register will cause a transmission to be

    initiated if the serial port has been enabled.

    The SYNC bit should be cleared to select asynchronous operation. The BRGH bit selects

    between the high and low speed baud rate options in asynchronous mode. This allows a greater rangeof baud rates to be selected. The TRMT bit indicates that there is data in the transmit shift register.

    This means that there is a transmission in progress. Data that is written to the TXREG register is

    loaded into the transmit shift register when this register is empty. The transmit shift register is internal

    and is not a readable register.

    USART -- RCSTA Register

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    Purpose.

    The RCSTA register is mainly used to control reception but does have other functions. For

    example, the SPEN bit is used to enable the entire serial port, both for transmissions and receptions.

    Setting SPEN also configures both port pins associated with the USART to their USART functions.

    The RX9 bit enables nine bit reception. This causes the ninth data bit received to be loaded into the

    RX9D bit in the RCSTA register. The SREN bit has no effect in asynchronous mode.

    The CREN bit enables reception of data continuously while it is set and disables reception

    when cleared. The ADDEN bit enables address detection in nine bit asynchronous mode and is only

    available on parts with an addressable USART. When this bit is set, only data that has the ninth data

    bit set will be received. The FERR bit indicates a framing error which means that the stop bit was not

    detected. The framing error is associated with a particular byte in RCREG and once the RCREG has

    been read, the FERR bit will be meaningless until the next data is received into RCREG. Framing

    errors are often caused by incorrect baud rates. The OERR bit indicates an overrun error which means

    that a complete byte was received when the FIFO was still full with the two previous bytes. The new

    data will be lost and no further data will be received until the CREN bit has been cleared and set again

    by software. The two bytes in the FIFO can still be read from RCREG however.

    USART -- Setting up

    We will now look at some examples of code used to set up and use the USART in

    asynchronous mode. To set up eight bit asynchronous mode, this code sets the TXEN bit to enable

    transmission, the CREN bit to enable reception and the SPEN bit to enable the serial port. The BRGH

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    Purpose.bit is set to select the high baud rate. The TX9 and RX9 bits are cleared since eight bit operation is

    desired and the SYNC bit is cleared for asynchronous operation.

    The PORT pins used by the USART must be set as inputs. This is the default state after a

    reset but it is good practice to explicitly set the pins to inputs anyway.

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    Purpose.To set up nine bit asynchronous mode, this code sets the TXEN bit to enable transmission, the

    CREN bit to enable reception and the SPEN bit to enable the serial port. The BRGH bit is set to select

    the high baud rate. The TX9 and RX9 bits are set since nine bit operation is desired and the SYNC bitis cleared for asynchronous operation.

    To set up nine bit asynchronous mode with address detect, this code sets the TXEN bit to

    enable transmission, the CREN bit to enable reception and the SPEN bit to enable the serial port. The

    BRGH bit is set to select the high baud rate. The TX9, RX9 and ADDEN bits are set since nine bit

    operation and address detection is desired and the SYNC bit is cleared for asynchronous operation.

    USART Transmitting

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    Purpose.

    Before a byte can be transmitted, a check should be made to ensure that the previous byte

    written to the TXREG register does not get overwritten. Data is only moved from the TXREG when

    the transmit shift register is empty so if a transmission is in progress, data will stay in the TXREG

    until the previous data has been transmitted. The TXIF flag gets set when the data in the TXREG gets

    moved into the transmit shift register so this bit must be tested before new data is written to TXREG.

    The code tests the TXIF bit in the PIR1 register and keeps looping back until the bit is

    detected high. In some situations, the processor cannot spare the time to wait for the current

    transmission to end and in this case the code might return to a main program instead of waiting in a

    loop. An alternative is to use interrupts to detect when data can be written.

    After the TXIF bit has been tested to check that new data can be transmitted, the data can be

    written. If a nine bit transmission is required, the ninth bit must be written before the other eight bits

    are written to TXREG since writing to TXREG will immediately initiate a transmission if the transmit

    shift register is empty.

    In this example the ninth data bit is assumed to be in the least significant bit of a general

    purpose register labeled Data Bits. A rotate instruction is used to get this bit into the carry flag in the

    STATUS register which is then tested to set or clear the TX9D bit which holds the ninth data bit.

    This code can be simplified if the Data Bits register is in the same bank as the TXSTA

    register. In this example they are assumed to be in different banks and the STATUS register is used

    for intermediate storage of the bit since it can be accessed in all banks.

    The method used to load the ninth data bit also depends on the particular application. For

    example if this bit is to be used as another stop bit, it can be set once when initializing the USART,

    and will never need to be changed.

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    Purpose.

    To initiate the transmission, data must be written to the TXREG. In this example, the data to

    be transmitted is assumed to be in a general purpose register labeled Data Byte. The code moves the

    data from Data Byte into the working register and then into the TXREG register. This initiates the

    transmission.

    USART Receiving

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    Purpose.

    We will now look at some code examples for receiving data with the USART. Before readingthe RCREG, a check should be made to determine whether new data has been received. When there is

    new data in the RCREG register, the RCIF bit in the PIR1 register will be set.

    The code tests the RCIF bit in the PIR1 register and keeps looping back until the bit is

    detected high. In many situations, the processor cannot spare the time to wait for the the next data to

    be received and there is also the danger of being stuck in an endless loop if data cannot be received for

    some reason. It is usually better to return to the main program instead of waiting in a loop. An

    alternative is to use interrupts to detect when data has been received.

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    Purpose.

    After the RCIF bit has been tested to check that new data has been received, the data can be

    read. If a nine bit reception is being performed, the ninth bit in RX9D must be read before the other

    eight bits are read from RCREG since reading from RCREG will immediately allow the next data inthe FIFO to be loaded into RCREG and the RX9D bit. In this example it is assumed that the ninth data

    bit should be loaded into the least significant bit of a general purpose register labeled DataBits. Since

    the ninth data bit, RX9D, is the least significant bit of RCSTA, a rotate instruction is be used to place

    this bit into the carry flag of the STATUS register. The least significant bit of the DataBits register is

    then set or cleared depending on the carry flag. This code can be simplified if the DataBits register is

    in the same bank as the RCSTA register.

    The STATUS register is used for intermediate storage since it can be accessed in all banks.

    The method used to read the ninth data bit also depends on the particular application. For example if

    this bit is to be used as another stop bit, it can tested directly and cause a branch to an error handling

    routine if it is zero.

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    Purpose.

    After detecting that new data has been received and reading the ninth data bit if required, the

    eight bits of data can be read from the RCREG register. In this example, it is assumed that the data

    received should be put into a general purpose register labeled Data Byte. The code moves the data

    from the RCREG register into the working register and then into the Data Byte register.

    USART -- Flow Control

    The USART will receive data as fast as the baud rate allows. In some circumstances, the

    software that must read the data from the RCREG register may not be able to do so as fast as the data

    is being received. In this case, there is a need for the PICmicro to tell the transmitting device to

    suspend transmission of data temporarily.

    Similarly, the PICmicro may need to be told to suspend transmission temporarily. This is

    done by means of flow control. There are two common methods of flow control, XON/XOFF andhardware. XON/XOFF flow control can be implemented completely in software with no external

    hardware, but full duplex communications is required. When incoming data needs to be suspended, an

    XOFF byte is transmitted back to the other device that is transmitting the data being received. To start

    the other device transmitting again, an XON byte is transmitted. XON and XOFF are standard ASCII

    control characters. This means that when sending raw data instead of ASCII text, care must be taken

    to ensure that XON and XOFF characters are not accidentally sent with the data. Hardware flow

    control uses extra signals to control the flow of data and they are defined as part of the RS-232

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    Purpose.communications standard, for example. To implement hardware flow control on a PICmicro, extra I/O

    pins must be used.

    Generally, an output pin is controlled by the receiving device to indicate that the transmitting

    device should suspend or resume transmissions. The transmitting device tests an input pin before a

    transmission to determine whether data can be sent.

    USART Interrupts

    Interrupts are useful to minimize the time that the software spends polling to check for received data

    or testing whether a new transmission can be started. This can make implementing other tasks easier

    since they to not have to stop to test the USART. The software can respond faster to incoming data

    since it does not wait the polling interval before detecting that there is new data. Because of the faster

    response, data spends less time in RCREG waiting to be read and overflow errors are less likely to

    occur. Typically, interrupts are used to receive data without being used to transmit data. In most

    software it is impossible to know when data will be received and interrupts provide a convenient

    means to avoid the need to continuously check for new received data.

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    Purpose.

    The USART interrupts are controlled by three registers. The INTCON register contains theGIE and PEIE bits. These are the global interrupt enable and peripheral interrupt enable bits and both

    must be set in order for the receive or transmit interrupts to occur.

    The PIE1 register contains the TXIE and RCIE bits and these are the transmit and receive interruptenable bits. They allow the transmit and receive interrupts to be independently enabled or disabled.

    The PIR1 register contains the TXIF and RCIF bits and these are the transmit and receive interrupt

    flag bits. When one of these bits get set while the appropriate interrupt enable bits are set, an interrupt

    will occur.

    The PIR1 register contains the TXIF and RCIF bits and these are the transmit and receive

    interrupt flag bits. When one of these bits get set while the appropriate interrupt enable bits are set, an

    interrupt will occur. The RCIF bit gets set when new data is available in RCREG and gets cleared

    when all data is emptied from the FIFO. Reading RCREG in the interrupt routine therefore clears the

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    Purpose.flag automatically if there is no other data in the FIFO. The TXIF bit gets cleared when data is written

    to TXREG and gets set when this data moves into the transmit shift register to get transmitted. The

    interrupt therefore occurs when new data can be transmitted. When the last byte of data has beenwritten to TXREG, the TXIE bit should be cleared to stop the interrupts from occurring. The interrupt

    can be enabled again when new data needs to be transmitted and this will immediately cause an

    interrupt.

    This code example shows how the transmit and receive interrupts are enabled by setting the

    appropriate bits in the INTCON and PIE1 registers. Note that the INTCON register can be accessed in

    all banks. There is no need to clear the interrupt flags since these are controlled by the USART

    hardware. This code may be combined with other initialization code that enables other interrupts. In

    that case it may be more efficient to write to the registers instead of using several bit set instructions.

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    Purpose.

    When an interrupt occurs, the code at the interrupt vector immediately starts executing. This

    can happen at any time that the interrupts are enabled and the interrupt routine could use the same

    registers as the code that was interrupted. For example, only a very simple interrupt routine will not

    use the working register or affect the STATUS bits. It can be catastrophic for the interrupted code to

    have these registers changed unexpectedly. For this reason, it is important to save the data from any

    registers that may be changed by the interrupt routine and restore the contents of the registers before

    returning to the interrupted code. Another register that is often affected by interrupts is the PCLATH

    register if the software uses more than one page of program memory. On the newer 18C devices there

    is automatic saving of critical registers for high priority interrupts.

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    Purpose.

    This code is an example of how the working register, STATUS register and PCLATH register

    can be saved at the start of an interrupt service routine. This should usually be the very first code at

    the interrupt vector but it is possible to first have some other code that does not affect these critical

    registers and does not require a specific bank.

    The working register is saved first into a register called W_Save. Since the bank is not known

    at this point, W_Save must be in shared memory or all the possible locations of W_Save in all the

    banks must be reserved. In other words the software must not use any of the locations that W_Save

    could represent in each of the banks. Once the working register has been saved, STATUS is moved

    into the working register. This can affect the Z bit in the STATUS register but note that the original

    contents of STATUS has been saved unchanged in the working register. The bank bits can now be

    cleared to select bank zero and the working register moved into the STATUS_Save register defined in

    bank zero. This now contains the original contents of STATUS.

    Finally the PCLATH register is saved into the PCLATH_Save register defined in bank zero.

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    Purpose.

    After executing the interrupt routine it is necessary to restore the critical registers to their

    original state and this code example shows how this can be done. First PCLATH is restored from

    PCLATH_Save in bank zero. Then STATUS is restored from STATUS Save in bank zero. At this

    point the STATUS register has been restored and it is critical not to change any of the STATUS bits.

    STATUS contains the correct bank for the data stored in W_Save but using a movf instruction to

    restore the working register would affect the Z bit in STATUS. To avoid this problem, the swapf

    instruction is used instead because it does not affect any STATUS flags. Two swapf instructions are

    required to swap the nibbles of W_Save and then swap them back to their original positions while

    putting the data into the working register.

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    Purpose.In the interrupt routine, after the context has been saved, the cause the interrupt must be

    determined. In many cases it is not sufficient to test the interrupt flags, since these flags will get set

    regardless of whether the interrupt is enabled or not. For example if the TXIE bit is cleared to disablea transmit interrupt, and a timer interrupt occurs, the interrupt routine will get executed and the TXIF

    flag may be tested. This could cause the transmit interrupt code to get executed even though a transmit

    interrupt did not occur. The safest solution is to test the interrupt enable flag as well as the interrupt

    flag itself, as shown in this example. The transmit interrupt routine Put TX Data will only get

    executed if both the TXIE and the TXIF bits are set.

    USART Errors

    There are several errors that can occur during serial communications and the USART can

    detect two types of errors automatically. These are indicated by two error flags in the RCSTA register

    for framing errors and overrun errors. In addition, software can be used to detect other errors if parity

    or checksums are used. By using the ninth data bit as a parity bit, any single bit error in the data can

    be detected. A checksum on several bytes of data can provide an extra level of certainty about the

    validity of the data.

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    Purpose.

    A framing error occurs when the stop bit is zero. The stop bit should always be one. The

    framing error is always associated with the byte in the RCREG and is passed through the FIFO in the

    same way as the data with which it is associated. Reading the RCREG allows the next data byte to be

    loaded into RCREG with its own framing error flag. For this reason it is essential to read the error flag

    before the data is read from RCREG, in the same way that the ninth data bit is read before the data in

    RCREG. There is no need to clear the framing error flag since the FERR bit will be updated as soon

    as new data is received into RCREG.

    An overrun error occurs when the FIFO is full with two bytes that have already been received

    and a third byte has been clocked into the receive shift register. Since this third byte needs to be

    moved into the FIFO and there is no space available, it is discarded and an overrun error is indicated.

    Overrun errors can be avoided by reading the incoming data from RCREG fast enough. Interrupts can

    often be used to ensure that data is read in time. Once an overrun error occurs, no new data will be

    received until the receive logic has been reset by clearing the receive enable bit, CREN, and enabling

    it again. A common symptom of an overrun error is that the USART stops receiving unexpectedly,

    often after the first two bytes.

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    Purpose.

    This code shows how the framing and overrun error bits can be tested. The code branches to

    the appropriate error handling routine when it detects that an error flag is set.

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    Purpose.This code shows how the framing error can be cleared, in effect, by reading the RCREG. Note

    that the error bit will remain set until new data has been received and loaded into the RCREG register.

    How the error is handled will depend entirely on the application. In this code, a general purposeregister called Error Code is loaded with a predefined value represented by the label FRAME_ERR

    and a routine called Error Handler is called. This routine will take the appropriate action.

    This code shows how the overrun error can be cleared by clearing and setting the CREN bit.

    In some cases the two bytes in the FIFO will need to be read out first since they represent valid data.

    How the error will be handled will again depend on the application. In this code, a general purpose

    register called Error Code is loaded with a predefined value represented by the label OVRUN_ERR

    and a routine called Error Handler is called. This routine will take the appropriate action.

    RELAY

    A relay is an electrically operated switch. Many relays use an electromagnet to

    operate a switching mechanism mechanically, but other operating principles are also used. Relays

    are used where it is necessary to control a circuit by a low-power signal (with complete electrical

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    Purpose.isolation between control and controlled circuits), or where several circuits must be controlled by

    one signal. The first relays were used in long distance telegraph circuits, repeating the signal

    coming in from one circuit and re-transmitting it to another. Relays were used extensively intelephone exchanges and early computers to perform logical operations.

    A type of relay that can handle the high power required to directly drive an

    electric motor Is called a contactor. Solid-state relays control power circuits with no moving parts,

    instead using a semiconductor device to perform switching. Relays with calibrated operating

    characteristics and sometimes multiple operating coils are used to protect electrical circuits from

    overload or faults; in modern electric power systems these functions are performed by digital

    instruments still called "protective relays"

    Basic design and operation

    Small relay as used in electronics

    A simple electromagnetic relay consists of a coil of wire surrounding a soft iron core, an

    iron yoke which provides a low reluctance path for magnetic flux, a movable iron armature, and oneor more sets of contacts (there are two in the relay pictured). The armature is hinged to the yoke and

    mechanically linked to one or more sets of moving contacts. It is held in place by a spring so that

    when the relay is de-energized there is an air gap in the magnetic circuit. In this condition, one of the

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    Purpose.two sets of contacts in the relay pictured is closed, and the other set is open. Other relays may have

    more or fewer sets of contacts depending on their function. The relay in the picture also has a wire

    connecting the armature to the yoke. This ensures continuity of the circuit between the movingcontacts on the armature, and the circuit track on the printed circuit board (PCB) via the yoke, which

    is soldered to the PCB.

    When an electric current is passed through the coil it generates a magnetic field that

    attracts the armature, and the consequent movement of the movable contact (s) either makes or

    breaks (depending upon construction) a connection with a fixed contact. If the set of contacts was

    closed when the relay was de-energized, then the movement opens the contacts and breaks the

    connection, and vice versa if the contacts were open. When the current to the coil is switched off, the

    armature is returned by a force, approximately half as strong as the magnetic force, to its relaxed

    position. Usually this force is provided by a spring, but gravity is also used commonly in industrial

    motor starters. Most relays are manufactured to operate quickly. In a low-voltage application this

    reduces noise; in a high voltage or current application it reduces arcing.

    When the coil is energized with direct current, a diode is often placed across the coil to

    dissipate the energy from the collapsing magnetic field at deactivation, which would otherwise

    generate a voltage spike dangerous to semiconductor circuit components. Some automotive relaysinclude a diode inside the relay case. Alternatively, a contact protection network consisting of a

    capacitor and resistor in series (snubber circuit) may absorb the surge. If the coil is designed to be

    energized with alternating current (AC), a small copper "shading ring" can be crimped to the end of

    the solenoid, creating a small out-of-phase current which increases the minimum pull on the

    armature during the AC cycle.

    A solid-state relay uses a thyristor or other solid-state switching device, activated by the

    control signal, to switch the controlled load, instead of a solenoid. An optocoupler (a light-emittingdiode (LED) coupled with a photo transistor) can be used to isolate control and controlled circuits.

    Simple electromechanical relay

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    Purpose.Types

    Latching relay

    A latching relay has two relaxed states (bistable). These are also called "impulse",

    "keep", or "stay" relays. When the current is switched off, the relay remains in its last state. This is

    achieved with a solenoid operating a ratchet and cam mechanism, or by having two opposing coils

    with an over-center spring or permanent magnet to hold the armature and contacts in position while

    the coil is relaxed, or with a remanent core. In the ratchet and cam example, the first pulse to the coil

    turns the relay on and the second pulse turns it off. In the two coil example, a pulse to one coil turns

    the relay on and a pulse to the opposite coil turns the relay off. This type of relay has the advantage

    that it consumes power only for an instant, while it is being switched, and it retains its last settingacross a power outage. A remanent core latching relay requires a current pulse of opposite polarity to

    make it change state.

    Reed relay

    A reed relay is a reed switch enclosed in a solenoid. The switch has a set of contacts

    inside an evacuated or inert gas-filled glass tube which protects the contacts against atmospheric

    corrosion; the contacts are made of magnetic material that makes them move under the influence of

    the field of the enclosing solenoid. Reed relays can switch faster than larger relays, require only little

    power from the control circuit, but have low switching current and voltage ratings.

    Top, middle: reed switches, bottom: reed relay

    Mercury-wetted relay

    A mercury-wetted reed relay is a form of reed relay in which the contacts are wetted

    with mercury. Such relays are used to switch low-voltage signals (one volt or less) where themercury reduces the contact resistance and associated voltage drop, for low-current signals where

    surface contamination may make for a poor contact, or for high-speed applications where the

    mercury eliminates contact bounce. Mercury wetted relays are position-sensitive and must be

    mounted vertically to work properly. Because of the toxicity and expense of liquid mercury, these

    relays are now rarely used. See also mercury switch.

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    Purpose.Polarized relay

    A polarized relay placed the armature between the poles of a permanent magnet toincrease sensitivity. Polarized relays were used in middle 20th Century telephone exchanges to

    detect faint pulses and correct telegraphic distortion. The poles were on screws, so a technician could

    first adjust them for maximum sensitivity and then apply a bias spring to set the critical current that

    would operate the relay.

    Machine tool relay

    A machine tool relay is a type standardized for industrial control of machine tools,

    transfer machines, and other sequential control. They are characterized by a large number of contacts

    (sometimes extendable in the field) which are easily converted from normally-open to normally-

    closed status, easily replaceable coils, and a form factor that allows compactly installing many relays

    in a control panel. Although such relays once were the backbone of automation in such industries asautomobile assembly, the programmable logic controller (PLC) mostly displaced the machine tool

    relay from sequential control applications.

    Contactor relay

    A contactor is a very heavy-duty relay used for switching electric motors and lighting

    loads, although contactors are not generally called relays. Continuous current ratings for common

    contactors range from 10 amps to several hundred amps. High-current contacts are made with alloys

    containing silver. The unavoidable arcing causes the contacts to oxidize; however, silver oxide isstill a good conductor. Such devices are often used for motor starters. A motor starter is a contactor

    with overload protection devices attached. The overload sensing devices are a form of heat operated

    relay where a coil heats a bi-metal strip, or where a solder pot melts, releasing a spring to operateauxiliary contacts. These auxiliary contacts are in series with the coil. If the overload senses excess

    current in the load, the coil is de-energized. Contactor relays can be extremely loud to operate,

    making them unfit for use where noise is a chief concern.

    Solid-state relay

    Solid state relay, which has no moving parts

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