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1PLACEMENT IN PHYSICAL DESIGN

(ASHISH KUMAR SINGH,PRIYANKA BRAHMA,SWEETY KUMARI) M.TECH –VLSI NIT SILCHAR,ASSAM

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2AGENDAWHAT IS PLACEMENT AND ITS TYPESBACK END PROCESSPLACEMENT PROBLEM FORMULATIONALGORITHMSSIMULATED BASED PLACEMENT PARTITIONING BASED PLACEMENT

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PLACEMENT AND ITS TYPES

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Placement is the process of determining the locations of circuit devices on a die surface. It is an important stage in the VLSI design flow, because it affects rout ability,performance, heat distribution, and to a less extent, power consumption of a design. Traditionally, it is applied after the logic synthesis stage and before therouting stage

PLACEMENT-

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5Cont-

Placement is a critical step in the VLSI design flow mainly for the following four reasons. First, placement is a key factor in determining the performance of a circuit. Placement largely determines the length and, hence, the delay of interconnect wires. As feature size in advanced VLSI technology continues to reduce, interconnect delay has become the determining factor of circuit performance

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6Types of placement- 1. STANDARD CELL PLACEMENT –STANDARD CELLS HAVE BEEN DESIGNED IN SUCH A WAY THAT POWER AND CLOCK CONNECTIONS RUN HORIZONTALLY THROUGH THE CELL AND OTHER I/O LEAVES THE CELL FROM THE TOP OR BOTTOM SIDES.

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72. Building block placement

CELLS TO BE PLACED HAVE ARBITRARY SHAPE.

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8Placement is done in three steps:1. Global placement

generate a rough placement that may violate some placement constraints (e.g., there may be overlaps among modules)

2. Legalization placement

makes the rough solution from global placement legal (no placement constraint violation) by moving modules around locally.

3. Detailed placement

further improves the legalized placement solution in an iterative manner by rearranging a small group of modules in a local region while keeping all other modules fixed.

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9Out of the three steps important one is global placement

Approaches for global placement are : Partitioning based approach (min cut partitioning) Simulated annealing approach Analytical approach (best)

Placement is the problem of automatically assigning correct positions to predesigned cells on the chip with no overlapping such that some objective function is optimized.

Placement is design state after logic synthesis and before routing.

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BACK END PROCESS

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121. PARTITIONING

GOAL: PARTITION OF A SYSTEM INTO NUMBER OF ASIC’S(APPLICATION SPECIFIC INTEGRATED CHIP)

OBJECTIVE: MINIMISE THE NUMBER OF EXTERNAL CONNECTIONS BETWEEN EACH ASIC. KEEP EACH ASIC SMALLER THAN MAX SIZE.

2. FLOORPLANNING GOAL: CALCULATE THE SIZE OF BLOCKS AND ASSIGN THEM LOCATIONS.

OBJECTIVE: KEEP HIGHLY CONNECTED BLOCKS PHYSICALLY CLOSE TO EACH OTHER.

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3. PlacementGoal: assign the interconnect areas and the locations of all the logic cells within the flexible blockObjective: minimise the ASIC area and the interconnects4. Global routing Goal: determine the location of all the interconnects Objective: minimise the total interconnect area.5. Detailed routingGoal: completely route all the interconnects on the chipObjective: minimise the total interconnect length used

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PLACEMENT PROBLEM FORMULATION

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INPUT:

Placement region, a set of modules, and a set of nets. The

widths and heights of the placement region and all modules

are given. The locations of I/O pins on the placement region

and on all modules are fixed.

OUTPUT:

A set of location on the chip : one location for each cell.

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16•OBJECTIVES:

Minimize the ASIC area and the interconnects

•GOAL:

Arrange all the logic cells within flexible blocks

The cells are placed to produce a routable chip that meets

timing and other constraints (e.g., low-power, noise, etc.)

•CHALLENGE:

The number of cells in a design is very large (> 1 million).

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17Global and Detailed Placement

IN GLOBAL PLACEMENT , THE APPROXIMATELOCATIONS FOR CELLS IS DECIDEDBY PLACING CELLS IN GLOBAL BINS.

IN DETAILED PLACEMENT, CELLS ARE PLACED WITHOUT OVER LAPPING.

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Good and bad placement

Good placement Minimize area (total wiring

area) Ensure routability Avoid signal interference Distribute heat Maximize performance

Bad placement

Consumes large areas Results in performance

degradation Results in difficult and

sometimes impossible tasks (Routing)

An ill-placed layout cannot be improved by high quality routing.

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PLACEMENT ALGORITHMS

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Optimisation of the following is done using placement algorithm

•TOTAL AREA•TOTAL WIRE LENGTH•HEURISTICS ARE USED IN THE ALGORITHMS.

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Estimation of Wirelength The speed and quality of estimation has a drastic

effect on the performance of placement algorithms. For 2-terminal nets, we can use Manhattan distance as

an estimate. If the end co-ordinates are (x1,y1) and (x2,y2), then the

wire length

L = ⎥ x1 – x2 ⎥ + ⎥ y1 – y2⎥

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23 Constructive

Once the position of the cell is fixed , it can not be modified

Constructive algorithms are used to obtain aninitial placement.

Iterative

Intermediate placements are modified in an attempt to improve the cost function.

The initial placement is followed by an iterative improvement phase.

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24Techniques for initial placement

A TOP-DOWN METHOD:MIN-CUT PARTITIONING AND PLACEMENT (BISECT THE CIRCUIT RECURSIVELY)

MIN-CUT PLACEMENT METHOD:1. CUT PLACEMENT AREA INTO TWO PIECES

2. SWAP LOGIC CELLS TO MINIMIZE CUT COST

3.REPEAT PROCESS FROM STEP 1, CUTTING SMALLER PIECES UNTIL ALL LOGIC CELLS ARE PLACED

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A bottom-up method: cluster growth (selectcells with strongest connections one by one)

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SIMULATED ANNEALING PLACEMENT

•INITIAL PLACEMENT IMPROVED THROUGH SWAPS AND MOVES•ACCEPT A SWAP/MOVE IF IT IMPROVES THE COST

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Classification of Algorithm

CLASSIFICATION OF ALGORITHM

Simulation based Partitioning based Other

Simulated AnnealingSimulated EvolutionForce Directed

Breuer’s AlgorithmTerminal Propagation

Cluster GrowthForce Directed

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Simulation annealing placement-

Various algorithms proposed for placement in circuits.

Constructive placement vs Iterative improvement.

Simulated Annealing – an iterative improvement algorithm

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30 Simulated

Annealing Annealing in metals Heat the solid state metal to a high temperature Cool it down very slowly according to a specific

schedule. If the heating temperature is sufficiently high to

ensure random state and the cooling process is slow enough to ensure thermal equilibrium, then the atoms will place themselves in a pattern that corresponds to the global energy minimum of a perfect crystal.

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31Simulated Annealing and

VLSI Placement: Arrangement of atoms = a new configuration of

cells ( a new solution) Total configurations = Total solution set Perturbation = small random movement of cells

to get new configuration (possible solution). Energy = Cost function Temperature = control parameter Cooling schedule = starting temperature and a

rule how to decrease the temperate or how to cool

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Steps-Step 1: Initialize – Start with a random initial placement.

Initialize a very high “temperature”.

Step 2: Move – Perturb the placement through a defined move.

Step 3: Calculate score – calculate the change in the score due

to the move made.

Step 4: Choose – Depending on the change in score, accept or

reject the move. The probability of acceptance depending on

the current “temperature”.

Step 5: Update and repeat– Update the temperature value by

lowering the temperature. Go back to Step 2.

The process is done until “Freezing Point” is reached.

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Simulated Annealing AlgorithmAlgorithm SA_Placementbegin T = initial_temperature; P = initial_placement; while ( T > final_temperature) do while (no_of_trials_at_each_temp not yet completed) do new_P = PERTURB (P); ΔC = COST (new_P) – COST (P); if (ΔC < 0) then P = new_P; else if (random(0,1) > exp(-ΔC/T)) then P = new_P; T = SCHEDULE (T); /** Decrease temperature **/ end

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34 Parameters

INIT-TEMP = 4000000 C; INIT-PLACEMENT = Random; PERTURB(place)

1. Displacement of a block to a new position.2. Interchange blocks.

3. Orientation change for a block. SCHEDULE.

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35 Timber Wolf

One of the most successful placement algorithms.

Developed by Sechen and Sangiovanni-Vincentelli.

Parameters used:

– Initial_temperature = 4,000,000 C

– Final_temperature = 0.1 C

– SCHEDULE(T) = α(T) x T

• α(T) specifies the cooling rate which depends on the

current temperature.

• α(T) is 0.8 when the cooling process just starts.

• α(T) is 0.95 in the medium range of temperature.

• α(T) is 0.8 again when temperature is low.

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36Simulated Evolution / Genetic

Algorithm The algorithm starts with an initial set of placement

configurations.

Called the population. The process is iterative, where each iteration is called a

generation.

The individuals of a population are evaluated to measure their goodness. To move from one generation to the next, three genetic

operators are used: Crossover Mutation Selection

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Breuer’s Algorithm

Partitioning technique used to generate placement.

The given circuit is repeatedly partitioned into two sub-

circuits

At each level of partitioning, the available layout area is

partitioned into horizontal and vertical subsections

alternately.

Each of the sub-circuits is assigned to a subsection.

Process continues till each sub-circuit consists of a single

gate, and has a unique place on the layout area.

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38Cont-

Different sequences of cut lines used:

1. Cut Oriented Min-Cut Placement

2. Quadrature Placement

3. Bisection Placement

4. Slice Bisection Placement

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39Terminal Propagation

Algorithm Partitioning algorithms merely reduce net cut. Direct use of partitioning algorithms would increase net

length. To prevent this, terminal propagation is used. When a net connecting two terminals is cut, a dummy

terminal is propagated to the nearest pin on the boundary.

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41Cluster Growth

In this constructive placement algorithm, bottom-up

approach is used. Blocks are placed sequentially in a partially completed

layout. The first block (seed) is usually placed by the user. Other blocks are selected and placed one by one. Selection of blocks is usually based on connectivity with

placed blocks

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Layouts produced are not usually good.Does not take into account the interconnections and other circuit features. Useful for generating initial placements. For iterative placement algorithms

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Algorithm Cluster_GrowthbeginB = set of blocks to be placed;Select a seed block S from B;Place S in the layout;B = B – S;while (B ≠ φ) dobeginSelect a block X from B;Place X in the layout;B = B – X;end;end

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44Performance Driven

Placement The delay at chip level plays an important role in

determining the performance of the chip.

- Depends on interconnecting wires. As the blocks in a circuit becomes smaller and

smaller:

-The size of the chip decreases.

-Interconnection delay becomes a major issue in highperformance circuits. Placement algorithms for high-performance chips:

-Allow routing of nets within timing constraints.

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45Cont-

Two major categories of algorithms:

1. Net-based approach Try to route the nets to meet the timing constraints on the

individual nets instead of considering paths. The timing requirement for each net has to be decided by the

algorithm. Usually a pre-timing analysis generates the bounds on the net-

lengths which must be satisfied during placement.

2. Path-based approach Critical paths in the circuit are considered. Try to place the blocks in a manner that the path length is

within the timing constraint.

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Thank you