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EE582 Physical Design Automation of VLSI Circuits and Systems Prof. Dae Hyun Kim School of Electrical Engineering and Computer Science Washington State University Placement

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Page 1: Placement - Washington State University

EE582

Physical Design Automation of VLSI Circuits and Systems

Prof. Dae Hyun Kim

School of Electrical Engineering and Computer Science

Washington State University

Placement

Page 2: Placement - Washington State University

2 Physical Design Automation of VLSI Circuits and Systems

Metrics for Placement

• Wirelength

• Timing

• Power

• Routing congestion

Page 3: Placement - Washington State University

3 Physical Design Automation of VLSI Circuits and Systems

Wirelength Estimation

• Half-perimeter wirelength (HPWL)

A W

H

HPWL = W + H B

C D

Page 4: Placement - Washington State University

4 Physical Design Automation of VLSI Circuits and Systems

Wirelength Estimation

Page 5: Placement - Washington State University

5 Physical Design Automation of VLSI Circuits and Systems

Placement Algorithms

• Constructive – Min-cut based placement

– Force-directed

• Analytical – Gordian

– Kraftwerk

• Iterative improvement – Simulated annealing (Timberwolf)

– Pairwise exchange

Page 6: Placement - Washington State University

6 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Idea

– Cutsize minimization ≈ Reduction of global wires

Partition A Partition B

Local connections

Global connections

Page 7: Placement - Washington State University

7 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Partitioning

Page 8: Placement - Washington State University

8 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Algorithm – Min_Cut_Placement (N, n, C)

/* N: layout

n: # cells to be placed

n0: # cells in a slot

C: connectivity matrix (netlist) */

begin

if ( n ≤ n0 ) then

place_cells (N, n, C);

else

(N1, N2) = cut_surface (N);

(n1, C1), (n2, C2) = partition (n, C);

Min_Cut_Placement (N1, n1, C1);

Min_Cut_Placement (N2, n2, C2);

end

Page 9: Placement - Washington State University

9 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example (Quadrature placement)

– KL partitioning + Quadrature placement

Page 10: Placement - Washington State University

10 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Terminal propagation

– Dunlop and Kernighan, TCAD’85

• Original min-cut placement algorithm

– Does not consider the locations of terminal pins.

Page 11: Placement - Washington State University

11 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• What if we swap {1,3,6,9} and {2,4,5,7}?

Page 12: Placement - Washington State University

12 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Terminal propagation

Page 13: Placement - Washington State University

13 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Terminal propagation

Page 14: Placement - Washington State University

14 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Terminal propagation

Page 15: Placement - Washington State University

15 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Terminal propagation

Page 16: Placement - Washington State University

16 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 17: Placement - Washington State University

17 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 18: Placement - Washington State University

18 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 19: Placement - Washington State University

19 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 20: Placement - Washington State University

20 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 21: Placement - Washington State University

21 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 22: Placement - Washington State University

22 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 23: Placement - Washington State University

23 Physical Design Automation of VLSI Circuits and Systems

Min-Cut-Based Placement

• Example

Page 24: Placement - Washington State University

24 Physical Design Automation of VLSI Circuits and Systems

• This page is intentionally left blank.

Page 25: Placement - Washington State University

25 Physical Design Automation of VLSI Circuits and Systems

Analytical Placement

• Kraftwerk2

– Spindler, “Kraftwerk2 – A Fast Force-Directed

Quadratic Placement Approach Using an Accurate

Net Model”, TCAD’08

Page 26: Placement - Washington State University
Page 27: Placement - Washington State University

27 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Net model – Two-pin nets

• Connectivity matrix

• Ideal wirelength cost function – Γ = |x1 – x2| + |y1 – y2|

• Quadratic placement – Cost function Γ is quadratic.

Page 28: Placement - Washington State University

28 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Quadratic cost function – Γ = (x1 – x2)

2 + (y1 – y2)2 = Γx + Γy

• Γx: x-component

• Γy: y-component

• How can we optimize the cost function?

–𝜕Γ

𝑥

𝜕𝑥1

= 0,𝜕Γ

𝑥

𝜕𝑥2

= 0

–𝜕Γ

𝑦

𝜕𝑦1

= 0,𝜕Γ

𝑦

𝜕𝑦2

= 0

Page 29: Placement - Washington State University

29 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Example

p1 p2 x

Γ𝑥 = 𝑥 − 𝑝12+ 𝑥 − 𝑝2

2

𝜕Γ𝑥𝜕𝑥

= 0 = 2 𝑥 − 𝑝1 + 2 𝑥 − 𝑝2

𝑥 =𝑝1+ 𝑝2

2

Page 30: Placement - Washington State University

30 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Example

p1 p2 x1

Γ𝑥 = 𝑥1− 𝑝12+ 𝑥1− 𝑥2

2+ 𝑥2− 𝑝22

𝜕Γ𝑥𝜕𝑥1

= 0 = 2 𝑥1 − 𝑝1 + 2 𝑥1− 𝑥2

𝜕Γ𝑥𝜕𝑥2

= 0 = −2 𝑥1− 𝑥2 + 2 𝑥2− 𝑝2

𝑥1 =2𝑝1+ 𝑝2

3

𝑥2 =𝑝1+ 2𝑝2

3

x2

Page 31: Placement - Washington State University

31 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• The location of each cell is represented by

– (x, y)

• The x-locations of M movable cells

– x = (x1, x2, …, xM)T

– Cx: cell-to-cell connectivity matrix

– dx: cell-to-pin connectivity matrix (constant)

Γx = 0.5 xTCxx + xTdx + const.

Page 32: Placement - Washington State University

32 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Wirelength minimization

–𝜕Γ

𝑥

𝜕𝑥1

= 0, 𝜕Γ

𝑥

𝜕𝑥2

= 0, …, 𝜕Γ

𝑥

𝜕𝑥𝑀= 0

– i.e., 𝛻xΓx = Cxx + dx = 0

• where 𝛻x = (𝜕

𝜕𝑥1

, 𝜕

𝜕𝑥2

, …, 𝜕

𝜕𝑥𝑀)T

– Net force: Fxnet = 𝛻xΓx = Cxx + dx

Γx = 0.5 xTCxx + xTdx + const.

Page 33: Placement - Washington State University

33 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Applying only the net force makes a lot of

overlaps.

Page 34: Placement - Washington State University

34 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Move force

– Removes overlaps = spread cells out.

• x: current location (to be computed)

• x’: last location

• Change in the cell location

– Δx = x – x’

Page 35: Placement - Washington State University

35 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Density function

– Dcell(x, y)

• Cell density at each location

• Move force

– Fx,imove = wi·(xi – xi

o)

• xi: current location (to be computed)

• xio: target location

Density

Page 36: Placement - Washington State University

36 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Net force

• Move force

Fxnet = Cxx + dx

Fxmove = Cx

o (x – xo) = Cxo (x – x’ + Φx)

Page 37: Placement - Washington State University

37 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Net force is used for wirelength minimization

• Do not collapse the cells back to their initial

locations.

• Hold force

Fxhold = –(Cxx’ + dx)

Page 38: Placement - Washington State University

38 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

• Final equation

Fxnet + Fx

move + Fxhold = 0

[Cxx + dx] + [Cxo (x – x’ + Φx)] + [–(Cxx’ + dx)] = 0

(Cx + Cxo)·(x – x’) = –Cx

o·Φx

(Cx + Cxo)·Δx = –Cx

o·Φx

x = x’ + Δx

Page 39: Placement - Washington State University

39 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

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40 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

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41 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

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42 Physical Design Automation of VLSI Circuits and Systems

Kraftwerk2

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43 Physical Design Automation of VLSI Circuits and Systems