placement - washington state university
TRANSCRIPT
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EE582
Physical Design Automation of VLSI Circuits and Systems
Prof. Dae Hyun Kim
School of Electrical Engineering and Computer Science
Washington State University
Placement
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2 Physical Design Automation of VLSI Circuits and Systems
Metrics for Placement
• Wirelength
• Timing
• Power
• Routing congestion
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3 Physical Design Automation of VLSI Circuits and Systems
Wirelength Estimation
• Half-perimeter wirelength (HPWL)
A W
H
HPWL = W + H B
C D
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4 Physical Design Automation of VLSI Circuits and Systems
Wirelength Estimation
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5 Physical Design Automation of VLSI Circuits and Systems
Placement Algorithms
• Constructive – Min-cut based placement
– Force-directed
• Analytical – Gordian
– Kraftwerk
• Iterative improvement – Simulated annealing (Timberwolf)
– Pairwise exchange
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6 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Idea
– Cutsize minimization ≈ Reduction of global wires
Partition A Partition B
Local connections
Global connections
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7 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Partitioning
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8 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Algorithm – Min_Cut_Placement (N, n, C)
/* N: layout
n: # cells to be placed
n0: # cells in a slot
C: connectivity matrix (netlist) */
begin
if ( n ≤ n0 ) then
place_cells (N, n, C);
else
(N1, N2) = cut_surface (N);
(n1, C1), (n2, C2) = partition (n, C);
Min_Cut_Placement (N1, n1, C1);
Min_Cut_Placement (N2, n2, C2);
end
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9 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example (Quadrature placement)
– KL partitioning + Quadrature placement
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10 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Terminal propagation
– Dunlop and Kernighan, TCAD’85
• Original min-cut placement algorithm
– Does not consider the locations of terminal pins.
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11 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• What if we swap {1,3,6,9} and {2,4,5,7}?
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12 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Terminal propagation
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13 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Terminal propagation
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14 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Terminal propagation
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15 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Terminal propagation
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16 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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17 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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18 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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19 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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20 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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21 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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22 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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23 Physical Design Automation of VLSI Circuits and Systems
Min-Cut-Based Placement
• Example
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24 Physical Design Automation of VLSI Circuits and Systems
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25 Physical Design Automation of VLSI Circuits and Systems
Analytical Placement
• Kraftwerk2
– Spindler, “Kraftwerk2 – A Fast Force-Directed
Quadratic Placement Approach Using an Accurate
Net Model”, TCAD’08
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27 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Net model – Two-pin nets
• Connectivity matrix
• Ideal wirelength cost function – Γ = |x1 – x2| + |y1 – y2|
• Quadratic placement – Cost function Γ is quadratic.
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28 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Quadratic cost function – Γ = (x1 – x2)
2 + (y1 – y2)2 = Γx + Γy
• Γx: x-component
• Γy: y-component
• How can we optimize the cost function?
–𝜕Γ
𝑥
𝜕𝑥1
= 0,𝜕Γ
𝑥
𝜕𝑥2
= 0
–𝜕Γ
𝑦
𝜕𝑦1
= 0,𝜕Γ
𝑦
𝜕𝑦2
= 0
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29 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Example
p1 p2 x
Γ𝑥 = 𝑥 − 𝑝12+ 𝑥 − 𝑝2
2
𝜕Γ𝑥𝜕𝑥
= 0 = 2 𝑥 − 𝑝1 + 2 𝑥 − 𝑝2
𝑥 =𝑝1+ 𝑝2
2
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30 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Example
p1 p2 x1
Γ𝑥 = 𝑥1− 𝑝12+ 𝑥1− 𝑥2
2+ 𝑥2− 𝑝22
𝜕Γ𝑥𝜕𝑥1
= 0 = 2 𝑥1 − 𝑝1 + 2 𝑥1− 𝑥2
𝜕Γ𝑥𝜕𝑥2
= 0 = −2 𝑥1− 𝑥2 + 2 𝑥2− 𝑝2
𝑥1 =2𝑝1+ 𝑝2
3
𝑥2 =𝑝1+ 2𝑝2
3
x2
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31 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• The location of each cell is represented by
– (x, y)
• The x-locations of M movable cells
– x = (x1, x2, …, xM)T
– Cx: cell-to-cell connectivity matrix
– dx: cell-to-pin connectivity matrix (constant)
Γx = 0.5 xTCxx + xTdx + const.
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32 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Wirelength minimization
–𝜕Γ
𝑥
𝜕𝑥1
= 0, 𝜕Γ
𝑥
𝜕𝑥2
= 0, …, 𝜕Γ
𝑥
𝜕𝑥𝑀= 0
– i.e., 𝛻xΓx = Cxx + dx = 0
• where 𝛻x = (𝜕
𝜕𝑥1
, 𝜕
𝜕𝑥2
, …, 𝜕
𝜕𝑥𝑀)T
– Net force: Fxnet = 𝛻xΓx = Cxx + dx
Γx = 0.5 xTCxx + xTdx + const.
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33 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Applying only the net force makes a lot of
overlaps.
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34 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Move force
– Removes overlaps = spread cells out.
• x: current location (to be computed)
• x’: last location
• Change in the cell location
– Δx = x – x’
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35 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Density function
– Dcell(x, y)
• Cell density at each location
• Move force
– Fx,imove = wi·(xi – xi
o)
• xi: current location (to be computed)
• xio: target location
Density
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36 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Net force
• Move force
Fxnet = Cxx + dx
Fxmove = Cx
o (x – xo) = Cxo (x – x’ + Φx)
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37 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Net force is used for wirelength minimization
• Do not collapse the cells back to their initial
locations.
• Hold force
Fxhold = –(Cxx’ + dx)
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38 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
• Final equation
Fxnet + Fx
move + Fxhold = 0
[Cxx + dx] + [Cxo (x – x’ + Φx)] + [–(Cxx’ + dx)] = 0
(Cx + Cxo)·(x – x’) = –Cx
o·Φx
(Cx + Cxo)·Δx = –Cx
o·Φx
x = x’ + Δx
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39 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
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40 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
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41 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
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42 Physical Design Automation of VLSI Circuits and Systems
Kraftwerk2
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43 Physical Design Automation of VLSI Circuits and Systems