Solid-State Electronics 99 (2014) 45–50

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Solid-State Electronics

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Planarized ambipolar a-SiGe:H thin-film transistors: Influence of thesequence of fabrication process

http://dx.doi.org/10.1016/j.sse.2014.06.0240038-1101/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author. Tel.: +52 (222) 266 3100; fax: +52 (222) 247 0517.E-mail addresses: madominguezj@gmail.com, prosales@inaoep.mx (M. Domin-

guez).

Miguel Dominguez a,⇑, Pedro Rosales b, Alfonso Torres b, Francisco Flores a, Joel Molina b, Mario Moreno b,Jose Luna a, Abdu Orduña c

a Centro de Investigaciones en Dispositivos Semiconductores, Instituto de Ciencias, Benemerita Universidad Autonoma de Puebla (BUAP), Puebla 72570, Mexicob National Institute for Astrophysics, Optics and Electronics (INAOE), Electronics Department, Luis Enrique Erro No. 1, Puebla Z.P. 72840, Mexicoc Centro de Investigación en Biotecnología Aplicada (CIBA), IPN, Tlaxcala Tlax. 72197, Mexico

a r t i c l e i n f o

Article history:Received 13 January 2014Received in revised form 24 March 2014Accepted 9 June 2014

The review of this paper was arranged byDr. Y. Kuk

Keywords:Thin-film transistorHydrogenated amorphous silicon–germaniumModelingSpiceAmbipolarPlanarized gate

a b s t r a c t

This work presents the fabrication, characterization and modeling of inverted staggered a-SiGe:H TFTswith planarized gate electrode. Using this structure two different sequences of fabrication are presented,where spin-on glass and silicon nitride are used as passivation layer, respectively. The results show ambi-polar and unipolar behavior in the a-SiGe:H TFTs depending on the fabrication sequence. Also, trap den-sity and characteristic energies for the deep localized states in the a-SiGe:H film are obtained. Using theseparameters the device modeling is presented.

� 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Electronic devices fabricated on flexible and large-area sub-strates are of great interest for the research community. Thin-filmtransistors (TFTs) based on a-Si:H technology have a high potentialto be integrated in this technology due to its low-temperature pro-cess. Also, a-Si:H technology offers the advantage of materials sci-ence, device physics and equipment already well established.

Although complementary logic circuits based on discrete n- andp-type transistors are currently under development [1], the use ofambipolar TFTs that work as both p- and n-type transistors cansimplify the design and reduce the cost of the complementary logiccircuits. The development of an ambipolar TFT technology requiresgood ohmic source and drain contacts (metal–semiconductorinterface) and the use of a high-quality gate dielectric (dielectric-semiconductor interface). So far the ambipolar behavior has beenreported only in devices with a gate dielectric based on SiO2

[2–6], thus, alternative techniques that allow the deposition ofhigh quality SiO2 at low temperatures (<300 �C) are a current fieldof research.

An alternative semiconductor for obtaining ambipolar TFTs fab-ricated at low temperature is hydrogenated amorphous silicon–ger-manium (a-SiGe:H). This film is barely used as an active layer inTFTs, since a high content of germanium increases the density ofstates (DOS) in the film. However, a low incorporation of germa-nium improves some properties of the a-Si:H films, such as electronand hole mobilities [7–9]. Our a-SiGe:H films have estimated elec-tron and hole mobilities of the same magnitude, which indicates apossible candidate for ambipolarity.

Since one of the bottlenecks in this technology is the source/drain contact resistance, different techniques have been imple-mented in order to improve the main device interfaces. Chenet al. reported a reduction in the contact resistance by the planari-zation of the gate electrode [10]. Using this structure, two differentsequences of fabrication are presented, where spin-on glass (SOG)and silicon nitride (SiNx) are used as passivation layer, respec-tively. Also, trap density and characteristic energies for the deep

46 M. Dominguez et al. / Solid-State Electronics 99 (2014) 45–50

localized states in the a-SiGe:H film are obtained. Finally, usingthese parameters the device modeling is presented.

2. Experiment

The planarized a-SiGe:H TFTs used the inverted staggered struc-ture and were fabricated on corning 1737 glass substrates. The pro-cess flow and cross section of the a-SiGe:H TFTs are shown in Fig. 1.The simplified process flow is as follows: first, to planarize the gate,100 nm of SiO2 film was deposited over the corning glass. The highquality SiO2 film was obtained by SOG diluted with deionizedwater (DI) and cured at 200 �C [11]. Then, photoresist was appliedand patterned to leave uncovered the place that will be used forthe gate. Later, the SiO2 film was etching by Reactive Ion Etching(RIE) leaving the place of the gate. The SiO2 film was etched withCF4 plasma at a pressure of 160 mTorr and RF power of 50 W.Finally, as shows Fig. 1a, the planarized gate is formed by lift-offand 100 nm of e-gun evaporated Al. Afterwards, 80 nm-thick ofhigh quality SiO2 by SOG/DI was used as the gate dielectric for bothtransistors (Fig. 1b and f) [11]. From this step, two different fabri-cation sequences were applied. For the a-SiGe:H TFTs using SiNx aspassivation layer, a 100 nm-thick undoped a-SiGe:H and 100 nm-thick SiNx films (Fig. 1c) were deposited using low frequency(110 kHz) plasma enhanced chemical vapor deposition (PECVD)at 200 �C, pressure of 0.6 Torr and an RF power of 300 W. The a-SiGe:H films were deposited from SiH4 and GeH4 feed gases withH2 dilution. The flow rate of SiH4 (10% H2), H2 was 45 sccm and1000 sccm, respectively and the GeH4 (90% H2) flow rate was105 sccm. Later, the SiNx film was patterned as passivation layerabove the a-SiGe:H film using RIE. In this step, in order to achievea high quality metal–semiconductor interface, the surface of the a-SiGe:H film in the source/drain regions was prepared before to

Fig. 1. Process flow and cross section of the inverted staggered a-SiGe:H TFTs (notto scale). (a) Planarization process, (b)–(e) fabrication process for a-SiGe:H TFTsusing SiNx as passivation layer, (f)–(j) fabrication process for a-SiGe:H TFTs usingSOG as passivation layer.

deposit the contact layer [12]. An overetching in the a-SiGe:H filmwas done by RIE as shown in Fig. 1d. The time of the overetchingwas of 30 s (20% of the a-SiGe:H film thickness). After that, ahydrogen plasma was done at 200 �C, with H2 flow of 3500 sccm,pressure of 0.6 Torr and RF power of 300 W for 5 min. Next, as con-tact layer, it was used a lightly doped a-Ge:H film in order to haveohmic contacts and low contact resistance. 40 nm-thick n-type a-Ge:H film was deposited using low frequency PECVD at 200 �Cwith a pressure of 0.6 Torr and RF power of 300 W, with a GeH4

(90% H2) flow of 250 sccm, H2 flow of 3500 sccm and PH3 (99%H2) flow of 20 sccm. Then, 300 nm-thick aluminum was e-gunevaporated and patterned to form the source and drain electrodes.After, the n-type a-Ge:H film was etched using RIE (Fig. 1e). Finally,a thermal treatment at 180 �C for 40 min was done. On the otherhand, for the a-SiGe:H TFTs using SOG as passivation layer, afterplanarize the gate electrode and deposit the SiO2 by SOG/DI as gatedielectric (Fig. 1f), a 100 nm-thick undoped a-SiGe:H and 40 nm-thick n-type a-Ge:H films were deposited using the same recipepreviously used (Fig. 1g). After that, 300 nm-thick aluminum wase-beam evaporated and patterned to form the source and drainelectrodes (Fig. 1h). Then, the n-type a-Ge:H film was etched usingRIE to self-align and to form the source and drain regions (Fig. 1i).Finally, a 80 nm-thick SiO2 passivation layer by SOG/DI cured at200 �C for 1 h. was deposited and patterned (Fig 1j).

3. Results and discussion

3.1. Contact region a-Ge:H films

The requirements for getting a high-quality metal–semiconduc-tor interface are complex. In amorphous semiconductors, the dop-ing efficiency drops at high doping levels. Le Comber and Spear[13] reported that amorphous silicon prepared by PECVD can effec-tively be doped by adding small amounts of phosphine (PH3) to thesilane (SiH4) in the discharge gas. Since in amorphous semiconduc-tors the donors deliver their electrons to empty states at the Fermilevel (deep states), the shift of Fermi level depends on the densityof states distribution [14]. For phosphorus doping, the conductivityincreases at low doping levels. At higher doping levels, conductiv-ity decreases presumably due to the generation of defect states.Therefore, to be used as contact layer, a lightly doped a-Ge:H filmwas previously characterized. The objective was to find the lowestcontact resistance by the characterization of aluminum/a-Ge:Hcontacts. To measure the contact resistance, the Transfer LengthMethod (TLM) was used. This method consists in current–voltagemeasurements of contacts at different separation [15]. Theextracted contact resistance in the Al/a-Ge:H contacts with a-Ge:H films varying the PH3 flow is shown in Fig. 2. It can be seenthe effect of the PH3 flow in the contact resistance, where at lowflow of PH3 the contact resistance decreases but at higher flowincreases. From the values of contact resistance, the lowest wasobtained with PH3 flow of 20 sccm and was close to 1 k Ohms. Thisbehavior agrees with the reported by Le Comber and Spear [13,14].

Moreover, in the a-SiGe:H TFTs using SiNx as passivation layer,the source/drain regions of the a-SiGe:H active layer were preparedprior to deposit the lightly doped a-Ge:H film, in order to achieve ahigh quality metal–semiconductor interface [12]. The interfacepreparation consist in a RIE overetching process, hydrogen plasmaapplication and final thermal treatment. The overetching processassures the etching of the SiNx passivation film and gets closethe lightly doped a-Ge:H film with the induced-channel, reducingthe series resistance associated to the thickness of the a-SiGe:Hfilm [12]. The plasma-induced damage by the RIE overetching pro-cess is reduced with the applied hydrogen plasma and the finalthermal treatment [12]. In the case of a-SiGe:H TFTs using SOGas passivation layer, is important to recall that the a-SiGe:H and

Fig. 2. Contact resistance of the aluminum/a-Ge:H contact as function of the PH3

flow rate.

M. Dominguez et al. / Solid-State Electronics 99 (2014) 45–50 47

a-Ge:H films were deposited with no vacuum break in the cham-ber, for this reason is not possible to use the preparation procedureof the source/drain regions without breaking the vacuum betweenthe followed depositions of the films, however, the final thermaltreatment was replaced with the curing at 200 �C for 1 h of theSOG passivation layer. A longer time in the final thermal treatmentor curing, would result in lower-quality metal–semiconductorinterface.

Fig. 3. Transfer characteristics of the planarized a-SiGe:H TFTs. (a) Using SiNx aspassivation layer and (b) using SOG as passivation layer.

Fig. 4. Output characteristic of the ambipolar a-SiGe:H TFTs.

3.2. Electrical characterization and modeling of thin film transistors

The electrical characterization of the devices was conductedusing the HP 4156B Semiconductor Parameter Analyzer. All the mea-surements were done under dark conditions. The transfer charac-teristics, linear and saturation regime, of both a-SiGe:H TFTs areshown in Fig. 3. For both a-SiGe:H TFTs, in the saturation regime(Vds = |Vgs|), it can be observed an on/off-current ratio > 105 andan off-current < 1 pA at 0 Vgs which are in the range of those inhigh-temperature a-Si:H TFTs. In the transfer characteristics of a-SiGe:H TFTs using SOG as passivation layer, for positive gate biasthe TFTs show n-type behavior, whereas for negative gate bias theyexhibit p-type behavior, as ambipolar devices. The n-type regionshows a subthreshold slope of 0.45 V/decade while the p-typeregion shows a subthreshold slope of 0.49 V/decade. The a-SiGe:HTFTs using SiNx as passivation layer show an unipolar n-typebehavior, the subthreshold slope value was 0.56 V/DEC. From thispoint, the a-SiGe:H TFTs using SOG as passivation layer are referredas ambipolar devices and the TFTs using SiNx as passivation layeras unipolar devices.

Since both a-SiGe:H TFTs have identical gate dielectric-semi-conductor interface and the change in the sequence of fabricationprocess affects only the metal–semiconductor interface, we con-sider the difference in the subthreshold slope just as statisticalfluctuation.

Figs. 4 and 5 show the output characteristics of the ambipolarand unipolar a-SiGe:H TFTs for both positive and negative gatebias. In the case of ambipolar devices, for positive gate bias (n-typeregion), there is an increase in the drain current at high values ofVds due to the superposition of the flow of electrons and holes.In literature the above behavior is called the ambipolar behaviorand is due to the contribution of the drain-induced holes [3]. Fornegative gate bias (p-type region), the output characteristics showa non-linear behavior, however, good current modulation with theapplied gate bias can be seen. This is due to the contribution of the

drain-induced electrons [16–18]. This behavior is also reported inambipolar organic and nanocrystalline silicon TFTs [5,6,16–18].In the case of unipolar devices, for positive gate bias, there is an

Fig. 5. Output characteristics of the unipolar a-SiGe:H TFTs.

Fig. 6. Ids and M curves for the (a) n-type and (b) p-type regions of ambipolar a-SiGe:H TFTs.

Table 1Parameters of planarized a-SiGe:H TFTs.

Parameter Unipolar Ambipolar (n-, p-type)

VT 1.12 V 1.11, �2.18 VVfb 0.18 V 0.16, �0.29 VEA2, ED2 30 meV 26, 47 meV

48 M. Dominguez et al. / Solid-State Electronics 99 (2014) 45–50

expected n-type behavior for output characteristics. For negativegate bias, there is no current modulation with the applied gatebias. These confirm the ambipolar and unipolar behavior of thedevices. Also, it is possible to observe that there is no effect of highcontact resistance, such as current crowding, at low values of Vdsfor ambipolar devices. However, in unipolar devices, is possibleto observe a small effect of current crowding at values of 0 to0.4 Vds.

In summary, the ambipolar behavior was not present in the a-SiGe:H TFTs using SiNx as passivation. However, the a-SiGe:H TFTsusing SOG as passivation presented the ambipolar behavior.

In the ambipolar devices, after deposit the active layer, the con-tact region film was deposited first instead of the passivation filmwith no vacuum break in the chamber. This lead to form ohmiccontacts instead of blocking contacts at negative gate bias. Block-ing contacts in a-SiGe:H TFTs using SiNx as passivation wereobserved at negative gate bias (Fig 5). This may be possible bythe fact that in unipolar devices the a-SiGe:H active layer in thesource/drain regions is exposed to plasma-induced damage bythe RIE overetching process [19,20] and to air (contamination)before to the a-Ge:H film deposition. Meanwhile, in the case ofambipolar devices, the a-SiGe:H active layer is protected with thefollowed a-Ge:H film deposition without vacuum break. In thiswork, the use of SOG or SiNx as passivation layers apparentlymay not have influence in the electrical behavior of the devices.Further studies are required to address these subjects.

On the other hand, the density of states can be obtained fromthe analysis of the transfer characteristics. It is usual to make theassumption that the density of states is homogeneous throughoutthe active layer and that there are no surface states [21]. Since inreality the DOS is not homogeneous, the calculation is a great chal-lenge. The obtained DOS reflects contributions from interfaces, thismake mandatory to have good ohmic source and drain contacts(metal–semiconductor interface) and a high-quality gate dielec-tric-semiconductor interface. It was used the method proposedby Wu et al. [2], to obtain the characteristic energies for the deeplocalized states of the a-SiGe:H film with other device parametersfor the a-SiGe:H TFTs, such as, flat-band voltage Vfb and thresholdvoltage VT. This method was previously used to calculate the deep-states characteristic energies in unplanarized ambipolar a-SiGe:HTFTs fabricated on silicon wafers [22]. Fig. 6 shows the curvesobtained from the M parameter, which is the ratio of the transcon-ductance and drain current in planarized ambipolar a-SiGe:H TFTs.Table 1 summarize results of the electrical measurements. More-over, in the a-SiGe:H TFTs, the subthreshold slope is dependent

on the trap density in the active layer a-SiGe:H (NT) and at theSiO2/a-SiGe:H interface (Dit). The subthreshold slope can beapproximated as the following equation [23]:

S ¼ qKBTðNTtsþ DitÞ=Cox logðeÞ ð1Þ

where q is the electron charge, KB is the Boltzmann constant, T is theabsolute temperature, ts is the a-SiGe:H thickness and Cox is theSiO2 dielectric capacitance per unit area. If NT or Dit is separatelyset to zero, the respective maximum values of NT and Dit areobtained. The NT and Dit values for a-SiGe:H TFTs using SiNx as pas-sivation layer were of 2.65 � 1017 cm�3 eV�1 and 2.65 � 1012 -cm�2 eV�1, respectively, and for a-SiGe:H TFTs using SOG aspassivation layer the values were of 2.13 � 1017 cm�3 eV�1 and2.13 � 1012 cm�2 eV�1, respectively.

As far as we know, since in literature there is no existence eitherphysical nor SPICE models for a-SiGe:H TFTs, we use a typical SPICEmodel used in a-Si:H TFTs. The a-Si:H TFT model used was thepresented by Shur et al. in [24]. This model has been implementedin AIM-SPICE [25]. The details of the a-Si:H TFT model are

Fig. 8. Output characteristics measured and simulated for the ambipolar a-SiGe:HTFTs.

M. Dominguez et al. / Solid-State Electronics 99 (2014) 45–50 49

presented in [26]. Using the parameters extracted from the electri-cal characterization of the planarized ambipolar a-SiGe:H TFTs,SPICE simulations were analyzed.

The density of deep states plays an important role on the sub-threshold region of the device performance. In a-Si:H films, thetypical value of minimum density of deep states g0 is 1 � 1023 -m�3 eV�1 [24,26]. In previous work [22], electrical characterizationof the a-SiGe:H TFTs showed a relatively higher DOS due to theincorporation of germanium, therefore, the value of g0 used to sim-ulate the ambipolar a-SiGe:H TFTs was higher than that in a-Si:HTFTs but lower than the maximum trap density (NT) in the a-SiGe:H film. The value of g0 was of 1.9 � 1023 m�3 eV�1 and wascorroborated by the agreement of the simulated with the experi-mental data. Also, an exponential dependence of the deep states,g(E) = g0 exp [(E � EF0)/EDD], has been demonstrated in the sub-threshold region. EDD is the characteristic energy of the deep statesand its typical value is �120 meV [24,26]. The electrical character-ization of the ambipolar a-SiGe:H TFTs showed characteristic ener-gies of 26 meV and 47 meV for n-type (acceptor-deep states) andp-type (donor-deep states), respectively. The value of EDD used tosimulate the ambipolar a-SiGe:H TFTs was approximately an aver-age of the acceptor and donor characteristic energies (EDD = 40 -meV for both n-type and p-type current models). The values ofEDD and g0 were kept equal for both current models because thisgenerally reports better fit of the experimental data, since bothmodels contribute to simulate a single TFT [5].

The value of the mobility ln in the n-type and p-type (lp) cur-rent models was of 28 and 10 cm2/Vs, respectively. While the otherSPICE parameters were VAA = 16 � 103 V and c = 0.6 for both n-typeand p-type current models.

In Fig. 7, the simulated transfer characteristic of the ambipolardevice is shown. As in the unipolar devices (inset on figures)[27], the simulated transfer characteristic agrees very well withthe measured data. The same parameter set, was used to simulatethe output characteristics as shown in Fig. 8. However, in the out-put characteristics there is no good agreement between the simu-lated and measured data for ambipolar a-SiGe:H TFTs. Despite onthis, it can be see an accurate description of the output character-istics at values of Vds < Vgs. While at values of Vds > Vgs there is anincrease in the drain current due to the superposition of the cur-rents flow of electrons and holes, in the literature this behavior iscalled the ambipolar behavior [3]. While the device is operating insaturation region, an induced hole layer begins to form at the

Fig. 7. Transfer characteristics measured and simulated for the ambipolar a-SiGe:HTFTs. Inset unipolar device [27].

pinch-off region. This hole layer is formed as a result of the largerdrain potential than the gate potential, the drain-gate voltage Vdg.The effects of this ambipolar behavior are not observed in the deviceperformance until the device enters to the condition of Vds > Vgs.As the device enters to this condition, the current begins toincrease due to the current contribution of holes. This behaviorcan be seen in Fig. 9, where the transitions of linear to saturationregions and then to ambipolar behavior (at Vds > Vgs) are appreci-ated, as is reported in literature [3,16–18].

The SPICE model agrees with the experimental data in transfercharacteristics and in the linear and saturation regions of the out-put characteristics (at Vds < Vgs). However, the model needs to beadapted to reproduce the ambipolar behavior (at Vds > Vgs).

It is necessary to add an ambipolar current (Iamb) to Ids [16].This Iamb is the current contribution of the drain-induced carrierin the ambipolar region, holes for the n-type region and electronsfor the p-type region. The current in the ambipolar region is a spacecharge limited current [16]. When Vgs < VT and Vds < Vgs, theIamb = 0. When the device enter to the ambipolar region, the Iambcurrent take the follow value [16]:

Fig. 9. Output characteristic measured and simulated for the ambipolar a-SiGe:HTFTs at 4 V of Vgs. Inset unipolar device [27].

Fig. 10. Output characteristic measured and simulated for the ambipolar a-SiGe:HTFTs taking into account the ambipolar current contribution.

50 M. Dominguez et al. / Solid-State Electronics 99 (2014) 45–50

Iamb ¼ lFE � CoxðW=2LÞðVds� ðVgs� VTÞÞ2 ð2Þ

where lFE is the field-effect mobility, Cox is the capacitance per unitarea of the gate dielectric, W and L are the channel width and thelength, respectively, and VT is the threshold voltage. Then, the Idscurrent is the Iamb current add to the unipolar current previouslysimulated. The value of lFE is the lFET parameter used in the SPICEmodel presented by Shur, which is a weak function of gate bias andcan be adequately described by a power law with a constant expo-nent as shows Eq. 3.

lFET ¼ lnðVGTe � VT=VAAÞc ð3Þ

Fig. 10 shows the simulated output characteristics of the ambi-polar device, the simulation agrees very well with the measureddata. The model successfully reproduces both measured transferand output characteristics over a wide range of Vgs and Vdsvoltages.

4. Conclusions

The a-SiGe:H TFTs using SOG as passivation presented ambipo-lar behavior, while the a-SiGe:H TFTs using SiNx as passivationpresented unipolar behavior. The use of SOG or SiNx as passivationlayers apparently may have no influence in the electrical behaviorof the devices. Thus, this ambipolar behavior apparently is more

related with the quality in the metal–semiconductor interface ofthe device, since the a-SiGe:H active layer is protected with the fol-lowed a-Ge:H film deposition without vacuum break. The results ofthe SPICE modeling are in agreement with the reported in litera-ture, where the ambipolar behavior is observed when the deviceenters to the condition Vds > Vgs. In the SPICE modeling, the tran-sitions of linear to saturation regions and then to ambipolar behav-ior (at Vds > Vgs) are appreciated.

Acknowledgment

The authors want to thank to all personnel of the Laboratory ofMicroelectronics at INAOE and to the CONACYT-Mexico for thescholarship No. 160547.

References

[1] Moustapha O, Abramov A, Daineka D, Oudwan M, Bonnassieux Y, Roca iCabarrocas P, et al. Phys Status Solidi C 2010;7.3-4:1140.

[2] Wu B, Hao C, Wu T, Chen M, Jow M, Chen H. IEEE Trans Electron Dev1989;36(12):2903.

[3] Neudeck G, Bare H, Chung K. IEEE Trans Electron Devices ED-34 1987;2:344.[4] Pfleiderer H. IEEE Trans Electron Devices ED-33 1986;1:145.[5] Subramaniam A, Cantley K, Stiegler H, Chapman R, Vogel E. IEEE Trans Electron

Devices 2012;59:359.[6] Lee C, Sazonov A, Rad M, Chaji G, Nathan A. Mater Res Soc Symp Proc

2006;910:A22–05.[7] Lin C, Yeh R, Li I, Hong J. Solid State Electron 2003;47:1787.[8] Rosales P, Torres A, Murphy R, De la Hidalga F, Marsal L, Cabre R, et al. J Appl

Phys 2005;97:083710–1.[9] Rosales P, Torres A, Murphy R, Landa M. Semiconduct Sci Technol 2004;19:366.

[10] Chen M, Chou J, Lee S. IEEE Trans Electron Devices 1995;42:1918.[11] Dominguez M, Rosales P, Torres A, Moreno M, Orduña A. Thin Solid Films

2012;520:5018.[12] Dominguez M, Rosales P, Torres A. Solid State Electron 2012;76:44.[13] LeComber P, Spear W. Solid State Commun 1975;17:1193.[14] Baranovski S. Charge transport in disordered solids with applications in

electronics. Chichester: John Wiley & Sons Ltd.; 2006. pp. 115–121.[15] Schroder D. Semiconductor material and device characterization. New

York: Wiley; 1998.[16] Zaumseil J, Sirringhaus H. Chem Rev 2007;107:1296.[17] Ye R, Baba M, Suzuki K, Mori K. Solid State Electron 2008;52:60.[18] Yang C, Kwack Y, Kim S, An T, Hong K, Nam S, et al. Org Electron 2011;12:411.[19] Chen C, Wang S, Shieh M, Chen W, Lin H, Yeh K, et al. J Electrochem Soc

2007;154:H30.[20] Kuo Y, Crowder M. J Electrochem Soc 1992;139:548.[21] Powell M. IEEE Trans Electron Devices 1989;36:2753.[22] Dominguez M, Rosales P, Torres A, Moreno M, Molina J, De la Hidalga F, et al. J

Non-Cryst Solids 2012;358:2340.[23] Lee C, Striakhilev D, Tao S, Nathan A. IEEE Electron Device Lett 2005;26:637.[24] Shur M, Slade H, Jacunski M, Owusu A, Ytterdal T. J Electrochem Soc

1997;144:2833.[25] http://www.aimspice.com/.[26] Shur M, Slade H, Ytterdal T, Wang L, Xu Z, Hack M, et al. Mater Res Soc Symp

Proc 1997;467:831.[27] Dominguez M, Rosales P, Torres A. Rev Mex Fis 2013;59:62.