plasma display address electrode driving.pdf

7/27/2019 plasma display address electrode driving.pdf

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www.fairchildsemi.com

2007 Fairchild Semiconductor Corporation www.fairchildsemi.comRev. 1.0.0 9/4/07

AN-9038

PDP Panel Drive System Using PDP-SPM

TMModule

By S.N. Kim, D.C. Choi, J.E. Yeon, C.K. Kim

Contents

1. Introduction

2. Plasma Display Panel

2.1. Consist of an AC PDP Panel2.2. Commercial Driving Scheme for AC PDPs

2.3. Driving Methods for AC PDPs

2.4. Driving Sequence and Waveforms in Sustain Mode

3. Product Outline of PDP-SPM

3.1. Ordering Information

3.2. Product Selection

3.3. Internal Circuit and features

3.4. Package Outline

4. Application Outline

4.1. Overview of Application Circuit

4.2. Bootst rap Circuit

4.3. Footpr int Guide of PDP-SPM for PCB Design

5. Package

5.1. Heat Sink Mounting

5.2. Handling Precaution

5.3. Marking Specifications

5.4. Packaging Specifications


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APP NOTE NUMBER APPLICATION NOTE

2007 Fairchild Semiconductor Corporation www.fairchildsemi.comRev. 1.0.0 9/4/07 2

1. Introduct ion

This PDP-SPMTM module combines an optimized circuit

in a buffer IC and a drive that is matched to the IGBTs

switching characteristics. System reliability is further

enhanced by integrated under-voltage protection and high

driving capability. The PDP- SPM module is an advanced

module designed to achieve high system reliability.

This application note explains how to design the detailed

power circuit of PDP-SPM and its applications for users.

This document provides a design example with a sustain

and ER module, which is a well-known driving method and

sequence of PDP panel driving.

2. Plasma Display Panel

2.1 Consist of an AC PDP panelA PDP is a display device with self-emission

characteristics. This device used plasma discharge in order

to utilizing the light emission.

This device has commonly Surface Discharge Structure for

long life and high brightness.

Fig. 1. is simplified cross sectional structure of Alternating

Current (AC) PDP.

Figure 1. Cross Sectional Structure of AC Plasma

Display Panel (PDP)

As shown in the figure above, the AC PDP is composed of

three electrodes, two bus electrodes, whose role is to makelight emissions, one bus and address electrode, whose

function is to make a wall charge before plasma discharge

during sustain period.

Meanwhile, since bus electrodes are covered with the

dielectric and MgO, the load characteristics of the AC PDP

can be represented by the capacitive load.

Fig. 2. is an equivalent circuit for inherent capacitance of

PDP cell.

Figure 2. Equivalent Circuit for inherent

capacitance of PDP cell

2.2 Commercial driving scheme for AC PDPsMost AC PDPs use Address Data Separation(ADS)

method for displaying one picture as shown Fig. 3.

On every sub-fields consist of reset, address and sustain

period. The number of subfield is variable by picture

brightness and power consumption. During the reset period,

the PDP cell is initiated without any charge for unexpected

discharging. During the address period, wall charge

accumulated in the PDP cell for sustaining. The gas

discharge occurs during sustain period, which is for light

emission.

Meanwhile, most of the power that is required to drive the

PDP is consumed driving the sustaining period. In otherwords, the power switches in the sustain circuit are

primarily responsible for efficiency and size of the overall

system.

SF : sub-field

Figure 3. ADS of one TV field

2.3 Driving Methods for AC PDPsThis application note deals with Weber driving method that

is commonly used.


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Fig.4. is conventional driving pulse at Weber driving

method, X and Y are Bus electrodes, A is Address

electrode.

Figure 4. Weber Driving Method

In general, X and Y electrode are operating a full-

bridge configuration as shown in Fig.5. This schematic

diagram is conventional Weber circuit. This is the leadingthat is now used by many PDP manufacturers.

This application note focus on the sustain period, so there

is a focus on sustain and energy recovery block.

Power devices in Fig.5. can be grouped as a functional

unit :

- Energy recovery circuit : Q3~4, Q7~8, D3~4, D7~8

- Sustain circuit : Q1~2, Q5~6, D1~2, D5~6

The sustain block is operating as full-bridge and the

energy recovery block is operating leading and lagging

energy for give-and-take charges to the PDP cells with the

assistance of sustain operating.

2.4 Driving Sequence and Waveform in SustainModeFig.6. is shown t1~t5 which are the timing flows at Y-

board at sustain period.

The t1 is given the energy through the PDP panel from Y-

board to X-board. The panel voltage goes high as rate of LC

resonance frequency. L is series inductor including

parasitic inductance and C is an equivalent capacitor of

panel.

The t2 is sustaining the energy. During the t2, PDP panel

is charged positive across Y to X board, and the panel

voltage is maintained to Vs.

The t3 is recovered the energy which is charged in Panel,

and the panel capacitor discharges until the panel voltagedrops to zero.

The t4 is free-wheel time and the ground potential is

supplied to the panel.

The t5 is same function like t1, energy flow from X-board

to Y-board

Next time sequence is alternating as same flow.

Figure 6. Driving sequence during sustain period

The waveform in board output is Fig.7. in PDP set.

Figure 7. X & Y board voltage waveform at

sustain period

Figure 5. Schematic diagram of Y- & X- electrode

Reset Address SustainSustain


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3. Product outline of PDP-SPM module

3.1 Ordering Information3.2 Product Selection

Rating

Part Number Current

(A)

Voltage

(V)

MainApplication

FVP18030IM3LSV1 180 300 Sustain

FVP12030IM3LEG1 120 300 ER

3.3 Internal Circuit and features Use of high speed 300V IGBTs with parallel FRDs

Single-grounded power supply by means of built-in

HVIC

Sufficient current driving capability for IGBTs due to

adding buffer ICs.

Low leakage current due to using an insulated metal

substrate

Metal part IMS is connected with IGND pin for heat-sink

ground.

Sustain and ER module each consist of a board

(a) Sustain ( FVP18030IMS3LSG1 ) (b) ER ( FVP12030IMS3LEG1 )

Figure 8. Internal circu it


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3.4 Package DimensionsThese two modules are distinguished from IGND(Pin7)

(a) Sustain ( FVP18030IMS3LSG1 ) (b) ER ( FVP12030IMS3LEG1 )

Figure 9. Package Dimensions

4. Application Outline

4.1 Overview of Application Circuit

(1) COML

(2) VINL

(3) VCCL

(4) VBL

(5) G L(6) VS

L

(7) I GND

(8) COMH

(9) VINH

(10) VCCH

(11) VBH

(13) VSH

(12) GH

(19) EL

(18) AL

(17) CL

(16) AH

(15) EH

(14) CH

(1) COML

(2) VINL

(3) VCC L

(4) VBL

(5) GL

(6) VSL

(7) I GND

(8) COMH

(9) VINH

(10) VCCH

(11) VBH

(13) VSH

(12) GH

(19) EL

(18) CL

(17) AL

(16) KH

(15) EH

(14) CH

SUS_DN

+ Vcc

SUS_UP

ER_DN

ER_UP

+ Vs

+ Vs

DZSP

CSPC

CSP

RIN

DZBS

CBS

RIN

DBSRBS

DZBS

CBS

DZSP

CSPC

CSP

RIN

DZBS

CBS

RIN

DBSRBSDZBS

CBS

RBS

DBS

ERC

C CLAMP

C CLAMP

ERL

CP

CP

FVP

18030IM3LSG1

FVP1203

0IM3LEG1

(1) COML

(2) VINL

(3) VCCL

(4) VBL

(5) GL

(6) VSL

(7) I GND

(8) COMH

(9) VINH

(10) VCCH

(11) VBH

(13) VSH

(12) GH

(19) EL

(18) AL

(17) CL

(16) AH

(15) EH

(14) CH

(1) COML

(2) VINL

(3) VCCL

(4) VBL

(5) GL

(6) VSL

(7) I GND

(8) COMH

(9) VINH

(10) VCC H

(11) VBH

(13) VSH

(12) GH

(19) EL

(18) CL

(17) AL

(16) KH

(15) EH

(14) CH

SUS_DN

+ Vcc

SUS_UP

ER_DN

ER_UP

+ Vs

+ Vs

DZSP

CSPC

CSP

RIN

DZBS

CBS

RIN

DB S RB SDZBS

CBS

DZSP

CSPC

CSP

RIN

DZBS

CBS

RIN

DB S RB S

DZBS

CBS

RBS

DBS

ERC

CCLAMP

C CLAMP

ERL

CP

CP

FVP1

8030IM3LSG1

F

VP12030IM3LEG1

Panel

Y - Board X- Board

Cp

CSP

CSP CSP

CSP

Figure 10. Overview of Application circu it


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Figure 4.1 shows a typical application circuit of a sustain

and energy recovery block to compose the Webber circuit

that is used to drive the PDP. The circuits of X and Y-

board are identical and symmetry structure.

4.2 Bootst rap Circuit4.2.1 Operation of Bootstrap Circuit of Sustain part

The VBS voltage, which is the voltage difference between

VB and VS, provides the supply to the HVICs and the

buffer ICs within the PDP-SPM in VPM19. This supply

must be in the range of 13.0~20V to ensure that the buffer

IC can fully drive the IGBT. The PDP-SPM module

includes an under-voltage detection function for the VBS to

ensure that the HVIC does not drive the IGBT. If the VBS

voltage drops below a specified voltage (refer to the

datasheet). This function prevents the IGBT from operating

in a high dissipation mode.

There are a number of ways in which the VBS floating supply

can be generated. One of them is the bootstrap method

described in the following way. This method has the advantage

ofbeing simple and inexpensive. However, the duty cycle

and on-time are limited by the requirement to refresh the

charge in the bootstrap capacitor. The bootstrap supply is

formed by a combination of an external diode, resistor and

capacitor as shown in Figure 10. The current flow path of

the bootstrap circuit is shown in Figure 11, 12, 13. When theSUS-DNs switch is on, the SUS-UP and ER-UPs bootstrap

capacitor (CBS) is charged through the bootstrap diode (DBS)

and the resistor (RBS) from the VCC supply. And when the

ER-UPs switch is on, the ER-DNs bootstrap capacitor is

charged through the bootstrap diode(DBS), the resister(RBS)

and the ER-UPs IGBT in figure 13. ER-DNs bootstrapsystem uses the ER-UPs bootstrap voltage to power source

instead of the VCC supply.

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

DBS

RBS

CBS

+Vs

VCC

SUS-DN

Figure 11. SUS-UP Boots trap Circuit

+Vs

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

DBS

RBS

VCC

CBS

CBS

RBS

DBS

SUS-DN

SUS-UP

ER-UP

ER-DN

ERC

ERL

Figure 12. ER-UP Boots trap Circuit

+Vs

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

DBS

RBS

VCC

CBS

CBS

RBS

DBS

SUS-DN

SUS-UP

ER-UP

ER-DN

ERC

ERL

Figure 13. ER-DN Boots trap Circuit

4.2.2 Initial Charging of Bootstrap Capacitor

An adequate on-time duration of the IGBT on the current

flow path of the bootstrap circuit to fully charge the

bootstrap capacitor is required for initial bootstrap

charging. The initial charging time (tcharge) can be calculated

from the following equation:

for SUS-UP

)ln((min)

arg

LSfBSCC

CCBSBSech

VVVV

VRCt

1 (4-1)

for ER-UP

)ln(

)(

(min)

arg

LSfBSCC

CC

ERLBSBSech

VVVV

V

RRCt

+

1

(4-2)

for ER-DN

)ln((min)_

_

arg

HSfBSUPERBS

UPERBS

BSBSech

VVVV

V

RCt

1

(4-3)


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Vf = Forward voltage drop across the bootstrap diode

VBS(min) = The minimum value of the bootstrap capacitor

VHS = Voltage drop across the high-side IGBT in ER

VLS = Voltage drop across the low-side IGBT in SUS

RERL = The equivalent resistance of ERL inductor

= Duty ratio of of the IGBT on the current flow path

VIN: SUS-Down

0V

0VSustain

&

Energy

Recovery

Circuits

Operation

t

VBS

VCC

VIN : ER-Up

Figure 14. Timing Chart of Initial Boots trapCharging

4.2.3 Selection of a Bootstrap Capacitor

The bootstrap capacitance can be calculated by:

V

tIC

BS

BS

=

(max) (4-4)

Where

t = maximum ON pulse width of floating-side IGBTV = the allowable discharge voltage of the CBS.

IBS(max) = maximum discharge current of the CBS mainly via

the following mechanisms:

(1) Gate charge for turning the floating-side IGBT on

(2) Quiescent current to the high-side circuit in the IC

(3) Level-shift charge required by level-shifters in the IC

(4) Leakage current in the bootstrap capacitor(CBS)

leakage current (ignored for non-electrolytic

capacitors)

(5) Bootstrap diode reverse recovery chargeBy taking consideration of dispersion and reliability, the

capacitance is generally selected to be 2~3 times of the

calculated one. The CBS is only charged when the floating-

side IGBT is off and the VS voltage is pulled down to

ground. Therefore, the on-time of the SUS-DNs IGBT(ER-

UPs IGBT for ER-DN) must be sufficient to ensure that

the charge drawn from the CBS capacitor can be fully

replenished. Hence, inherently there is a minimum on-time

of the SUS-DNs IGBT(ER-UPs IGBT for ER-DN) (or

off-time of the floating-side IGBT).

The bootstrap capacitor should always be placed as close to

the pins of the SPM as possible. At least one low ESR

capacitor should be used to provide good local de-coupling.

For example, a separate ceramic capacitor close to the SPM

is essential, if an electrolytic capacitor is used for the

bootstrap capacitor. If the bootstrap capacitor is either a

ceramic or tantalum type, it should be adequate for localdecoupling.

4.2.3 Selection of a Bootstrap Diode

When floating-side IGBT or diode conducts, the bootstrap

diode (DBS) supports the entire sustain voltage. Hence the

withstand voltage more than 300V is recommended. It is

important that this diode should be fast recovery (recovery

time < 100ns) device to minimize the amount of charge that

is fed back from the bootstrap capacitor into the VCC

supply.

4.2.4 Selection of a Bootstrap Resistance

A resistor RBS

must be added in series with the bootstrapdiode to slow down the dVBS/dt and it also determines the

time to charge the bootstrap capacitor. That is, if the

minimum ON pulse width of the IGBT on the bootstrap

charging current flow path or the minimum OFF pulse

width of floating-side IGBT is t0, the bootstrap capacitor

has to be charged V during this period. Therefore, the

value of bootstrap resistance can be calculated by the

following equation.

VC

tVVccR

BS

OBSBS

=

)( (4-5)

In conclusion, RBS is selected to the maximum value

between the two values calculated by the equations and its

power rating is greater than 1/4W. Note that if the rising

dVBS/dt is slowed down significantly, it could temporarily

result in a few missing pulses during the start-up phase due

to insufficient VBS voltage.

4.2.4 Charging and Discharging of the Bootstrap Capacitor

The bootstrap capacitor (CBS) charges through the path as

shown Fig. 11, 12 and 13 when the floating-side IGBT is

off, and the VS voltage is pulled down to ground. Itdischarges when the floating-side IGBT is on.

Example 1: Selection of the Initial Charging Time

An example of the calculation of the minimum value of the

initial charging time is given with reference to equation

(4.1) to (4.3).

Conditions:

CBS = 10 F

RBS = 5.6

Duty Ratio()= 0.2


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DBS = 1N4937 (600V/1A rating)

VCC = 15V

Vf = 0.5V

VBS(min) = 13V

VHS =VLS= 0.7V

VERL=0.01

us

VVVV

VuFt ech 821

70501315

15

20

16510

)

..

ln(

.

.arg

(4-6)

In order to ensure safety, it is recommended that the

charging time must be at least three times longer than the

calculated value.

Example 2: The Minimum Value of the Bootstrap

Capacitor

Conditions :

V = 0.8V

t = 0.5usec

IBS(max) = 5A

uFV

usACBS 13380

505..

.=

The calculated bootstrap capacitance is about 3uF. By

taking consideration of dispersion and reliability, the

capacitance is generally selected to be 2-3 times of the

calculated one. Note that this result is only an example. It is

recommended that you design a system by taking

consideration of the actual control pattern and lifetime of

components.

4.2.5 Recommended Boot Strap Operation Circuit and

Parameters

Figure 4.6 is the recommended bootstrap operation circuit and

parameters.

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

+VsDBSRBS

+15V line

10uF

5.6

1uF

10uF 1uF

(a) Sustain circuit

+Vs

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

VCC

VB

OUTCOM

IN Vs

VCC

OUTIN

GND

DBS

RBS

RBS

DBS

SUS-DN

SUS-UP

ERC

ERL

5.6

5.610uF 1uF

10uF 1uF+15V line

(b) ER circuit

Figure 15. Recommended Boots trap Circuit and Parameters

4.3 Footpr int Guide of PDP-SPM for PCB design

Since the lead pins of the PDP- SPM have 7o angle as

shown figure 16 (a), the specific footprint guide is needed

to design the PCB for assembly between PCB and PDP

SPM and for the distance of electric safety between each

pins as shown figure 16 (b) and (c).


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Unit : mmUnit : mm

(a)Pin Pitch of PDP-SPM( side view )

Min.Min.

Max. Max.

Unit : mm

Min.Min.

Max. Max.

Unit : mm

(b) Footprint guide of Sustain

( top view )

Min.

Max.

Min.

Max.

Unit : mm

Min.

Max.

Min.

Max.

Unit : mm

(c) Footprint guide of ER

( top view )Figure 16. Recommended Footpr int Guide for PCB design.

5. Package

5.1 Heat Sink MountingThe following precautions should be observed to maximize

the effect of the heat sink and minimize device stress, when

mounting an SPM on a heat sink.

Heat Sink

Please follow the instructions of the manufacturer, when

attaching a heat sink to a PDP-SPM module. Be careful not

to apply excessive force to the device when attaching theheat sink.

Drill holes for screws in the heat sink exactly as specified.

Smooth the surface by removing burrs and protrusions of

indentations. Refer to Table 1.

Heat-sink-equipped devices can become very hot when in

operation. Do not touch, as you may sustain a burn injury.

Silicon Grease

Apply silicon grease between the SPM and the heat sink toreduce the contact thermal resistance. Be sure to apply the

coating thinly and evenly, do not use too much. A uniform

layer of silicon grease (100 ~ 200um thickness) should be

applied in this situation.

Screw Tightening Torque

Do not exceed the specified fastening torque. Over

tightening the screws may cause ceramic cracks and bolts

and AL heat-fin destruction. Tightening the screws beyond

a certain torque can cause saturation of the contact thermal

resistance. The tightening torques in table 1 isrecommended for obtaining the proper contact thermal

resistance and avoiding the application of excessive stress

to the device.

Avoid stress due to tightening on one side only. Figure 17

shows the recommended torque order for mounting screws.

Table 1 Torque Rating


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Figure 17. Flatness Measurement Position

5.2 Handling PrecautionWhen using semiconductors, the incidence of thermal

and/or mechanical stress to the devices due to improper

handling may result in significant deterioration of their

electrical characteristics and/or reliability.

Transportation

Handle the device and packaging material with care. To

avoid damage to the device, do not toss or drop. During

transport, ensure that the device is not subjected to

mechanical vibration or shock. Avoid getting devices wet.

Moisture can also adversely affect the packaging (by

nullifying the effect of the antistatic agent). Place the

devices in special conductive trays. When handling devices,

hold the package and avoid touching the leads, especially

the gate terminal. Put package boxes in the correct

direction. Putting them upside down, leaning them or

giving them uneven stress might cause the electrode

terminals to be deformed or the resin case to be damaged.

Throwing or dropping the packaging boxes might cause the

devices to be damaged. Wetting the packaging boxes might

cause the breakdown of devices when operating. Pay

attention not to wet them when transporting on a rainy or a

snowy day.

Storage

1) Avoid locations where devices will be exposed to

moisture or direct sunlight. (Be especially careful during

periods of rain or snow.)

2) Do not place the device cartons upside down. Stack the

cartons atop one another in an upright position only.: Do

not place cartons on their sides.

3) The storage area temperature should be maintained

within a range of 5C to 35C, with humidity kept within

the range from 40% to 75%.

4) Do not store devices in the presence of harmful

(especially corrosive) gases, or in dusty conditions.

5) Use storage areas where there is minimal temperature

fluctuation. Rapid temperature changes can cause moisture

condensation on stored devices, resulting in lead oxidation

or corrosion. As a result, lead solder ability will be

degraded.6) When repacking devices, use antistatic containers.

Unused devices should be stored no longer than one month.

7) Do not allow external forces or loads to be applied to the

devices while they are in storage.

Environment

1) When humidity in the working environment decreases,

the human body and other insulators can easily become

charged with electrostatic electricity due to friction.

Maintain the recommended humidity of 40% to 60% in the

work environment. Be aware of the risk of moistureabsorption by the products after unpacking from moisture-

proof packaging.

2) Be sure that all equipment, jigs and tools in the working

area are grounded to earth.

3) Place a conductive mat over the floor of the work area,

or take other appropriate measures, so that the floor surface

is grounded to earth and is protected against electrostatic

electricity.

4) Cover the workbench surface with a conductive mat,

grounded to earth, to disperse electrostatic electricity on the

surface through resistive components. Workbench surfacesmust not be constructed of low-resistance metallic material

that allows rapid static discharge when a charged device

touches it directly.

5) Ensure that work chairs are protected with an antistatic

textile cover and are grounded to the floor surface with a

grounding chain.

6) Install antistatic mats on storage shelf surfaces.


11/14



7) For transport and temporary storage of devices, use

containers that are made of antistatic materials of materials

that dissipate static electricity.

8) Make sure cart surfaces that come into contact with

device packaging are made of materials that will conduct

static electricity, and are grounded to the floor surface with

a grounding chain.

9) Operators must wear antistatic clothing and conductiveshoes (or a leg or heel strap).

10) Operators must wear a wrist strap grounded to earth

through a resistor of about 1M&.

11) If the tweezers you use are likely to touch the device

terminals, use an antistatic type and avoid metallic

tweezers. If a charged device touches such a low resistance

tool, a rapid discharge can occur. When using vacuum

tweezers, attach a conductive chucking pad at the tip and

connect it to a dedicated ground used expressly for

antistatic purposes.

12) When storing device-mounted circuit boards, use a

board container or bag that is protected against static

charge. Keep them separated from each other, and do not

stack them directly on top of one another, to prevent static

charge/discharge which occurs due to friction.

13) Ensure that articles (such as clip-boards) that are

brought into static electricity control areas are constructed

of antistatic materials as far as possible.14) In cases where the human body comes into direct

contact with a device, be sure to wear finger cots or gloves

protected against static electricity.

Electrical Shock

A device undergoing electrical measurement poses the

danger of electrical shock. Do not touch the device unless

you are sure that the power to the measuring instrument is

off.

5.3 Marking Specifications

(a) Sustain ( FVP18030IMS3LSG1 ) (b) ER (FVP12030IMS3LEG1 )Figure 18. Marking Layout (bottom side)

(a) Sustain ( FVP18030IMS3LSG1 ) (b) ER (FVP12030IMS3LEG1 )


12/14



Figure 19. Marking Dimension of PDP-SPM

1. F : FAIRCHILD LOGO (STYLE & SIZE : SEE SPEC BD-2249)2. XXX : Last 3 digits of Lot No (OPTION CODE)3. YWW : WORK WEEK CODE ("Y" refers to the right alphabet character table)

Table 2 Work Week Code

5.4 Packaging Specifications


13/14



Figure 20. Description of packaging process


14/14

www.fairchildsemi.com

2007 Fairchild Semiconductor Corporation www.fairchildsemi.comRev. 1.0.0 9/4/07

References

[ 1 ] Sang-Kyoo Han, New High-Performance Energy-

Recovery Driver System and High-Efficiency PowerConversion Circuit for Plasma Display Panel

[ 2 ] Motion System Gr, Smart Power Module, Motion

SPM in Mini-Dip Users Guide, Fairchild Semiconductor

Application Note AN-9035, Rev.B.

DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTSHEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THEAPPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITSPATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICYFAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMSWITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or(b) support or sustain life, or (c) whose failure to performwhen properly used in accordance with instructions for useprovided in the labeling, can be reasonably expected toresult in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonablyexpected to cause the failure of the life support device orsystem, or to affect its safety or effectiveness.

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