PLC front-end Design Review

Curtis Mayberry

7-5-11

Revised Project Description

Block Diagram

RTDTC

Thermistor+/-10v, +/-5v

4-20mA

Signal Conditioning MicrocontrollerADC

Cost-Effective

High-Accuracy

Super-Mini DigLabview

Stage 1 Stage 2

The Plan

• May 16: First Day

• May 21: Project Definition & training (1 week)

• June 5 - June 10: FAE conference in Tucson (1 week)

• July 5: Block Diagrams, calculations (accuracy), simulations, Part selection & ordering, initial schematic (4 weeks)

• July 14: PCB layout (2 weeks)

• July 21: Basic LabView Coding & Testing preparation (1 week)

• July 29: Initial lab results -Oven(~1 weeks)

• August 3: Accuracy tests (Tucson?)

• August 5: Final Report (2 days)

• August 10: Preliminary Presentation (2 days)

• August 12: Final Presentation (2 days)

• August 18: Last Day (1 week)

Universal Inputs

0-10v and +/- 10v, 0-5v and +/- 5v, 4-20mA

Universal Voltage Input

• 0-5v, 0-10v, +/- 5v and +/- 10v universal voltage input

• Change resistance values to change input voltage levels

• Second order RC filter with poles at 39 Hz and 3900Hz

• Opamp to scale down input

• 2.5v reference generated to scale input

• Opa2333: Low offset voltage and drift, rail-to-rail input, dual opamp part

Noise Calculations: Voltage Reference

• 2.5v Reference– REF5025: 625nVRMS

– OPA333: 869 nVRMS

– Filter KTC noise: 202.8nVRMS

– Reference Output 10kΩ: 202.8 nVRMS

– Total Noise: 1.108µVRMS

RMSHznV

BB

n

HznV

nVHzen

HzHzBW

86963.249)55(

63.249)57.1)(159(

noise) 1/f (no 55 :noise BB

RMS

KJ

R

n

nV

Hzkken

HzHzBW

8.202

)9.249)(10)(15.298)(1038.1(4

9.249)57.1)(15.159(

23

RMSKJ

filter nVnF

ken 84.202

100

)15.298)(1038.1( 23

RMSREF VnVnVnVen 108.1)625()8.202(2)869( 222

– Current Noise: 26.34nVRMS (negligible)

RMS

HznV

BB

nV

kHzen

34.26

)67.16(63.249)100(

RMSppREF nVVen 625)5.7(21

5025

Noise Calculations

• Input Filter – 82nF filter KTC noise: 224 nVRMS

– 820pF filter noise: 211.47 nVRMS

– Total Noise: 308.5 nVRMS

• Amplifier Noise:– Feedback Network (16.67kΩ):

828nVRMS

– OPA333 noise: 869.5nVRMS

– Total Noise: 1.2µVRMS

RMSHznV

BB

n

HznV

nVHzen

HzHzBW

5.8699.249)55(

9.249)57.1)(15.159(

noise) 1/f (no 55 :noise BB

RMS

KJ

R

nV

Hzkken

47.211

)4.1)(818.38)(50)(15.298)(1038.1(4 23

Noise Calculations: Total

• ADC V+ input noise total: 1.503µVRMS

• ADC V- input noise total:1.089uVRMS

RMS

kk

kk

V

V

nVVnVVen

503.1

)8.202()2.1)2.1(()5.308))(2.1(()108.1))(2.1(( 2

filteroutput

2

amplifier

2

filterinput

1201002

Ref

12020

RMSV VnVnVnVen 089.1)625()8.202()869( 222

Noise Calculations: Bringing it all together

• ADC noise: 1.35 µVRMS

– Noise at Apga =1 and 5 SPS

FS of %000358.060

771.13295.2

)089.1()503.1()35.1(noiseOuput 2

-V

2

V

2

ADC

bits

VV

VVV

PPRMS

Resistor Mismatch Errors (Worse Case)

• Resistor Options (worse case)– Set 1: 668.7 µV (0.1% resistors)

– Set 2: 3.337 mV (0.1% resistors)

– Set 2: 1.668 mV (0.05% resistors)

– Set 2:666.8 µV (0.02% resistors)

– Total: 1.797mV

mV

vVERROR

337.3

)100

20

%1.0100%1.020120

%1.02020)(67.1(

VvVERROR 67.668)100

20

20*%1.0100

20*%1.020)(67.1(

mV

vVERROR

668.1

)100

20

%05.0100%05.020120

%05.02020)(10(

V

vVERROR

8.666

)100

20

%02.0100%02.020120

%02.02020)(10(

mVmVV 797.1)668.1()7.668(ErrorGain Mismatch Total 22

Set 1

Set 2

Resistor Tolerance Monte Carlo Simulation

• Ran Monte Carlo Simulation using 0.1% resistors

• 2.5 mV max error on output

• Used an ideal op-amp to isolate the error source

• Small variation between resistor tolerances

Error Estimation

• ADC– 15µV offset– INL: 6 ppm– Gain Error: 0.02%– External Reference: 0.05%*2.024V = 1.024 mV– Total: 1.230 mV

• Level shifting OPA2333– Offset: 10 µV– Offset drift: 0.05 µV/oc– CMRR >106 dB– PSRR: 5 µV/V (max)

• 2.5v Reference OPA2333– Offset: 10 µV– Offset drift: 0.05 µV/oc (3µV over 25oC ± 60oC temperature range)– CMRR >106 dB– PSRR: 5 µV/V (max)

Vv 244*10

66

Vv 8004*0002.0

20,,, 10

CMRR

dcmincmincmcmo AVVAV

PSRRAVV dPSnoiseoffset PS o,

Error Estimation

• Resistor Mismatch: 1.797 mV

• REF5025 2.5v reference: 1.25 mV offset is cancelled out

• Total:

with no “interference”: 2.178 mV

2PSnoise

220,

2222 )(2)10(2))25)(05.0((2)797.1()10(2)230.1( PSRRAVAVCTmVVmV d

CMRR

dcmino

C

Vo

mVmVmV 178.2)797.1()23.1( 22

Simulation: +/- 10v

Simulation: +/- 5v

Universal Current input

• 4-20mA

• Second order RC filter

• Internal 2.048v reference

• 221Ω shunt converts 4-20mA to 884mV-4.420V

• OPA2333: Rail-to-Rail common mode input, low offset voltage and drift

Simulation

2.5v reference

Differential output

Noise Analysis

• OPA333 buffer noise: 869.5 nVRMS

• Resistor Noise– 10kΩ: 202.8 nV– 16kΩ: 123 nV– 1.6kΩ: 31.1 nV

• V+ Total Noise: 901.8 nVRMS

• V- Total Noise: 1.089 µVRMS (Same as Vinput V-)

• ADC noise: 1.35 µVRMS – Noise at Apga =1 and 5 SPS

• Total noise: 11.729 µVPP

RMSHznV

BB

n

HznV

nVHzen

HzHzBW

5.8699.249)55(

9.249)57.1)(15.159(

noise) 1/f (no 55 :noise BB

RMSV VnVnVnVen 089.1)625()8.202()869( 222

FS of %1029249

729.11954.1

)089.1()8.901()35.1(noiseOuput

6

2

-V

2

V

2

ADC

bits

VV

VnVV

PPRMS

Error Estimation

• ADC– 15µV offset– INL: 6 ppm– gain error: 0.02%– Noise error: 7.78 µVpp– External Reference: 1.024 mV

• Shunt resistor tolerance: 20mA*221*.1% =4.42 mV

• Level shifting OPA333– Offset: 10 µV– Offset drift: 0.05 µV/oc– CMRR >106 dB– PSRR: 5 µV/V (min)

• 2.5v Reference OPA333– Offset: 10 µV– Offset drift: 0.05 µV/oc (3µV over 25oC ± 60oC temperature range)– CMRR >130 dB– PSRR: 2 µV/V

• REF5025: 1.25mV

• Total

Vv 244*10

66

Vv 8004*0002.0

20,,, 10

CMRR

dcmincmincmcmo AVVAV

PSRRAVV dPSnoiseoffset PS o,

mVmVmVVV 669.4)2.4()25.1()10(2)839( 2222

2PSnoise

220,

22222 )(2)10(2))25)(05.0((2)2.4()25.1()10(2)839( PSRRAVAVCTmVmVVV d

CMRR

dcmino

C

Vo

Temperature Sensors

Thermistor

RTD

Thermocouple

Targeted industrial temperature range: -40oc to 85oc

Thermistor

• Temperature proportional to resistance

• Calibrated: 25oC and 85oC

• NTC thermistor– 30kΩ ±1% @ 25oC

• 2 Designs: – Single-ended – Bridged

)1

15.3981

(3992exp(

30

%1399285/25

Tk

kR

Simulation

Error Estimation

• Resistor Mismatch: 374.81µV

• Current Accuracy:0v– Ratio metric measurement

• Thermistor Errors: 5.027 mV– Thermistor 25oC R-tolerance: 3.731mV (R±1%)

– Beta Error: 3.37 mV (Beta±1%)

• ADC Errors: – 15µV offset

– INL: 6 ppm

– gain error: 0.02%

– External reference R: 2mV

• Minimum 4.4 mV/oC

• Total Error: 5.425mV (~1.23oC)

V

kkk

kkkA

81.374

)15001.*3060

)001.*3030)(30()(50(Error mismatch R

Vv 122*10

66

Vv 4002*0002.0

mV

kkk

kkkA

731.3

)20001.*4080

)001.*4040)(40()(50(Error -R thermistor

Output Voltage Temperature Dependence

0

100

200

300

400

500

600

700

800

0 20 40 60 80 100

temp (degrees C)

Ou

tpu

t V

olt

age

(mV

)

B nominal

B + 1%

B - 1%

Simulation

Error Estimation

• Resistor Mismatch: 1.677mV (0.1% resistors)

• Current Accuracy: 0v– Ratio metric reading (external ref)– Mismatch between current sources:

• ±0.15% of FS (50 µV) = 75nV (negligible)

• Thermistor Errors: 5.027 mV– Thermistor 25oC R-tolerance: 3.731mV (R±1%)– Beta Error: 3.37 mV (Beta±1%)

• ADC Errors: 400.5µV– 15µV offset– INL: 6 ppm– gain error: 0.02%

• Minimum 4.4 mV/oC

• Total Error: 5.311mV

mVVmV

VkAmVkA

677.1)750()5.1(Error

750)001.*15)(50(:Right 5.1)001.*30)(50(

22mismatch R

Vv 122*10

66

Vv 4002*0002.0

RTD

• PT100, PT 1000

• Resistance proportional to temperature

• Callendar-Van Dusen equation

Simulation

Error Estimation

• Class A RTD probe: ±0.15oC @ 0oC

• ADC Errors: 400.5µV– 15µV offset– INL: 6 ppm– gain error: 0.02%– External reference tolerance:

• Total Error: 2.040 mV

Vv 122*10

66

Vv 4002*0002.0

case)(worst 2

)001.*20)(100(

mV

kAErrorREFERENCE

Thermocouple

• Seebeck effect

• Need to measure voltage across the element

• Cold junction compensation: RTD close to the cold junction

• PCB layout designed to keep the cold junction isothermal with the RTD

• Types: K, J, T, E, N, R, S, B

• Different materials, temperature ranges, TC

• Example: K type: ~55µV/oC

Error Estimation

• RTD Error: 2.040 mV

• Thermocouple element error: Varies by type

• Max element error (using K type): 1.1oC or 0.4%

Digital Interface

SM-USB-DIG

Stage 2 Interface

• Add MCU

• Excluded from stage 1 (Rev. A)

• MCU controls data converters

• MCU communicates through SM-USB-DIG to computer

• Adds extra capabilities

Power

• Powered by a lab supply for prototyping

• Banana plug input jack

Floor plan

Front-Ends

Control and Power

The Plan

• May 16: First Day

• May 21: Project Definition & training (1 week)

• June 5 - June 10: FAE conference in Tucson (1 week)

• July 5: Block Diagrams, calculations (accuracy), simulations, Part selection & ordering, initial schematic (4 weeks)

• July 14: PCB layout (2 weeks)

• July 21: Basic LabView Coding & Testing preparation (1 week)

• July 29: Initial lab results -Oven(~1 weeks)

• August 3: Accuracy tests (Tucson?)

• August 5: Final Report (2 days)

• August 10: Preliminary Presentation (2 days)

• August 12: Final Presentation (2 days)

• August 18: Last Day (1 week)