PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-1

P L L E X E R C I S E No.1 FM demodulator Analysis

Vodem odoutput

FMINPUT

0,22 µF

620

620

12 nF

1,2K

-9V

+9V

+9V

1 nF

7,5K

5K

4,3K

82K

82K4,3K

390 pF

390

pF

47 pF

47 pF

+9V

-9V

Fcen = 30 k Hz

C O MP

C O MP

LM301

LM301

LM301

10 pF

C OMP

-Vc c

PC in1

PC in2

VCOo

PC in

RE F

Vc RT

CT

NC

NC

NC

NC

+Vc c

L

M56

5

A) Draw a block diagram of the overall FM demodulator and derive its TF )()( SinSoV ω∆∆ B) Determine Kd, Kv, Fn1, ζ1 and Fn2 of the PLL demodulator and then sketch its gain response - label with

relevant parameters. Explain why the demodulator has a Butterworth response. C) If Fcar = 30 kHz, ∆F = 2 kHz and Fmod = 500 Hz, sinewave modulation, what is the minimum, maximum and

average phase error and the demodulated voltage? Use pages 10 or 11 of theory notes to read peak phase error.

D) Repeat for Fmod = 5 kHz. E) Derive the general TF for )()( SinSe ω∆∆Φ and then calculate the exact values of the phase error for

steps C and D. F) For what modulation frequency is the phase error maximum? G) Explain the function of the last stage. H) What is amplitude of the demodulated O/P signal, the HF ripple at the final output and the % ripple if the FM input has Fmod = 500 Hz, ∆F = 2 kHz at Fcar = 30 kHz. I) Simulate the demodulator gain response and the phase error response to an FM input with sinewave

modulation. J) Simulate for determination of lock range and capture range. K) Simulate for determination of output HF ripple.

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-2

No.2 FM demodulator Design

Design a 3rd order FM demodulator that has a low-pass Bessel response, given the following input signal. FM input: Fcar = 100 kHz ∆F = 0 to 10 kHz Modulation: sinewave, Fmod = 0 to 3 kHz Final output: 0 to 5Vp Select Fn of PLL for a reasonable phase error and large enough to pass the demod signal. N0.3 FSK demodulator Design

Design a 4th order FSK demodulator that has a Bessel low-pass response with a bandwidth of 15 kHz. The two input frequencies are 100 kHz and 110 kHz. What is the maximum bit rate that can be demodulated?

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-3

No.4 PLL Frequency Synthesiser Analysis

M

PHASE DETECTOR

VCO

650

M = 110 to 220

LOOP FILTER

LOW-PASS FILTER

Fo

130 MHz OSCILLATOR

A) Determine the two possible sets of output frequencies. B) How do we ensure operation of the synthesiser on one set of frequencies only? C) Why is there spurious FM sidetones in the spectrum of the output signal? Is this good or bad? How can they be minimized? D) Are ζ and ωn constant in this system? Explain. No.5 RF PLL Synthesizer Design and Analysis Re-do the example on pages 33 to 40 with the following data: Using the same frequencies, re-design for a phase margin of 55o, an ωp value of 2π*10 kHz and additional spurious sideband attenuation of 20 dB from the R3C3 section added to the loop filter. Modify the SystemView file given for the theory example to simulate your new design.

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-4

SOLUTIONS

No.1A)

( )

( )

( )

( ) ( )

( )

( ) ( )

+

××

+

+

+

++

+=∆∆

+

××

+

+

+

++

+=

×

+++××+

+

××++

×=

−=

Φ

×++

+×−−

+

××++

×

=−

=Φ

FFE

F

VdVd

d

in

So

FFE

F

VdVd

d

S

So

Vd

FFE

Fd

SSin

So

Vd

FFE

Fd

SSin

So

RSCRR

RRCKK

RRCCRKKSS

RRCK

SV

RSCRR

RRCKK

RRCCRKKSS

RRCKS

S

V

SRRSCRSCKK

RSCRR

RRSCK

LNTV

SK

SCRR

SCR

K

RSCRR

SCRR

SCK

LNTV

in

11

1)((

11

1(

11

11

11

11

1(

1

1

1

11

1

1

1(

212212

222

212)

212212

222

212)(

)

212

22

212

)(

11

)(

)

221

22

221

2

)(

11

)(

)

ω

ω

B) Kd = 0.68 V/r if Vin > 100 mVpp , that is if LM565 phase detector O/P is saturated - see data sheets.

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-5

Kv = 49.4 Fcen/∆Vcc = 49.4*30K/18 = 82333 r/s or 13.1 kHz/V.

( ) HzkknRRC

KKF dvn 4962

)2.16.3(*1268.0*82333

21

21

2121 =

+=

+=

ππ ( ) 5029.0

21

2121

221 =

++

=RRCRKCK

n

d

ωζ

( ) HzCRF Fn 49772 12 == −π

Fn1 and Fn2 are almost equal and ζ1 ≈ 0.5 which corresponds to a third order Butterworth response whose

normalised poles are oo SandS 120/1180/1 3,21 ±== . µω

6.2311)(

( )=×=

∆∆

E

F

Vin

So

RR

KSV

C) ∆F = 2 kHz, Fmod = 500 Hz, Fcar = 30 kHz

( )( ) 10076.049625008.12.16.31249622)(

1

mod211 ===+××=+

nn F

Fandkknπττω

For all phase error graphs, the LF frequency value of ( ) 8.11

)(1

2111

=+

≈∆

∆Φττω nnin

e

FF , therefore we have

( )p

nine rFFpeak 224.0

8.149622000

8.1)( 1 ==

∆≈∆Φ Average phase error is π/2 if Fcen = Fcar for LM565

P H A S E E R R O R (r)

Time (ms)

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-6

D) ∆F = 2 kHz, Fmod = 5 kHz, Fcar = 30 kHz

( )( ) 0077.1496250008.12.16.31249622)(

1

mod211 ===+××=+

nn F

Fandkknπττω

At =1

mod

nFF

1, we read on the phase error graphs (pp 10-11)

( ) 1)(5.1)(

2111

=+≈∆

∆Φ ττω nnin

e forFFpeak

( ) 5)(0.1)(

2111

=+≈∆

∆Φ ττω nnin

e forFFpeak

Using linear interpolation, we have

( )p

nine rFFpeak 288.0

4.149622000

4.1)( 1 ==∆≈∆Φ

Average phase error is π/2 if Fcen = Fcar for LM565

P H A S E E R R O R (r)

TIME (S)

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-7

E)

( )

( )( )( )

( ) ( )

( )

( ) ( )

+

+

+

++

+

+=

∆∆Φ

+

+

+

++

+++

=Φ

×

+++××+

=

×++

+×−−

×=−

=ΦΦ

212212

222

212)(

212212

222

212

212

)(

)(

212

22

221

22

)(

11

)(

)(

1

1

)(1

1

11

11

1

1

1

1

111

RRCKK

RRCCRKKSS

RRCS

SRRC

KKRRCCRKKSS

RRCRRSCS

S

SRRSCRSCKK

SK

SCRR

SCR

K

LNT

VdVdin

Se

VdVdS

Se

VdV

d

SSin

Se

in ωω

( )

( ) ( )

( )

( ) ( ) ( )

+

+++

+

+

+×∆=∆Φ

+

+

+

++

+

+×∆=∆Φ

212

22

212

2

212)(

212212

222

212)(

1

1

)(

1

1

)(

RRCCRKKj

RRCKKj

RRCj

jj

RRCKK

RRCCRKKSS

RRCS

S

Vdm

Vdm

m

minme

VdVdinSe

ωω

ωωωω

ω

( )

( ) ( )( )( )

( )( )8.313571097217361)()(

8.313571097217361)(

26

62)(

mm

mine

mm

mminme

jjpeakpeak

jjjjj

ωωωω

ωωωωωω

+−×+×∆=∆Φ

+×++×∆=∆Φ

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-8

For Fm = 500 Hz we have ( )( )( )( ) rr

jjpeake 179.0/2258,0

8.31357100010001097217361100020002)( 26

=×+−×

+××=∆Φππ

ππ

Compared to 0.224 rp found in step C. The phase angle of the phase error signal is the phase shift between the modulation signal and the phase error signal. For Fm = 5 kHz we have

( )( )( )( ) rr

jjpeake 066.1/2302,0

8.31357100001000010972173611000020002)( 26

=×+−×

+××=∆Φππ

ππ

Compared to 0.288 rp found in step D – I guess the graph was not that accurate. F) For )( 211 ττω +n values of 5 and over the maximum phase error occurs at Fm = Fn1 = 4962 Hz.

But for )( 211 ττω +n = 1 the peak has shifted to about 0,8 Fn1, so my estimate is that for )( 211 ττω +n = 1.8 the maximum phase error will occur at approximately 0.9 Fn1 = 4466 Hz G) All yours to answer. H) Ripple calculation (see chart page 19 of theory section) From phase detector O/P to final O/P, we have

R 1 R 2

C 2

R E

RF CF

R E

RF

CF

Vd

Vo

HF r ipple

ACg ro und

( )

( ) ( ) PPrip

oo

EFE

FF

Sd

So

mVKF

AAppVppV

SA

SA

RSCRRSCRSC

R

SCRR

SCVV

1.194608448001012103904300

116.284

)()(

111

1

1

2912221

21

212

221

2

)(

)(

=××××××××

×=××

×∆=∆

×=×+

≈×++

=

−−

O/P signal level pE

F

V

ino V

kk

RR

KpeakV 91.2

3.482

8233320002)( =××=×∆= πω

% ripple = 194.1m / (2.91*2) *100 = 3.33%

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-9

I) PHASE ERROR SIGNAL FOR Fm = 500 Hz, ∆∆∆∆F = 2 kHz

0 1 2 3 4 5 6

0

-0.5

-1

-1.5

-2

Tim e (m s)

0.425 r(pp )-1 .57r (ave)

I/P is captu red

Pha

seer

ror

(r)

From the previous page, we obtained the following theoretical values: Vo = 5.82 Vpp and ripple of 191.4 mVpp The ripple component is off because the duty cycle was assumed to be 50% at an average frequency of Frip = 2Fcar at the phase detector O/P. At Fmin and Fmax of the FM signal, the duty cycle is above and below 50% and Frip = 2Fmin and 2Fmax respectively. Read ripple at top and bottom of demod O/P and average the two values which should come close to the predicted value for 50% duty cycle.

PLL EXERCISE

Rev. 10/18/2002 Phase-Locked Loops Page CC-10

0 20 40 60 80e 100 120 140 160 180

300e+3

250e+3

200e+3

150e+3

Time (ms)

FREQ

UEN

CY

(r/s

)

I/P FREQUENCY

O/P FREQUENCY

UNLOCKS ATabout 274.3k r/s

The above simulation was done starting at Fin = 30 kHz and then ramping up Fin at a rate of 100 kHz/sec. If the ramp rate is too fast then the lock rage will be less – lock range is defined for a slow variation of Fin. You can find Fmin by starting at 30 kHz again but now ramping down Fin at –100 kHz/sec (Try it!) CAPTURE RANGE SIMULATION

( ) ( )HzkF

KKF

CAP

ndonCAP

73.11

4962268,082333496225,022

222

2 22

±=∆

×−××××××±=−×±≈∆ πππ

ωζωπ

Nos.2, 3 and 5 you are on your own – see theory examples for help. N0.4 A) Fo = 86 MHz to 108 MHz or Fo = 152 MHz to 174 MHz with steps of∆Fo = 200 kHz B, C and D are yours.

From the S/V simulation, the lock range is:

kHzkkFFFFFF

kHzF

kHzkF

L

cencenL

cen

66.1330656.43

30

656.432

3.274

minmax

max

=−=∆−=−=∆

=

==π

Theoretically we have:

kHzkF

VFF

LOCK

CC

cenLOCK

33.1318308

8

=×±=∆

∆×±≈∆

NOTE: The simulation shown beside is not to scale – run sim file for a better look at results.

From the S/V simulation, the capture range is:

kHzkkFFFFFF

kHzF

kHzkF

L

cencenL

cen

63.937.2030

30

37.202

128

maxmin

min

=−=∆−=−=∆

=

==π

Theoretically we have: