pll simulation

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    PLL Simulation on NI AWR to Understand the Impact of Various Parameters

    Schematic: Basic Type I PLL Topology

    Input Reference: Freq_in = 1!" Ph_in = #$utput: Freq_out = 1!" %&$ 'ain = #()!"*%Filter: &ut $+ Freq = #()!"

    ,fter aroun- .u sec output frequency is getting /loc0e- an- stea-y state error is appro( #(2ote: $utput is 3#-eg out of phase 4ith respect to input -ue the 0in- of phase -etector use- i(e(a multiplier 4hich lea-s to qua-rature shift(

    Lets no4 loo0 at the e+ect of changing a fe4 parameters:

    a) Filter Cut O Fre!uenc"

    i5 Increasing fc = #(6!"It reaches stea-y state faster i(e( system respon-s faster /ut the price 4e pay for faster loc0time is oscillations in error 4hich translate to phase noise( Phase noise means that the outputtune isn7t pure(

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    ii5 Re-ucing fc = #(8!" Transients too0 longer to settle /ut there 4ill /e no oscillations i(e( lo4er phase noise(

    #) Reference Fre!uenc" Phase

    i5 Increasing Ph_in = #()

    It loc0s 9ne means PLL is 4or0ing 9ne;

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    ii5  %&$ = #(.!"*% Transients may ta0e a little /it longer an- there 4ill /e more oscillations i(e( more phase noise( Itstarts to get more unsta/le(

    Really large > %&$ = ?!"*%$utput -oesn7t e@en settle an- is not e@en sinusoi-(

    ii5  %&$ = #(?!"*%

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    $utput settles smoothly(

    d) Input Reference Fre!uenc"

    i5 Increasing Freq_in = 1(#)!"$utput is /eing loc0e- /ut is no longer lea-ing the input /y 3#-eg( Ae also ha@e a non"eroerror signal

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    ii5  %&$ = 1!"*%$utput is /eing loc0e- /ut is no longer lea-ing the input /y 3#-eg( Ae also ha@e a non"eroerror signal

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    2ote that if 4e 0eep on increasing %&$ gainD the system 4ill 9nally get unsta/le -ue to poorphase margin an- output 4on7t loc0(

    i@5 Increasing Freq_in = 1(1!"  %&$ = #(1!"*%$utput 4on7t settle i(e( it 4on7t loc0 as there is not suGcient gain from %&$ lea-ing toinsuGcient  %&$(

    @5 Increasing Freq_in = 1(1!"  %&$ = 1!"*%Issue here is that frequency is loc0e- /ut out of phase -ue to phase error

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