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  • Phase-Locked Loops: A Control Centric Tutorial

    Daniel AbramovitchAgilent Laboratories

    Communications and Optics Research Lab3500 Deer Creek Road, M/S: 25U-9

    Palo Alto, CA 94304

    Phone: (650) 485-3806

    FAX: (650) 485-4080

    E-mail: [email protected]

    June 24, 2003

    AbstractThis paper will present a tutorial on

    phase-locked loops from a control sys-tems perspective. It will start with anintroduction of the loop as a feedbackcontrol problem, with both the similari-ties and dierences to traditional controlproblems. Chief among the dierences isthe necessary inclusion of two nonlineari-ties in the loop that are not parasitic, butessential to the loops operation. Analysismethods, both linear and nonlinear willbe discussed. Then digital loops will bediscussed, followed by loop componentsand a cursory look at noise. Finally, thepaper will end with a discussion of dier-ent applications of PLLs and their rela-tives.

    A subset of this appears in the Proceedings of the 2002 ACC.

    1 Introduction

    LoopFilter

    PhaseDetector

    VoltageControlledOscillatorSignal

    Phase-Lockedto Reference

    SignalReference

    Figure 1: A general PLL block diagram.

    Phase-locked loops (PLLs) have been around for manyyears[1, 2]. Gardners short history links the earliest

    widespread use of PLLs to the horizontal and verticalsweeps used in television, where a continuous clocking sig-nal had to be synchronized with a periodic synch pulse [3].In many respects, the eld is mature, with widespreadapplication to almost every type of communication andstorage device and a large number of books on the sub-ject [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13]. By the same token,PLLs and their relatives are included in so many bleed-ing edge applications that their designs are anything butstagnant.

    An incomplete list of specic tasks accomplished byPLLs include carrier recovery, clock recovery, trackinglters, frequency and phase demodulation, phase mod-ulation, frequency synthesis, and clock synchronization.PLLs nd themselves into a huge set of applications, fromradio and television, to virtually every type of communi-cations (wireless, telecom, datacom), to virtually all typesof storage device, to noise cancellers, and the like. Withthe widespread use by the public of such devices, one canclaim that PLLs are the most ubiquitous form feedbacksystem built by engineers.

    The most basic block diagram of a PLL is shown inFigure 1. This diagram shows the components that everyPLL must have, namely:

    A phase detector (PD). This is a nonlinear devicewhose output contains the phase dierence betweenthe two oscillating input signals.

    A voltage controlled oscillator (VCO). This is an-other nonlinear device which produces an oscillationwhose frequency is controlled by a lower frequencyinput voltage.

    A loop lter (LF). While this can be omitted, result-ing in what is known as a rst order PLL, it is alwaysconceptually there since PLLs depend on some sortof low pass ltering in order to function properly.

  • A feedback interconnection. Namely the phase de-tector takes as its input the reference signal and theoutput of the VCO. The output of the phase detec-tor, the phase error, is used as the control voltagefor the VCO. The phase error may or may not beltered.

    PLLs have several unique characteristics when viewedfrom a control systems perspective. First of all, their cor-rect operation depends on the fact that they are nonlin-ear. The loop does not exist without the presence of twononlinear devices, namely the phase-detector and VCO.These devices translate the problem from signal responseto phase response and back again. Accompanying thisis a time scale shift, as PLLs typically operate on sig-nals whose center frequency is much higher than the loopbandwidth. Secondly, PLLs are almost always low order.Not counting various high frequency lters and parasiticpoles, most PLLs in the literature are rst or second or-der. There are a few applications where third or fourthorder loops are used, but these are considered fairly riskyand sophisticated devices. Finally, with the exception ofPLL controlled motors, the PLL designer is responsiblefor designing/specifying all the components of the feed-back loop. Thus, complete feedback loop design replacescontrol law design, and the designers job is governed onlyby the required characteristics of the input reference sig-nal, the required output signal, and technology limita-tions of the circuits themselves. In the case of PLL con-trol of motors, the motor and optical coupler takes theplace of the VCO, leaving all other parts of the PLL tothe designers discretion.

    With that, one would expect that the study of PLLswould be strongly steeped in control theory and that con-trol theorists would have the highest expertise in PLLs.In fact, the control theory used in most PLL texts isstraight linear system design with a small amount of non-linear heuristics thrown in [3, 4, 5, 6, 8, 9]. The sta-bility analysis and design of the loops tends to be doneby a combination of linear analysis, rule of thumb, andsimulation[1, 2, 3, 4, 5]. The experts in PLLs tend to beelectrical engineers with hardware design backgrounds.The general theory of PLLs and ideas on how to makethem even more useful seems to cross into the controlsliterature only rarely [14, 15, 16, 17].

    This tutorial will take a control engineers view ofPLLs. The idea is to map out what is in the commonliterature on the devices against the background of con-trol design to see how the problem breaks down and whattools of modern control theory can be applied to these de-vices.

    1.1 PLL Basics

    The basic idea of a phase-locked loop is that if one injectsa sinusoidal signal into the reference input, the internal

    LoopFilter

    VoltageControlledOscillator

    VCOControlVoltage

    SignalPhase-Lockedto Reference

    SignalReference

    Asin( t + ) i i

    cos( t

    + )

    Figure 2: A classic mixing phase-locked loop.

    LoopFilter

    HighFrequency

    LP Filter

    BandpassFilter

    VoltageControlledOscillatorSignal

    Phase-Lockedto Reference

    SignalReference

    Figure 3: A practical version of the classic mixingphase-locked loop: note the addition of a bandpasslter preceding the loop to limit input noise and a highfrequency low pass lter within the loop to attenuatethe 2X frequency component with minimal impact onthe loop dynamics.

    oscillator in the loop will lock to the reference sinusoidin such a way that the frequency and phase dierencesbetween the reference sinusoid and the internal sinusoidwill be driven to some constant value or 0 (depending onthe system type). The internal sinusoid then representsa ltered or smoothed version of the reference sinusoid.For digital signals, Walsh functions replace sinusoids.

    Typical block diagrams of PLLs in the literature resem-ble Figure 2, however practical loops often more closelyresemble Figure 3, in which a high frequency low passlter is used to attenuate the double frequency term anda bandpass lter is used to limit the bandwidth of input

    -

    s

    Ko

    VCO

    i

    x

    F(s)K sin( )dd

    Figure 4: Conceptual block diagram of PLL with sinedetector. This is a transition stage in the analysis of theclassical mixing loop. This model represents the eectof the multiplying detector once the high frequencycomponent has been attenuated.

    2

  • F(s)

    -

    s

    Ko

    VCO

    i

    x

    Kdd

    Figure 5: Conceptual block diagram of linear PLL. Thisis derived from the sine detector loop by assuming thatthe phase error is small and thus sin(d) d. This isthe model with which most analyses of phase-lockedloops are done.

    signals to the loop. A general sinusoidal signal at the ref-erence input of a PLL as shown in Figure 3 can be writtenas:

    vi = R1(t) = A sin(it + i). (1)

    Without loss of generality, we can assume that the outputsignal from the Voltage Controlled Oscillator (VCO) intothe mixer is given by

    vo = V COout(t) = cos(ot + o). (2)

    The output of the mixer in Figure 3 is then given by

    vd = Mixerout(t) = AKm sin(it+i) cos(ot+o), (3)

    where Km is the gain of the mixer.Typically, analysis of such a PLL is done by taking sev-

    eral simplifying steps. Using the familiar trigonometricidentity in terms of the PLL:

    2 sin(it + i) cos(ot + o) = (4)sin((i + o)t + i + o) + sin((i o)t + i o)

    and then making two fundamental assumptions leads tothe commonly used model of the analog PLL. Let d =i o. Then these assumptions are:

    1. The rst term in (4) is attenuated by the high fre-quency low pass lter in Figure 3 and by the lowpass nature of the PLL itself.

    2. i o, so that the dierence can be incorporatedinto d. This means that the VCO can be modeledas an integrator.

    Making these assumptions leads to the PLL model shownin Figure 4.

    The problem is that this is still a nonlinear system,and as such is in general dicult to analyze. The typicalmethods of analysis include:

    1) Linearization: For d small and slowly varying

    sin d d, cos d 1, and d2 0.While this is useful for studying loops that arenear lock, it does not help for analyzing theloop when d is large.

    2) Phase plane portraits [3, 5]. This method isa classical graphical method of analyzing thebehavior of low order nonlinear systems abouta singular point. The disadvantage to this isthat phase plane portraits can only completelydescribe rst and second order systems.

    3) Simulation. Note that explicit simulation of theentire PLL is relatively rare. Because the prob-lem is sti, it is more typical to simulate the re-sponse of the components (phase detector, l-ter, VCO) in signal space and then simulate theentire loop only in phase space.

    The linearized model is shown in Figure 5. This is whatis used for most analysis and measurements of PLLs. Aswill be seen in Section 6, changing the phase detectorand VCO can result in a system for which this model isvery accurate. It is possible to learn quite a bit about thephase behavior of the PLL from linear analysis. However,this model has some very important omissions that comeinto play when simulating or constructing the classicalPLL:

    1) The texts typically omit the input bandpass l-ter shown in Figure 3. While this is not inthe loop itself and the actual input frequencyis often not known or is variable, it is most of-ten the case that the designer has some ideaof the range of the signal. In this case, an in-put bandpass lter can considerably reduce thebroadband noise entering the system.

    2) The texts typically omit the high frequency lowpass lter shown in Figure 3. This is importantbecause this lter is highly useful in attenuat-ing the eects of the 2ot signal. The loop lteritself is optimized for the stability and perfor-mance of the baseband (phase). The prevalenceof the linear phase model often leads design-ers and simulation tool builders to forget thisimportant component. However, experiencedPLL circuit designers include this feature.

    3) As seen in (3), the amplitude of the phase er-ror is dependent upon A, the input signal am-plitude. The linearized model has a loop gainthat is dependent upon the loop components.Thus, in practical loop design, the input ampli-tude must either be regulated or its aects onthe loop must be anticipated.

    4) The equations of a PLL are sti. That is, theloop has a component at baseband and one at2ot. Simulations that sample fast enough tocharacterize the latter are often far too slow(due to the huge number of sample points) toeectively characterize the former.

    3

  • 2 Linear Analysis Methods forClassical PLLs

    The PLL model in Figure 5 is a closed-loop feedbacksystem. The complimentary sensitivity transfer functionfrom reference phase input to VCO phase output, T (s),can be obtained as

    T (s) =o(s)i(s)

    =KdF (s)Kv/s

    1 + KdF (s)Kv/s(5)

    =KdKvF (s)

    s + KdKvF (s). (6)

    Similarly, the sensitivity transfer function from the refer-ence phase input to the phase error, S(s), is

    S(s) =d(s)i(s)

    =1

    1 + KdF (s)Kv/s(7)

    =s

    s + KdKvF (s). (8)

    Among the basic properties of interest in this transferfunction are the loop stability, order, and the system type.

    The order of the PLL system should be obvious fromthe denominator of Equation 6. The stability of the sys-tem can be determined by a variety of classical meth-ods including root locus, Bode plots, Nyquist plots, andNichols charts [18].

    2.1 The Hold Range

    The hold range, H , is dened as that frequency rangeat which the PLL is able to statically maintain phasetracking. It is determined by calculating the frequencyoset at the reference input that causes the phase errorto be beyond the range of linear analysis. For a multi-plying or XOR phase detector, this phase error is /2.For sequential detectors, it will be larger. Best statesthat since loops will be permanently out of lock if the fre-quency oset at the input is greater than the hold range,this quantity is more of an academic matter than a prac-tical one, but it can be calculated for a classical PLL(sinusoidal phase detector) as [8, 19]

    H = KoKdF (0). (9)

    2.2 The Lock Range

    The lock range, L, is dened as that frequency rangewithin which the PLL locks within one single-beat notebetween the reference frequency and output frequency [8].The lock range must be calculated from a nonlinear equa-tion, but there are several useful approximations that aremade. In particular, if the relative order of numeratorand denominator of the PLL are 1, then the loop can be

    said to behave like a rst order loop at higher frequencies,and thus the lock range can be estimated as [19]

    L KoKdF (). (10)

    2.3 The Pull-In and Pull-Out Range

    The pull-in range, P , is dened as the frequency rangein which the PLL will always become locked. The pull-outrange, PO, is dened as the limit of dynamic stabil-ity for the PLL [8]. Unfortunately, there are no simplerelationships for these.

    2.4 The Steady-State Error

    Steady state errors of PLLs are obtained from the linearanalysis via use of the Final Value Theorem, i.e.

    limt d(t) = lims0

    sd(s) (11)

    = lims0

    si(s)S(s). (12)

    As seen from Equation 7, the presence of a VCO makesevery PLL at least a Type 1 system, achieving zero steadystate error to a phase step at i. For a phase ramp or(equivalently) a frequency step, there must be anotherintegrator in the forward path, and the natural place forthis is the loop lter, F (s).

    It is worth noting that third order PLLs, which can beType 3 systems and have zero steady state error to a fre-quency ramp, are relatively rare. There are two apparentreasons for this. First of all, the applications that requirethat type of performance are typically only found in deepspace communications, where the Doppler shift of the sig-nal produces a frequency ramp. The second potential rea-son has to do with the stability of the third order loopversus that of the second order loop. It turns out thatthe parameter values that make the linear model of sec-ond and rst order PLLs stable also guarantee stability ofthe nonlinear PLL model shown in Figure 4. However, forthird order loops and higher, this is not the case [20, 21].

    3 Nonlinear Analysis Methods forClassical PLLs

    3.1 Phase Plane

    One of the earliest methods of nonlinear system analy-sis is the graphical method of phase plane design. Thishas been used in the early days of PLLs [5], before thewidespread use of computers for such calculations. Theuse of phase plane portraits for PLLs is made more prac-tical by the fact that most PLLs are rst or second order,which doesnt clash with the order restrictions on phaseplane techniques.

    4

  • 3.2 Lyapunov Redesign

    Starting with the the sinusoidal phase detector modelshown in Figure 4, it has been possible to apply thetechnique of Lyapunov Redesign [22] to phase-lockedloops [20, 21]. More recently, this method has been ex-tended to classical digital PLLs [23].

    3.3 Circle/Popov Criteria

    The diculty of applying Lyapunov methods to higherorder loops has led to the exploration of nonlinear analysismethods suitable for numerical techniques. In particular,the Circle Criterion [14] and the Popov Criterion [24] havebeen used to check the stability of higher order PLLs.

    4 Digital Signals

    Generally speaking, there are a variety of reasons to usedigital circuitry to implement PLLs rather than the clas-sical methods above. In this case analog voltage levels areoften replaced by digital logic levels. For example, clocksignals to drive digital circuitry, computers, and digitalcommunications systems all run better with Walsh func-tions (rectangular waves) rather than sinusoids. Further-more, these digital circuits are easier to integrate and ver-ify than their analog counterparts. Finally, as the speedof the logic outstrips the speed requirements of the appli-cations, such implementations become far more reliablethan the classical methods.

    PLLs that deal with digital signals have one or moreof their components replaced by digital circuitry. Thisresults in analysis that is considerably dierent from whatwe have seen up to now. However, once one converts themindset to that of digital signals, the analysis is oftenlinear.

    5 Digital PLLs

    The denition of most digital feedback loops is fairlystraightforward. Digital loops sample the input, convert-ing it to a digital quantity using an ADC, perform thecontrol law calculation using some type of computer, andoutput the resulting control signal through a DAC. How-ever, the denition of a digital PLL depends quite a bitupon which text one reads. Digital PLLs may consist en-tirely of analog components with the exception of usingone of the digital phase detectors described in Section 6.In other cases, the loop consists of a digital phase detec-tor, a digital lter, and a numerically controlled oscillator.Bests book distinguishes these as the Classical DigitalPLL and the All Digital PLL, respectively [8]. Finally,an all software PLL is possible on reference signals that

    are entirely digitized. The loop components themselvesare implemented entirely in computer code.

    5.1 Classical Digital PLLs

    LoopFilter

    DigitalPhase

    Detector

    VoltageControlledOscillator

    SignalPhase-Lockedto Reference

    SignalReference

    Figure 6: A classical digital phase locked loop.

    The classical digital PLL (CDPLL) shown in Figure 6is somewhat of a misnomer from the controls perspective.It is not a digital, sampled data system as the term dig-ital would imply to control theorists. Instead, it is ananalog PLL implemented with a digital phase detector,such as one of those in Section 6. In this case, the out-put of the digital phase detector is seen as a continuoustime voltage and this voltage is fed to an analog loop l-ter. PLL authors point out that this type of PLL hasall the disadvantages of the classical PLL due to its ana-log components. Still, this loop has advantages in thatit can be implemented at very high frequencies (multipleGigahertz) with fairly reliable logic. Furthermore, theseloops can be analyzed using continuous time linear feed-back theory. It is for this reason that some authors donot treat these loops as digital at all [6].

    5.2 All Digital PLLs

    Counter

    Up

    Down

    DigitalPhase

    Detector

    DigitallyControlledOscillator

    SignalPhase-Lockedto Reference

    SignalReference

    Figure 7: An all digital phase locked loop. The digitalphase detector produces pulses that go into the countup or count down inputs of the counter, which acts asthe loop lter. The counter then adjusts the frequencyof the digitally controlled oscillator (DCO).

    The rst dierence between the all digital PLL (AD-PLL) [8] and the classical digital PLL of Section 5.1 is inthe use of the digital phase detector (DPD). In the lat-ter case, the DPD was used to generate analog voltagesin continuous time. In the ADPLL, the DPDs outputis considered a digital quantity, either pulses or multi-bitvalues. The ADPLL [8] replaces the analog lter withsome sort of a digital lter and the VCO with a digitally

    5

  • DigitalLoopFilter

    DigitalPhase

    Detector

    DigitallyControlledOscillator

    n-bit PhaseError

    SignalPhase-Lockedto Reference

    SignalReference

    Figure 8: Another all digital phase locked loop. Thedigital phase detector produces samples of phase errorin an n-bit value. This value is fed to a digital lterwhose output adjusts the the frequency of the digitallycontrolled oscillator (DCO).

    controlled oscillator (DCO).The DPD and the loop lter are chosen together at

    this point. For a DPD that produces pulse streams on itsoutputs that correspond to either high or low phase error,the lter used is some type of counter. Note that while thepulse streams are essentially continuous time in nature,the counter relies on an input clock. This clock makes theDPD/counter combination a sample data system. This isshown in Figure 7.

    For a DPD that produces a sampled stream of multi-bitvalued numbers, a digital lter in the classical sense canbe used [25]. This case, shown in Figure 8, correspondsmost closely to what the controls world considers a digitalfeedback loop.

    5.3 Software PLLs

    Edge (Phase) AdjustmentEdge (Phase) Adjustment

    Window (Freq.) AdjustmentWindow (Freq.) Adjustment

    Int0

    z -1

    z -1

    z -1

    z -1

    Int0

    error

    edge

    win

    Figure 9: An example of a software PLL that doesclock/data recovery. This heuristic loop uses a zerocrossing detector on the sampled input. The eectivesample rate is derived from the average bit zero cross-ing rate.

    When data can be sampled at a rate substantially fasterthan the loop center frequency, the entire loop operationcan be implemented in software. This has the advantageof exibility. Any type of PLL can be implemented in

    software provided the sample rate is high enough. Soft-ware loops have a lot in common with simulation. Onekey dierence is that the software loops deal with realdata. Software PLLs may operate on the data in realtime, but can also be used in the post processing of mea-sured data. One cautionary note is that certain opera-tions which are highly eective in hardware, such as lim-iters which have a lot of high frequency content, createreal sampling issues for software loops.

    6 Phase Detectors

    The analysis methods of Section 2 above were appliedto the classic mixing loop. This has the property thatonce an ideal multiplication is done, the analysis of thebaseband signal can be more rigorous. This section willexplore phase detectors constructed from digital logic forwhich the initial reduction to baseband relies on argu-ments of pulse-width modulation and averaging [3, 6, 8].While these phase detectors have worse noise performancethan the classic mixing detectors, they often have bet-ter pull in range and are much more manufacturable, es-pecially for high speed applications. Furthermore, mostof these phase detectors have advantage that their lowfrequency response is actually linear over some rangerather than sinusoidal. The exception to this group isthe Alexander or Bang-Bang phase detector [26], whichas its name implies produces a response similar to thatof a relay.

    Analysis of digital phase detectors requires a dierentview from that of classical mixing detectors. First of all,while the exact behavior of these digital phase detectorsis necessarily nonlinear, the low frequency behavior is of-ten linear. Secondly, the circuitry of the phase detectorsare constructed more to deal with specic circuit condi-tions than to make analysis simpler. Finally, no one typeof phase detector is best for all situations. Thus, vastlydierent circuit designs are chosen to implement largelythe same functionality for dierent applications.

    6.1 Mixing

    Signal

    Reference

    VCO

    Signal

    e

    Vd

    Vdm

    Figure 10: Classical mixing phase detector

    The mixing (multiplying) phase detector shown in Fig-ure 10 and discussed in Sections 1.13, has superiornoise performance to all the other detectors discussedhere [6, 9], due to the fact that it operates on the en-tire amplitude of the input and VCO signals, rather than

    6

  • Signal

    Reference

    VCO

    SignalVdm

    Vdm

    e

    Vd

    Vdm

    Figure 11: Over driven mixing phase detector

    quantizing them to 1 bit. Balanced mixers are best suitedfor PLL applications in the microwave frequency range aswell as in low noise frequency synthesizers. However, asmentioned earlier, this results in a loop whose gain isdependent upon the signal amplitude. Furthermore, non-idealities in the circuit implementation of the mixer resultin responses that are far from linear. When noise is notan issue, it is advantageous to move to a detector thathas immunity to these eects.

    6.2 XOR

    Signal

    Reference

    VCO

    Signal

    vivb

    vova e

    Vd

    Vdm

    v = v - vd b a

    Figure 12: Phase detection using an XOR gate. Notethat this accomplishes the same thing as an over drivenmixer, but with digital circuitry.

    vi

    vo

    v XOR vi o

    residual

    vi

    vo

    v XOR vi o

    2X

    residual

    Figure 13: Phase detection using a XOR gate. On theleft, a phase shift between reference and VCO outputof /2 produces an output of the phase detector whosebaseband component is 0. On the right a relative phaseshift of /4 results in an output of the phase detectorwhose baseband component is vd/2. The output isbroken up here into a 2X frequency signal and a resid-ual. The 2X signal averages to 0, while the residualaverages to the baseband phase error.

    For a variety of reasons, it may be desirable to havea loop which does not produce a sinusoidal clock but in-stead a square wave clock. If one over-drives the mixercircuit, that is if one uses signals so large that the ampli-ers saturate, the output signals stop looking like sinu-soids and start looking like Walsh functions (rectangularsignals). Such a phase detector is shown in Figure 11.Understanding the output of such a phase detector relieson a combination of averaging analysis and heuristics.However, one of the more interesting features of such aphase detector is that it can be implemented using an

    Exclusive-OR (XOR) gate as shown in Figure 12. Oneadvantage of such a phase detector is that the loop gainis now independent of input signal amplitude. Further-more, an XOR phase detectors response can have a largerlinear range than a sinusoidal detector (mixer). The dis-advantage is that the linearity of the baseband responseis aected by the relative duty cycles of the input andVCO signals [6, 8]. The standard analysis done by PLLengineers involves drawing out square waves as shown inFigure 13 and then doing some heuristic analysis toconvince themselves that the baseband (low frequency)component of the signal behaves with the triangular phaseresponse shown in the right of Figure 12 (for a 50% dutycycle of the input signal).

    vo

    vi

    D

    D

    Q

    QQ1

    Q2V

    R

    Vde

    Vd

    Vdm

    Figure 14: Two state phase detection using gates. Thetwo logic combinations result in the same PD charac-teristic.

    6.3 Two State Phase Detectors

    To eliminate the duty cycle dependence of the XOR phasedetector, detectors using logic gates can be used. An ex-ample of this is found in Wolaver [6] is shown on the leftside of Figure 14. The addition of the two ip ops to theXOR gate has several results. First, the phase detectoris only sensitive to the rising edges of the input signals,rather than their duty cycles. Secondly, the linear regionof the phase detector is expanded to from /2. Fi-nally, the phase detector is no longer memoryless. Thus,noise spikes that are large enough to trigger a change ofstate have a larger eect than they do with the XORphase detector. The state analysis of this phase detectoris a bit involved.

    Because this phase detector uses only the leading edgeof the input signals, the linear region is increased as men-tioned above. The resulting baseband response can beunderstood from square wave manipulations as describedabove. The resulting baseband component of the phasedetector output now has a sawtooth, rather than trian-gle wave response, and so this detector is often called asawtooth detector.

    6.4 Phase-Frequency Detector

    An extremely popular phase detector is the combinationof the tri-state phase-frequency detector (PFD) with acharge pump shown in Figure 15. The charge pump canbe viewed as a 3 position switch controlled by the phase-

    7

  • Zvi Vu

    Vdvo

    D

    D

    R

    R

    Q

    Q

    R

    V

    1

    1

    Tri-StatePhase-Frequency

    Detector

    ChargePump

    e

    Vd

    Vdm

    Figure 15: The combination of a tri-state phase-frequency detector and a charge pump. Note that theloop lter is often implemented in the Z block of thecharge pump.

    vi

    vo

    vu

    vd

    vd

    Figure 16: Phase detection using an phase-frequencydetector (PFD). As only the leading edges are signi-cant, these are compared to show the phase behaviorof the detector.

    frequency detector. The action of the charge pump isto alleviate any loading of the phase detector in drivingthe rest of the circuit. This allows the response to besmoother than without the charge pump. Note that theloop lter is often implemented within the charge pumpas shown at the right of Figure 15. Figure 17 showsthe use and misuse of the PDF. In the case on the left,a dierence in frequencies is detected and the phase isramped that eventually the frequencies match. However,this same property means that if this detector were usedin clock/data recovery (Section 10.3), the missing tran-sitions are misinterpreted as a lower input frequency, re-

    vi

    vo

    vu

    vd

    vd

    vi

    vo

    vu

    vd

    vd

    Figure 17: The left diagram shows how the PFD re-sponds to frequency errors. The response rapidly slewsthe frequency towards the correct value. This sameproperty makes the PFD ineective for use in clockdata recovery (CDR) as the missing transitions inthe data trick the PFD into slewing the frequency toa lower clock rate, as shown in the right diagram.

    sulting in the phase detector ramping the VCO frequencydown.

    6.5 Sample and Hold

    -

    +vi

    vo

    e

    Vd

    Vdm

    Figure 18: Sample and hold as a phase detector.

    vi

    vo

    vd

    Figure 19: Signals through a sample and hold phasedetector.

    A sample and hold circuit may be used as a phase de-tector as shown in Figure 18. The basic idea here can beseen as follows. Assume the input signal, vi is sinusoidalas shown in the top plot of Figure 19. Furthermore, as-sume the VCO signal, vo is used to trigger sampling ofvi as shown in the middle plot of Figure 19. If the fre-quency of vo matches or is close to the input frequency,then the value of the sampled signal will depend only onthe relative phase of vi and vo. Because the sample rateis below the Nyquist frequency, the samples alias down.However, these aliased samples create a phase error sig-nal as seen in the lower plot of Figure 19. Note that theshape of the phase detector characteristic is based on theshape of the input signal, vi, so that if vi is sinusoidal,vd is sinusoidal. If vi is triangular, vd is triangular [6].Finally, if vi is a square/rectangular, then vd has a relaycharacteristic. Note also that there is no high frequencycomponent resulting from this phase detector. This canbe seen analytically due to the fact that the zero-orderhold has a zero at the sample frequency [27].

    6.6 A Linear Clock Phase Detector

    Clock recovery from a data stream, known as clock/datarecovery (CDR), requires a special type of phase detec-tor. One of the most popular is the so-called Hogge [28]detector, show in Figure 20. An improvement with lowerjitter was generated by Shin et. al. [29] and that versionis often called the Hogge-Shin detector.

    8

  • Data

    vi(Data)

    (Clock)

    vb

    vd

    vo

    va

    D

    Q1

    D

    Q2

    e

    Vd V - VH L

    4

    For 50% transition density.

    Figure 20: The Hogge phase detector. Used primarilyin clock data recovery applications (CDR), the Hoggedetector has a linear characteristic. Vb is modulated bythe signal phase while Va is not. The dierence givesa phase error for the data signal.

    vi

    vb

    va

    Q1

    Q2

    vo

    Figure 21: Phase detection using a Hogge phase de-tector.

    6.7 A Bang-Bang Clock Phase Detector

    The Bang-Bang phase detector [26] shown in Figure 22is unique among the detectors presented here in that itsbaseband behavior is never linear. Instead, the detectoracts as a relay over the region from to . The behaviorcan be seen from the timing diagram analysis shown inFigure 23. The behavior can be described as follows: thesignals a, b, and c are re-timed versions of the data signal.a and c are one bit period apart, b is sampled at the halfperiod between a and c. Basically, if a and c are thesame, then no transition has occurred and the output ofthe phase detector is tri-stated. If not, then the statedepends on b. If b = a, then the clock is early. If b = c,then the clock is late.

    While the nonlinear behavior of the detector is a disad-vantage, it has advantages for high speed clock data re-covery applications over the Hogge detector of Section 6.6in that it does not need to be calibrated on an individualbasis. This improves manufacturability when the circuittechnologies are being pushed to their limits.

    e

    Vd

    VdmDQ D Q

    D Q D Q

    c a

    b b

    Data(Data)

    (Clock)

    vi

    vo

    Latch tracks inputwhen clock = 0.

    c ab

    Data

    bit center

    bit edge

    Figure 22: The Alexander (bang-bang) phase detector.The original version made of component ip ops. Theversion shown here is a circuit well suited to integrationwhich substitutes a latch for the last ip op, therebysaving one latch. On the right is the phase detectorcharacteristic.

    vi

    c

    b

    b

    a

    CKM

    CKC

    Figure 23: Phase detection using a bang-bang phasedetector.

    6.8 Conclusions

    What should be clear from the above section is that themere existence of such wide variety of phase detectorsindicates that no one phase detector is optimal or evenapplicable in each situation. Their usefulness dependsgreatly on the type of PLL they will be used in and onthe input signals that they will be encountering.

    7 Voltage Controlled Oscillators

    F(s)

    G(s)

    + RC2C1

    L

    CL

    R

    Figure 24: On the left, a block diagram of an oscillatorimplemented as a positive feedback loop between avoltage to current amplier through a resonant circuit.On the right, examples of resonant circuits: a LC tankand a network.

    9

  • vc C2C1

    C3

    L

    R

    Figure 25: A VCO implemented through a network.The frequency is adjusted by adjusting the reverse biason the varactor diode, C1.

    The actual clock generated by a PLL comes from thevoltage controlled oscillator (VCO). The VCO is a non-linear device which generates a periodic oscillation. Thefrequency of this oscillation can be controlled by modu-lating some control voltage (hence the name). In a PLL,the control voltage corresponds to some ltered form ofthe phase error. In response to this, the VCO adjusts itsfrequency. As the VCO frequency is slewed by the con-trol voltage, the phase is error is driven towards 0. Thisfrequency adjustment to achieve phase lock results in themodel of a VCO as an integrator.

    VCOs are generally of the form of a ring oscillator,relaxation oscillator or a resonant oscillator. The ring os-cillator, common in monolithic topologies takes the formof an odd number of inverters connected in a feedbackloop [30]. The relaxation oscillator uses a Schmitt-triggerto generate a stable square wave [6]. The latter puts aresonant circuit in the positive feedback path of a voltageto current amplier as shown in Figure 24. The ampliershown for these circuits is a voltage to current amplierwith close to unity gain. The resonant circuit in the posi-tive feedback path has poles close to the j axis. Considerthe bandpass lter:

    F (s) =20s

    s2 + 20s + 20, (13)

    and G(s) = K < 1. Then

    V CO(s) =G(s)

    1G(s)F (s) = Ks2 + 20s + 20s2 + 210s + 20

    , (14)

    where 1 = (1 K). The lowering of the damping ra-tio is called Q amplication (Q = 12 ) and moves thepoles even closer to the j axis. (In the case of the network, there is a complex pair of poles and one pole onthe negative real axis. The dominant eect, Q ampli-cation, takes place on the complex pair.) The frequencyis controlled by altering the capacitance of the resonator,typically by using a varactor diode as a capacitor. A sim-ple circuit diagram for a resonant circuit VCO is shownin Figure 25. Other forms of VCOs, such as crystal os-cillators and YIG oscillators essentially run on the sameprinciple, but modify the resonant circuit.

    For the all digital and software PLLs, the VCO is re-placed by a digitally or numerically controlled oscillator

    (DCO/NCO) [8]. In this case, the input voltage is re-placed by some digital value. The output is a digitaloscillating waveform.

    8 Loop Filters

    -

    +

    vavovb

    R1

    R1

    R2

    R2

    C2

    C2

    C3

    C3

    Figure 26: Analog loop lter for dierential inputs. Forsingle ended input, the + terminal can be tied directlyto ground.

    DigitallyControlledOscillator

    DigitalLoopFilter

    n-bitPhaseError

    n-bit FilteredPhaseError

    Counter

    High state

    Low state

    DigitallyControlledOscillator

    n-count

    Figure 27: Digital PLL lters depend upon the out-put of the phase detector and the input of the DCO.The integration function can be accomplished with acounter.

    As noted earlier, there is at least conceptually al-ways a loop lter. Typical analysis ignores the high fre-quency low pass lter and other dynamics that do notaect the behavior of the loop at the time constants ofthe phase.

    As the vast majority of PLLs are second order and asthe actions of the VCO are modeled as an integrator, looplters are typically rst order. More specically, since aType II system will track a phase ramp and this cor-responds to tracking a step in frequency, the loop lteralmost always contains an integrator. For a double in-tegrator system, the loop lter needs a minimum phasezero to obtain stability. This is true whether the lter isimplemented as an analog or digital lter. Higher orderloops (which are rarer) can be obtained by adding extrapole/zero pairs to the lter.

    The analog circuit (classical or classical digital PLL)shown in Figure 26 shows the general form of a loop l-ter. This particular lter is fairly general with a transfer

    10

  • function of:

    VoVa Vb =

    sR2(C2 + C3) + 1sR1C2(sR2C3 + 1)

    . (15)

    For a typical second order loop, we let C3 = 0. For singleended input (Va only), simply tie the positive terminal ofthe op-amp to ground.

    Digital lters used in all digital PLLs very much dependupon the type of phase detector being used and the typeof DCO used at the output. There are many dierenttypes [8]. Figure 27 shows two. When the phase detectoroutput is a n-bit sampled number, then it is reasonable toconstruct a digital lter with classic Z-plane techniques.However, as seen in Section 6, many phase detectors sim-ply put out pulses. In this case, a n-bit counter can beused. The operation of this counter can be described asfollows. Assuming the DCO has a center frequency thatis set for the nominal counter value, N , if up pulses addto and down pulses subtract from N , then the counteroutput can be seen as an average of the PD pulses:

    nout(z) = (1 + z1 + z2 + z2 + . . .)d(z), (16)

    which can be interpreted as a digital integrator with azero at z = 0:

    nout(z)d(z)

    =1

    1 z1 =z

    z 1 . (17)

    Combining this with the digital integrator of the DCOand the PD gain yields a PLL open loop of:

    out(z)d(z)

    =KdKvT

    2z(z + 1)(z 1)2 , (18)

    which should have poles that stay within the unit circle.A large excess in up or down pulses would saturate thecounter in one direction or another, which would lowerthe eective open loop gain but not destabilize the loop.

    9 Noise

    F(s)

    -

    s

    Ko

    VCO

    i

    o

    vco

    Kdd

    Figure 28: Linear model of input and VCO noise pass-ing through a PLL.

    Since a PLL locks to the phase of the input signal, oneof the key measures of the performance of the loop is thephase noise (or jitter) in the output, o. Figure 28 shows

    the linear PLL model with noise at both the reference in-put, i, and the VCO, vco. In particular one may designthe loop to minimize o or to have o track i precisely.As with a standard linear feedback loop,

    o = T (s)i + S(s)vco (19)

    where T (s) and S(s) are obtained from Equations 5 and 7,respectively. As we can assume that the PSDs of i andvco are independent, the PSD of the output phase isgiven by:

    Goo(j) = T (j)2Gii(j) + S(j)2Gvv(j). (20)

    As with most feedback systems, the loop designer hassome control over the eect of i on o through the shap-ing of the loop, but beyond the loop bandwidth, o isdominated by vco.

    This discussion has touched on two noise sources, butevery component of a PLL is a potential source of phasenoise, from the phase detector to the resistors in the l-ter. A survey of these sources is found in Kroupa [31].The study of VCO noise is a eld unto itself. Perhapsmost commonly used model was presented by Leeson [32].Among the other sources of information on the analysisof noise in PLLs is Wolavers book [6] and a host of pa-pers [33, 34].

    10 Applications

    The ubiquity of PLLs is due to their usefulness in somany applications that proliferate through everythingfrom communications systems, to computer clocks, towireless systems, to consumer electronics. A set of repre-sentative examples is listed here.

    10.1 Carrier Recovery

    LoopFilter

    PhaseDetector

    NonlinearDevice

    VoltageControlledOscillator

    Clock orCarrier Out

    InputSignal

    Figure 29: General block diagram of frequency recov-ery from a modulated signal.

    A common process in communications systems is tomodulate a signal onto a carrier frequency. In order todemodulate the signal from the carrier, often called RFin a reference to the early days of radio, one must rstrecover the carrier signal from the composite signal. If

    11

  • LoopFilter

    PhaseDetector

    BandpassFilter ( )

    2

    VoltageControlledOscillatorCarrier Out

    InputSignal

    2

    m(t)sin ti m (t)cos2 t2

    i

    2ii

    Figure 30: Squaring loop to recover carrier from a mod-ulated signal.

    the signal spectrum contains a strong component at thecarrier frequency, then this is easily accomplished with aPLL. However, quite often there modulation removes thecarrier from the signal spectrum. The restoration of acarrier in this case is generally accomplished by precedingthe PLL with some sort of nonlinear element. A specicexample of one of these is carrier recovery when the signalhas the form:

    r(t) = m(t) sinit (21)

    and m(t) is 1. Known as binary phase shift keying(BPSK), this simple communication method results inthe spectrum of r having no component at i (for equallyprobable +1 and 1 bits). In this case, the squaring loopshown in Figure 30 is able to lock to 2i. The divide-by-2circuit recovers the carrier.

    10.2 Costas Loop

    BandpassFilter

    Signalwith BPSK

    Reference

    LoopFilter

    HighFrequency

    LP Filter

    VCO

    Clock

    DataHighFrequency

    LP Filter

    Quadrature

    In-Phase

    Figure 31: A Mixing Costas Loop

    In the example of BPSK in Section 10.1, it was shownhow a squaring loop can recover the carrier. A Costasloop, shown in Figure 31 is able to both recover the carrierand demodulate the data from such a signal. If therewere no modulation, the upper arm could be consideredsimply a PLL which could lock to a carrier. The eectof the lower arm of the loop is to lock to the modulationand cancel it out of the upper arm of the loop.

    10.3 Clock/Data Recovery

    An issue that pervades communication systems is thatof extracting a data clock and the data itself from anincoming signal. Known as clock/data recovery (CDR),this problem presents some unique issues not found in

    vi

    vi

    vo

    Figure 32: RZ data (dark dashed) and NRZ data (solidlight)

    DataIn

    d/dt

    ( )2

    d/dt ( )2 Bandpass

    Filter

    Figure 33: Conversion from NRZ data to RZ data usinganalog circuits.

    other PLL applications. Two common encoding methods,Return to Zero (RZ) and Non-Return to Zero (NRZ) areshown in Figures 32. Depending upon which format isused, a dierent version of clock recovery must be used.

    RZ formats have the advantage that the clock signalshows up in the data signal spectrum. However, in do-ing so, they require twice the bandwidth of data encodedusing NRZ format.

    The tasks of recovering the clock frequency is oftenseparated from that of recovering the data and the clockphase. With RZ data a PLL can usually lock onto theclock directly. However, with NRZ data, one must rstgenerate a signal whose spectrum contains the clock fre-quency. The circuit shown in Figure 33 detects the edgesof the NRZ data by dierentiating and then uses a squarer

    DataIn

    DelayT/2

    Delay T/2

    BandpassFilter

    XOR

    Figure 34: Conversion from NRZ data to RZ data usingdigital circuits.

    12

  • to rectify this signal. (A full wave rectier could also havebeen used.) The rectied signal is fed through a band-pass lter to obtain an input signal for a PLL. Dependingupon the frequencies involved and noise in the signal, asimilar result can be obtained with digital logic as shownin Figure 34.

    10.4 Frequency Synthesis

    fr

    N

    Nfr

    Phase-Lockedto Reference

    BandpassFilter

    LoopFilter

    HighFrequency

    LP Filter

    VCO

    PhaseDetector

    fr

    frSignalReference

    f

    Figure 35: A Harmonic Locking Phase-Locked Loopwhich uses a phase detector.

    N

    fr

    N fr

    ClockPhase-Lockedto Reference

    BandpassFilter

    LoopFilter

    HighFrequency

    LP Filter

    VoltageControlledOscillator

    fr

    PhaseDetector

    fr

    ClockSignal

    Reference

    d df

    HarmonicCorrector

    mT

    T

    Figure 36: A harmonic locking PLL with optional multi-rate harmonic correcting capability.

    In some cases, it is desirable to have a clock which isphase locked with an input signal of some dierent fre-quency. A common example of this is in synthesizing afrequency from an input signal at a dierent (often lower)frequency. A variant of a PLL called a harmonic lockingloop where the VCO frequency is at some multiple of theinput signal frequency, as shown in Figure 36. The outputof the divide by N operation is at the same frequency asthe input signal and thus the phase detector can providean error signal. For this to happen, however, the VCOmust run at a frequency N times the input frequency. Itis also possible to have values of N which are not integers.

    A recent example from the storage industry is the caseof linkless editing in the DVD+RW optical disk drive for-mat [35, 36] is enabled by locking a harmonic locking loopto a high frequency oscillation of the track walls on thedisk as shown in Figure 37.

    In some applications, the clocking loop is aected by

    Figure 37: A perspective schematic of high frequencywobbles. This allows a rewritable DVD optical drive touse the DVD-ROM format. There are no sector marksor edit gaps. The address and timing information areencoded in the wobble.

    harmonic disturbances. The same type of harmonic com-pensation done in rotating storage systems can be ap-plied to remove this component of the phase error [37] asshown by including the highlighted harmonic corrector inFigure 36.

    10.5 Modulation/Demodulation(Phase/Frequency)

    11 PLL Applications in ControlProblems

    Several applications of PLLs relate to controlling movingobjects, rather than only the tracking of signals. Threeexamples of these will be presented in this section.

    11.1 Disk Drive Control

    A Burst B Burst

    Re

    ad

    ba

    ck

    Sig

    na

    l

    A Field

    B Field

    R/WHead

    Dis

    kS

    urf

    ac

    e

    Data

    Figure 38: Amplitude encoded position error signal(PES) in a hard disk. PLLs are used to time the acqui-sition of the readback signal. Correct demodulation ofthe A and B elds depends upon proper timing.

    One broad use of PLLs is in storage systems. This dis-cussion will focus on hard disks, although similar issuesexist for optical disks and tape drives. Disk drives encodethe cross-track position in a variety of ways, but they all

    13

  • ASync BASync B

    Figure 39: Layout of amplitude encoded position in-formation on a hard disk. The role of the PLL is toresynchronize the timing before the servo signals andthe data can be read.

    Sync Time Shift DeterminesRadial Position

    Figure 40: In phase encoding of position error thephase dierence between the reference mark and theposition mark gives a measure of the cross track posi-tion.

    require some type of PLL to synchronize the reading ofthe position signal with the rotation of the disk [38]. Insectored servo the dominant format for modern harddisks, the data and the position information are inter-laced on the same disk. In amplitude encoded positioninformation (Figures 38 and 39), the read/write head de-modulates the amplitude of the A and B elds separately.If the head is on track, the amplitudes of the demodulatedsignals are nominally equal. If the head is o to one side,then either the A amplitude or the B amplitude will belarger. It should be clear that correct demodulation ofthese elds depends upon proper timing information, sothat the disk drive can distinguish between the dierentservo position elds, as well as the data. The synchro-nization pattern can be seen in Figure 39. It precedesthe position elds and the data elds. This allows theclock to be recovered at the beginning of each sector. Al-though the most common encoding is called amplitude

    encoding, an alternate example uses phase encoding ofposition error [39], shown in Figure 40. This method wasused on IBMs rst Magneto-Resistive (MR) Head drive,the Corsair [40]. The earlier MR heads had highly non-linear cross track behavior. Rather than deal with this,the IBM scheme wrote reference timing patterns followedby slanted position marks. The PLL would lock to thereference pattern and then the drive would do a time ofight calculation to the position marks. If the relativephase was 0, the head was on track. Deviations from theon track position produced phase dierences which couldbe used to servo the head.

    11.2 Harmonic Compensation

    One of the control oriented applications of PLLs that hasarisen the in the past few years is the one cancellationof harmonic disturbances [41, 42]. Most of these algo-rithms assume knowledge of the frequency of the periodicdisturbance. However, when that information is not avail-able, a PLL-like approach can be used to rst estimatethe disturbance frequency and feed this into the harmoniccorrector [16, 43, 44]. Furthermore, this approach is alsouseful in frequency estimation [45, 46].

    11.3 Motor Control

    LoopFilter

    PowerAmplifierPhase

    FrequencyDetector

    Motor

    Analogousto VCO

    Number of segments = KZ

    OpticalCoupler(GaAs)

    Setpoint(Shaft Speed)

    Measured Shaft Speed

    Figure 41: Motor control using PLL techniques.

    The use of PLL techniques for motor speed control isdescribed in Best [8]. Basically, in place of a linear controlsystem with a speed setpoint as the reference input and atachometer to measure the motors rotational velocity, asystem as shown in Figure 41 is used. Here, the tachome-ter has been replaced by an optical tachometer con-sisting of a segmented wheel attached to the rotor shaftand an optical coupler. The optical coupler consists of aphotodiode followed by a Schmitt Trigger which producesan oscillation proportional to the motor speed. The mo-tor and optical coupler together replace the VCO of thePLL. A phase-frequency detector (Section 6.4) is used asit has an innite pull in range and barring damage to thesegmented wheel there will be no missing samples.

    There are several interesting points about PLL basedmotor speed control. First, the motor model itself is sec-

    14

  • ond order (rather than the rst order model of the VCO):

    Gm(s) =KmKz

    s(1 + sTm), (22)

    where Km is the motor torque constant, Tm is the motortime constant, and Kz is the number of segments in thewheel. Allowing for the gain of the power amplier to beKa, the gain of the PFD to be Kd and the loop lter tobe an integrator with a minimum phase zero, the openloop linear response of the system is dened by [8]:

    HOL(s) = KaKd

    (1 + s2

    s1

    )(KmKz

    s(1 + sTm)

    ). (23)

    During normal operation, the PFD will be in a nonlinearregime [17] as the motor speed is ramped to dierent set-points. Some improvements to the steady state responsehave recently been reported by modifying the behavior ofthe PFD [47].

    12 Some Advanced Topics

    With all the available topologies and technologies, itshould be clear that the choice of what to use is veryapplication dependent. Digital techniques have the ad-vantages that they are relatively immune to circuit driftand easy to integrate into small chip packages. However,they are not suitable for every application.

    For high noise input signals, the traditional mixer isstill preferred as it makes the best use of informationin the signal amplitude to reject noise. Classical digitalPLLs are extremely useful in high speed digital commu-nications systems.

    Some of the tradeos can be seen in high speed digitalcommunications systems. As the standard for these sys-tems reaches beyond 10 gigabits per second (Gbps), to 40and 100 Gbps, the circuit technologies are hard pressedto produce the short pulses of phase detectors such as thelinear Hogge detector (Section 6.6). Thus, the nonlinearAlexander detector (Section 6.7) is often preferred. Thisis because the latter detectors components are easy tointegrate and the detector itself has pulses that are noshorter than half a bit interval.

    At the other end of the spectrum, as processing powergoes up, it becomes more practical to sample the dataand perform all the relevant operations in software (Sec-tion 5.3). Not only is this the ultimate in exibility, butit can also be the lowest in cost.

    13 Areas for Contribution

    It seems that there are several areas where use of ad-vanced control methods might improve PLLs. The rstobvious one is in the area of nonlinear analysis. While

    it is true that many loops can be considered to have lin-ear phase detectors close to lock, this is not true when theloop is unlocked and is never true for the Bang-Bang PLL.Furthermore, more analysis of the high frequency detec-tor eects on the loop performance and the injection ofnoise into the clock signals would be useful. Design toolsto optimize designs of PLLs for both phase performanceand signal performance would be another area of strongcontribution. Some of these tools might also be useful indesigning new phase detectors that are optimized for aparticular type of loop.

    For a variety of reasons mentioned earlier, PLLs arealways low order. However, knowing how to obtain stablehigh order nonlinear PLLs should allow for extra loopshaping so common in other control systems.

    Finally, ecient simulation of the entire PLL is a broadarea to study. Most packages break the problem into sig-nal simulation and phase response simulation. Methodsto allow for complete simulation of the system despite thetwo time scales would be very useful and could further beapplied to software PLLs.

    14 Useful References

    Andrew Viterbis classic book (sadly out of print), Princi-ples of Coherent Communication [5], has a wonderful rstintroduction to the analysis of a PLL. Floyd Gardners fa-mous little book, Phaselock Techniques [3], has been theclassic rst book for PLLs. It provides basic analysis andapplications for PLLs. Another of the classic PLL text isAlain Blanchards book, Phase-Locked Loops [4].

    Dan Wolavers book, Phase-Locked Loop Circuit De-sign [6] provides excellent coverage of the dierent cir-cuits used in PLLs, including many dierent phase detec-tor models. Wolaver tends to focus on classical analogand classical digital PLLs.

    Roland Bests book, Phase-Locked Loops: Design, Sim-ulation, and Applications [8] provides a more classicalanalysis of PLLs. It does an excellent job of describing thevarious classes of PLLs, including classical analog, classi-cal digital, all digital, and software PLLs. Furthermore,a software disk is included. However, the treatment ofactual circuits is far more cursory than Wolavers book.

    The IEEE Press has published two books containingpapers on PLLs, both co-edited by William C. Lindsey.Phase-Locked Loops and Their Application [11], co-editedwith Marvin K. Simon, contains many of the seminal pa-pers on PLLs. Phase-Locked Loops [12], co-edited withChak M. Chie, has a larger emphasis on digital loops. Athird book from the IEEE, edited by Behzad Razavi onMonolithic Phase-Locked Loops and Clock Recovery Cir-cuits: Theory and Design [13] goes into much more depthon issues of integration of PLLs and CDR circuits into sil-icon. The collection starts with an excellent tutorial [30].

    15

  • Hsieh and Hung have a nice tutorial on PLLs that notonly includes the basic theory, but also some applications,particularly to motor control [19].

    Paul Brennans book, Phase-Locked Loops: Principlesand Practice [7] is a brief book with a practical bent. Itgives an excellent explanation of phase-frequency detec-tors and charge pumps.

    Donald Stephens book, Phase-Locked Loops for Wire-less Communications: Digital and Analog Implementa-tion [10] has an interesting history section in the front aswell as a method of approaching analysis of digital PLLsthat is closer to a typical sampled data approach thanmost books. This second edition of the book includesinformation on optical PLLs.

    Acknowledgments

    The understanding of PLL circuit components presentedhere has been greatly enhanced by discussions with RickKarlquist, Rick Walker, and Len Cutler of Agilent Labo-ratories and with Salam Marougi of Agilent TechnologiesElectronic Products and Solution Group. The control sys-tems interpretation of various loop components improveddramatically after discussions with Gene Franklin of Stan-ford University. To them I owe a debt of gratitude fortheir insight and their patience.

    References

    [1] S. C. Gupta, Phase-locked loops, Proceedings ofthe IEEE, vol. 63, pp. 291306, February 1975.

    [2] W. C. Lindsey and C. M. Chie, A survey of dig-ital phase-locked loops, Proceedings of the IEEE,vol. 69, pp. 410431, April 1981.

    [3] F. M. Gardner, Phaselock Techniques. New York,NY: John Wiley & Sons, second ed., 1979. ISBN0-471-04294-3.

    [4] A. Blanchard, Phase-Locked Loops. New York, NY:John Wiley & Sons, 1976.

    [5] A. J. Viterbi, Principles of Coherent Communica-tion. McGraw-Hill Series in Systems Science, NewYork, NY: McGraw-Hill, 1966.

    [6] D. H. Wolaver, Phase-Locked Loop Circuit Design.Advanced Reference Series & Biophysics and Bio-engineering Series, Englewood Clis, New Jersey07632: Prentice Hall, 1991.

    [7] P. V. Brennan, Phase-Locked Loops: Principles andPractice. New York: McGraw Hill, 1996.

    [8] R. E. Best, Phase-Locked Loops: Design, Simula-tion, and Applications. New York: McGraw-Hill,third ed., 1997.

    [9] J. A. Crawford, Frequency Synthesizer Design Hand-book. Norwood, MA 02062: Artech House, 1994.

    [10] D. R. Stephens, Phase-Locked Loops for Wire-less Communications: Digital and Analog Imple-mentation. Understanding Science and Technol-ogy, Boston/Dordrecht/London: Kluwer AcademicPress, second ed., 2002.

    [11] W. C. Lindsey and M. K. Simon, eds., Phase-LockedLoops and Their Application. IEEE Selected ReprintSeries, New York, NY: IEEE Press, 1978.

    [12] W. C. Lindsey and C. M. Chie, eds., Phase-LockedLoops. IEEE Selected Reprint Series, New York, NY:IEEE Press, 1986.

    [13] B. Razavi, ed., Monolithic Phase-Locked Loops andClock Recovery Circuits: Theory and Design. IEEEPRESS Selected Reprint Series, New York, NY:IEEE Press, 1996.

    [14] N. E. Wu, Circle/Popov criteria in phaselock loopdesign, in Proceedings of the 1998 American Con-trol Conference, (Philidelphia, PA), pp. 32263228,AACC, IEEE, June 1998.

    [15] D. Y. Abramovitch, A method for obtaining MIMOopen-loop plant responses from closed-loop mea-surements, Invention Disclosure 191166, Hewlett-Packard Co., Corporate Patent Department, M/S20B-O, Palo Alto, CA, February 1991.

    [16] M. Bodson, J. S. Jensen, and S. C. Douglas, Ac-tive noise control for periodic disturbances, IEEETransactions on Control Systems Technology, vol. 9,pp. 200205, January 2001.

    [17] C. A. Adkins and M. A. Marra, Modeling ofa phase-locked loop servo controller with encoderfeedback, in Proceedings of IEEE Southeastcon99,pp. 5963, IEEE, IEEE, March 25-28 1999.

    [18] K. Ogata, Modern Control Engineering. Prentice-Hall Instrumentation and Controls Series, Engle-wood Clis, New Jersey: Prentice-Hall, 1970.

    [19] G.-C. Hsieh and J. C. Hung, Phase-Locked Looptechniques A survey, IEEE Transactions on In-dustrial Electronics, vol. 43, pp. 609615, December1996.

    [20] D. Y. Abramovitch, Analysis and design of a thirdorder phase-lock loop, in Proceedings of the IEEEMilitary Communications Conference, IEEE, Octo-ber 1988.

    [21] D. Y. Abramovitch, Lyapunov Redesign of analogphase-lock loops, The IEEE Transactions on Com-munication, vol. 38, pp. 21972202, December 1990.

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