Department of Science and Technology Institutionen för teknik och naturvetenskap Linköpings universitet Linköpings universitet SE-601 74 Norrköping, Sweden 601 74 Norrköping

ExamensarbeteLITH-ITN-ED-EX--07/014--SE

Polyelectrolyte based organicfield effect transistorsFareed Mohammad Ahmed

2007-06-13

LITH-ITN-ED-EX--07/014--SE

Polyelectrolyte based organicfield effect transistorsExamensarbete utfört i Elektronikdesign

vid Linköpings Tekniska Högskola, CampusNorrköping

Fareed Mohammad Ahmed

Handledare Xavier CrispinExaminator Xavier Crispin

Norrköping 2007-06-13

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LITH-ITN-ED-EX--07/014--SE

Polyelectrolyte based organic field effect transistors

Fareed Mohammad Ahmed

Polyelectrolyte based organic field-effect transistors.

Filed effect transistors, EDLC, polyelectrolyte

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© Fareed Mohammad Ahmed

Polyelectrolyte Based Organic Field-Effect Transistors

Organic Electronics group at the Department of Science and Technology (ITN) at Linköping University, Campus

Norrköping

Md. Fareed Ahmed

Handledare: Lars Herlogsson

Examinator: Xavier Crispin

Norrköping 31-06-2007

Abstract In this thesis work, the fabrication of dual gate organic field-effect transistors (DG-OFETs) using polyanionic proton conductor named polyvinylphosphonic acid and acrylic acid P(VPA-AA), SiO2 as gate insulating materials and poly(3-hexylthiophene) (P3HT) as organic semiconductor have been studied. Upon operation, the top insulating layer forms large electric double layer capacitors (EDLCs) at the Ti/P(VPA-AA) and P(VPA-AA)/P3HT interfaces. This new type of robust transistor, called as EDLC-OFET, displays fast response (<0.3 ms), a reasonably high field effect mobility (0.0030 cm² V-1 s-1), a low ION/IOFF ratio (150), and operates at low voltage (<1 V). Results concerning the influence of bottom gate on the DG-OFET are presented and discussed. The results presented are important for low-cost printed polymer electronics. Also, various conducting polymer gate electrode in addition to laminated OFET to form EDLC-OFET have been tested. Conducting polymers include PEDOT:PSS and polyaniline (PANI).

Acknowledgements I would like to express my sincere gratitude to the following persons: First of all, to Professor Magnus Berggren and my supervisor Xavier Crispin for giving me the opportunity to work in the Organic Electronics group and also for creating an encouraging research environment. Special thanks to PhD student Lars Herlogsson for guidance, valuable discussions, support and for always having time for my endless questions. Not only, I have learned many things from the persons mentioned above but also they have inspired my way of thinking. I am never going to forget this experience. To all group members of Organic Electronics field for the support and friendship. Congratulations in advance to Peter Andersson, Payman Tehrani and Joakim Isaksson who are likely to complete their PhD this year. To the staff members of ACREO institute for valuable discussions and the laboratory support. Especially to Anurak Sawatdee or “the EK”, who I think is one of the funniest person I ever met. I would like to extend my appreciation to those people, who have helped and supported the study presented in this work my friend Mikael Milevski, Ashkan and my family, for all their love and their support during my study at Linköping University. Last but not the least Sami Elhag for guidance, fun and free teacups.

Abbreviations DG-OFET Dual gate organic field-effect transistor EDLC Electric double layer capacitance µFET Field effect mobility Au Gold Ag Silver Ti Titanium Si Silicon Vth Threshold voltage SiO2 Silicon oxide S, D and G Source, drain and gate P(VPA-AA) Polyvinylphosphonic acid and acrylic acid P3HT Poly(3-hexylthiophene) PEDOT Poly(3, 4-ethylenedioxythiophene) PSS Polystyrene sulfonic acid DEG Diethylene glycol PANI Polyaniline PEG-DGE Poly(ethylene glycol)-diglycidy ether

Table of contents 1. Introduction............................................................................................................. 6

1.1 Goal........................................................................................................................... 1 1

1.2 Report structure......................................................................................................... 2 2. Organic Electronics............................................................................................ 3

2.1 Basic Structure .......................................................................................................... 4 2.2 Doping of polymers .................................................................................................. 6 2.3 Organic electronics based devices ............................................................................ 8

2.3.1 OLED (organic light-emitting diodes)............................................................... 8 2.3.2 Organic solar cells.............................................................................................. 9 2.3.3 OFET (organic field effect transistor).............................................................. 10

3. Electrolyte gated Organic field effect transistors.............................. 13 4. EDLCs/ polyelectrolytes ................................................................................. 16

4.1 Electric double layer capacitors (EDLCs) .............................................................. 16 4.2 Polymer-electrolytes (polyelectrolytes) .................................................................. 18

5. OFET model ......................................................................................................... 19 6. Specific materials ............................................................................................... 21

6.1 Poly(3-hexylthiophene)........................................................................................... 21 6.2 Polyanionic electrolyte............................................................................................ 22 6.3 PEDOT:PSS............................................................................................................ 23 6.4 Polyaniline .............................................................................................................. 24

7) Methods .................................................................................................................. 26 7.1 Spin coating ............................................................................................................ 26 7.2 Ellipsometer ............................................................................................................ 26 7.3 Electrical characterization....................................................................................... 27

8. Results and discussion ..................................................................................... 28 8.1 DG-OFET ............................................................................................................... 28

8.1.1 Fabrication ....................................................................................................... 28 8.1.2 Electrical characterization................................................................................ 29

8.1.2.1 Transfer characteristics ............................................................................. 30 8.1.2.2 ION/IOFF vs VG2 .......................................................................................... 35 8.1.2.3 VG2 vs Vth ................................................................................................. 36 8.1.2.4 Switching characteristics .......................................................................... 36

8.2 Conducting polymer gate electrode ........................................................................ 39 8.2.1 PEDOT:PSS gated device................................................................................ 39 8.2.2 PANI gated device ........................................................................................... 41 8.2.3 Laminated OFET ............................................................................................. 43

9. Conclusions/Future work............................................................................... 46 9.1 Conclusions............................................................................................................. 46 9.2 Future work............................................................................................................. 47

References................................................................................................................... 48 Text ............................................................................................................................... 48

Figures........................................................................................................................... 49 List of Figures: Figure 1: Schematic cross-section view of a dual-gate EDLC-OFET 2 Figure 2: Formation of polyethylene from ethylene 4 Figure 3: sp2 hybridization in case of carbon 4 Figure 4: Band structure in a conducting polymer 5 Figure 5: Representing different conjugated polymers 6 Figure 6: Two ground states of polyacetylene 6 Figure 7: Generation of positive polaron (A) and bipolaron (B) in poly (p-phenylene) 7 Figure 8: Mobility of semiconducting polymers 8 Figure 9: Schematic of OLED structure 9 Figure 10: Schematic of organic solar cells 9 Figure 11: Schematic figure of OFET 10 Figure 12: Output characteristics of OFET 12 Figure 13: Transfer characteristics of OFET 12 Figure 14: Polymer electrolyte gated FET structure and room temperature device characteristics 13 Figure 15: Polymer electrolyte-gated SC-OFET transfer characteristics 14 Figure 16: Chronoamperometric response of OFET 15 Figure 17: Concept of EDL Capacitors 16 Figure 18: Concept of EDLCs in OFET by using polyanionic polyelectrolyte 20

Figure 19: Channel of OFET (Top view) 20 Figure 20: Chemical structure of P3HT 22 Figure 21: Formation of EDLC in OFET 22 Figure 22: Chemical structure of P(VPA-AA) 23 Figure 23: Chemical structure of PEDOT:PSS 23 Figure 24: Several oxidation states of PANI 25 Figure 25: A large area Spin Coater 26 Figure 26: An ellipsometer 27 Figure 27: A parameter analyzer 28 Figure 28: Schematic cross-section view of a dual-gate OFET with top and bottom FET 29 Figure 29: Measurement on DG-OFET (top view) 30 Figure 30: Transfer curves for VG2 = 0 V (X-axis) and VG2 = + 100V (Y-axis) 31 Figure 31: Transfer curves for VG2 = 0 V (X-axis) and VG2 = -100V (Y-axis) 32 Figure 32: ID (log) vs VG2 for the ON state and the OFF state 33 Figure 33: Response in ON state when VG2 is varied 33 Figure 34: Graph indicating VG2 (X-axis) vs ION/IOFF (Y-axis) 35 Figure 35: Graph indicating VG2 (X-axis) vs Vth (Y-axis) 36 Figure 36: Switching characteristics of DG-OFET 37 Figure 37: Close up picture showing the response in ID when VG2 pulses are varied 38 Figure 38: Schematic cross-section view of a PEDOT:PSS gated device 40 Figure 39: I-V characteristics of Au/P3HT/P(VPA-AA)/PEDOT:PSS device simulating a part of the EDLC-OFET 40 Figure 40: Schematic cross-section view of a PANI based device 42 Figure 41: I-V characteristics of Au/P3HT/P(VPA-AA)/PANI device simulating a part of the EDLC-OFET 42 Figure 42: Schematic cross-section view of the Laminated OFET 44 Figure 43: Transfer characteristics of the Laminated OFET 45 Figure 44: Output characteristics of the laminated transistors using the two different gates 45

1. Introduction This thesis work has been performed in the Organic Electronics group at the Department of Science and Technology (ITN) at Linköping University. In the group, organic field-effect transistors (OFETs) [1, 2] based on conducting polymers has been developed that are operated at less than 1 V. These transistors come under a new kind of generation of OFETs called as Electric Double Layer Capacitance (EDLC)-OFETs. In comparison to electrochemical transistors, these systems are pretty fast and compare to FET they operate at low voltage. Currently, these types of transistors are being examined for use in printed [1, 3, 4], flexible, integrated electronics and displays. This thesis work is aiming towards the reader that has knowledge of organic electronics and understands the basics of transistors. This report will only include the concepts aiming towards the better understanding of p-type EDLC-OFETs. Initially this work was started with the attempts to manufacture a conducting polymer gate electrode for the EDLC-OFETs. To achieve these, various conducting polymers were tested but the end result was not as expected. For a better understanding of the reader this part will be described later. 1.1 Goal The goal of this thesis work is to develop a dual-gate organic field-effect transistor (DG-OFET). This device can be realized by using a solution-processed p-type organic semiconductor (active layer) and two insulator layers (top gated insulator 1 and bottom gated insulator 2). Patterned gold (Au) contacts are used as source/drain electrodes with Titanium (Ti) as top gate electrode and heavily doped Silicon (Si) as bottom electrode, shown in Figure 1. Due to the quick formation of electric double layer with large capacitance at the conjugated polymer-polyelectrolyte interface, fast and robust field-effect transistors can be formed which are capable of providing high current output for low operating gate voltage.

The goal will be reached through following steps:

• Planning of construction of the devices. • Design of the devices and experiments. • Fabrication of the devices in a cleanroom. • Electrical characterization. • Analysis of data.

1

Gate1 (Ti)

Insulator 1

Semiconductor Drain Source

Insulator 2

Gate 2 (Si)

Figure 1: Schematic cross-section view of a Dual-gate EDLC-OFET.

1.2 Report structure Structure of this report is reported in the following manner: Chapter 1: - Gives the introduction of the thesis works. Chapter 2: - Gives the overview, background of organic electronics and some devices

based on organic electronics. Chapter 3: - Gives the summary of previous works. Chapter 4: - Understanding of EDLC and polyelectrolytes. Chapter 5: - OFET model. Chapter 6: - Describe the important materials used in this thesis work. Chapter 7: - Methods used for measuring and characterizing EDLC-OFETs. Chapter 8: - Results, discussion and previous attempts to make conjugated polymer gated

FETs will be presented. Chapter 9: - Conclusions and future work.

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2. Organic Electronics Inorganic silicon, gallium arsenide and metals such as copper and aluminum have dominated the electronic industry for more than four decades. However, research efforts are being performed to improve the electrical and optical properties of organic electronics through novel synthesis and self-assembly techniques. This new electronics is referred as “organic electronics” since the materials consisting of both molecules and polymers are carbon-based. A molecule is a collection of atoms in a definite arrangement held together by chemical bonds whereas polymers can be seen as a big molecule or collection of molecules held together by covalent chemical bonds. Polymers cannot only occur naturally but it can also be made through synthetic processes (by polymerization). This thesis focuses on polymers since the organic materials used in this work where polymer based. Previously, polymers were considered as true insulators. But in the year 1977, with the discovery of iodine doped polyacetylene (-CH = CH-) x synthesized in a simple manner by the polymerization of gaseous acetylene, C2H2 by Alan J. Heeger, Alan G. MacDiarmid and Hideki Shirakawa [5], who were also awarded the Noble prize in Chemistry in 2000; it took a new turn. Today, polymers show a broad range of conductivities, all the way from semiconductors to reasonably good conductors and are called conducting or conjugated polymers. They belong to a novel class of semiconductors that combine the properties of semiconductors with the processing advantages and mechanical properties of polymers.

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2.1 Basic Structure Polymer structure consists of many subunits called monomers; each being the size of conventional small molecule and these units are linked to each other by chemical bonds. Figure 2 represents better understanding of how a polymer (polyethylene) is formed from a monomer (ethylene) during the polymerization process.

C

H

H

C

H

H

C

H

H

C

H

H

Monomer Polymer

n

Figure 2: Formation of polyethylene from ethylene. Conjugated polymers have a framework of alternating single and double carbon-carbon (sometimes carbon-nitrogen) bonds. Single bonds are referred as σ bonds and a double bond contains both an σ bond and a π bond. All conjugated polymers have an σ bond backbone of overlapping sp2 hybrid orbital, shown in Figure 3. The remaining out-of-plane pz orbital on the carbon (or nitrogen) atoms overlap with neighboring pz orbital to give π bonds.

E 2s 2px 2py

2pz

1s

Figure 3: sp2 hybridization in case of carbon.

Singly occupied 2s orbital along with singly occupied 2px and 2py orbitals are capable of forming

σ bonds to three neighboring atoms. The remaining 2pz orbital, not participating in sp2 hybridization, is capable of forming π bond with its neighboring pz orbital.

4

In reality, the electrons that constitute the π bonds are delocalized over the entire molecule and the quantum mechanical overlap of pz orbitals produces two orbitals, a bonding (π)-orbital and an antibonding (π*)-orbital. The lower energy (π)-orbital produces the valence band, and the higher energy (π*)-orbital forms the conduction band. The difference in energy between the two levels produces the band gap that determines the optical properties of the material. Most semiconducting polymers appear to have a band gap that lies in the range 1.5-3 eV, corresponding to the same range of inorganic semiconductors [6], which makes them ideally suited as optoelectronic devices working in the optical light range. Figure 4 shows the general band structure in a conducting polymer where LUMO is referred as the lowest energy unoccupied molecular orbital and HOMO is referred as the highest energy occupied molecular orbital.

LUMO

HOMO

Energy

bandgap

Figure 4: Shows band structure in a conducting polymer.

LUMO is referred as lowest energy unoccupied molecular orbital and HOMO is referred as highest energy

occupied molecular orbital [1]. Conjugated polymers can be divided into two categories depending upon their geometry: (a) Polymers having a degenerate ground state, in which alternating of single and double bonds results in a single (degenerate) ground state energy. Trans-polyacetylene (refer Figure 6) is the typical example of this class of conjugated polymers. (b) Polymers having a non-degenerate ground state, in which modification of single and double bonds leads to destabilized structure. Polymers like pentacene, polythiophene, polypyrrole, poly (p-phenylenevinylene) (refer Figure 5) and cis-polyacetylene (refer Figure 6) belongs to this class of polymers.

5

Figure 5 shows some of the common conjugated polymers.

n NH

Polyaniline (PAn) n

Poly(p-phenylene vinylene) (PPV)

N

n

Poly(2-vinylpyridine) (P2VP)

S n

Polythiophene (PTh)

NH

n

Polypyrrole (PPy) Pentacene

Figure 5: Representing different conjugated polymers.

All the above polymers have non-degenerated ground state. While polyacetylene itself is too unstable to be of any practical use, its structure constitutes the core of all conjugated polymers, shown in Figure 6.

Trans-polyacetyelene Cis-polyacetylene

Figure 6: Showing two categories of polyacetylene.

Trans-polyacetylene has a degenerate ground state and cis-polyacetylene has a non-degenerate ground

state.

2.2 Doping of polymers Conducting polymers are insulators in their neutral state and no intrinsically conducting polymer is known at this time. A polymer can be made conductive by oxidation (p-doping) and reduction (n-doping) of the polymer either by chemical or electrochemical doping. It is generally agreed that the mechanism of conductivity in these polymers is based on the motion of charged carriers within the conjugated framework. The charge carriers, either positive p-type (holes) or negative n-type (electrons), are the products of oxidizing or reducing the polymer respectively. So far, only p-doped conjugated polymers have wide applications in e.g. electrochromic devices, rechargeable batteries, capacitors etc. Less effort has gone into synthesizing and characterizing n-doped materials, as it is unstable in ambient atmosphere since they react quickly with oxygen in air. Generally, oxidation of the polymer initially generates a radical cation with both spin and charge. Referring from solid-state physics, this species is referred as polaron and comprises both a hole site and the structural distortion, which accompanies it. The cation and radical form a bound species, since any increase in the distance between them would

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necessitate the creation of additional higher energy quinoid units. In special cases, two nearby polarons might also combine to form the lower energy bipolaron. This can typically occur upon doping since the negative counterions stabilize the two positive charges of the positive bipolaron. In some cases, one bipolaron can be more stable than two polarons despite the coulombic repulsion of the two ions. Figure 7 shows Positive charged defects on poly (p-phenylene) A) Polaron and B) Bipolaron.

Figure 7: Generation of positive polaron (A) and bipolaron (B) in poly (p-phenylene).

Here . denotes an unpaired electron and + denotes a hole.

The conductivity (σ) of a polymer is related to the number of charge carriers (n) and their mobility (µ) and is given by

μσ n∝ (2.1) Since the band gap of most conjugated polymers is fairly large, n is very small at room temperature. Figure 8 compares mobility of semiconducting polymers with other semiconductors.

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Figure 8: Compares mobility of semiconducting polymers compared with other semiconductors.

Here ‘e’ denotes electron mobility and ‘h’ is the hole mobility [2]. 2.3 Organic electronics based devices In this section, some of the previous (opto) electronic devices fabricated from conjugated materials are demonstrated. 2.3.1 OLED (organic light-emitting diodes)

OLEDs were first reported in 1987 [7]. It is a special type of light-emitting diode formed by depositing thin layer of organic compounds sandwiched between two electrodes. Material such as poly[2-methoxy-5-(2’-ethylhexyloxy)-p-phenylenevinylene] (MEH-PPV) can be used as an organic film [8, 9]. In this case, calcium (Ca) with low work function is used as cathode electrode to inject electrons to the LUMO of organic film and indium-tin-oxide (ITO) with high work function is used as anode electrode to inject holes to the HOMO of organic film. In forward bias, this injected electrons and holes recombine in the organic film and emit light, shown in Figure 9.

8

hv

h+

Ca

LUMO

ITO

e-

HOMO

Figure 9: Schematic of OLED structure.

Light is emitted due to the recombination of holes from ITO electrode and electrons from Ca electrode in the organic film.

2.3.2 Organic solar cells

Generally, solar cells are used to convert light energy into electrical energy. In this kind of solar cells, conjugated polymer thin films are sandwiched between two electrodes, Ca and ITO (discussed above) and excitons (electrons and holes) in polymer is formed due to the absorption of photons. Compare to OLED when this device is in forward bias, the excitons decay radiatively or non-radiatively i.e. the holes are injected from the HOMO of the polymer film to the ITO electrode and electrons are injected from the LUMO of the polymer film to the Ca electrode, shown in Figure 10.

9

hv

h+

ITO

HOMO

LUMO

e-

Ca

Figure 10: Schematic of organic solar cells.

Excitons created by absorption of photons diffusive over a length of 5-15 nm and then decay either

radiatively or non-radiatively.

2.3.3 OFET (organic field effect transistor) This kind of transistor can be manufactured entirely based on organic materials. It consists of three electrodes: source, drain and gate. Usually, source and drain electrodes are made of metals to inject electrons/holes into the semiconductor layer. Gate is separated from source and drain by an insulator and a semiconductor layer, shown in Figure 11. By applying a voltage between gate and source contact density of charge carriers between drain and source can be modulated. Accordingly, current enhancement does not occur in the inversion region but in the accumulation regime.

Source

VG

VD

Drain

Gate

SemiconductorInsulator

Source

Figure 11: Schematic figure of OFET.

Showing gate electrode separated from source and drain electrode by an insulator and semiconductor layer.

VG and VD stand for gate voltage and the drain voltage, respectively.

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In general, the performance of an OFET depends on the following parameters: (1) Mobility. (2) ION/IOFF ratio. (1) Mobility (µ): - It describes how easily charge carriers can move within the semiconductor layer under the influence of an electric field and is therefore related to the switching speed of the device. Mobility has a strong dependence on: • Temperature. • The applied electric field. In disordered systems, like semiconducting polymers, transport involves phenomena such as hopping between localized states wherein the phonons help to overcome the energy difference between sites. The mobility due to thermally assisted hopping is many orders of magnitude lower than that due to band transport, as in inorganic semiconductors. However, increasing the temperature can increase the mobility. According to Poole-Frankel model, the application of electric field results in the lowering of the potential barrier in the direction of electric field, which in turn increases the charge carrier motion, and thus resulting in increase of mobility. This parameter is extracted from current-voltage measurements, and would be ideally be as large as possible. Although mobilities as high as 3 cm² V-1 s-1 have been reported [10, 11], the field effect mobility of OFETs remains by far lower than that of conventional silicon FETs. This due to the fact that charge carriers are not free to move in extended states, but are stored as polarons self-trapped into states localized in the forbidden band. The mobility in the linear region can be calculated from equation (2.2)

)()/( thGDiFETlin

D VVVLCWI −= μ (2.2)

and in the saturation region, it can be calculated from equation (2.3)

2)()2/( thGiFETsat

D VVLCWI −= μ (2.3) where ID

lin, IDsat = Drain current in the linear and saturation region.

W = Channel width. L = Channel length. Ci = Capacitance per unit area of the insulator. µFET = Field effect mobilities of holes. VG, VD = Gate voltage and drain-source voltage. Vth = Threshold voltage is the minimum VG required to open the channel. A low Vth

is desirable since it reduces power consumption.

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Linear and saturation regime (transfer characteristics) are shown schematically in Figure 12 and threshold voltage (output characteristics) in Figure 13.

)(satVV DSDS = Linear region

Saturated region

I – V curve in the ohmic region

DI

DV thV0

DI

GV

Intercept is turn-on voltage thV

Figure 12: Output characteristics of an OFET. Figure 13: Transfer characteristics of an OFET.

Current increase linearly with drain bias for a fixed gate bias. Vth and mobility can be obtained from ID -VG curve.

Once VD > VD (sat), the current is independent of VD.

(2) ION/IOFF ratio: - It is defined as the ratio of the current in the ‘on’ and ‘off’ states indicating the switching performance of OFETs. A low off current is desired to eliminate the leakage while in the inactive state. Ratios as high as 106 can be reached by current generation OFETs.

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3. Electrolyte gated organic field effect transistors OFETs were usually operated at high voltages to switch the operating modes between on and off due to the formation of low capacitance coupling between gate electrode and semiconductor. But for the past decade there has been a significant improvement in the performance of the OFETs that not only can operate at low voltages but also with efficient fast response. The content of this section summarizes some of the previous papers that describe all these kinds of OFETs. One of the common polymer electrolyte used in these kinds of OFETs is poly(ethylene oxide)/lithium perchlorate (PEO-LiC1O4). This polymer electrolyte can be used in two ways either readily or by mixing with Alfa Aesar i.e.LiC1O4.3H2O. In the former case [12], it can be used as a gate electrode by spin coating on a semiconductor layer of poly(2, 5-bis (3-tetradecylthiophen-2-yl) thieno [3, 2-b] thiophene) (pBTTT-C14) with patterned Au contacts as source and drain, shown in Figure 14. In the latter case [13], on a pentacene patch with patterned Au contacts has source, drain and top gate electrodes. Both of these combinations can be prepared on SiO2/Si substrate.

Figure 14: Polymer electrolyte gated FET structure and room temperature device characteristics.

(a) A schematic illustration of the four-probe device structure complete with the ionic polymer electrolyte layer (bottom) with the molecular structure shown (top). The molecular structure of pBTTT-C14 is also

shown (middle). (b) Typical current vs. Vg and (c) conductivity vs. Vg [3].

From Figure 14 (b), at VG = -3 V source-drain current (ID) reaches -21 mA, corresponding to a current density of 2 * 106 Acm-2 and channel conductivity of 9,700 Scm-1 which is comparable to conventional metals as shown in Figure 14 (c). By using the capacitance of polyelectrolyte double-layer capacitance 100 µFcm-2, the calculated mobility (µ) achieved is ~ 3.5 cm² V-1 s-1 much higher than the latter case having a calculated µ of ~ 0.01 cm² V-1 s-1. One more of way using this polyelectrolyte is by addition with polyethylene oxide in acetonitrile solution in order to achieve required ether O: Li+ stoichiometric ratio. Latter this combination can be used as an electrolyte layer to prepare a single crystal OFET (SC-OFET) [14].

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A important point to note here, is the use of the thick film of a insulating buffer layer material 4, 4”-diphenoxy- [1, 1’; 4’, 1”] terphenyl, which is deposited on top of organic semiconductor crystal (OSC) of rubrene and tetracene. At the end, this polyelectrolyte is cast directly on top of the buffer layer/OSC. In simple words, multiple layers of polyelectrolyte/Buffer layer/OSC can be formed on top of glass substrate with patterned Au contacts as source, drain and top gate electrodes. The transfer characteristics for both (a) rubrene and (b) tetracene SC-OFETs gated by the polymer electrolyte is shown in Figure 15.

Figure 15: Polymer electrolyte-gated SC-OFET transfer characteristics measured for (a) rubrene and (b) tetracene at a drain voltage of −1 V. The gate voltage sweep rate and channel area for the rubrene

device were 300 mV/s and 20 * 200 µm2, respectively; these values were 85 mVs-1 and 200 * 2000 µm2 for the tetracene device. Insets show the molecular structures of (a) rubrene and

(b) tetracene [4].

From Figures 15 (a) and 15 (b), it is clear that the ID modulation of rubrene is much higher than the ID modulation of tetracene. The difference could be due to the interface trapping of the tetracene device. Carrier densities can be estimated by calculating the polymer electrolyte double-layer capacitance (C´) which is ~ 100 µFcm-2 and charge densities of induced holes can be calculated by C´VG which gives a value of approximately 2 * 1015 holes cm-2 at VG = -3 V. Therefore, using this calculated charge density, estimated µ’s were ~ 2 * 10-3 and 6 * 10-5 cm² V-1 s-1 for the rubrene and tetracene SC-OFETs.

14

In all the above-described OFETs, electrolyte used is composed of small ions, dispersed in a matrix of PEO, which may penetrate the semiconductor surface. Because of this reason, it is unclear whether these OFETs undergoes electrochemistry in the channel and behave like electrochemical transistors or if the mechanism is not involving electrochemistry and instead a field effect. To avoid electrochemistry in the channel and obtain a field effect transistor, polyanions were used. The size of those ions is so large that they are virtually immobile and cannot penetrate into the organic semiconductor layer. Note, in this kind of devices the mobility term used is µFET since doping is due to field effect. It can be fabricated with Au source/drain bottom electrodes, a regioregular P3HT thick layer and [P(VPA-AA)] thick layer with top electrode as Ti gate [15]. The transfer characteristics of the device gave mobility (µFET) ~ 0.012 cm² V-1 s-1 and ION/IOFF ratio of about 140. To be sure of the time response, gate potential was varied from 0 V to -1 V and vice-versa for drain electrode at a constant potential of -1 V, shown in Figure 16.

Figure 16: Chronoamperometric response [5].

From the graph, rise/fall occurred in 3.5 ms and included 90% of the response, which is 100 times faster than previous electrolyte-based transistors.

15

4. EDLCs/ polyelectrolytes In this part of the section EDLCs and polyelectroltes are explained briefly 4.1 Electric double layer capacitors (EDLCs) Capacitors have been used to store electricity without carrying out any conversion in TVs or radio-sets for long time. Although the storage capabilities of capacitors are much smaller than batteries, recently very large capacitors have been developed called as Electric double layers capacitors (EDLCs). They are also often referred as Super or Ultra capacitors. Basically, EDLCs can be seen as physical absorption and electrochemical capacitors as chemical absorption. For better understanding, it is advisable to follow the basic principle behind the capacitor, shown in Figure 17.

Electric Double Layers

cathode anode

Electrolyte

cation

anion

Figure 17: Concept of EDL Capacitors.

Operating principle in EDLCs.

When an external field is applied, the positive ions (cations) from the electrolyte are attracted towards the negative electrode (cathode) and at the same time, the negative ions (anions) from the electrolyte are attracted towards the positive electrode (anode). Both these ions are distributed relative to each other over a short distance forming a phenomenon called electric double layer that occurs at the boundary of electrode and electrolyte. After some time, ions in electrolytic solutions are absorbed to activated electrodes and again desorbs from the electric double layers. Generally, EDLCs using water-soluble or aqueous electrolytes can withstand a voltage up to 1 V.

16

Table 1 shows some of the EDLCs features

Small eco impact Very safe Possible to charge/discharge many times

Long expected life span

Capable of speedy charge/discharge

High charge/discharge efficiency

Wide span of operating temperature

Low maintenance

Easy to measure remaining amount

Free depth of discharge

The large capacitance of electric double layer is due to the small distance between ions and the charged metal electrode and is given by equation (4.1)

dAC r /0εε= , (4.1)

where rε = Dielectric constant of electrolyte.

0ε = Vacuum permittivity. A = Area of the electrodes. d = Distance between ions and the metal electrodes.

This large capacitance can be achieved by applying low voltage, as it depends upon the amount of ions in the electrolyte and the voltage applied between these electrodes and is given by the equation (4.2)

VCQ = , (4.2)

where Q = Amount of ions in the electrolyte. C = Capacitance of the electrolyte in farads. V = Voltage applied.

17

4.2 Polymer-electrolytes (polyelectrolytes) Generally, an insulator can be divided into two categories: • Dielectric. • Polyelectrolyte.

Usually, gates based on dielectric layers often requires large operating voltages to switch OFET on and off because of the low capacitance coupling between gate electrode and semiconductor. Examples of dielectric are SiO2 and insulating polymers like benzocyclobutene and poly(methyl methacrylate), but the amount of charge induced by these materials in the semiconductor layer is limited because of their low dielectric constants and large film thickness. Using a solution-processed solid polyelectrolyte, this capacitance coupling can be increased as mentioned above. This work uses polyelectrolyte in order to form EDLC. Polyelectrolytes are good conductors of ions and poor conductor of electrons/holes or in other words polymers which are capable of ionic dissociation and may be a constituent or subsistent of the polymer chain. Table 2 shows the different ways to incorporate ions into polymers.

Type Composition Mobile species Examples Gel polyelectrolyte

Polymer, salt and solvent

Cations, anions and solvent

Pv2

Ionomers Polymeric salt None, unless wet

Nafion

Solvating polymer Polymeric solvent + salt

Cations and anions

Peo + Lico4

Solvating ionomer Polymeric solvent / salt

Cations and anions

The number of these groups capable of ionic dissociation in polyelectrolytes is normally so large that the polymers are water soluble in the dissociated form (also called polyions). Depending on the nature of the groups capable of dissociation, polyelectrolytes are divided into polyacids and polybases. On dissociation of polyacids there is formation of polyanions, i.e. elimination of protons, which could be both inorganic as well as organic polymers. Examples of polyacids are polyphosphoric acid, polyvinylsulfuric acid, polyvinylsulfonic acid, polyvinylphosphonic acid and polyacrylic acid. Polybases contain groups able to take up protons. Examples of polybases with groups capable of dissociation located on the chains or laterally are polyethyleneimine, polyvinylamine and polyvinylpyridine. Polybases form polycations by taking up protons. It is also possible to employ linear or branched polyelectrolytes. The use of branched

18

polyelectrolytes leads to less compact polyelectrolyte multifilms with a higher degree of porosity of the walls. To increase the capsule stability it is possible to cross link polyelectrolyte molecules within or/and between the individual layers, for example by cross-linking amino groups with aldehydes. There are in principle no restrictions on the polyelectrolytes to be used as long as the molecules used have a sufficiently high charge or/and have the ability to enter into a linkage with the underlying layer via other interactions such as, hydrogen bonding and/or hydrophobic interactions. 5. OFET model

OFETs are particularly interesting as their fabrication process are much less complex compared with convential Si technology, which involves high-temperature, high vacuum deposition and sophisticated photolithographic patterning methods. In general, low-temperature deposition and solution processing can replace complicated methods mentioned above in Si technology. In addition, the mechanical flexibility of organic materials makes them naturally compatible with plastic substrates for lightweight and foldable products. OFET inherits its design architecture from its inorganic counterpart, namely the metal-oxide-semiconductor field-effect transistor (MOSFET). It is mainly composed of three main components:

(1) Source, drain and gate. (2) A polyelectrolyte layer. (3) The semiconductor layer.

These three components are described in detail below:

(1) Basically, OFET is a three terminal device, in which a voltage applied to a gate

electrode controls the current flow between source and drain under an imposed bias. The control of source-drain via a third terminal has resulted in their widespread use as switches. Nowadays, the source and drain electrodes of OFETs can be printed with a separation of less than 1 µm. In this work, Au contacts are used as source and drain electrodes and the two gate electrodes are Ti and Si.

(2) By using thin layers of solution-processed solid polyelectrolyte [in this case P(VPA-

AA)] capacitive coupling between the gate-semiconductor can be increased for low applied voltage due to very large capacitance of the electrolyte. When a negative voltage is applied to the gate electrode, mobile P(VPA-AA) protons are attracted to the gate electrode forming a Helmholtz layer and leaving behind immobile P(VPA-AA) anions chains close to positively-doped organic semiconductor [in this case P3HT] chains forming a Diffuse layer. Thus, electric double layers are formed at the interfaces between gate/polyelectrolyte and polyelectrolyte/P3HT, shown in Figure 18. A consequence of this mechanism is that the capacitance in OFET does not change dramatically irrespective of the thickness of polyelectolyte due to the

19

spontaneous formation of EDLCs at the interfaces. Usually, thick layer of polyelectrolyte is preferred for printing.

Figure 18: ELDCs formation.

P(VPA-AA)

P3HT DrainSource

SiO2

Si

Helmholtz layer

Diffusive layer

Ti

Figure 18: Concept of EDLCs in OFET by using polyanionic polyelectrolyte.

In reality, the channel of OFET where EDLC formed is in the range of few ångströms showed in Figure 19 (top view) with length and width equal to 84 µm and 202 µm for complete FET.

202 µm

G

EDLC

D

S84 µm

Figure 19: Shows the three electrodes with the channel of OFET where EDLC is formed in the range of

few angstroms (top view).

(3) Organic semiconductors are also referred as active layer. Organic semiconductors were first discovered in 1948 [16]. However, these materials remain confidential until the late 1980’s, with the emergence of modern OLED and organic photovoltaic cells. In an inorganic device, the active semiconductor layer is generally highly doped Si or combinations of group III-IV elements. In these materials, the applied gate voltage causes an accumulation of minority carriers at the dielectric interface causing existence of inversion regime whereas in an organic transistor, the active layer is comprised of a thin film of highly conjugated small molecules or polymers such as p-channel pentacene and P3HT or n-channel benzobisimidazobenzophenaathroline (BBL). In contrast to inorganic materials, organic pass current by majority carriers (holes in p-type device and as electrons in n-type device) causing the formation of

20

accumulation regime. This is due to the nature of charge transport in each of these semiconductors. In well-ordered inorganic, e.g. single crystal Si, the delocalization of electrons over equivalent sites leads to a band-type mode of transport, with charge carriers moving through a continuum of energy levels in the solid. In less-ordered organic materials, the proposed mechanism is hopping between discrete, localized states of individual molecules. The presence of impurities or inconsistencies in structure may result in ‘traps’ that alter the relative energy levels and inhibit the flow of charge carriers.

There are three ways that causes the doping of the semiconductor layer: • Due to the charge injection (polarons) from source/drain electrodes. • Due to the presence of impurities in the semiconductor layer resulting in the chemical doping. • Due to optical excitation. Thus, hole densities in P3HT are achieved using capacitive coupling between the polyelectrolyte gate insulator and P3HT (i.e. field effect) and not via chemical or electrochemical doping.

6. Specific materials

In this section, following materials are described: • P3HT • P(VPA-AA) • PEDOT:PSS • Polyaniline 6.1 Poly(3-hexylthiophene)

One of the first solution-processable organic semiconductors used for FETs was an intrinsic material, namely a poly(3-hexylthiophene) (P3HT) [17, 18]. The structure of P3HT is shown in Figure 20. It is widely used as a hole-transporting material in OFETs. P3HT can have 3-alkyl substituents incorporated into the polymer in three types of arrangements: head-to-tail (HT), tail-to-tail (TT) and head-to-head (HH). If P3HT consists of both (HH-HT) 3-alkylthiophene, it is called as regiorandom. However, regioregular P3HT can have only one type of arrangement, either (HT-HT) or (HH-TT). High field-effect mobilities (0.045 cm² V-1 s-1 in the accumulation mode) can be achieved using a solution cast regioregular P3HT [19]. This is due to the fact that, it self-orients into a well-ordered lamellar structure with an edge-on orientation of the thiophene rings relative to the substrate. Spin-coated films of regioregular P3HT are also well ordered, but the lamellae adopt different orientations depending on the degree of regioregularity.

21

Highly regioregular P3HT (greater than 91% head-to-tail linkages) forms lamellae with an edge-on orientation (π – π stacking direction in the plane of the substrate) when spun from chloroform. Thus, in addition to degree of order of the polymer film, the orientation of the π – π stacking direction relative to the substrate has a large influence on field-effect mobility. The P3HT used in this work was provided by a company called as Sigma-Aldrich and it contained ≥ 98.5% of HT.

S n

Figure 20: Chemical structure of P3HT. 6.2 Polyanionic electrolyte In this work, polyanionic electrolyte consisting of mobile protons is used. It means, when a negative gate voltage is applied, polyanionic electrolyte provides sufficient mobile protons that are attracted towards the negative voltage of gate electrode and also immobile anions that remain near the positively-doped conjugated polymer to form EDLCs, shown in Figure 21.

Ti Gate

P3HTAu S Au D

PV(PA-AA)

Figure 21: Depletion of mobile protons from polyanionic electrolyte near Ti gate and immobile anions near doped P3HT layer is shown.

The polyanionic electrolyte used here is a random copolymer of polyvinylphosphonic acid and acrylic acid P(VPA-AA). The chemical structure of P(VPA-AA) protonated (left) and deprotonated (right) that occurs near the P3HT channel when negative gate potential is applied, shown in Figure 22.

22

P OH

O

OHO OH

n m n m

P

-OHO

OO OH

Figure 22: Chemical structure of P(VPA-AA).

Protonated (left) and deprotonated (right) that occurs near P3HT. Other examples of polyanions are poly(vinylsulfate) and poly(4-styrene-sulfonate) and some other applications [20] of polyanions are: (1) As storage depots for proteins. (2) As molecular chaperones. (3) To exhibit potent antiviral activity in vitro and may also be used as future therapeutic agents to fight against HIV and other virus diseases. 6.3 PEDOT:PSS The conducting polymer poly(3, 4-ethylenedioxythiophene) (PEDOT) [21] has become an important part in plastic electronics in the form of a complex with polystyrene sulfonic acid (PSS) [22], shown in Figure 23.

Figure 23: Chemical structure of PEDOT:PSS.

Pedot is positively doped and sulfonate anionic groups of PSS are counter ions to balance doping charges.

Hto gate+ +

O O

+S

O O

S

SO3H SO3- SO3H SO3H SO3H SO3- SO3H

O O

S

O O

S+

O O

S

O O

S

O O

S

23

This work uses conducting polymer PEDOT:PSS to simulate the gate electrode in the OFET (later described in chapter 8.3). This can be prepared as a water-based colloidal suspension, which forms high-quality conducting films. PEDOT:PSS can be thought as a weakly miscible polymer blend of free PSS and single-chain complexes of PEDOT:PSS. PEDOT is one of the best-known conjugated polymers because of its excellent conductivity (1000 S cm-1) [23], electrochromic properties and processability. It is prepared with oxidative chemical or electrochemical polymerization methods. PEDOT was initially found to be insoluble polymer and the problem was solved by using a water dispersible polyelectrolyte PSS, which acts as a charge-balancing counterion during polymerization. This yields PEDOT:PSS, with good film forming properties such as high electrical conductivity, high transmission of visible light and excellent chemical stability. PEDOT:PSS and its derivatives can be use in a wide variety of applications and new patterning techniques, combined with improved electrical conductivity of PEDOT:PSS by secondary dopant diethylene glycol (DEG) [24] (increased by 2-3 orders of magnitude) which now enable the design of all-organic flexible devices with example PEDOT:PSS as transparent electrodes in transistors and PEDOT:PSS based electrochemical logic circuits. Additionally, other components (solvents, surfactants) are added to modify the conductivity and/or tune the viscosity and wetting properties to suit example an inkjet printing properties. Even if the mixing of the blend components is homogeneous (same nature or uniform) in the dispersion, once a thin film is made through a particular coating technique, there will be substantial reorganization both in the bulk of the film, at the vapor and at the substrate interfaces. Foremost applications are of vital importance to know the resulting films at the interfaces, as this will influence contacting, wetting and the charge-injection properties. 6.4 Polyaniline

Another conducting polymer used in this work simulating the gate electrode in the OFET is Polyaniline (PANI) [25] with the solvent system as Panipol T i.e. PANI in toluene containing solvent and doped PANI with the concentration range between 1-10%. It comes in a family of conjugated polymers and has properties similar to metals. It was discovered as “aniline black” in an organic form as a part of melanin, a type of organic polymer in 1934. It can conduct across a wide range, from non-conductive insulator to highly conductive for electrical purposes. Like any other polymers, it is highly flexible and it exists in a variety of forms that differ in chemical and physical properties but the most common one is a green protonated emeraldine salt (ES) that has a conductivity of 1

S cm-1, many orders of magnitude higher than that of conjugated polymer (< 10-9 S cm-1) but lower than typical metals (> 104 S cm-1). It also has several non-conductive oxidation states. The most stable of those is emeraldine base (EB), having equal amounts of reduced and oxidation repeating units, shown in Figure 24.

24

NH

NH

NH

NH

A A+ +

n

Emeraldine salts (ES) +2HA

NH

NH

NH

NH

A A+ +

Emeraldine base (EB)

n

+2e, +2H*

NH

NH

NH

NH

A A+ +

n

Leucoemeraldine (ES)

Figure 24: Several oxidation states of PANI.

The fully oxidized form is pernigraniline and fully reduced form is leucoemeraldine. Doping Emeraldine base (EB) with acid (dopant) results in a conductive Emeraldine salts (ES).

The changes in physicochemical properties of PANI occurring in the response to the various external stimuli are used in various applications [26] for e.g. (1) Organic electrodes (2) Sensors (3) Actuators Other uses are based on the combination of electrical properties typical of semiconductors with material parameters characteristic of polymers, like in the development of (1) Plastic microelectronics (2) Electrochromic devices (3) Smart fabrics

25

7) Methods This section describes the methods used and also the device used for electrical characterization of the device. All electrical measurements have been performed in a cleanroom environment with a relative humidity of approximately 40%. 7.1 Spin coating Spin coating is the most popular way of direct solution deposition. In this case, it was used for depositing polymers such as regioregular P3HT and also for polyelectrolyes. A large area spin coater is shown in Figure 25. An excess amount of polymer solution is placed onto the center of the substrate. The substrate is then rotated at high speed (typically around 3000 rpm) in order to spread the fluid by centrifugal force. Rotation is continued for some time, with fluid being spun off the edges of the substrate, until the desired film thickness is achieved. Final film thickness and other properties will depend on the nature of the resin (viscosity, drying rate, percent solids, surface tension, etc.) and the parameters chosen for the spin process. Note in this work P3HT is spin coated with the help of spin coater Solitec and P(VPA-AA) is spin coated with the help of Laurell WS-400A-8NPP.

Figure 25: A large area Spin Coater [6].

7.2 Ellipsometer In this work, ellipsometer was used for measuring refractive index and thickness of films or layers of the device. The principle of operation is illustrated in Figure 26. It works by shining a well-defined source of light, typically helium/neon laser, on a material and capturing the reflection. The ellipsometer beam first goes through a polarizer and then through a quarter wave plate, which provide a state of polarization by varying the angle of polarizer. The beam is then bounced off the material under study and focused on the analyzer-detector system. The operator changes the angle of polarizer and analyzer until a minimal signal is detected. The analysis follows Snell’s law: when a beam of light strikes a material some will reflect immediately and some will pass through the far side of the material before reflecting. By measuring the difference between two reflections, the thickness of the device can be determined. The reflected light also undergoes a change in

26

polarization; this change can be used to calculate the refractive index and absorption coefficient.

Other applications include: (1) Identification of materials and thin layers. (2) Characterization of surfaces. (3) In biological sciences etc. Some of its advantages are: (1) Can be used to measure layers as thin as 1 nm up to layers, which are several microns thick. (2) Highly accurate and reproducible. (3) Non-destructive; its process does not affect a material. (4) Not as susceptible to scatter, lamp or purge fluctuations. (5) Provides value at each wavelength.

Figure 26: An ellipsometer.

The ellipsometer works on the principle of shining a light on a material and capturing the reflection [7].

7.3 Electrical characterization This device was electrically characterized by using a parameter analyzer (PA)-HP4155B, shown in Figure 27. In this work, it was used for the measurement of: • I-V curve of a simple two terminal device. • IDS-VDS-VG graphs for OFETs. • Switching characteristics.

It contains four probes that can serve as voltage source, current source, voltage monitor and current monitor that can be programmed by a menu driven user interface. It can automatically extract process parameters without manually manipulating screen markers and can evaluate materials with measurements down to 1 fA and 0.2 µV.

27

Measurement data collected during the I-V measurements was saved as text files (.txt) and displayed as IDS versus voltage graphs, by the measurement program. When the electrical measurements were performed, the collected data from OFET were analyzed in Origin v.7.

Figure 27: An Agilent 4156C SPA and a Hewlett Packard 4192A LF impedance analyzer [8]. 8. Results and discussion

This part of the thesis work is divided into two main sections: • First section focuses on dual-gate organic field-effect transistor (DG-OFET). • Second section focuses on various conducting polymer gate electrode for the EDLC-

OFETs. 8.1 DG-OFET This section is reported in the following manner: • Fabrication. • Electrical characterization. 8.1.1 Fabrication Here, we build a DG-OFET sketched in Figure 28. A heavily doped silicon wafer, 0.5 mm thick, was used as a bottom gate electrode and substrate for the top gated transistor. Si used in this case is N doped with dopant antimony (Sb) and has a resistivity of 0.01-002 Ω cm. The silicon wafer was thermally oxidized (i.e. high temperature with no presence of water) to form a 200 nm thick uniform insulating layer of SiO2. To contact electrically the Si gate, this SiO2 is locally removed by scratching the wafer far away from the device. Next, Au is patterned by photolithography to form the source and drain electrodes (channel length L = 20 µm and width W = 2000 µm). The organic semiconductor P3HT, dissolved in chloroform (10 mg/ml) is spin coated on the patterned

28

substrate to obtain a, 10-20 nm thick layer. After this step, the bottom FET is finished. The next step is to spin coat the proton conducting insulator layer P(VPA-AA) (50-60 nm thick) from a solution containing a ratio of n-proponal and DI (nPA:DI) = 4:1 for promoting wetting on the P3HT surface. The device structure is then placed in vacuum to deposit Titanium (Ti) top electrode through a shadow mask (90 nm thick). One thing to note here is that, all electrodes used here have high work functions.

60 nm

0.5 mm

50-60 nm

10-20 nm

200 nm

Gate1 (Ti) P(VPA-AA)

P3HT Drain Source

SiO2

Gate 2 (Si)

90 nm

Top channel

Bottom channel

Figure 28: Schematic cross-section view of a dual-gate OFET with top and bottom FET.

Top channel is formed at the interface between P(VPA-AA) and P3HT when negative top gate (-VG1) is applied and bottom channel is formed due to the presence of hole accumulation layer when negative bottom

gate (-VG2) is applied. 8.1.2 Electrical characterization All measurements described in this section are made on the above device, a typical EDLC-OFET. As mentioned above (refer chapter 7.3, page 27), the electrical characterizations of the fabricated FET were measured with parameter analyzer HP4155B in the ambient atmosphere at room temperature. Using the four-probe method, with two probes touching source (grounded) and drain electrodes and other two probes touching the two gates, measurements were carried out, shown in Figure 29.

29

S

D G1

Figure 29: Measurement being carried out on DG-OFET (top view).

Shows two probes touching source and drain electrodes, while the third probe is touching the top Ti gate

electrode. The fourth probe touching the bottom Si gate electrode is not shown here. Following graphs are described in this section: • Transfer characteristics. • ION/IOFF vs VG2. • VG2 vs Vth. • Switching characteristics. 8.1.2.1 Transfer characteristics The goal with this DG-OFET is to control the current between drain and source (ID) via applying a potential to one or the other gate electrode (top gate VG1 or bottom gate VG2). Usually, the OFET operates in the accumulation mode with the negative bias on the drain and the gate electrodes with the source electrode grounded. The negative bias will enlarge the conduction channel due to the formation of a hole accumulation layer. Increasing the negative gate bias can increase the conductivity of the channel between drain and the source. We have tried to open the bottom channel by applying VD = VG2 = -100 V, but the top electrode were destroyed systematically with the top Ti electrode melted. Hence, in the rest of this section, we consider only small VD = -1 V and see the influence of the two gate potentials on ID. The transfer characteristics are obtained by plotting VG1 versus ID at saturation (VD = -1 V) (left axis) and (ID)1/2 vs VG1 (right axis). When no potential is applied to the bottom gate (VG2 = 0 V), the top transistor channel is opened when the top gate (VG1) is negatively biased. A threshold voltage of Vth = -0.318 V and field effect mobility (µFET) is ~ 0.0030 cm² V-1 s-1 can be estimated from those curves. Those results demonstrate that we are able to manufacture the EDLC-OFET properly.

30

Before investigating the effect of the VG2 on the transfer characteristics, we try to predict the drain current that will be measured from the transistor equations. Note that the area capacitance Ci of the polyelectrolyte P(VPA-AA) defining the top channel of DG-OFET is 20 µFcm-2 [15]. The capacitance per unit area of the silicon oxide layer (Cd) for bottom channel of DG-OFET can be calculated by using equation 4.1, giving Cd = 17 nFcm-2

(calculated for ε0 = 8.854 * 10-12 Fm-1, ε =3.9 and d = 200 nm) which is quite low compare to the value of Ci. The total current (ID) can be calculated by adding ID1

satand ID2lin. The part of the drain

current that comes from the bottom channel using VG2= -100V but VD = -1V is called ID2

lin since it is in the linear regime of the bottom channel. ID2lin can be calculated by

using equation 2.2, giving ID2lin = -442 nA (calculated for Vth = 0V, L = 20 µm, W =

2000 µm, µFET = 0.0026 cm² V-1 s-1, Cd = 17 nFcm-2, at VG2 = -100 V and VD = -1 V). The contribution of the drain current from the top channel in the saturation regime (ID1

sat) is estimated to be -1.4 µA. Hence, one realize that the main contribution from the drain current is indeed from the top channel using the polyelectrolyte insulator, while the bottom channel is barely open for those voltages. This large difference in current is due to the large discrepancy in capacitance (Ci= ~ 1000 Cd). We now investigate the effect of the bottom gate potential on the transfer characteristics of the EDLC-OFETs by varying the VG2 from 0 to ±100 V as shown in Figures 30 and 31.

0.0 -0.2 -0.4 -0.6 -0.8 -1.0

1E-8

1E-7

1E-6

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

-I D (A

)

VG1 (V)

Vth= -0.268 V

(-I D

)1/2 (1

0-3 A

1/2 )

VG2= 0 VVG2= 100 V

VG2= 0 V

VG2= 100 V

Figure 30: Transfer curves for VG2 = 0 V and VG2 = +100V.

VG1 vs ID at saturation (VD = -1 V) (left axis) and VG1 vs (ID) 1/2 (right axis).

31

0.0 -0.2 -0.4 -0.6 -0.8 -1.0

1E-8

1E-7

1E-6

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

-I D (A

)

VG1 (V)

VG2= -100 VVG2= 0 V

VG2= 0 VVG2= -100 V

Vth= -0.273 V

(-I D

)1/2 (1

0-3 A

1/2 )

Figure 31: Transfer curves for VG2 = 0 V and VG2 = -100V.

VG1 vs ID at saturation (VD = -1 V) (left axis) and VG1 vs (ID)1/2 (right axis).

When the top channel is closed (VG1 = 0 V) and the bottom gate is positively biased (Figure 30), the ID is almost constant for VG2 from 0 V to +100 V. This is understandable and could be because of the reason, that it is hard to inject electrons from Au into P3HT layer since Au has high work function. As calculated previously, keeping VG1=0V and decreasing the potential of the bottom gate (VG2) towards negative values should slightly open the bottom channel and if the OFET is not injection limited, one expects to measure an increase of current ID2

lin by -0.4 µA. As seen in figure 31, this is not the case: a much smaller current increase is measured (-0.004 µA) indicating that hole injection could be a problem for the bottom channel.

32

-100 -80 -60 -40 -20 0 20 40 60 80 100

0,01

0,1

1

I D (μ

A)

VG2

ION

IOFF

Figure 32: VG2 vs ID (log) for the ON state (VG1 = -1 V) and the OFF state (VG1 = 0 V).

Now, we consider that the top gate is negatively biased (VG1= -1V) such that the top channel opens and see the influence of the bottom gate potential on the drain current ION (Figure 32). This characteristic of the bottom gate shows its heavy dependency on the top gate negative potential while the drain current varies less for positively biased bottom gate. The behavior of ION can be explained better by looking at a zoom-up picture shown in Figure 33.

-100 -80 -60 -40 -20 0 20 40 60 80 100

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

I D (μ

A)

VG2 (V)

ION

Figure 33: Response in ON state (VG1=-1V) when VG2 is varied from –100 V to +100 V.

33

This evolution of the drain current and the discrepancy between negative and positive VG2 is tentatively explained as followed: At VG1 = -1 V and for negative potential of VG2 the bottom channel starts to open and an increase of ION is observed by -0.47 µA (from -1.56 µA at VG2= 0 V to -2.03 µA at VG2= -100 V), identical to theoretical value of ID2

lin. Because VG1= -1 V, the top channel is open, which lead to the injection of holes into P3HT to form the top channel at P3HT/P(VPA-AA) interface (refer Figure 28). While this process happens, there is a possibility that some of the holes start to accumulate at the P3HT/SiO2 interface because of the negative bias applied to the bottom gate. This leads to the formation of bottom channel slightly open (that was prevented to be opened if VG1= 0 V and VG2= -100 V because of lack of hole injection) and causes increase in ION. The plot plotted for positive potential of VG2 is not explained; ideally this should be a straight line from 0 to +100 V. It is difficult to interpret the reason for this kind of behavior. By linearly extrapolating the curve (ID) 1/2 vs VG1 to the VG1 axis (Figures 30, 31), Vth obtained are -0.268 V for VG2 = +100 V and -0.273 V for VG2= -100 V. By the definition of Vth (refer section 2.3), these values clearly suggest that it takes less positive voltage (-0.268 V) of VG2 to open the channel compare to its negative voltage (-0.273 V). The large value of ID1

sat (i.e. ID1sat = -1.4 µA from the above graphs) obtained for low

operation voltage (VG1 = -1 V) for both ± VG2 reflects the large capacitance per unit area (Ci) of P(VPA-AA) [c1]. From the slope of the drain current as a function of the gate voltage shown in the transfer characteristics (Figs 30, 31), field-effect mobilities (µFET) were extracted by using equation (2.3) with reference to ±VG2. For VG1 = -1 V and VG2 = 100 V, µFET is ~ 0.0026 cm² V-1 s-1 (calculated for Vth = -0.268 V, ID1

sat = -1.4µA, Ci = 20 µFcm-2, L = 20 µm, W = 2000 µm at VG1 = -1 V and VD = -1 V) and for - VG2, µFET is ~ 0.0026 cm² V-1 s-1

(calculated for Vth = -0.273 V, ID1sat = -1.4 µA, Ci = 20µFcm-2, L = 20 µm, W = 2000 µm

at VG1 = -1 V and VD = -1 V). The ION is defined for VG1 = -1 V and the IOFF for VG1 = 0 V. The ION/IOFF ratios for both VG2 = +100 V and –100 V were about 150, which is quite low, but can be improved further by optimizing the P3HT layer.

34

8.1.2.2 ION/IOFF vs VG2 The corresponding graph is obtained by plotting VG2 from ± (0 to 100 V) on the X-axis versus their corresponding ION/IOFF ratio on the Y-axis, shown in Figure 34.

-100 -50 0 50 100

150

200

250

300

350

400

I ON/I O

FF

VG2 (V)

Figure 34: VG2 = +100 V and = -100 V vs ION/IOFF. This Figure is similar to the one plotted in Figure 33, but in this case it is with respect to ION/IOFF ratio. When VG2 operates in the positive mode, the ION/IOFF ratio = ~ 175 far lower compare to VG2 operating in the negative mode with ION/IOFF ratio = ~ 270. This is understanble and because of the high ION of VG2 operating in the negative mode, previously discussed.

35

8.1.2.3 VG2 vs Vth The corresponding graph is obtained by plotting VG2 from ± (0 to 100 V) on the X-axis versus the corresponding Vth on the Y-axis, shown in Figure 35.

-100 -50 0 50 1000.16

0.18

0.20

0.22

0.24

0.26

0.28

-Vth

(V)

-VG2 (V)

Figure 35: Shows VG2 vs -Vth. The above graph shows the effect of VG2 on the Vth of VG1. From the above graph, the values obtained for VG2 at ±100 are quite small with a difference of 0.03 V between them, which clearly suggests that there is very small effect of VG2. This could be due to the fact that the ID1

sat (-1.4 µA) obtained from the upper channel is greater than the ID2lin

(-0.4 µA) obtained from the lower channel and thus dominating the DG-OFET ID characteristics leaving behind a little room for ID2

sat to play a significant role. 8.1.2.4 Switching characteristics In addition to the above characteristics, the time response of the OFET is of great importance. Transient curve shows how fast the drain current of the OFET rise and fall (switch-on and switch-off time) by the application of square shape VG1 pulse at the gate potential. Transient measurements were performed by applying a square shaped pulse from 0 V to –1 V and vice-versa to VG1 while the drain electrode was held constant at a potential of –1 V, shown in Figure 36. The corresponding graphs show the chronoamperometric response in ID for various values of VG2 (0 V, 100 V and –100 V). This is plotted time (s) on the X-axis versus ID on the Y-axis.

36

0.0 0.2 0.4 0.6 0.80.0

-0.2

-0.4

-0.6

-0.8

-1.0

-1.2

-1.4

I D (μ

A)

Time (s)

VG2 = 0 V (1st time) VG2 = 100 V VG2 = -100 V

0

-1

VG1

Time (sec)

Figure 36: Switching characteristics of DG-OFET.

Plot shows response in ID when VG2 pulses of 0 V, 100 V and –100 V are applied. Square shape in ID

(down) is due to the square shape of applied VG1 (up) when varied from 0 to –1 V and vice-versa.

37

The behavior in ID can be explained by looking at a zoom-up picture shown in Figure 37.

0.398 0.399 0.400 0.401

0.0

-0.4

-0.8

-1.2

I D

(μA

)

Time (s)

VG2 = 0 V VG2 = 100 V VG2 = -100 V

Figure 37: The close up picture showing the response in ID when VG2 pulses of 0 V, 100 V and –100 V are

applied.

The above graphs show the rise and fall of ID. The zoom on the fall of ID reveals that the OFET switches off in less than 0.3 ms. All the plots obtained for applied voltages of VG2 are identical to each other and indicates that the response of the top channel remains unaffected irrespective of the applied bottom gate potential. The rise in ID is slower (60% of ID in 0.2ms) because of the time required to form the top channel over the complete length of the channel. The fast fall in ID is because of the removing of the top channel when VG1 is set to 0V.

38

8.2 Conducting polymer gate electrode As mentioned previously (refer section 1), this thesis work started with attempts to manufacture a conducting polymer gate electrode for the EDLC-OFETs. This is a first step towards printing the EDLC-OFETs, since this would demonstrate the possibility to print a plastic gate electrode. This section describes those attempts in detail together with their reasons of failure. The most challenging task to print the EDLC-OFET is to deposit the conducting polymer gate electrode from solution and to avoid dissolution of the polyelectrolyte and organic semiconductor layers. Hence, as a first approach, we manufactured two electrode-devices simulating part of the OFET: a bottom gold electrode simulating the drain electrode in the OFET and a top conducting polymer electrode simulating the gate electrode in the OFET. Those two electrodes sandwiched a bilayer composed of the organic semiconductor and the polyelectrolyte layers. In this kind of devices, electrical measurements are carried out by probing these two electrodes and instead of conducting channel, conducting path term is used. Note that the thickness of the layers and the dimensions of electrodes are same as DG-OFET described previously (refer section 8.1). • PEDOT:PSS gated device. • PANI gated device. • Laminated OFET. 8.2.1 PEDOT:PSS gated device In the PEDOT:PSS gated device, a silicon wafer is used as the substrate followed by the thermal oxidation to form an insulating SiO2 layer. Au was patterned on that substrate to form the single bottom electrode. After this, P3HT was spin-coated, followed by the spin coating of a top proton conducting insulator layer P(VPA-AA) with the cross- linking agent poly(ethylene glycol)-diglycidy ether (PEG-DGE), shown in Figure 38 (a) and its top view in Figure 38 (b). To finalize this device, a drop of the conducting polymer PEDOT:PSS doped by a secondary dopant diethylene glycol was deposited as the top electrode in a two terminal device simulating part of the EDLC-OFETs. Far from the sandwiched structure, silver (Ag) is painted on PEDOT:PSS to improve the electrical contact. The reasons of using PEG-DGE are (1) to achieve good wetting and adhesion on the P3HT and (2) to cross-link the P(VPA-AA) and prevent the diffusion of the PEDOT:PSS water emulsion through the polyelectrolyte layer. Note P(VPA-AA) used here has 37% polymer concentration in deionized (DI) water.

39

G D

Ag

(a) (b)

Figure 38: (a) Schematic cross-section view of a PEDOT:PSS gated device and (b) Its top view showing

drain (D) and gate (G) electrodes with Ag on top of the gate electrode for the probing purpose.

PEDOT:PSS simulates the gate electrode, while the Au bottom gate electrode simulates the drain electrode in an EDLC-OFET.

Ideally, since the P(VPA-AA) layer is a good electrical insulator, only a vanishing small current should flow from the gold to PEDOT:PSS electrode when applying a potential difference. Unfortunately, the current-voltage (I-V) characteristic showed in Figure 39 displays a large leakage current of -50 µA at 1 V for a thick layer of P(VPA-AA) (50nm).

Figure 39: I-V characteristics of Au/P3HT/P(VPA-AA)/PEDOT:PSS device simulating a part of the EDLC-OFET.

PEDOT:PSS was doped with 10% of DEG.

PEDOT:PSSP(VPA-AA)

P3HT Drain

SiO2/Si

Ag Gate

0.0 -0.2 -0.4 -0.6 -0.8 -1.0

0

10

20

30

40

50

60

-I D (μ

A)

VG (V)

1 layers P(VPA-AA) 4 layer P(VPA-AA)

40

The reason of this kind of characteristic or failure is because of the short circuit in the P(VPA-AA) layer described below. Similar procedure was repeated with four multilayers of P(VPA-AA) and by varying the doping concentrations of DEG in PEDOT:PSS (i.e. 0%, 5%, 15% and 20%) but the results obtained were similar. With four cross-linked P(VPA-AA) layers, the current was reduced 50 times and reaches -1 µA at -1 V (Figure 39). We have not investigated thoroughly if the layers were properly cross-linked and the resulting thickness of the P(VPA-AA) film. Although this is a substantial improvement, the leakage current is still too large to consider this approach as reasonable for the EDLC-OFETs. The high leakage current or short-circuits between Au and PEDOT:PSS electrodes could be because of the following reasons: • Due to the presence of pinholes in P(VPA-AA) layer. The solution of PEDOT:PSS

can diffuse through these pinholes and dissolve the fragile P3HT layer to reach the Au electrode.

• Due to the poor cross-linking mixing of PEG-DGE in the P(VPA-AA) layer. The water emulsion of PEDOT:PSS can dissolve the P(VPA-AA) layer until it reaches the Au electrode. Forming a conducting path from the gate to the drain electrode and thus resulting in a leakage current.

8.2.2 PANI gated device From the previous experiment, we have learnt that it is difficult to prevent the dissolution of the P(VPA-AA) layer and the diffusion of PEDOT:PSS water emulsion through the hydroscopic P(VPA-AA) even though the P(VPA-AA) was cross-linked to form a tight polymer network. Hence, we had to use a conducting polymer using a solvent that cannot easily dissolve the P(VPA-AA) layer. PANI in its emeraldine form can be prepared in an emulsion using toluene (Panipol T). Toluene is a non-polar solvent that does not dissolve the P(VPA-AA) layer. PANI is used as the top electrode in a two terminal device simulating part of the EDLC-OFETs followed by the painting of Ag PANI to improve the electrical contact, shown in Figure 40 (a) and its top view in Figure 40 (b).

41

PANI

P(VPA-AA)

P3HT Drain

SiO2/Si

Ag Gate

G

D

Ag

(b) (b)

Figure 40: (a) Schematic cross-section view of a PANI based device and (b) Its top view showing

the G and D electrodes with Ag on top of the gate electrode for the probing purpose.

PANI simulates the gate electrode, while the Au bottom gate electrode simulates the drain electrode in an

EDLC-OFET.

The I-V characteristic is shown in Figure 41.

0.0 -0.2 -0.4 -0.6 -0.8 -1.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-I D (μ

A)

VG (V)

Figure 41: I-V characteristics of Au/P3HT/P(VPA-AA)/PANI device simulating a part of the EDLC-OFET.

42

This graph indicates that the value of leakage current lies in the range of µA. The reason of this kind of characteristic is again because of the short circuits in the P(VPA-AA) layer described below: • Due to the presence of pinholes in P(VPA-AA) layer. • The partial dissolution of P(VPA-AA) by toluene or the diffusion of PANI by

osmotic forces. Forming a conducting path from the gate to the drain electrodes and thus resulting in a leakage current.

8.2.3 Laminated OFET

The Laminated OFET is manufactured in two parts. The first part is composed of patterned Au source and drain electrodes on SiO2 substrate, coated by a layer of the organic semiconductor and a thick layer of polyelectrolyte layer (I). The second part of the OFET is composed of a conducting polymer, PEDOT:PSS layer onto a flexible polyester substrate (OrgaconTM EL-350, AGFA), which is coated by a polyelectrolyte layer (II). These two parts of the OFET are terminated together by a polyelectrolyte layer consisting of polyelectrolyte (I) and polyelectrolyte (II). The two parts are exposed to a vapor of water to swallow the polyelectrolyte layers followed by gluing them together by applying mechanical pressure. The partially dissolved polyelectrolyte (I) and polyelectrolyte (II) interface is then “welded”, laminated. The resulting structure for the OFET is Au (S and D)/semiconductor/polyelectrolyte/PEDOT:PSS (G), shown in Figure 42 (a). On the wafer substrate, two PEDOT:PSS gate stripes are deposited on two rows of source and drain electrodes. Ag is painted on top of them to ensure a good electrical contact. The PEDOT:PSS stripes partially cover the S and D electrodes, such that it is still possible to probe them. One PEDOT:PSS gate electrode (GA) is positioned above the source and drain electrodes. One can also try to use the other PEDOT:PSS stripe as gate electrode (GB), which is not positioned above the source and drain electrodes, shown in Figure 42 (b).

43

S D

GB

Figure 42: (a) Schematic cross-section view of the Laminated OFET (b) Its top view showing S and D

electrodes with two top gate electrodes (GA and GB) based on PEDOT coated flexible B

polyester with Ag on top of them for probing purpose.

The transfer characteristic is obtained by plotting in the similar fashion as the above one’s but this time for top two gates (VGA and VGB), shown in Figure 43. A modulation of ID is observed versus VG, thus indicating that a channel is really formed. The output characteristic is shown in Figure 44. The reason for the transistor to work with is likely the same as explained in the paper by L. Herlogsson et al. [Advanced Materials, 19, 97-101 (2007)].

GA

Ag

P(VPA-AA)

P3HT

Drain Source Si/SiO2

P(VPA-AA)

PEDOT:PSS (G) Laminated

44

0.0 -0.2 -0.4 -0.6 -0.8 -1.00.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

-I D (μ

A)

VG (V)

VGA (V) VGB (V)

Figure 43: Transfer characteristics of Laminated FET.

GA is above the S-D contacts and GA is at several mm from the S-D contacts. VGA and VGB represent the gate voltages of the two PEDOT polyester top gate electrodes varying form 0 to –1 V.

0.0 -0.2 -0.4 -0.6 -0.8 -1.0

0

1

2

3

4

5

I D (μ

A)

VD (V)

VGA(V) VGB(V)

VGA, VGB = 0 V

VGB = -1 V

VGA = -1 V

Figure 44: Output characteristics of the laminated transistors using the two different gates.

45

The poor performance of the OFET is likely due to the large leakage current between gate and drain electrodes. This could be because of the following reasons: • Due to the presence of pinholes in P(VPA-AA) layer. • Alternation of the polyelectrolyte layer by mechanical pressure during the lamination. Even though, the ION/IOFF ratio is poor (1.9), these results are encouraging and suggest that it might be possible to create low-voltage operating OFET by simple lamination techniques. 9. Conclusions/Future work In this part of the section, the overall conclusion and the work that is possible in the near future are explained. 9.1 Conclusions In this thesis work, a Dual gate OFET composed of a top FET and a bottom FET have been studied. In this device, two conduction channels were used, polyanionic proton conductor as a top insulator (polyelectrolyte) and SiO2 as a bottom insulator (dielectric) with the combination of two gate electrodes, Ti as a top gate electrode and Si as a bottom gate electrode. Due to the formation of high capacitance layer, top EDLC-OFET operates at a low voltage and improves the response time compared to electrochemical transistors. Also, the top channel was opened due to the quick formation of EDLC at the interfaces between gate/polyelectolyte and polyelectrolyte/P3HT. Although the bottom channel of the dual gate FET could not be operated alone, it appears that the bottom gate affects the total drain current of the dual-gated OFETs when the top channel is open. This is tentatively explained by the partial opening of the bottom channel facilitated by the holes coming from the top channel. The PEDOT:PSS and PANI electrodes in the two-electrode devices modeling part of the OFETs show high leakage currents. Hence PEDOT:PSS and PANI top gate in a complete OFET structure have not been considered. In contrast, the Laminated OFET shows a small modulation of drain current versus gate voltage. This suggests that it might be possible to create an all-plastic, low-voltage operating OFET using the lamination technique.

46

9.2 Future work In future, there is a possibility to improve the performance of DG-OFET. Both gates can be operated at low voltages independently to control the drain current, which may lead to twice the drain output current compare to a single gate OFET. The recent progress in printing source-drain gate electrodes makes possibility of printing such OFETs in the low-cost electronics by making use of much thicker layers of P(VPA-AA) and P3HT and by replacing the Au electrodes. Also, these devices could be used for memory storage and as an input to the ring oscillator. The above OFET can be used for printing by using much thicker of P(VPA-AA) and P3HT and replacing the Au electrodes with (1) Au electrode deposited with a liquid dispersion of Au nanoparticles or (2) PEDOT:PSS electrodes. Moreover, there is also a possibility of more improving the performance of conducting polymer gate electrodes, which are capable to form EDLC-OFETs. Another possibility is to work more with n-type EDLC-OFETs by using polycations as the polyelectrolyte layer and electrodes with low work functions such as calcium (Ca).

47

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