power delivery challenges for next generation high...

POWER DELIVERY

CHALLENGES FOR NEXT

GENERATION HIGH

PERFORMANCE SOCS

Stephen Kosonocky

AMD Senior Fellow

2 | Power Delivery Challenges for Next Generation High Performance SOCs | November 18, 2012 | PWRSOC 2012

AGENDA

High Performance APU Overview

– Voltage rail requirements

– IP components

– Fine grain power gating

– SVI2 interface

Package Power Delivery Constraints

– Physical constraints

– Potential issues for integrated voltage regulator (IVR) solutions

System AC Response

– Simplified power distribution model

– Variable frequency clocks

Minimal IVR efficiency requirement

Concluding remarks


HIGH PERFORMANCE APU “TRINITY”

Nominal

Voltage (V) TDC (A)

Max Load

Step (A)

VDD Variable 50 42

VDDNB Variable 29 37

VDDIO 1.5 3.2 -

VDDR 1.2 3.5 -

VDDP 1.2 4 -

VDDA 2.5 0.75 -

“Piledriver” Cores

– Quad CPU Core with total of 4MB L2

2nd-Gen AMD Radeon™ with DirectX® 11 support

– 384 Radeon™ Cores 2.0

HD Media Accelerator

– Accelerates and improves HD playback

– Accelerates media conversion

Enhanced Display Support

– 3 Simultaneous DisplayPort 1.2 or HDMI/DVI links

– Up to 4 display heads with display multi-streaming

6 voltage rails


“TRINITY” APU 32nm SOI, 246mm2, 1.303BN TRANSISTORS

DDR3 Controller DDR3 Controller Dual Channel DDR3

Memory Controller

AMD HD Media Accelerator

(UVD, AMD Accelerated

Video Converter)

AM

D H

D M

ed

ia

Ac

ce

lera

tor

AM

D H

D M

ed

ia

Ac

ce

lera

tor

L2

Cache

L2

Cache

L2

Cache

L2

Cache

GPU

GPU AMD Radeon™ GPU

Dual

Core

x86

Module

Dual

Core

x86

Module

Dual

Core

x86

Module

Dual

Core

x86

Module

Up to 4

“Piledriver”

Cores with total 4MB L2

Display

PLL

Display

PLL

DP/

HDMI®

DP/

HDMI®

HDMI, DisplayPort 1.2,

DVI controllers

Display Controller Display Controller

Unified Northbridge

PCIe® PCIe® PCIe® PCIe®

PCIe® PCIe®

PCI Express® I/O —

24 lanes, optional digital

display interfaces

Nort

hbridge

Sebastien Nussbaum, Hot Chips, Palo Alto, 2012

Multiple, mode configurable IP blocks

Provides performance on demand


“TRINITY” APU FINE-GRAIN POWER GATING ISLANDS

DDR3 Controller DDR3 Controller

AM

D H

D M

ed

ia

Ac

ce

lera

tor

AM

D H

D M

ed

ia

Ac

ce

lera

tor

L2

Cache

L2

Cache

L2

Cache

L2

Cache

GPU

GPU

GMC GMC

Dual

Core

x86

Module

Dual

Core

x86

Module

Dual

Core

x86

Module

Dual

Core

x86

Module

Display

PLL

Display

PLL DP ™ /

HDMI®

DP ™ /

HDMI®


UNB UNB

PCIe® PCIe® PCIe ® PCIe ®

PCIe ® PCIe ®


“TRINITY” FINE-GRAIN POWER GATING ISLANDS (2)


AM

D H

D M

ed

ia

Ac

ce

lera

tor

AM

D H

D M

ed

ia

Ac

ce

lera

tor

L2

Cache

L2

Cache

L2

Cache

L2

Cache

GPU

GPU

GMC GMC

Display

PLL

Display

PLL DP / HDMI DP / HDMI


UNB UNB

PCIe® PCIe® PCIe PCIe

PCIe PCIe

x86

Module 1

x86

Module 1

NB

GMC

SIMD

SIMD

SIMD

SIMD

SIMD

SIMD

Display Controller PCIe PHYs

DP /

HDMI®

UVD

VCE Independent

on-die power gated islands


“TRINITY” FINE-GRAIN POWER GATING ISLANDS (3)


AM

D H

D M

ed

ia

Ac

ce

lera

tor

AM

D H

D M

ed

ia

Ac

ce

lera

tor

L2

Cache

L2

Cache

L2

Cache

L2

Cache

GPU

GPU

GMC GMC

Display

PLL

Display

PLL DP / HDMI DP / HDMI


UNB UNB

PCIe® PCIe® PCIe PCIe

PCIe PCIe

x86

Module 1

x86

Module 1

UNB

GMC

SIMD array

SIMD array

SIMD array

SIMD array

SIMD array

SIMD array

Display Controller

PCIe ® PHYs DP /

HDMI®

UVD

VCE Independent

on-die power gated islands

Misc

Graphics

Additional power-down

region when all graphics

functions are shut down

Power gating is very

effective for configuring

the power rails for different

operating modes!

> 20X leakage current

reduction


PLATFORM POWER SAVINGS

AMD SERIAL VOLTAGE INTERFACE 2.0 (SVI2)

SVI is the interface which allows the system power

management unit to communicate information to and from voltage regulator

SVI2 enables quicker power state transitions

– Faster data transmission rates (33Mhz)

– Adds regulator response when transition is complete

– 80+% improvement in 500mV set point change latency over SVI1

Power efficiency features

– Multiple Power State Indicators sent to regulator

PSI0 – Current low enough that regulator can shed phases

PSI1 – Current low enough that regulator can use pulse skipping / diode emulation

– Load Line trim, offset

Ability to adjust DC offset and load line slope based on APU state

Regulator Efficiency vs. Load

Load Current (A)

Effic

ien

cy (

%)

0 30

0

85

1 phase regulation

2 phases regulation

SVI2 provides a fast power

management control path


CLIENT FM2 MOTHERBOARD

Example Client configuration

– IR3550 “PowIRstage” ICs from

International Rectifier

– 2X Copper PCB routes

– High current Ferrite Core

Chokes rated up to 60A

Minimal resistive losses from

VRM to APU are possible

Rs < 1mOhm typical (as seen in similar systems)

http://www.pcper.com/news/Motherboards/GIGABYTE-

Unveils-Exclusive-Ultra-Durable-5-Technology-

Computex-2012

http://www.irf.com

Today’s system power delivery

solutions are highly optimized

for low loss and efficiency

http://www.pcper.com/news/Motherboards/GIGABYTE-Unveils-Exclusive-Ultra-Durable-5-Technology-Computex-2012


















http://www.irf.com/


TYPICAL PACKAGE CONSTRUCTION

Package resources limitations

– Limited number of metal layers

– Competing resources

– z-height constraints

– Dielectric maximum voltage limits

Additional layers or size increase costs

Metal Resource Usage

VDD

VDDIO

VDDNB

VDDPCIE

VDDR

VDDA

Signals

VSS

Typical package cross-section

Package design is optimized for

power delivery and signal integrity


PACKAGE LEVEL DISCRETE SURFACE MOUNT INDUCTOR

Not as simple as it sounds

– Thermal heating of inductor

I2R heating in inductor can be

significant

Physical height should match

die

– Variations can cause problems

– Can have poor thermal

conduction to heat spreader

– Power loss of route

I2R loss in package trace

CV2f loss in package trace

Skin effect loss at high Fsw

Rin

Rout

tDIE tL

Thermal Conduction

Ctrace

Integrated voltage regulation

presents numerous challenges


PACKAGE SPACE CONSTRAINTS

Limited number of locations available for passive components

Keep-out regions add further limitations

Back-side cavity locations can provide some relief

– At the cost of inductive connections

Multi-chip packages

– Additional cost and complexity

Possible IVR components

– Controller IC

– Power FETs

– Inductors

– Capacitors Physical package size is a major constraint

for an integrated voltage regulator solution


IVR ROUTING CONSTRAINTS

Top level metal already very congested with I/O routing

New chip floorplans are required to optimize connections to discrete components

Package routes still have significant resistance

– Resistance in the single digit mOhm range for reasonable metal usage

Potential routes to discrete inductors

An IVR solution must compete

with signal routes and external

supplies


TYPICAL FREQUENCY AND TRANSIENT STEP RESPONSE

1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10

Su

pp

ly D

roo

p

Current excitation frequency (Hz)

1.05

1.10

1.15

1.20

1.25

1.30

1.35

0 25 50 75 100 125 150 175 200 225 250

Su

pp

ly v

olt

ag

e (

V)

time (ns)

1st droop 1st droop 2nd droop 2nd droop

1st droop 1st droop

2nd droop 2nd droop 3rd droop 3rd droop

On-die

de-caps

Package

de-caps Board

de-caps


TYPICAL MICROPROCESSOR POWER DELIVERY NETWORK

Different resonance frequencies (100s of MHz – KHz)

Sudden changes in load (idie(t)) cause undershoot/overshoot in supply

– De-cap added at different levels to suppress this supply noise

On-die de-cap typically < 100nF per voltage rail

– Not enough to satisfy the demands of a high performance processor

– Significantly more will require expensive MIM cap technology

IVR designs will require large filter capacitance

– Package mounted capacitors would have similar ESL as today’s VRM based designs

MB Package Die RMB

idie(t)

DVdd(t)

VRM CMB

RMB

LMB

LMB

Rpkg1 Lpkg1

Rpkg1 Lpkg1

Cpkg Cdie

Rdie

Rdie

Rpkg2

Rpkg2

Lpkg2

Lpkg2

Ldie

Ldie

Simplified power distribution lumped model

Transient response to noise would be very similar

between an IVR and non-IVR solution


NON-IVR SOLUTIONS FOR DI/DT NOISE

1st droop occurs very fast

– ~5ns from onset of current step

– Caused by the depletion of the low ESL on-die decoupling capacitance

Variable frequency clocks can provide high speed adaptation to di/dt events at low cost

– VFCG PLL dynamically reduces the CPU clock when supply goes below a threshold

– > 5% performance increase for same power supply

– > 10% power saving at same performance level

Alain Artieri: “Embedded Multicore in Mobile

Platforms”, presented at the Power/Performance

Optimization of Many-core Processor SoCs, ISSCC

Forum, San Francisco, Feb 2012.

Variable frequency

clock enabled

Variable frequency

clock disabled

Techniques like variable frequency

clocks can reduce the need for very

high speed regulator response


SINGLE PHASE POWER DELIVERY EXAMPLE

Today’s VRM efficiencies can be very high

– Does not include PWM controller power

– High quality power components

– Low DCR inductor

– Low loss PCB routes

Switching Frequencies

– 200KHz – 1MHz

Losses to board component

– I2R DCR loss

– I2R PCB route loss

Multiple phases can further reduce losses

78%

80%

82%

84%

86%

88%

90%

92%

94%

96%

0 10 20 30

Eff

icie

ncy

Load Current (A)

VRM

Component

+90% Efficiency across wide load

range typical today


SYSTEM CONSTRAINED POWER SENSITIVITY

TO VRM POWER EFFICIENCY

0.0%

0.5%

1.0%

1.5%

2.0%

2.5%

3.0%

3.5%

4.0%

4.5%

0

0.2

0.4

0.6

0.8

1

1.2

0 0.2 0.4 0.6 0.8 1

Fre

qu

en

cy D

eg

red

ati

on

No

rmalized

Fre

qu

en

cy

Normalized Power Envelope

FMAX 5% Lower Efficiency

Performance impact of power

delivery efficiency can be significant,

especially at low power points

Example Fmax vs. Power


HIGH CURRENT IVR REQUIREMENT

Break Even Requirement

– Assume Today’s VRM Efficiency > 90%

– 1st stage regulation efficiency needs to be very high to avoid excessive loss

Need enough package space to support components for all rails

– +2 High current rails, +4 low current rails

– Difficult to accommodate many high current multi-phase designs

VR

IVR1

IVR2

APU

IVR3 IVR4

IVR5 IVR6

12V

Fixed

Voltage

1st Stage

90%

92%

94%

96%

98%

100%

90% 95% 100%

IVR

Eff

icie

nc

y

1st Stage Regulator Efficiency

Minimum IVR Efficiency for 90% Total Efficiency

Potential IVR based system


CONCLUDING REMARKS

High performance SOC’s are integrating more and more IP blocks

– Additional voltage rails will open up more possibilities for advanced power management

Fine grain power gating has proven to be an effective solution for powering down unused IP blocks

– IVR solutions must compete with computational sprinting techniques

SVI2 provides fast power state transitions and power management control

– Phase shedding

– Pulse skipping

– Load line trimming

State-of-the-art external VRMs and good board design can provide a high efficiency power delivery solution

– Present solutions set a very high bar, integrated solutions need a high ROI

Package constraints limit number and placement of discrete components on package

– We don’t have unlimited space

Variable frequency clocks can provide a low cost solution to di/dt droops

– High speed regulator response is not a large motivation


CONCLUDING REMARKS (CONTINUED)

The three most important criteria for an integrated voltage

regulator solution:

1. Efficiency

2. Efficiency

3. Efficiency

At low cost


DISCLAIMER & ATTRIBUTION

The information presented in this document is for informational purposes only and may contain technical

inaccuracies, omissions and typographical errors.

The information contained herein is subject to change and may be rendered inaccurate for many reasons, including but not limited to

product and roadmap changes, component and motherboard version changes, new model and/or product releases, product differences

between differing manufacturers, software changes, BIOS flashes, firmware upgrades, or the like. There is no obligation to update or

otherwise correct or revise this information. However, we reserve the right to revise this information and to make changes from time to

time to the content hereof without obligation to notify any person of such revisions or changes.

NO REPRESENTATIONS OR WARRANTIES ARE MADE WITH RESPECT TO THE CONTENTS HEREOF AND NO RESPONSIBILITY

IS ASSUMED FOR ANY INACCURACIES, ERRORS OR OMISSIONS THAT MAY APPEAR IN THIS INFORMATION.

ALL IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE ARE EXPRESSLY

DISCLAIMED. IN NO EVENT WILL ANY LIABILITY TO ANY PERSON BE INCURRED FOR ANY DIRECT, INDIRECT, SPECIAL OR

OTHER CONSEQUENTIAL DAMAGES ARISING FROM THE USE OF ANY INFORMATION CONTAINED HEREIN, EVEN IF

EXPRESSLY ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

AMD, the AMD arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. All other names used in this

presentation are for informational purposes only and may be trademarks of their respective owners.

AMD, the AMD Arrow logo and combinations thereof are trademarks of Advanced Micro Devices, Inc. in the United States and/or other

jurisdictions. Other names used in this presentation are for identification purposes only and may be trademarks of their respective owners.

© 2012 Advanced Micro Devices, Inc. All rights reserved.

power delivery challenges for next generation high...

Documents