power delivery network analysis (rev. a) - ti. · pdf filepower delivery network analysis...

Application Report SWPA222A – November 2012

1

Power Delivery Network Analysis Erwan Petillon HW Systems Solutions

ABSTRACT

The purpose of the Application Note (APN) is to present the flow, the environment settings and TI requirements used to perform the analysis of critical power nets of a platform using an application processor. In complement to the APN, a package including all necessary data to perform a PDN analysis of the OMAP4430 Blaze processor board are attached (layout, stack-up, schematic….)

The Power Delivery Network (PDN) performance is measured by extracting of the Printed Circuit Board (PCB) 3 parameters, DC resistivity, capacitor loop inductance and target impedance decoupling.

The application note explained each parameter theoretically and detailed the environment, set-up for the parameters extraction and comparisons to TI recommendations. To conclude each parameter sections, PDN extraction results of the OMAP4430 Blaze processor board with some general layout recommendations are presented.

Document History Version Date Author Notes

1.0 August 2012 E. Petillon First release

A November 2012 E. Petillon Numerous typo corrections.

WARNING: EXPORT NOTICE Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws. This provision shall survive termination or expiration of this Agreement. According to our best knowledge of the state and end-use of this product or technology, and in compliance with the export control regulations of dual-use goods in force in the origin and exporting countries, this technology is classified as follows: US ECCN: 3E991 EU ECCN: EAR99 And may require export or re-export license for shipping it in compliance with the applicable regulations of certain countries.

SWPA222A

2 Power Delivery Network Analysis

Contents 1 Generals ........................................................................................................................................ 3 2 DC resistance ............................................................................................................................... 4 3 Capacitor Loop inductance ......................................................................................................... 7 4 Target impedance ....................................................................................................................... 10 5 OMAP4430 Blaze processor board PDN analysis. ................................................................... 13

Figures Figure 1: Power Delivery Network model ........................................................................................... 3 Figure 2: DC resistance ....................................................................................................................... 4 Figure 3: DC resistance extraction flow ............................................................................................. 5 Figure 4: VCORE1_OMAP_MPU OMAP4430 Blaze OMAP4430 processor board. ........................... 6 Figure 5: VCORE1_OMAP_MPU voltage mapping ............................................................................. 7 Figure 6: Loop inductance principle ................................................................................................... 8 Figure 7: Capacitors loop inductance extraction flow ...................................................................... 8 Figure 8: Capacitors Loop inductance on VCORE1_OMAP_MPU .................................................... 9 Figure 9: Target impedance extraction flow ..................................................................................... 10 Figure 10: VCORE1_OMAP_MPU OMAP4430 Blaze processor board ZTARGET response ......... 12 Figure 11: Different ZTARGET responses of VCORE2_OMAP_IVAUD net .................................... 13

Tables Table 1: OMAP4430 Blaze processor board stack-up ....................................................................... 4 Table 2: DC resistance OMAP4430 blaze processor board ............................................................... 6 Table 3: DC resistance OMAP4430 blaze processor board with GND return path included ........... 6 Table 5: DC resistivity OMAP4430 PDN requirements ...................................................................... 7 Table 6: Loop Inductance OMAP4430 PDN requirements ................................................................. 9 Table 7: Target Impedance OMAP4430 PDN requirements ............................................................. 11 Table 8: OMAP4430 Blaze processor board ZTARGET results ....................................................... 11

SWPA222A

Power Delivery Network Analysis 3

1 Generals PDN performances were not considered as major criteria in the early of the PCB designs. In today’s platform with lower voltage, higher current, smaller voltage noise margin, PDN performances should be estimated early in the PCB design and optimized to meet the device specification.

The objective of a PDN is to supply a clean and stable voltage to the device. However the PDN is not ideal due to the parasitic added by the elements constituting the power network. Figure 1 presents a break-down model of a complete PDN network from Voltage Resource Manager (VRM) to the Application Processor (AP).

Figure 1: Power Delivery Network model

This APN focuses on the analysis of the PCB and the decoupling capacitors strategy used.

To extract the PDN performances of the PCB layout, you will need: • Platform Schematic. • PCB Layout out. • PCB Stack-up with dielectric properties (Dk and Df), refer to Table 1. • S-parameters capacitors models from manufacturer. • Power Integrity (PI) tool.

PDN results for the OMAP4430 blaze processor board were extracted using nVolt from Nimbic.

Thickness Dielectric properties

In um In mils Dk Df

L1 5 0.197 prepreg 50 1.969 4.5 0.035 L2 35 1.378

SWPA222A


prepreg 50 1.969 4.5 0.035 L3 35 1.378 prepreg 60 2.362 4.5 0.035 L4 35 1.378 prepreg 140 5.512 4.5 0.035 L5 17 0.669 prepreg 304 11.969 4.5 0.035 L6 17 0.669 prepreg 140 5.512 4.5 0.035 L7 35 1.378 prepreg 60 2.362 4.5 0.035 L8 35 1.378

prepreg 50 1.969 4.5 0.035 L9 35 1.378 prepreg 50 1.969 4.5 0.035

L10 5 0.197

Total 1158 45.5905512

Table 1: OMAP4430 Blaze processor board stack-up

2 DC resistance DC resistance is determined by the geometry of the net, its material conductivity, refer to Figure 2.

Figure 2: DC resistance

Once DC resistance is determined, IR drop can be calculated with Ohm’s law.

𝐷𝐶 𝐼𝑅 𝑑𝑟𝑜𝑝 = 𝑅𝑑𝑐 . 𝐼

An IR drop of 0.5%-2.5% of the nominal voltage is tolerated depending on the total system-level margin allowed for proper device functionality and sense line position.

SWPA222A


TI specifies in the Data Manual (DM) a board DC resistance budget, from VRM to OMAP balls for critical power nets.

Due to the shape geometry complexity, vias and multilayer’s used during the net routing, it is difficult to calculate manually the DC resistance. Numerous Signal Integrity (SI) or Layout EDA tools extract the DC resistance.

To extract DC resistance, you will need: • Platform Schematic. • PCB Layout out. • PCB Stack-up. • DC resistance extracting tool.

Figure 3 describe the flow used by most of the tool to extract DC resistance. In TI PDN analysis, the lumped methodology is preferred; each power and GND pins of VRM and AP are grouped.

Figure 3: DC resistance extraction flow

SWPA222A


Figure 4: VCORE1_OMAP_MPU OMAP4430 Blaze OMAP4430 processor board.

Table 2 presents the DC resistivity analysis of VCORE1_OMAP_MPU, VCORE2_OMAP_IVAUD and VCORE2_OMAP_CORE nets.

Net Name Volt (v)

Max Current (A)

TI recommendations (mOhm)

Extracted resistance (mOhm)

Max Irdrop (mV)

VCORE1_OMAP_MPU 1.38 1.45 14 8.45 12.25 VCORE2_OMAP_IVAUD 1.26 0.7 29 13.80 9.66 VCORE3_OMAP_CORE 1.1 0.85 13.75 18.34 15.58

Table 2: DC resistance OMAP4430 blaze processor board

In this configuration, DC resistivity is measured between VRM and OMAP balls. GND return path (GND plane) is not included as its effect is minor as it is shown in Table 3.

Current

(Amps) Loop Resistance

(Ohms) OMAP balls

Voltage(Volts) V+ (Volts) V- (Volts)

VCORE1_OMAP_MPU 1.45 0.00860495 1.36729 1.36775 0.000459935 VCORE2_OMAP_IVAUD 0.7 0.0139813 1.24986 1.25032 0.000459935 VCORE3_OMAP_CORE 0.85 0.0185016 1.08394 1.0844 0.000459935

Table 3: DC resistance OMAP4430 blaze processor board with GND return path included

Other tool offers the possibility to map current and voltage distribution over the power nets and GND return path, refer to Figure 5.

SWPA222A


Figure 5: VCORE1_OMAP_MPU voltage mapping

Table 4 presents maximum DC resistivity of OMAP4430 for 1GHz and 1.2GHz operation.

PARAMETERS

PDN IMPEDANCE CHARACTERISTICS PCB RESISTANCE BETWEEN SPMS

and OMAP

MAXIMUM LOOP INDUCTANCE PER

CAPACITOR (WITHOUT ESL) (nH)

IMPEDANCE TARGET (mΩ)

FREQUENCY OF INTEREST (MHz)

VCORE3_OMAP_CORE

122 48 13.75 1 VCORE1_OMAP_MPU

1GHz 93 40 14 0.7 1.2GHz 71 28 10 0.7

VCORE2_OMAP_IVAUD 194 46 29 1

Table 4: DC resistivity OMAP4430 PDN requirements

General recommendations for minimizing DC resistivity: • Shorten the length of the power nets trace by optimizing VRM and AP placement but also

their balls positioning. • Widen the power nets trace. • Avoid discontinuity in power nets trace by inserting other signal nets or matrix of vias with

their associated anti-pads (Swiss cheese effect) within the power nets. • Avoid via starvation by determining maximum current carrying capacity and numbers of

transitional via.

3 Capacitor Loop inductance The loop inductance is a parameter quantifying the effectiveness of a decoupling capacitor. Figure 6 represents the different loop inductances added to the capacitor ESL.

mailto:[email protected]%20(0.725A%20transient)


SWPA222A


Figure 6: Loop inductance principle

Figure 7 shows a typical flow for capacitors Z-parameters extraction. Once Z-parameters is extracted, the loop inductance of a capacitor is determined by

𝐿𝑒𝑓𝑓 =𝐼𝑚𝑎𝑔𝑖𝑛𝑎𝑟𝑦 𝑍𝑝𝑜𝑤𝑒𝑟,𝑔𝑛𝑑 𝑝𝑎𝑑𝑠 𝑜𝑓 𝑐𝑎𝑝𝑠

2𝜋 ∗ 𝐹𝑟𝑒𝑞

Where Leff is the effective loop inductance, Zpower , gnd pads of caps represents the Z-response of the port defined across the power and ground pads of the corresponding capacitors,

Typically, capacitors loop inductance is determined at a frequency of 50 MHz.

Figure 7: Capacitors loop inductance extraction flow

SWPA222A


TI specifies in the Data Manual (DM) a maximum capacitor loop inductance, for example Table 5 refers to OMAP4430 PDN requirements. Following this requirement will help significantly to meet TI target impedance decoupling requirement, refer to section 4 for more details.

PARAMETERS


and OMAP





VCORE3_OMAP_CORE


1GHz 93 40 14 0.7 1.2GHz 71 28 10 0.7


Table 5: Loop Inductance OMAP4430 PDN requirements

To extract capacitors loop inductance, you will need: • Platform Schematic. • PCB Layout out. • PCB Stack-up. • Loop inductance extracting tool.

Figure 8 presents the loop inductance results of all decoupling capacitors on VCORE1_OMAP_MPU at 50 MHz. All capacitors loop inductances are below recommendations.

Figure 8: Capacitors Loop inductance on VCORE1_OMAP_MPU

It is also interesting to extract VRM loop inductance and compare it to DM specification.

General recommendations for minimizing capacitors loop inductance: • Keep the power and ground plane pair as close to the TOP and BOTTOM surfaces. • Placing power and ground plane pairs closer to the surface where the capacitor is

mounted. • Avoid discontinuity in power or GND planes to provide continuous return path for return

current.



SWPA222A


• Use via-in-pads for capacitors. • Place vias as close to AP balls. • Place decoupling capacitors closed to AP. • Select capacitors with small footprint to minimize ESL.

4 Target impedance To complete the PDN analysis, it is necessary to determine the target impedance of the overall power net. Target impedance extraction is achieved using the Frequency Domain Target Impedance Method (FDTIM ).and the objective is to maintain the target spectrum below the Z target value (Ztarget) from DC to Fmax.

The Ztarget value is determined by:

𝑍𝑡𝑎𝑟𝑔𝑒𝑡 =𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑅𝑎𝑖𝑙 ∗ % 𝑅𝑖𝑝𝑝𝑙𝑒

0.5 ∗ 𝐼𝑚𝑎𝑥 𝑡𝑟𝑎𝑛𝑠𝑖𝑒𝑛𝑡

FMAX is the point in frequency after which adding a reasonable number of decoupling capacitors does not bring down the power rail impedance |ZEFF| below the target impedance (ZTARGET ) due to the dominance of the parasitic planar spreading inductance and package inductances. Figure 9 presents a typical flow for a Target impedance extraction.

Figure 9: Target impedance extraction flow

TI specifies, in the DM, an impedance target (ZTARGET) and a frequency range (FMAX). Table 6 refers to OMAP4430 PDN requirements.

SWPA222A


PARAMETERS


and OMAP





VCORE3_OMAP_CORE


1GHz 93 40 14 0.7 1.2GHz 71 28 10 0.7


Table 6: Target Impedance OMAP4430 PDN requirements

To determine target impedance response, you will need: • Platform Schematic. • PCB Layout out. • PCB Stack-up. • S-parameters capacitors models from manufacturer. • Target impedance (S-parameters) extracting tool.

During the PDN analysis it is important to capture the decoupling frequency achieved for the required target impedance but also the target impedance achieved at the required decoupling frequency.

Table 7 resumes the target impedance results achieved on OMAP4430 Blaze processor board.

Figure 10 represents the complete target impedance response of the VCORE1_OMAP_MPU net on OMAP4430 blaze processor board.

Net Name

TI recommendations OMAP4430 Blaze processor board results

Value (mΩ)

Frequency (MHz)

At TI recommended

value (mΩ)

Reached frequency

(MHz)

At TI recommended

frequency (MHz)

Reached value (mΩ)

VCORE1_OMAP_MPU 93 40 93 49.2 40 75

VCORE2_OMAP_IVAUD 194 46 194 86 46 98

VCORE3_OMAP_CORE 122 48 122 48.4 48 122

Table 7: OMAP4430 Blaze processor board ZTARGET results



SWPA222A


Figure 10: VCORE1_OMAP_MPU OMAP4430 Blaze processor board ZTARGET response

Recommendations for improving target impedance response are similar to the recommendations to reduce the capacitors loop inductances. It is clear that reducing or removing capacitors with high loop inductance could help improving the ZTARGET response.

If resonant peak appears before the required decoupling frequency then the decoupling strategy should be modified, add or replace a capacitor by the appropriate value to remove or decrease the resonant peak.

Figure 11 represents various target impendence responses with different decoupling strategy, only bulks capacitors, only 100nF capacitors, no capacitors.

SWPA222A


Figure 11: Different ZTARGET responses of VCORE2_OMAP_IVAUD net

5 OMAP4430 Blaze processor board PDN analysis. A complete package to perform the PDN analysis of OMAP4430 Blaze processor board is attached to the application note. Use the Adobe paperclip icon to access the files below:

• OMAP4430 processor board Schematic (750-2165-001-SCH_REVB_PDN_only.pdf). • PCB Layout out (720-2165-002_RevA_PDN_only.brd) • PCB Stack-up with dielectric properties (Dk and Df) attached in the excel sheet. • S-parameters capacitors models used for target impedance extraction. • Excel sheet (TI-blaze4430_rev720-2165-002_results.xlsx) resuming the PDN results of

VCORE1_OMAP_MPU, VCORE2_OMAP_IVAUD and VCORE3_OMAP_CORE extracted using nVolt tool.

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2012, Texas Instruments Incorporated

http://www.ti.com/audio

http://www.ti.com/automotive

http://amplifier.ti.com

http://www.ti.com/communications

http://dataconverter.ti.com

http://www.ti.com/computers

http://www.dlp.com

http://www.ti.com/consumer-apps

http://dsp.ti.com

http://www.ti.com/energy

http://www.ti.com/clocks

http://www.ti.com/industrial

http://interface.ti.com

http://www.ti.com/medical

http://logic.ti.com

http://www.ti.com/security

http://power.ti.com

http://www.ti.com/space-avionics-defense

http://microcontroller.ti.com

http://www.ti.com/video

http://www.ti-rfid.com

http://www.ti.com/omap

http://e2e.ti.com

http://www.ti.com/wirelessconnectivity

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A ATitle Page

Table of ContentsPg# - Schematic Page Name -----------------------------------------------1 - Title Page2 - Buck/Boost Converters, Charger & Ref Clock Driver3 - Phoenix Input Power APM Sense4 - Phoenix Power Component5 - Phoenix Audio Component6 - OMAP4430 Symbol "A"7 - OMAP4430 Symbol "B"8 - OMAP4430 Symbol "C"9 - OMAP Auxilary Input Power APM Sense10 - OMAP Debug Interface11 - P11 Flash Memory, EEPROM Bd ID 12 - AV Switch & HDMI13 - Board-to-Board Connectors (North & West)14 - Board-to-Board Connectors (South & East)

Rev Date Author Notes

Functional Block Labels

NOTES LEGEND:

Schematic Page Titles

Circuit design notes

A 11/17/2010 OMAPDP Team New release - Improved HDMI routing, VDD1 routing, thermal, and small cleanup items

B 12/3/2010 OMAPDP Team Added DNI - C188, C207-C209, R102, R108

Size Document Number Rev

Date: Sheet of

Wireless Terminal Business UnitOMAP Development Platforms (OMAPDP)12500 TI BlvdDallas, TX 75243

Texas Instruments, Inc.

TI - Proprietary Information

Modified by:

PRELIMINARY documentscontain information on aproduct under developmentand is issued for evaluationpurposes only.Features characteristic dataand other information aresubject to change.

Under Non Disclosure Agreement

Do Not Copy

1

AOMAPDP Team

VOMAP4430 ES2.1 Processor Board ITitle Page

14

750-2165-001-SCHCustom

Friday, December 03, 2010


Date: Sheet of




Modified by:



Do Not Copy

1

AOMAPDP Team


14




Date: Sheet of




Modified by:



Do Not Copy

1

AOMAPDP Team


14



Z1

Bottom-Side CM S/N

0.50 X 0.25710-0027-001Z1

Bottom-Side CM S/N

0.50 X 0.25710-0027-001

1 2

Z2

750-2165-001-ASY REV A

0.50 X 0.25710-0026-001Z2

750-2165-001-ASY REV A

0.50 X 0.25710-0026-001

1 2

Z3

Top-Side CM S/N

0.50 X 0.25710-0027-001

SYMBOL = 0.50_X_0.25_CM_SN_LABEL_REVA_050307

Z3

Top-Side CM S/N

0.50 X 0.25710-0027-001

SYMBOL = 0.50_X_0.25_CM_SN_LABEL_REVA_050307

1 2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A APhoenix Power Management IC

BOOT3 = '1' -> Enable VAUX1 LDO to eMMC Core VoltageBOOT2 = '0' -> VAUX1 LDO default = 2.8VBOOT1 = '1' -> VMEM = 1.2V (S4b LPDDR2 used)BOOT0 = '0' -> High battery thresholds for VBATMIN

Controls

SMPS Power Inputs & Outputs

Battery Charger I/F

USB I/F

RTC Clock Ref

LDO Power Inputs

LDO Outputs

Backup Battery

Component ROOM = PMIC

OMAP4 Power Management

If used, GGAUGE_RESN & GGAUGE_RESP must be routed differentially

NOTE: VBAT (ball B13) is a sense line,and should be routed independently of VBAT for the remainder of the board.

Thermistor to be placed close to OMAP pin AH1

CLK32_PHO_AOCLK32_PHO_AUD

CLK32_PHO_G

PHO_BOOT0

PHO_BOOT1

PHO_BOOT2

PHO_BOOT3

PHO_CHRG_BOOTPHO_CHRG_CSIN

PHO_CHRG_CSOUT

PHO_CHRG_PMID

PHO_CHRG_SW

PHO_CHRG_VREF

PHO_OSC32K_CAP

PHO_PWMFORCE

PHO_PWR_IREFPHO_PWR_VBG

PHO_XTAL_32KIPHO_XTAL_32KO

V1V29_FDBK

V1V8_FDBK

V1V8_PMIC_VIO

V2V1_FDBK

V2V1_PMIC_VCXIO_VDAC

V2V1_PMIC_VCXIO_VDAC

VBAT_V1V29

VBAT_V1V8

VBAT_V2V1

VBAT_VCORE1

VBAT_VCORE2

VBAT_VCORE3

VBAT_VMEM

VCORE1_FDBK

VCORE2_FDBK

VCORE3_FDBK

VMEM_FDBK

VPMIC_V1V8

VPMIC_VANA

VPMIC_VRTC

VPMIC_VRTC

V_BKUP_PHO

V_CORE1_SW

V_CORE2_SW

V_CORE3_SW

V_V1v2_SW

V_V2v1_SW

V_VIO_SW

V_VMEM_SW

GPADC_VREF4

GPADC_IN4

VAC_PHOE

VBUS_USB

VBAT_PROC

VBAT_PROC

VBAT_PROC

H_SYS_PWRREQ7

USB_ID14

H_I2C1_SDA2,5,7,11

H_SRI2C_SDA7

H_I2C1_SCL2,5,7,11

H_SRI2C_SCL7

PHO_GG_RESP 14

BAT_REMOVAL7

DYNAMO_EN2

DYNAMO_STAT2

BATT_TS 14

USB_CHGEN7

BATT_ID 14

H_SIM_PWRCTRL6,13MMC1_CD14

H_SYS_NIRQ17

EXT_RPWRON14

PHO_REGEN12

H_SYS_NRESPWRON2,5,7,10H_SYS_NRESWARM2,7,10,11,13

SW_PWRON14PHO_GG_RESN 14

PHO_REGEN214

PHO_PWM114PHO_PWM214

GPADC_IN3 14AUD_ECI 5

H_SYS_PREQ2A14H_SYS_PREQ2B14H_SYS_PREQ2C14H_SYS_PREQ314

CHRG_LED_DRV14

PHO_SYSEN2,14

H_SYS_DRM_MSEC7

GPADC_IN5 14GPADC_IN6 14GPADC_VREF1 14GPADC_VREF4 14

GPADC_IN4 14

VBAT_PMIC_VMEM 3

VBAT_PMIC_V2V1 3

VBAT_PMIC_V1V29 3

VBAT_PMIC_VCORE3 3

VBAT_PMIC_V1V8 3

VBAT_PMIC_VCORE1 3

VBAT_PMIC_VCORE2 3

VCORE2_OMAP_IVAUD 8

VCORE3_OMAP_CORE 8

VPMIC_V1V8 2,5,7,8,9,11,12,14

VPMIC_V2V1 5

VPMIC_V1V29 8,9,14

VPMIC_VMEM 8

VBAT_PMIC_VANA3

VBAT_PMIC_VDD_BINS3

VPMIC_V1V82,5,7,8,9,11,12,14

CM_P_V1V8_PMIC_VIO14

CM_N_V1V8_PMIC_VIO14

VPMIC_V2V15

CM_P_V2V1_PMIC_VCXIO_VDAC14

CM_N_V2V1_PMIC_VCXIO_VDAC14

VPMIC_VUSB 9

VPMIC_VMMC 2

VPMIC_VDAC 2,9

VPMIC_VCXIO 9VPMIC_VUSIM2

VPMIC_VAUX111

VPMIC_VAUX212,14

VPMIC_VAUX314

VPMIC_OMAP_VPP_CUST 8

VBBO_PMIC2

VCORE1_OMAP_MPU 8

V1V8_OMAP_VIO 7,8

V1V29_OMAP_1V2 8,9

CLK32K_GATE13

CLK32K_AUD5CLK32K_MAIN7,13

PHO_GPADC_START 14

VMEM_OMAP_VDD2_LPDDR2 8

H_FREF_CLK3_REQ 14


Date: Sheet of




Modified by:



Do Not Copy

14

A

Phoenix Power ICVOMAP4430 ES2.0 Processor Board IV

OMAPDP Team

4




Date: Sheet of




Modified by:



Do Not Copy

14

A


OMAPDP Team

4




Date: Sheet of




Modified by:



Do Not Copy

14

A


OMAPDP Team

4



R650.0681%0.2W

R650.0681%0.2W12

34

R155 0.050.50% 0.1WR155 0.050.50% 0.1W

1 2

3 4

R88 0R88 0

R63 0R63 0

C59 10uFC59 10uF

C18

2.2u

FC

182.

2uF

L3BLM15PD121SN1D

1.3A

L3BLM15PD121SN1D

1.3A

C47

12pF

C47

12pF

R66 DNI10KR66 DNI10K

C10

12.

2uF

C10

12.

2uF

C62

2.2u

FC

622.

2uF

C52 4.7UF 16VC52 4.7UF 16V

C90 4.7UFC90 4.7UF

R2 10KR2 10K

R131DNI

0R131DNI

0

R1043220KR1043220K

C17

2.2u

FC

172.

2uF

R260 0R260 0

C58

2.2u

FC

582.

2uF

C43 0.1uFC43 0.1uF

R234 0DNI

R234 0DNI

L15BLM15PD121SN1D

1.3A

L15BLM15PD121SN1D

1.3A

R48 10KR48 10K

C91 4.7UFC91 4.7UF

C11

02.

2uF

C11

02.

2uF

TP158TP158

R97 1MegR97 1Meg

C13 0.1uFC13 0.1uF

C69 4.7UFC69 4.7UF

C93 10uFC93 10uF

R130 0R130 0

C86 10uFC86 10uF

B1

XH414HG

B1

XH414HG

12

R168 0R168 0

C45

2.2u

FC

452.

2uF

R104110KR104110K

C142.2uFC142.2uF

L9 0.68uHL9 0.68uH

C25 2.2uFC25 2.2uF

C4410uFC4410uF

t RT447K

t RT447K

C5110 nFC5110 nF

R50 0R50 0

R112DNI

0R112DNI

0

R93 0R93 0

C63 10uFC63 10uF

R49 DNI10KR49 DNI10K

C53 4.7UF16V

C53 4.7UF16V

R239 0DNI

R239 0DNI

R87DNI

0R87DNI

0

L5 1.0uHL5 1.0uH

C21

2.2u

FC

212.

2uF

L11 1.0uH3.0AL11 1.0uH3.0A

R51 DNI0R51 DNI0

R5 DNI0R5 DNI0

t RT347K

t RT347K

R92DNI

0R92DNI

0

L4 1.0uHL4 1.0uH

R1044220KR1044220K

C10

72.

2uF

C10

72.

2uF

C55

2.2u

FC

552.

2uF

L10BLM18KG221SN1D

2200mA

L10BLM18KG221SN1D

2200mAL2 1uHL2 1uH

R142 0R142 0

R52 0R52 0

C10

92.

2uF

C10

92.

2uF

L6BLM15PD121SN1D

1.3A

L6BLM15PD121SN1D

1.3A

R261 0R261 0

C80

2.2u

FC

802.

2uF

C48

2.2u

FC

482.

2uF

R95 0R95 0

C67 4.7UFC67 4.7UF

R118 0R118 0

C15

2.2u

FC

152.

2uF

R104210KR104210K

C16

2.2u

FC

162.

2uF

C19

2.2u

FC

192.

2uF

C46

12pF

C46

12pF

C73

2.2u

FC

732.

2uF

L14 1.0uHL14 1.0uH

C85 4.7UFC85 4.7UF

L16BLM15PD121SN1D

1.3A

L16BLM15PD121SN1D

1.3A

R129 DNI0R129 DNI0

C92 10uFC92 10uF

R55 0R55 0

C75 10uFC75 10uF

L7 1.0uHL7 1.0uH

C20

2.2u

FC

202.

2uF

Y232.768kHzY232.768kHz

12

C11

12.

2uF

C11

12.

2uF

Phoenix PMIC

FBGA 7x7 mmBallout Version 1.9 (5/6/2009) 16x16 package 0.4mm pitch

VCORE1 SMPS

VCORE2 SMPS

VCORE3 SMPS

V1V8 SMPS

V2V1 SMPS

V1V29 SMPS

VMEM SMPSMisc LDO's

Power input

BUS CTRL ON/OFF/BOOTCD/JTAGBandgap

USB OTG

Charger

Gauge ADC'sCLK CTRL

32kHz

GND

U6Phoenix PMIC 1.9

Phoenix PMIC

FBGA 7x7 mmBallout Version 1.9 (5/6/2009) 16x16 package 0.4mm pitch

VCORE1 SMPS

VCORE2 SMPS

VCORE3 SMPS

V1V8 SMPS

V2V1 SMPS

V1V29 SMPS

VMEM SMPSMisc LDO's

Power input

BUS CTRL ON/OFF/BOOTCD/JTAGBandgap

USB OTG

Charger

Gauge ADC'sCLK CTRL

32kHz

GND

U6Phoenix PMIC 1.9

VBUS_B1C1

VBUS_B2D1

VBUS_B3C2

CHRG_LED_TESTD5

PR

EQ

1J9

PR

EQ

2BK

8

VBGG12

CTL

I2C

_SC

LM

4C

TLI2

C_S

DA

N4

BO

OT2

G9

NR

ES

PW

RO

NN

5

NR

ES

WA

RM

M5

CH

RG

_PG

ND

_B4

B5

PW

RO

NL5

RE

GE

N1

K7

RP

WR

ON

K5

SY

SE

NM

6

INT

K10

MS

EC

UR

EN

2

SR

I2C

_SC

LM

13S

RI2

C_S

DA

N13

IDE12

V1V8_FDBKL15

V1V8_GND_B1M16

V1V8_GND_B2L16

V1V8_IN_B1T13

V1V8_IN_B2T14

V1V8_SW_B1N16

V1V8_SW_B2P16

V2V1_FDBKF16

V2V1_GND_B1E16

V2V1_GND_B2E15

V2V1_IN_B1C16

V2V1_IN_B2C15

V2V1_SW_B1D16

V2V1_SW_B2D15

VCORE1_FDBKL2

VCORE1_GND_B1M1

VCORE1_GND_B2L1

VCORE1_GND_B3M2

VCORE1_IN_B1T4

VCORE1_IN_B2T3

VCORE1_IN_B3R3

VCORE1_SW_B1N1

VCORE1_SW_B2P1

VCORE1_SW_B3P2

VCORE2_FDBKR4

VCORE2_GND_B1T5

VCORE2_GND_B2R5

VCORE2_IN_B1T7

VCORE2_IN_B2R7

VCORE2_SW_B1T6

VCORE2_SW_B2R6

VCORE3_FDBKG1

VCORE3_GND_B1H1

VCORE3_GND_B2H2

VCORE3_IN_B1K1

VCORE3_IN_B2K2

VCORE3_SW_B1J1

VCORE3_SW_B2J2

V1V29_FDBKG16

V1V29_GND_B1H16

V1V29_GND_B2H15

V1V29_IN_B1K16

V1V29_IN_B2K15

V1V29_SW_B1J16

V1V29_SW_B2J15

VMEM_FDBKR13

VMEM_GND_B1T12

VMEM_GND_B2R12

VMEM_IN_B1T10

VMEM_IN_B2R10

VMEM_SW_B1T11

VMEM_SW_B2R11

CHRG_AUXPWRE6

CHRG_BOOTG2

CHRG_CSINE4

CHRG_CSOUTD4

CHRG_DET_NE5

CH

RG

_PG

ND

_B1

A5

CH

RG

_PG

ND

_B2

A6

CH

RG

_PG

ND

_B3

B6

CHRG_PMID_B1E1

CHRG_PMID_B2F1

CHRG_PMID_B3E2

CHRG_EXTCHRG_STATZH7

CHRG_SW_B1A3

CHRG_SW_B2A4

CHRG_SW_B3B4

CHRG_EXTCHRG_ENZJ7

VACF4

CHRG_VREFF5

IREFH12

REFGND_B1A9

MM

CN

11S

IMN

12

GG

AU

GE

_RE

SN

D13

GG

AU

GE

_RE

SP

E13

CHRG_SW_B4B3

VBUS_B4D2

GP

AD

C_I

N0

D12

GP

AD

C_I

N1

B11

GP

AD

C_I

N2

B14

GP

AD

C_I

N3

A13

GP

AD

C_I

N4

B12

GP

AD

C_I

N5

A14

GP

AD

C_I

N6

B15

GP

AD

C_S

TAR

TK

12

GN

D_A

NA

_B1

N8

GN

D_A

NA

_B2

M10

GN

D_A

NA

_B3

E11

GN

D_A

NA

_B4

L13

GN

D_A

NA

_B5

D9

GN

D_A

NA

_B6

H4

VD

D_B

1N

9

VD

D_B

2G

13

VD

D_B

3B

9

VD

D_B

4L4

VIO

M9

VB

AT

B13

CLK32KAUDIOE9

PR

EQ

3N

6

VB

AC

KU

PE

10

CLK32KAOH10

CLK32KGJ10

OSC32KINA10

OSC32KCAPE8

GN

D_D

IG_V

IOM

8

VA

NA

B10

VA

UX

1T8

VA

UX

2T9

VC

XIO

F15

VD

AC

G15

GN

D_D

IG_V

RTC

G4

REFGND_B2F12

VM

MC

J13

VP

PK

4

BA

TRE

MO

VA

LL1

2

VR

TCD

7

VU

SB

A7

VU

SIM

B8

BO

OT3

H9

VA

NA

_IN

D10

VA

UX

1_IN

N7

VA

UX

2_IN

N10

VA

UX

3R

9

VA

UX

3_IN

R8

VC

XIO

_IN

F13

VD

AC

_IN

H13

VM

MC

_IN

1J1

2

VP

P_I

NJ4

VU

SIM

_IN

1D

8

GP

AD

C_V

RE

F1A

11

GP

AD

C_V

RE

F4A

12

V1V8_GND_B3M15

V1V8_IN_B3R14

V1V8_SW_B3P15

PB

KG

_B31

T16

PB

KG

_B32

T15

PB

KG

_B33

R16

PB

KG

_B41

A1

PB

KG

_B42

A2

VM

MC

_IN

2K

13

VU

SIM

_IN

2B

7

BO

OT0

H8

CHRG_PMID_B4F2

BO

OT1

G8

RE

GE

N2

J5OSC32KOUT

A8

PW

M1

M11

PB

KG

_B11

T1

PB

KG

_B2

H5

PB

KG

_B13

R1

PB

KG

_B12

T2

PB

KG

_B43

B1

PBKG_B51A16

PBKG_B53B16

TES

TEN

J8

TES

TVA

15

PR

EQ

2AK

9P

RE

Q2C

M7

PW

M2

M12

PW

MFO

RC

EN

15

CHRG_LED_IND6

GN

D_A

NA

_B7

G7

VPROGG10

VR

TC_I

ND

11

R78 0.050.50% 0.1WR78 0.050.50% 0.1W

1 2

3 4

C71 10uFC71 10uF

L13 1.0uHL13 1.0uH

R99 DNI0R99 DNI0

C57 4.7UFC57 4.7UF

L8BLM15PD121SN1D

1.3A

L8BLM15PD121SN1D

1.3A

C10

82.

2uF

C10

82.

2uF

C81 4.7UFC81 4.7UF

L12BLM18KG221SN1D

2200mA

L12BLM18KG221SN1D

2200mA

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AOMAP4430 Symbol "C" - Core Area

OMAP / Host Power Component ROOM = OMAP

Note: Capacitors are on backside of PCB.

LPDDR21_ZQLPDDR22_ZQ

OMAP4430_IFORCE

OMAP4430_VSENSE

OMAP_CAP_PWR1OMAP_CAP_PWR2OMAP_CAP_PWR3OMAP_CAP_PWR4OMAP_CAP_PWR5OMAP_CAP_PWR6

V1V29_OMAP_CA_LPDDR2




V1V29_OMAP_Q_LPDDR2

V1V29_OMAP_Q_LPDDR2

V1V29_OMAP_Q_LPDDR2

V1V8_OMAP_BDGP_VBB

V1V8_OMAP_VDD1_LPDDR2

V1V8_OMAP_VIO

V1V8_OMAP_VIO

V1V8_OMAP_VIO

VCORE2_OMAP_IVAUD

VCORE3_OMAP_CORE

VCORE3_OMAP_DLLVCORE3_OMAP_DLL

VMEM_OMAP_VDD2_LPDDR2

VCORE1_OMAP_MPU

VCORE3_OMAP_CORE4

VCORE3_OMAP_CORE 4

CM_P_VCORE3_OMAP_DLL 14

CM_N_VCORE3_OMAP_DLL 14

VPMIC_V1V82,4,5,7,9,11,12,14

CM_P_V1V8_OMAP_VDD1_LPDDR214

CM_N_V1V8_OMAP_VDD1_LPDDR214

V1V8_OMAP_LDO_SRAM_MPU9V1V8_OMAP_LDO_SRAM_IVAUD9

V1V8_OMAP_LDO_SRAM_CORE9

VPMIC_V1V8 2,4,5,7,9,11,12,14

CM_P_V1V8_OMAP_BDGP_VBB 14

CM_N_V1V8_OMAP_BDGP_VBB 14

VPMIC_V1V8 2,4,5,7,9,11,12,14

CM_P_V1V8_OMAP_VIO 14

CM_N_V1V8_OMAP_VIO 14

V1V29_OMAP_1V2 4,9

V1V29_OMAP_LDO_EMU_WKUP9

VPMIC_V1V29 4,9,14

CM_P_V1V29_OMAP_CA_LPDDR2 14

CM_N_V1V29_OMAP_CA_LPDDR2 14

CM_N_V1V29_OMAP_Q_LPDDR2 14

VPMIC_V1V29 4,9,14

CM_P_V1V29_OMAP_Q_LPDDR2 14

VUSB_OMAP_OTG_3V39

VDAC_OMAP_HDMI_VDAC9

VCXIO_OMAP_DPLL_MPU9

VMMC_OMAP_MMC1 9

VCXIO_OMAP_DPLL_CORE_AUD9

V1V8_OMAP_1V8_FREF9

VCXIO_OMAP_DSI9

VCXIO_OMAP_CSI9

VCXIO_OMAP_DPLL_IVA_PER9

VCXIO_OMAP_OTG_1V89

VPMIC_OMAP_VPP_CUST 4

VUSIM_OMAP_SIM 9

V1V8_OMAP_VIO 4,7

VCORE1_OMAP_MPU4

VCORE2_OMAP_IVAUD4

VPMIC_VMEM4

CM_P_VMEM_OMAP_VDD2_LPDDR214CM_N_VMEM_OMAP_VDD2_LPDDR214

VMEM_OMAP_VDD2_LPDDR24


Date: Sheet of




Modified by:



Do Not Copy

8

OMAPDP Team

VOMAP4430 ES2.0 Processor Board IVOMAP4430 Symbol "C"

A

14




Date: Sheet of




Modified by:



Do Not Copy

8

OMAPDP Team


A

14




Date: Sheet of




Modified by:



Do Not Copy

8

OMAPDP Team


A

14



C122470nFC122470nF

C1300.1uFC1300.1uF

R1510.050.50%0.1WR1510.050.50%0.1W

12

34

C940.1uFC940.1uF

C2010.1uFC2010.1uF

C1891uFC1891uF

C560.1uFC560.1uF

C1990.1uFC1990.1uF

C32470nFC32470nF

C128470nF C128470nF

C2041uFC2041uF

C83 0.1uFC83 0.1uF

C117 0.1uFC117 0.1uF

C541uFC541uF

C23470nFC23470nF

C100220nF C100220nF

R70 240R70 240

C2021uFC2021uF

OMAP4430 GP, 12X12MM, FCPOP1 (547 BOTTOM BALLS AT 0.4MM PITCH, 216 TOP BALLS)

U7COMAP4430

OMAP4430 GP, 12X12MM, FCPOP1 (547 BOTTOM BALLS AT 0.4MM PITCH, 216 TOP BALLS)

U7COMAP4430

VDD_MPUV8

VDD_MPUW8

VDD_MPUW9

VDD_MPUY8

VDD_MPUY10

VDD_MPUAA10

VDD_COREM20

VSS

N9

VDD_COREN20

VDD_CORER20

VDD_CORET20

VDD_COREU20

VDD_COREH12

VDD_COREH18

VDDQ_VREF_LPDDR22T8

VDD_COREJ9

VDD_COREJ11

VDD_COREJ12

VDD_COREJ13

VDD_COREJ15

VDD_COREJ16

VDD_COREJ17

VDD_COREJ18

VDD_COREJ19

VDD_COREJ20

VDD_COREK9

VDD_COREK20

VDD_COREL9

VDD_COREL20

VDD_COREM9

VDD_MPUV9

VDD_IVA_AUDIOV21

VDD_IVA_AUDIOW20

VDD_IVA_AUDIOW21

VDD_IVA_AUDIOY18

VDD_IVA_AUDIOY19

VDD_IVA_AUDIOY20

VDD_IVA_AUDIOY21

VDD_IVA_AUDIOAA19

VDDQ_LPDDR2A17

VDDQ_LPDDR2A22

VDDQ_LPDDR2A25

VDDQ_LPDDR2D1

VDDQ_LPDDR2E28

VDDQ_LPDDR2G1

VDDQ_LPDDR2G8

VDDQ_LPDDR2G21

VDDQ_LPDDR2H8

VDDQ_LPDDR2H21

VDDQ_LPDDR2H9

VDDQ_LPDDR2H20

VDDQ_LPDDR2AA8

VDDS_1P8K7

VSS

K8

VDDQ_LPDDR2L28

VDDA_DLL0_LPDDR22M7

VDDQ_LPDDR2Y1

VDDQ_LPDDR2AA9

VDDQ_LPDDR2AB9

VDDQ_LPDDR2AF1

VDDQ_LPDDR2AH4

VDDQ_LPDDR2AH9

VDDQ_LPDDR2A4

VDDQ_LPDDR2A9

VDDQ_LPDDR2AH12

VSS

U17

VSS

A10

VSS

A20

VSS

A23

VSS

B3

VSS

B6

VSS

B13

VSS

B27

VSS

F2VS

SC

2

VSS

T17

VSS

F25

VSS

H11

VSS

H17

VSS

H19

VSS

H28

VSS

J3

VSS

J4

VSS

H1

VSS

U13

VSS

U14

VSS

J21

VSS

L26

VSS

M1

VDDQ_LPDDR2M8

VSS

M21

VSS

P16

VSS

T15

VSS

T16

VSS

U2

VSS

U8

VSS

U12

VSS

U15

VSS

U16

VSS

U21

VSS

U28

VSS

Y25

VSS

Y26

VSS

AA11

VDD_IVA_AUDIOAA18

VDDCA_LPDDR2AA21

VSS

AB1

VSS

AA12

VSS

AG4

VSS

AG17

VSS

AG26

VSS

AH8

VSS

AH10

VSS

AH13

VDDQ_LPDDR2U1

POP_VDD1_LPDDR2_SHARED_AH28AG27

VDD_COREJ10

VDDQ_LPDDR2AC1

VDDCA_VREF_LPDDR21Y14

VSS

Y17

VDD_COREAA13

VDDCA_VREF_LPDDR22R27

VDDCA_LPDDR2T28

VDDS_1P8W22

VPP_STDY22

VSS

AA20

VDDS_DV_BANK1AB20

VDDCA_LPDDR2AB28

VDDCA_LPDDR2AD28

VDDCA_LPDDR2AH20

VDDCA_LPDDR2AH25

POP_VDD1_LPDDR21_A15A13

POP_VDD1_LPDDR21_C28C27

POP_VDD1_LPDDR22_N2N1

POP_VDD1_LPDDR22_R1P1

POP_VDD1_LPDDR21_AJ15AH14

POP_VDD1_LPDDR2_SHARED_C1C1

POP_VDD1_LPDDR2_SHARED_AH2AG2

VDDQ_LPDDR2A6

VDDQ_LPDDR2A12

VDDQ_LPDDR2J28

RSVD3C6RSVD2C5RSVD1C4

VDDS_DV_SDMMC2H16

RSVD12M27RSVD11K22RSVD10K21

NC3B28

RSVD13N27

NC2B1NC1A28

RSVD4D3

IFORCEAH27

RSVD14T21

VDDA_DPLL_IVA_PERY16 VDDA_DPLL_MPUP9

VSS

H13

CAP_VDD_LDO_SRAM_COREU22

VDDA_LDO_SRAM_MPUAB14

PBIAS_SDMMC1A1

PBIAS_SIMA2

VDDA_LDO_SRAM_CORET22

VDDS_1P2VAA16

VDDA_CSI21W28

VDDA_CSI22V28

VDDA_LDO_SRAM_IVA_AUDION22

CAP_VDD_LDO_SRAM_IVA_AUDION21

VDDA_LDO_EMU_WKUPP7

VDDA_DSI1L1

VDDA_DSI2L2

VDDA_HDMI_VDACA11

VSSA

_DSI

P8

CAP_VBB_LDO_IVA_AUDIOR21

VDDS_DV_BANK0AB16

VDDS_DV_BANK7M28

VDDA_USBA0OTG_1P8VA7

VDDA_USBA0OTG_3P3VA5

VDDA_BDGP_VBBAB12

VDDCA_LPDDR2AA22

VDDS_1P8J22

VDDS_1P8U7

VDDS_1P8V7

CAP_VBB_LDO_MPUAB13

VDDS_DV_BANK2AB19

VDDCA_LPDDR2AB21

VDDS_DV_BANK2AB8

VDDS_DV_BANK3AB18

VDDS_DV_BANK4AA7

VDDS_DV_BANK5AB17

CAP_VDD_LDO_SRAM_MPUAB11

VDDS_DV_CAMV22

VDDS_DV_FREFW7

VDDS_1P8_FREFY7

VDDS_DV_C2CG18

VDDS_DV_GPMCG20

VDDS_DV_C2CG17

VDDQ_VREF_LPDDR21G15

VDDS_DV_SDMMC2G16

VDDS_SDMMC1H7

VDDS_SIMJ7

VDDS_SDMMC1G7

VPP_CUSTJ8

VSENSEAG28

VDDS_DV_BANK6AA14

VSSA

_CSI

2R

22

VSSA

_DSI

N8

RSVD9N7

VSSA

_HD

MI_

VDAC

G11

RSVD8L22

VSSA

_USB

A0O

TGH

10

VSSA

_USB

A0O

TG_3

P3V

G10

VSS

T14

VSS

T13

VSS

T12

VSS

R17

VSS

R16

VSS

R15

VSS

R14

VSS

R13

VSS

R12

VSS

P17

VSS

AF2

POP_VDD2_LPDDR21_A16A15

POP_VDD2_LPDDR21_B16B15

POP_VDD2_LPDDR22_P28N28

POP_VDD2_LPDDR22_T1T1

POP_VDD2_LPDDR22_T2T2

POP_VDD2_LPDDR2_SHARED_A3A3

POP_VDD2_LPDDR2_SHARED_AG28AF27

POP_VDD2_LPDDR2_SHARED_AH3AH3

POP_VDD2_LPDDR21_AH15AG14

POP_VDD2_LPDDR2_SHARED_C29C28

POP_LPDDR21_ZQ_AJ17AH16

POP_LPDDR22_ZQ_AG29AF28

POP_VACC_LPDDR2_B28A26

POP_VACC_LPDDR2_B2B2

VSS

P15

VSS

P14

VSS

P13

VSS

P12

VSS

N17

VSS

N16

VSS

N15

VSS

N14

VSS

N13

VSS

N12

VSSA

M22

VSS

M17

VSS

M16

VSS

M15

VSS

M14

VSS

M13

VSS

AE27

VSS

L25

VSS

L21

VDDQ_LPDDR2L8

VSS

K28

VSS

K2

VDDCA_LPDDR2AH18

VDD_CORET9

VDD_MPUU9

VDD_COREV20

VDD_IVA_AUDIOAA17

VDDS_1P8H22

CAP_VDD_LDO_EMU_WKUPT7

VDDA_HDMI_VDACG12

VSS

AH21

C2C_VREFH15

RSVD5D4

RSVD6D5

RSVD7D6

VDD_COREY11

VDD_COREY12

VDD_COREY13

VDD_MPUY9

VDDA_DPLL_CORE_AUDIOG13

POP_VDD1_LPDDR22_P29R28

VDDCA_LPDDR2AB22

VDDS_DV_C2CG19

VDDA_DLL0_LPDDR21G22

VDDA_DLL1_LPDDR21G9

VDDQ_LPDDR2L7

VDDA_DLL1_LPDDR22AB10

VDDS_1P8AB7

LPDDR21_NCS0AH28

C1970.1uFC1970.1uF

C87 1uFC87 1uF

C640.1uF C640.1uF

C390.1uF C390.1uF

C600.1uFC600.1uF

C74 1uFC74 1uF

C1030.1uFC1030.1uF

C1310.1uFC1310.1uF

R59DNI

0R59DNI

0

C720.1uFC720.1uFC88

0.1uFC880.1uF

C97 1uFDNI

C97 1uFDNI

C1320.1uF C1320.1uF

C41 0.1uFC41 0.1uF

C1250.1uF C1250.1uF

C1200.1uFC1200.1uF

C2030.1uFC2030.1uF

TP51TP51

C300.1uFC300.1uF

R620.050.50%0.1WR620.050.50%0.1W

12

34

C2081uFDNI

C2081uFDNI

C22470nFC22470nF

C34 1uFC34 1uF

C129220nF C129220nF

C1020.1uF C1020.1uF

C105 0.1uFC105 0.1uF

C84470nFC84470nF

C700.1uF C700.1uF

C2060.1uFC2060.1uF

C990.1uF C990.1uF

C610.1uFC610.1uF

R71 240R71 240

R560.050.50%0.1WR560.050.50%0.1W

12

34

C1950.1uFC1950.1uF

C1960.1uFC1960.1uF

C790.1uFC790.1uF C35

0.1uFC350.1uF

R167 0.050.50% 0.1WR167 0.050.50% 0.1W

1 2

3 4

C1060.1uFC1060.1uF

C1884.7UFDNI

C1884.7UFDNI

C1140.1uF C1140.1uF

C1874.7UFC1874.7UF

TP33TP33

C1941uFC1941uF

C1270.1uFC1270.1uF

C890.1uFC890.1uF

C370.1uF C370.1uF

C119 0.1uFC119 0.1uF

C780.1uFC780.1uF

C96 0.1uFC96 0.1uF

C2000.1uFC2000.1uF

C980.1uFC980.1uF

C31 1uFC31 1uF

C126470nFC126470nF

C1130.1uFC1130.1uF

C115 0.1uFC115 0.1uF

C400.1uFC400.1uF

C2050.1uFC2050.1uF

C490.1uFC490.1uF

C1230.1uFC1230.1uF

C1240.1uFC1240.1uF

C2071uF

DNI

C2071uF

DNI

C420.1uFC420.1uF

C68220nF C68220nF

C380.1uFC380.1uF

R270.050.50%0.1WR270.050.50%0.1W

12

34

C77 1uFC77 1uF

C820.1uF C820.1uFC95 0.1uFC95 0.1uF

R610.050.50%0.1WR610.050.50%0.1W

12

34

C36 0.1uFC36 0.1uF

C330.1uFC330.1uF

R117 0.050.50% 0.1WR117 0.050.50% 0.1W

1 2

3 4

C1040.1uF C1040.1uF

C2091uFDNI

C2091uFDNI

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

APM DIFFERIENTAL SENSING SIGNALS

East Positioned Bd-to-Bd I/F South Positioned Bd-to-Bd I/F

East & South Bd-to-Bd Connectors

Component ROOM = EBB_CONN Component ROOM = SBB_CONN

J5/ South Bd-to-Bd Conn Visibility TestpointsComponent ROOM = SBB_CONN

J4/ East Bd-to-Bd Conn Visibility TestpointsComponent ROOM = EBB_CONN

sEVM APM I/FComponent ROOM = SBB_CONN

Three different R-Muxes have been provisioned for User to select key power rail of interest.

In addition, other 3 power rail connections have series 0-ohmsto enable any APM power rail to beselected for monitoring by removing0-ohm & adding wires to any CM sense signal.

BATT_IDBATT_TS

CHRG_LED_DRV

CHRG_LED_DRV CM_APM_N_R1

CM_APM_N_R2

CM_APM_N_R3

CM_APM_N_R4

CM_APM_N_R5

CM_APM_N_R6

CM_APM_P_R1

CM_APM_P_R2

CM_APM_P_R3

CM_APM_P_R4

CM_APM_P_R5

CM_APM_P_R6

CM_N_V1V29_OMAP_Q_LPDDR2

CM_N_V1V8_EMMC_VCCQ

CM_N_V1V8_HDMI_VCCA

CM_N_V1V8_OMAP_LDO_SRAM_CORE

CM_N_V1V8_OMAP_LDO_SRAM_IVAUD

CM_N_V1V8_OMAP_VIO

CM_N_V1V8_PAUD_VIO

CM_N_V1V8_PMIC_VIO

CM_N_V2V1_PAUD_2V1_NCP

CM_N_V2V1_PMIC_VCXIO_VDAC

CM_N_VANA_CLKB

CM_N_VAUX1_EMMC_VCC

CM_N_VAUX2_AVSW_VP

CM_N_VBAT_APPL

CM_N_VBAT_APPL

CM_N_VBAT_APPL

CM_N_VBAT_BB_VIN

CM_N_VBAT_BST_AVIN

CM_N_VBAT_CLKB

CM_N_VBAT_HDMI

CM_N_VBAT_PAUD

CM_N_VBAT_PMIC_V1V29

CM_N_VBAT_PMIC_V1V8

CM_N_VBAT_PMIC_V2V1

CM_N_VBAT_PMIC_VANA

CM_N_VBAT_PMIC_VDD_BINS

CM_N_VBAT_PMIC_VMEM

CM_N_VBAT_PROC

CM_N_VBAT_PROC

CM_N_VBAT_PROC

CM_N_VBBO_PMIC

CM_N_VCLKB_TCXO_VCC

VCORE1_OMAP_MPU

VCORE1_OMAP_MPU

VCORE2_OMAP_IVAUD

VCORE2_OMAP_IVAUD

VCORE3_OMAP_CORE

VCORE3_OMAP_CORE

CM_N_VCORE3_OMAP_DLL

CM_N_VCXIO_OMAP_CSI

CM_N_VCXIO_OMAP_DPLL_CORE_AUD

CM_N_VCXIO_OMAP_DPLL_CORE_AUD

CM_N_VCXIO_OMAP_DPLL_IVA_PER

CM_N_VCXIO_OMAP_DPLL_MPU

CM_N_VCXIO_OMAP_DSI

CM_N_VCXIO_OMAP_OTG_1V8

CM_N_VDAC_OMAP_HDMI_VDAC

CM_N_VHS_PAUD_VINS

CM_N_VLS_PAUD_VINS

CM_N_VMEM_OMAP_VDD2_LPDDR2

CM_N_VNCP_PAUD_LDOIN

CM_N_VUSB_OMAP_OTG_3V3

CM_N_VUSIM_OMAP_SIM

CM_P_V1V29_OMAP_Q_LPDDR2

CM_P_V1V8_EMMC_VCCQ

CM_P_V1V8_HDMI_VCCA

CM_P_V1V8_OMAP_LDO_SRAM_CORE

CM_P_V1V8_OMAP_LDO_SRAM_IVAUD

CM_P_V1V8_OMAP_VIO

CM_P_V1V8_PAUD_VIO

CM_P_V1V8_PMIC_VIO

CM_P_V2V1_PAUD_2V1_NCP

CM_P_V2V1_PMIC_VCXIO_VDAC

CM_P_VANA_CLKB

CM_P_VAUX1_EMMC_VCC

CM_P_VAUX2_AVSW_VP

CM_P_VBAT_APPL

CM_P_VBAT_APPL

CM_P_VBAT_APPL

CM_P_VBAT_BB_VIN

CM_P_VBAT_BST_AVIN

CM_P_VBAT_CLKB

CM_P_VBAT_HDMI

CM_P_VBAT_PAUD

CM_P_VBAT_PMIC_V1V29

CM_P_VBAT_PMIC_V1V8

CM_P_VBAT_PMIC_V2V1

CM_P_VBAT_PMIC_VANA

CM_P_VBAT_PMIC_VDD_BINS

CM_P_VBAT_PMIC_VMEM

CM_P_VBAT_PROC

CM_P_VBAT_PROC

CM_P_VBAT_PROC

CM_P_VBBO_PMIC

CM_P_VCLKB_TCXO_VCC

CM_P_VCORE1_OMAP

CM_P_VCORE1_OMAP

CM_P_VCORE2_OMAP_IVAUD

CM_P_VCORE2_OMAP_IVAUD

CM_P_VCORE3_OMAP_CORE

CM_P_VCORE3_OMAP_CORE

CM_P_VCORE3_OMAP_DLL

CM_P_VCXIO_OMAP_CSI

CM_P_VCXIO_OMAP_DPLL_CORE_AUD

CM_P_VCXIO_OMAP_DPLL_CORE_AUD

CM_P_VCXIO_OMAP_DPLL_IVA_PER

CM_P_VCXIO_OMAP_DPLL_MPU

CM_P_VCXIO_OMAP_DSI

CM_P_VCXIO_OMAP_OTG_1V8

CM_P_VDAC_OMAP_HDMI_VDAC

CM_P_VHS_PAUD_VINS

CM_P_VLS_PAUD_VINS

CM_P_VMEM_OMAP_VDD2_LPDDR2

CM_P_VNCP_PAUD_LDOIN

CM_P_VUSB_OMAP_OTG_3V3

CM_P_VUSIM_OMAP_SIM

h_SYS_PREQ2A

h_SYS_PREQ2B

h_SYS_PREQ2C

h_SYS_PREQ3

J4_P005J4_P007

J4_P015

J4_P028

J4_P034

J4_P054J4_P056J4_P058J4_P060J4_P062

J4_P063 J4_P064J4_P065 J4_P066J4_P067 J4_P068J4_P069 J4_P070

J4_P072

MMC1_CD

PHO_PWM1PHO_PWM2

PHO_REGEN2

PHO_SYSEN

SW_PWRON

VBAT_PACK

VBAT_PACK

VBUS_USB

VAC_PHOE

GNDHSETGNDAMIC

VDD_DCIN_5v0

GNDDMIC

GNDDMIC

GNDAMIC

GNDHSET

VBAT_PROC

BATT_ID 4BATT_TS 4

AUD_HFR_N5AUD_HFR_P5

AUD_HFL_N 5AUD_HFL_P 5

AUD_EARN5AUD_EARP5

VIB_L_N5VIB_L_P5

AV_OUT_P12

AUD_FMIN_L 5AUD_FMIN_R 5

AUD_AUXLP5AUD_AUXLN5

AUD_PLUGDET5SMIC_P 5SMIC_N 5

AUD_HSL5AUD_HSR5

PHO_AUD_GPO3 5

AUD_AUXRN 5AUD_AUXRP 5

USB_ID4

SW_PWRON4

H_SYS_PREQ2C 4H_SYS_PREQ3 4

H_SYS_PREQ2B 4H_SYS_PREQ2A 4

GPADC_VREF4 4

PHO_SYSEN 2,4CHRG_LED_DRV 4

EXT_RPWRON4PHO_REGEN24

VIB_R_N 5VIB_R_P 5

GPADC_VREF14

GPADC_IN64PHO_PWM14PHO_PWM24

MMC1_CD4

PHO_GG_RESP 4PHO_GG_RESN 4

AV_OUT_N5

GPADC_IN4 4

GPADC_IN54

DBIAS25DBIAS15

GPADC_IN34

H_SDMMC1_DAT3 6H_GPIO_106 6H_SDMMC1_DAT06

H_SDMMC1_CLK6

H_SDMMC1_DAT16H_SDMMC1_DAT26

H_SDMMC1_CMD6

H_USB1_DP7H_USB1_DM7

MMIC_N 5MMIC_P 5

H_GPIO_107 6H_GPIO_108 6H_GPIO_109 6

VPMIC_V1V8 2,4,5,7,8,9,11,12

VPMIC_V1V294,8,9

VSEL_VUSIM2,9

VPMIC_VAUX2 4,12

VPMIC_VAUX34

VSEL_VMMC2,9

CM_P_VBAT_CLKB 2CM_N_VBAT_CLKB 2

SDP_I2C0_SDA11SDP_I2C0_SCL11

VBAT_PACK2,11

CM_P_VANA_CLKB 2CM_N_VANA_CLKB 2

VSDP_3V311

CM_N_V1V8_HDMI_VCCA12CM_P_V1V8_HDMI_VCCA12

CM_N_VBAT_HDMI12CM_P_VBAT_HDMI12

CM_P_V2V1_PAUD_2V1_NCP5CM_N_V2V1_PAUD_2V1_NCP5

CM_N_VCORE3_OMAP_DLL8CM_P_VCORE3_OMAP_DLL8

CM_N_VAUX2_AVSW_VP12CM_P_VAUX2_AVSW_VP12CM_P_VBBO_PMIC2CM_N_VBBO_PMIC2

CM_P_VCXIO_OMAP_CSI9CM_N_VCXIO_OMAP_CSI9

CM_N_VAUX1_EMMC_VCC11CM_P_VAUX1_EMMC_VCC11

CM_P_V1V8_OMAP_VIO8CM_N_V1V8_OMAP_VIO8CM_P_V1V8_EMMC_VCCQ11CM_N_V1V8_EMMC_VCCQ11CM_P_VBAT_BST_AVIN2CM_N_VBAT_BST_AVIN2

CM_P_V1V8_OMAP_LDO_SRAM_IVAUD9CM_N_V1V8_OMAP_LDO_SRAM_IVAUD9

CM_N_VUSB_OMAP_OTG_3V39CM_P_VUSB_OMAP_OTG_3V39

CM_P_VCXIO_OMAP_DSI9CM_N_VCXIO_OMAP_DSI9

CM_P_VDAC_OMAP_HDMI_VDAC9CM_N_VDAC_OMAP_HDMI_VDAC9CM_N_VCXIO_OMAP_OTG_1V89CM_P_VCXIO_OMAP_OTG_1V89CM_N_VCXIO_OMAP_DPLL_CORE_AUD9CM_P_VCXIO_OMAP_DPLL_CORE_AUD9

CM_P_V1V8_OMAP_LDO_SRAM_CORE9CM_N_V1V8_OMAP_LDO_SRAM_CORE9

CM_N_VUSIM_OMAP_SIM9CM_P_VUSIM_OMAP_SIM9

CM_N_VBAT_PMIC_VMEM3CM_P_VBAT_PMIC_VMEM3

CM_P_VBAT_PMIC_VCORE33CM_N_VBAT_PMIC_VCORE33CM_P_VLS_PAUD_VINS5CM_N_VLS_PAUD_VINS5CM_P_VNCP_PAUD_LDOIN5CM_N_VNCP_PAUD_LDOIN5

CM_P_VCXIO_OMAP_DPLL_IVA_PER 9CM_N_VCXIO_OMAP_DPLL_IVA_PER 9

CM_P_VCXIO_OMAP_DPLL_MPU 9CM_N_VCXIO_OMAP_DPLL_MPU 9CM_N_V1V29_OMAP_LDO_EMU_WKUP 9CM_P_V1V29_OMAP_LDO_EMU_WKUP 9CM_N_VMMC_OMAP_MMC1 9CM_P_VMMC_OMAP_MMC1 9

CM_N_VBAT_PMIC_V1V8 3CM_P_VBAT_PMIC_V1V8 3CM_N_VBAT_PMIC_V1V29 3CM_P_VBAT_PMIC_V1V29 3CM_N_VBAT_PMIC_VANA 3CM_P_VBAT_PMIC_VANA 3

CM_P_VBAT_PMIC_V2V1 3CM_N_VBAT_PMIC_V2V1 3

CM_N_V1V29_OMAP_Q_LPDDR2 8CM_P_V1V29_OMAP_Q_LPDDR2 8CM_P_VCLKB_TCXO_VCC 2CM_N_VCLKB_TCXO_VCC 2

CM_N_V1V8_OMAP_VDD1_LPDDR2 8CM_P_V1V8_OMAP_VDD1_LPDDR2 8

CM_N_V2V1_PMIC_VCXIO_VDAC 4CM_P_V2V1_PMIC_VCXIO_VDAC 4

CM_P_V1V29_OMAP_CA_LPDDR2 8CM_N_V1V29_OMAP_CA_LPDDR2 8

CM_P_V1V8_OMAP_LDO_SRAM_MPU 9CM_N_V1V8_OMAP_LDO_SRAM_MPU 9

CM_P_VBAT_PAUD 5CM_N_VBAT_PAUD 5CM_P_VHS_PAUD_VINS 5CM_N_VHS_PAUD_VINS 5CM_P_V1V8_PAUD_VIO 5CM_N_V1V8_PAUD_VIO 5

CM_P_V1V29_OMAP_1V2 9

CM_P_V1V8_CLKB_ETM_VDD 2CM_N_V1V8_CLKB_ETM_VDD 2CM_N_V1V8_OMAP_1V8_FREF 9CM_P_V1V8_OMAP_1V8_FREF 9

CM_P_V1V8_OMAP_BDGP_VBB 8CM_N_V1V8_OMAP_BDGP_VBB 8

CM_P_VBAT_PMIC_VDD_BINS 3CM_N_VBAT_PMIC_VDD_BINS 3CM_P_VBAT_BB_VIN 2CM_N_VBAT_BB_VIN 2CM_P_V1V8_PMIC_VIO 4CM_N_V1V8_PMIC_VIO 4

CM_N_V1V29_OMAP_1V2 9

PHO_GPADC_START 4

CM_N_VBST_PAUD_VDDHF 2CM_P_VBST_PAUD_VDDHF 2

CM_N_VMEM_OMAP_VDD2_LPDDR28CM_P_VMEM_OMAP_VDD2_LPDDR28

VCORE1_OMAP_MPU4

VCORE2_OMAP_IVAUD4VCORE3_OMAP_CORE4

CM_N_VBAT_PMIC_VCORE2 3CM_P_VBAT_PMIC_VCORE2 3

CM_N_VBAT_PMIC_VCORE13CM_P_VBAT_PMIC_VCORE13


Date: Sheet of




Modified by:



Do Not Copy

VOMAP4430 ES2.0 Processor Board IV

14

OMAPDP Team A

14

750-2165-001-SCH

Board-to-Board Connector (East) + South (power measurement)

Custom



Date: Sheet of




Modified by:



Do Not Copy


14

OMAPDP Team A

14

750-2165-001-SCH


Custom



Date: Sheet of




Modified by:



Do Not Copy


14

OMAPDP Team A

14

750-2165-001-SCH


Custom


R210 DNI0R210 DNI0

TP107TP107

TP126TP126

TP141TP141

TP310TP310

GND2GND2

TP299TP299

TP296TP296

TP283TP283TP262TP262

TP303TP303

TP319TP319

TP282TP282

R211 DNI0R211 DNI0

TP132TP132 TP309TP309

TP321TP321

TP67TP67

GND1GND1

TP136TP136

TP114TP114

TP147TP147

TP83TP83

R237 0R237 0

TP297TP297

TP250TP250

TP327TP327

R200 0R200 0

TP249TP249

TP265TP265

R219 DNI0R219 DNI0

L34BLM18KG221SN1D

2200mA

L34BLM18KG221SN1D

2200mA

TP306TP306

TP311TP311

TP73TP73

TP97TP97

TP277TP277

R230 0R230 0

TP328TP328

R241 0R241 0

R203 DNI0R203 DNI0

TP138TP138

TP287TP287

TP255TP255

TP308TP308

TP144TP144

R207 DNI0R207 DNI0

TP300TP300

TP87TP87

TP275TP275


TP301TP301

TP82TP82

R231 0R231 0

R220 DNI0R220 DNI0

TP110TP110

TP150TP150

R201 0R201 0

R199 0R199 0

TP314TP314

TP261TP261

TP322TP322

TP295TP295

TP260TP260

TP274TP274

TP264TP264

TP316TP316

R225 0R225 0

TP318TP318

TP280TP280

TP320TP320

TPWR1DNI

TP_RED_LOOP_TH

TPWR1DNI

TP_RED_LOOP_TH

TP291TP291

TP285TP285

R240 0R240 0

TP312TP312

R214 DNI0R214 DNI0

TP129TP129

TP111TP111

TP313TP313

TP273TP273

R226 0R226 0

TP292TP292

TP125TP125

TP90TP90

TP323TP323

TP259TP259

TP325TP325

R202 0R202 0

R238 0R238 0

TP267TP267

TP272TP272

TP305TP305

TP271TP271

TP281TP281

L32BLM18KG221SN1D

2200mA

L32BLM18KG221SN1D

2200mA

TP252TP252

TP293TP293

R215 DNI0R215 DNI0

TP257TP257

TP326TP326

J4

QTH-060-02-L-D-A

J4

QTH-060-02-L-D-A1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100

101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120

121122123124

125126127128

R205 DNI0R205 DNI0

TP290TP290

TP329TP329

TP266TP266

TP115TP115

TP145TP145


TP101TP101

TP135TP135

TP146TP146

R218 DNI0R218 DNI0

P2

HDMI TYPE C CON-SMT

P2

HDMI TYPE C CON-SMT

D2 Shield1

D2+2

D2-3

D1 Shield4

D1+5

D1-6

D0 Shield7

D0+8

D0-9

CK Shield10

CK+11

CK-12

GND13

CEC14

DDC SCL15

DDC SDA16

NC17

+5V18

HPD19

SHELL120

SHELL221

SHELL322

SHELL423

TP317TP317

TP253TP253

GND3GND3

TP122TP122

TP254TP254

R76 0.020.50% 0.1WR76 0.020.50% 0.1W

1 2

3 4TP298TP298

GRN

D1

GRN

D1

TP315TP315

TP330TP330

TP302TP302

TP269TP269

TP288TP288

TP251TP251

TP149TP149

TP248TP248

TP276TP276

GND4DNIGND4DNI

TP119TP119

TP284TP284

TP279TP279

TP268TP268

TP247TP247

TP130TP130

TP134TP134

TP131TP131

TP246TP246

L33DNI

BLM18KG221SN1D2200mA

L33DNI

BLM18KG221SN1D2200mA

TP278TP278

TP270TP270

TP133TP133

TP289TP289

TP65TP65

TP286TP286

TP304TP304

TP139TP139

TP258TP258

TP148TP148

TP263TP263

TP142TP142

TP140TP140

J5

QTH-060-02-L-D-A

J5

QTH-060-02-L-D-A1 23 45 67 89 10

11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 4849 5051 5253 5455 5657 5859 6061 6263 6465 6667 6869 7071 7273 7475 7677 7879 8081 8283 8485 8687 8889 9091 9293 9495 9697 9899 100

101 102103 104105 106107 108109 110111 112113 114115 116117 118119 120

121122123124

125126127128

TP256TP256

power delivery network analysis (rev. a) - ti. · pdf filepower delivery network analysis...

Documents