Power Reduction and Low Risk Implementation of UFS v2.0 Design

Hezi Saar

Staff Product Marketing Manager

Mobile Forum 2014 Copyright © 2014 Synopsys

AgendaAgenda

• UFS system overview and challenges

• Power saving features and techniques in UFS sub-systems

• Reducing risk for current and future UFS implementations

• MIPI IP Solutions for Mobile SoCs

• Q&A

UFS UFS System Overview and System Overview and ChallengesChallenges

StorageSoC

Un

iPro

Un

iPro

Tx

Rx UFS Host

ContrlRx

Tx

UF

S

De

vic

e Core

Systembus

• Achieving throughput goals can be challenging

• Best practices are required to maximize throughput

Un

iPro

Un

iPro

M-PHYM-PHY

UF

S

De

vic

e

Point to point topology

How to Overcome Throughput How to Overcome Throughput Challenges?Challenges?

• Configurable and scalable parameters assist in meeting required throughput

– Burst length (2…to 32)

– FIFOs / buffer sizes– FIFOs / buffer sizes

– Data bus widths (currently 64, scalable to 128)

– Number of outstanding requests

– Group acknowledge

SoC

Un

ipro

M-PHY

Tx

Rx UFS

Host

Contlr

Core

SystemBus

SW

Power Saving Features and Techniques in

UFS sub-SystemsUFS sub-Systems

• MPHY low power states– HIBERN8

– STALL

– SLEEP

• UniPro low power states– HIBERN8

UFS Power UFS Power Mode Mode State “Machine”State “Machine”

– HIBERN8

– SLEEP

• Further hooks – DEEP SLEEP

– DEEP STALL

UFS Power States

Additional Power Savings with Additional Power Savings with Low Low Power Power Features Features && TechniquesTechniques

• Clock Gating

– Reduces the dynamic power

• Power Gating – Multi power rails

– Reduces the leakage power– Reduces the leakage power

– Deep power saving in Hibernate power state

– Only a small portion of the entire UFS Controller hierarchy will be on ‘Always-On’ Power Domain; Rest of the core can be switched off

Clock Gating and Power GatingClock Gating and Power Gating

• Clock Gating at various functional states:

– UFS idle

– Hibernate

– Power gated Hibernate

– Non active Tx Burst

• Power Gating states supported:

– S/W Hibernate: DWC_ufshc can be power gated when S/W programs Hibernate Entry through UIC command interface

– Auto Hibernate: DWC_ufshc can be power gated in AH8 state

– In the above states, PSW power domain can be switched off to save power

• Always On Domain: Modules in this power domain are not switched off in Hibernate

• Power-Down Domain: Modules in this power

Multi Power Rails ImplementationMulti Power Rails Implementation

Modules in this power domain can be switched off in Hibernate

• Power Domains are well mated to the UniPro and MPHY layers

Power Savings Achieved Power Savings Achieved –– Few Few ExamplesExamples

%

• The numbers are normalized values with respect to Normal mode without any power saving technique applied

Reducing Risk for Current and Future UFS ImplementationsFuture UFS Implementations

Growth and Growth and Maturity in Mobile Maturity in Mobile DevicesDevices

MainstreamSmartphone

High EndSmartphone

Tablet

Portable PC

Desktop PC

Source: IDC Worldwide Quarterly Smart Connected Device Tracker, September 11, 2013

High End Mobile Market High End Mobile Market Commands Premium and Drives Commands Premium and Drives

InnovationInnovation

High end mobile device

• Feature-rich smartphones, tablets and laptops

• Multiple image sensors• Multiple image sensors

• Very high resolution display

High data traffic to the storage device

• Data transmission

• Image, video capture and playback

Development Costs Development Costs CContinue to ontinue to RRiseise

Future Speeds Demand Future Speeds Demand Scalable IP Features Scalable IP Features

• Scalable UFS Host and UniPro Controller IP features

– Without compromising on latency and operating frequency

• Wide and Flexible Data bus width

• Higher number of outstanding RTTs

• Out-of-order execution granularity on system bus side

• Future versions of the UFS Specification can (and will) • Future versions of the UFS Specification can (and will) demand higher throughput

– G3L2, G4L1

– G3L4, G4L2

• Architectural amenability to add Inline encryption schemes

Reducing Risk for Current and Future Reducing Risk for Current and Future

UFS UFS ImplementationsImplementations• UFS System should be:

– Driving and developing specifications for rapid adoption

• Compliant with latest JEDEC Universal Flash Storage (UFS) standard and

JEDEC UFS Host Controller interface specification

• Integrated with UniPro Controller, compliant with latest MIPI Alliance UniPro

specificationspecification

– Single traffic class

– Support M-PHY v3.x and access to attributes

• Gear4 Performance

– Low-power operation, small area, and low latency

– Deployed in UFS Host and Device ICs

MIPI IP Solutions for Mobile SoCsSoCs

Integrate HighIntegrate High--Quality UFS IP in Mobile Quality UFS IP in Mobile SoCsSoCs

Future Proof, Interoperable Host & Device Solution

UniPro v1.60

UFS Host v2.00

Fully Verified, Gear3

UFS Software DriversLinux, OS-less

Future Proof

M-PHY, UFS IP

Power Modes

CDinDoutC

UniPro v1.60

Fully Verified, Flexible

RMMI

Silicon-Proven M-PHY HS-Gear3 Compliant to v3.x

Compact and Configurable

Host and Device Customers

Prototyping System

Deployed

DesignWareDesignWare MIPI IP SolutionsMIPI IP Solutions

MIPI Connectivity IP between Various ICs

JEDEC

UFS v2.0

Contributor since 2006

Synopsys UFS Solution in ActionSynopsys UFS Solution in ActionReads HD Video Stream from UFS Device and Plays on PC

UFS Host

System

3rd PartyUFS Device

UFS Host Controller

M-PHY v3.0

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