Introduction Power Semiconductor ApplicationsPhilips SemiconductorsCHAPTER 1Introduction to Power Semiconductors1.1General1.2Power MOSFETS1.3High Voltage Bipolar Transistors1Introduction Power Semiconductor ApplicationsPhilips SemiconductorsGeneral3Introduction Power Semiconductor ApplicationsPhilips Semiconductors1.1.1An Introduction To Power DevicesTodays mains-fed switching applications make use of awide variety of active power semiconductor switches. Thischapter considers therange of power devicesonthe markettoday, making comparisons both in terms of their operationand their general areas of application. The P-N diode willbeconsideredfirst sincethisisthebasisof all activeswitches. This will be followed by a look at both 3 layer and4 layer switches.Before lookingat theswitchesletsbrieflyconsiderthevarious applications in which they are used. Virtually allmains fed power applications switch a current through aninductive load. This is the case even for resonant systemswhere the operating point is usually on the "inductive" sideof the resonance curve. The voltage that the switch isnormally required to block is, in the majority of cases, oneor twotimes themaximumrectifiedinput voltagedependingon the configuration used. Resonant applications are theexception to this rule with higher voltages being generatedby the circuit. For 110-240 V mains, the required voltageratings for the switch can vary from 200 V to 1600 V.Under normal operating conditions the off-state losses inthe switch are practically zero. For square wave systems,theon-statelosses(occurringduringtheon-time), areprimarily determinedby the on-state resistance which givesrise to an on-state voltage drop, VON. The (static) on-statelosses may be calculated from:At the end of the "ON" time the switch is turned off. Theturn-off current is normally high which gives rise to a lossdependent on the turn-off properties of the switch. Theprocess of turn-on will also involve a degree of power lossso it is important not toneglect the turn-on properties either.Most applications either involve a high turn-on current orthe current reaching its final value very quickly (high dI/dt).The total dynamic power loss is proportional to both thefrequency and to the turn-on and turn-off energies.The total losses are the sum of the on-state and dynamiclosses.The balance of these losses is primarily determined by theswitchused. If theon-statelossdominates, operatingfrequency will have little influence and the maximumfrequency of the device is limited only by its total delay time(the sum of all its switching times). At the other extreme adevice whose on-state loss is negligible compared with theswitchingloss, will belimitedinfrequencyduetotheincreasing dynamic losses.Fig.1Cross section of a silicon P-N diodeHighfrequencyswitchingWhenconsideringfrequencylimitation it is important to realise that the real issue is notjust the frequency, but also the minimum on-time required.For example, an SMPS working at 100 kHz with an almostconstant output power, will have a pulse on-time tPof about2-5s. This canbe compared with ahigh performance UPSworking at 10 kHz with low distortion which also requires aminimum on-time of 2 s. Since the 10 kHz and 100 kHzapplications considered here, require similar shorton-times, both may be considered high frequencyapplications.Resonant systems have the advantage of relaxing turn-onor turn-off or both. This however tends to be at the expenseof V-Aproduct of the switch. The relaxed switchingconditions imply that in resonant systems switches can beused at higher frequencies than in non resonant systems.When evaluating switches this should be taken intoaccount.PNCATHODEANODEPSTATIC .VON.ION(1)PDYNAMIC f .(EON+ EOFF) (2)PTOT .VON.ION+ f .(EON+ EOFF) (3)5Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.2Field distribution in the N- layerEHIGH RESISTIVITYThicknessEThicknessLOW RESITIVITYEINTERMEDIATE CASEThicknessCase 1 Case 2 Case 3At higher values of throughput power, the physical size ofcircuits increases and as a consequence, the strayinductances will also tend to increase. Since the requiredcurrents are higher, the energy stored in the strayinductances risessignificantly, which inturn meanstheinduced peak voltages also rise. As a result suchapplications force the use of longer pulse times, to keeplosses down, and protection networks to limit overshoot ornetworks to slow down switching speeds. In addition theuseof larger switches will also have consequences intermsof increasing the energy required to turn them on and offand drive energy is very important.So, apart fromthevoltageandcurrent capabilitiesofdevices, it isnecessarytoconsiderstaticanddynamiclosses, driveenergy, dV/dt, dI/dt andSafeOperating Areas.The silicon diodeSilicon is the semiconductor material used for all powerswitching devices. Lightly doped N-silicon is usually takenas the starting material. The resistance of this materialdepends upon its resistivity, thickness and total area.A resistor as such does not constitute an active switch, thisrequires an extra step which is the addition of a P-layer.The result is a diode of which a cross section is drawn inFig.1The blocking diodeSince all active devices contain a diode it is worthconsidering its structure in a little more detail. To achievethe high blocking voltages required for active powerswitches necessitates the presence of a thickN-layer. Towithstand a given voltage the N-layer must have the rightcombination of thickness and resistivity. Some flexibilityexists as to what that combination is allowed to be, theeffects of varying the combination are described below.Case 1: Wide N-layer and low resistivityFigure 2 gives the field profile in the N-layer, assuming thejunction formed with the P layer is at the left. The maximumfieldat theP-Njunctionislimitedto22 kV/cmbythebreakdown properties of the silicon. The field at the otherend is zero. The slope of the lineis determined by theresistivity. The total voltage across the N-layer is equal tothe area underneath the curve. Please note that increasingthethicknessof thedevicewouldnot contributetoitsvoltage capability in this instance. This is the normal fieldprofile when there is another P-layer at the back as in 4layer devices (described later).Case 2: Intermediate balanceIn this case the higher resistivity material reduces the slopeof the profile. The field at the junction is the same so thesame blocking voltage capability (area under the profile)can be achieved with a thinner device.The very steep profile at the right hand side of the profileindicates the presence of an N+layer which often requiredto ensure a good electrical contactCase 3: High resistivity materialWith sufficiently high resistivity material a near horizontalslopetothe electric field is obtained. It isthis scenariowhichwill give rise to the thinnest possible devices for the samerequired breakdown voltage. Again an N+layer is requiredat the back.An optimum thickness and resistivity exists which will givethelowest possibleresistancefor agivenvoltagecapability.Both case 1 (very thick device) and case 3 (high resistivity)give high resistances, the table belowshows the thicknessand resistivity combinations possible for a 1000 V diode.R . lA(4)6Introduction Power Semiconductor ApplicationsPhilips SemiconductorsThe column named RA gives the resistance area product.(A devicethicknessof less than50 mwillneveryield1000 V and the same goes for a resistivity of less than26 cm.) The first specification is for the thinnest devicepossibleand the last oneis for the thickest device, (requiredwhen a P layer is present at the back). It can be seen thatthelowest resistanceis obtainedwith an intermediate valueof resistivity and material thickness.Thickness Resistivity RA Comments(m) (cm) cm250 80 0.400 case 360 34 0.20465 30 0.19570 27 0.189 min. R75 26 0.19580 26 0.20890 26 0.234100 26 0.260 case 1To summarise, a designer of high voltage devices has onlya limited choice of material resistivity and thickness withwhich to work. The lowest series resistance is obtained fora material thickness and resistivity intermediate betweenthe possible extremes. This solution is the optimum for allmajority carrier devices such as the PowerMOSFET andthe J-FET where the on-resistance is uniquely defined bythe series resistance. Other devices make use of chargestorage effects to lower their on-state voltage.Consequently to optimise switching performance in thesedevices the best choice will be the thinnest layer such thatthe volume of stored charge is kept to a minimum. Finallyasmentioned earlier, the design of a 4layer device requiresthe thickest, low resistivity solution.The forward biased diodeWhen a diode is forward biased, a forward current will flow.Internallythis current will have twocomponents: anelectroncurrent which flows from the N layer to the P layer and aholecurrent inthe other direction. Both currents willgenerate a charge in the opposite layer (indicated with QPandQNin Fig.3). The highest dopedregion will deliver mostof the current and generate most of the charge. Thus in aP+ N- diode the current will primarily be made up of holesflowing from P to N and there will be a significant volumeof hole charge in the N-layer. This point is important whendiscussing activedevices: whenevera diode isforwardbiased (suchas abase-emitter diode) therewill be a chargestored in the lowest doped region.Fig. 3Diode in forward conductionThe exact volume of charge that will result is dependentamongst otherthingsontheminoritycarrier lifetime, .Using platinum or gold doping or byirradiation techniquesthe value of can be decreased. This has the effect ofreducing the volume of stored charge and causingit todisappear more quickly at turn-off. A side effect is that theresistivity will increase slightly.Three Layer devicesThe threebasic designs, which formthe basis for all derived3layer devices, are given in Fig.4. It should be emphasisedherethat the discussionis restricted tohigh voltage devicesonly as indicated in the first section. This means that allrelevant deviceswill haveavertical structure, characterisedby a wide N--layer.The figure shows how a three layer device can be formedby adding an N type layer to the P-N diode structure. Twoback to back P-N diodes thus form the basis of the device,where the P layer provides a means to control the currentwhen the device is in the on-state.TherearethreewaystousethisP-layer asacontrolterminal. The first is to feed current into the terminal itself.The current through the main terminals is nowproportionalto the drive current. This device is called a High VoltageTransistor or HVT.The second one is to have openings in the P-layer andpermit themaincurrent toflowbetweenthem. Whenreverse biasing the gate-source, a field is generated whichblocks the opening and pinches off the main current. Thisdevice is known as the J-FET (junction FET) or SIT (StaticInduction Transistor).PCATHODEANODEIpINQPQNNN-+7Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.4The three basic three layer devicesPNEMITTERCOLLECTOR-NBASEPNSOURCEDRAIN-NGATEPNSOURCEDRAIN-NGATEBIPOLAR TRANSISTOR J-FET (SIT) MOSN N NThe third version has an electrode (gate) placed very closeto the P-layer. The voltage on this gate pushes away theholes in the P-area and attracts electrons to the surfacebeneath the gate. A channel is thus formed between themain terminals so current can flow. The well known namefor this device is MOS transistor.In practice however, devices bear little resemblance to theconstructionsof Fig.4. Invirtuallyall casesaplanarconstruction is chosen i.e. the construction is such that onemain terminal (emitter or source) and the drive contact areon the surface of the device. Each of the devices will nowbe considered in some more detail.The High Voltage Transistor (HVT)The High Voltage Transistor uses a positive base currenttocontrol the main collector current. The relation is:IC = HFE * IB. Thebase driveforwardbiasesthebase emitterP-N junction and charge (holes and electrons) willpassthrough it. Now the base of a transistor is so thin that themost of the electrons do not flow to the base but into thecollector - giving rise to a collector current. As explainedpreviously, theratiobetweentheholes andelectronsdepend on the doping. So by correctly doping the baseemitter junction, the electron current can be made muchlarger than the hole current, which means that IC can bemuch larger than IB.Whenenoughbase driveis providedit is possibletoforwardbiasthebase-collector P-Njunctionalso. This has asignificant impact on the resistance of the N-layer; holesnowinjected fromthe P type base constitute stored chargecausingasubstantial reductioninon-stateresistance,much lowerthanpredictedbyequation4. Undertheseconditionsthecollector isaneffectiveextensionof thebase.Unfortunately the base current required to maintainthisFig.5The HVTcondition causes the current gain to drop. For this reasononecannot useaHVTat averyhighcurrent densitybecause then the gain would become impractically low.The on-state voltage of an HVT will be considerably lowerthan for a MOS or J-FET. This is its main advantage, buttheresultingchargestoredintheN- layer has tobedelivered and also to be removed. This takes time and thespeed of a bipolar transistor is therefore not optimal. Toimprovespeedrequires optimisationof afineemitterstructure in the form of fingers or cells.Both at turn-on and turn-off considerable losses may occurunless care is taken to optimise drive conditions. At turn-ona short peak base current is normally required. At turn-offa negative base current is required and negative drive hasto be provided.PCOLLECTORB B B E ENN-+N+ N+IBElectrons8Introduction Power Semiconductor ApplicationsPhilips SemiconductorsA serious limitation of the HVT is the occurrence of secondbreakdownduring switchoff. The current contracts towardsthe middle of the emitter fingers and the current density canbecomeveryhigh. TheRBSOAR(ReverseBiasSafeOperating Area) graph specifies where the device can beused safely. Device damage may result if the device is notproperly used and one normally needs a snubber (dV/dtnetwork) to protect the device. The price of such a snubberis normally in the order of the price of the transistor itself.In resonant applications it is possible to use the resonantproperties of the circuit to have a slow dV/dt.So, the bipolar transistor has the advantage of a very lowforward voltage drop, at the cost of lower speed, aconsiderable energy is required to drive it and there arealso limitations in the RBSOAR.The J-FET.The J-FET (Junction Field Effect Transistor) has a directresistancebetweentheSourceandtheDrainviatheopening in the P-layer. When the gate-source voltage iszero the device is on. Its on-resistance is determined by theresistance of the silicon and no charge is present to makethe resistance lower as in the case of the bipolar transistor.WhenanegativevoltageisappliedbetweenGateandSource, a depletion layer is formed which pinches off thecurrent path. So, the current through the switch isdetermined by the voltage on the gate. The drive energy islow, it consists mainly of the charging and discharging ofthe gate-source diode capacitance. This sort of device isnormally very fast.Fig.6The J-FETIts main difficulty is the opening in the P-layer. In order tospeed up performance and increase current density, it isnecessary to make a number of openings and this impliesfinegeometrieswhicharedifficult tomanufacture. AsolutionexistsinhavingtheP-layer effectivelyonthesurface, basically a diffused grid as shown in Fig.6.Unfortunately the voltages now required to turn the deviceoff may be very large: it is not uncommon that a voltage of25 V negativeisneeded. Thisisamajor disadvantagewhich, when combined with its "normally-on" property andthe difficulty to manufacture, means that this type of deviceis not in mass production.The MOS transistor.The MOS (Metal Oxide Semiconductor) transistor isnormallyoff: apositivevoltageisrequiredtoinduceachannel in the P-layer. When a positive voltage is appliedto the gate, electrons are attracted to the surface beneaththe gate area. In this way an "inverted" N-type layer isforced in the P-material providing a current path betweendrain and source.Fig.7The MOS transistorModerntechnologyallowsaplanar structurewithverynarrow cells as shown in Fig.7. The properties are quitelike the J-FET with the exception that the charge is nowacross the (normally very thin) gate oxide. Charging anddischargingthegateoxidecapacitancerequires drivecurrents when turning on and off. Switching speeds canbecontrolled bycontrollingthe amount of drivechargeduring the switching interval. Unlike the J-FET it does notrequire anegative voltagealthough anegative voltage mayhelp switch the device off quicker.The MOSFET is the preferred device for higher frequencyswitching sinceit combines fast speed, easy drive and widecommercial availability.DRAINS GNN-+SN+ N+P PDRAING G G S SP P PN+ N+NN-+9Introduction Power Semiconductor ApplicationsPhilips SemiconductorsRefinements to the basic structureAnumber of techniquesarepossibletoimproveuponbehaviour of the basic device.First, the use of finer geometries can give lower on-statevoltages, speed up devices and extend their energyhandling capabilities. This has led to improved"Generation 3" devices for bipolars and to lower RDS(ON) forPowerMOS. Secondly, killing the lifetime in the devicecanalsoyieldimprovements. For bipolar devices, thispositively effects the switching times. The gain, however,will drop, and this sets a maximumto the amount of lifetimekilling. For MOS a lower value for yields the so-calledFREDFETs, with an intrinsic diode fast enough for manyhalf bridge applications such as in AC Motor Controllers.Thepenalty hereis that RDS(ON)is adversely effected(slightly). Total losses, however, are decreasedconsiderably.Four layer devicesThe three basic designs from the previous section can beextended with a P+-layer at the back, thereby generatingthree basic Four Layer Devices. The addition of this extralayer creates a PNP transistor from the P+-N--P-layers. Inall casesthe 3layer NPNdevice will nowdeliver an electroncurrent into the back P+-layer which acts as an emitter. ThePNP transistor will thus become active which results in ahole current flowing fromthe P+-layer into the high resistiveregion. This in its turn will lead to a hole charge in the highresistive region which lowers the on-state voltageconsiderably, as outlined above for High VoltageTransistors. Again, the penalty is in the switching timeswhich will increase.All the devices with an added P+-layer at the back will injectholes into the N--layer. Since the P+-layer is much heavierdoped than the N--layer, this hole current will be the majorcontributor to the main current. This means that the chargein the N--layer, especially near the N--P+-junction, will belarge. Under normal operation the hole current will be largeenough to influence the injection of electrons from the topN+-layer. Thisresults inextraelectroncurrent beinginjected fromthe top, leading to extra hole current fromtheback etc. This situation is represented in the schematic ofFig.8.Animportant point islatching. Thishappenswhentheinternal currents are such that we are not able to turn offthe device using the control electrode. The only way to turnit off is by externally removing the current from the device.The switching behaviour of all these devices is affected bythe behaviour of the PNP: as long as a current is flowingthroughthedevice, thebackwill inject holesintotheN--layer. Thisleadstoswitchingtailswhichcontributeheavily to switching losses. The tail is strongly affected bythelifetime andby the application of negative drive currentwhen possible. As previously explained, adjustment of thelifetimeaffects the on-state voltage. Carefully adjusting thelifetime will balance the on-state losses with the switchinglosses.All four layer devices showthis trade-off between switchinglossesandon-statelosses. Whenminimising switchinglosses, the devices are optimisedfor high frequencyapplications. Whentheon-statelossesarelowest thecurrent density is normally highest, but the device is onlyuseful at low frequencies. So two variants of the four layerdevice generally exist. In some cases intermediate speedsare also useful as in the case of very high power GTOs.The ThyristorA thyristor (or SCR, Silicon Controlled Rectifier) isessentially an HVT with an added P+-layer. The resultingP--N--P+transistor is on when the whole device is on andprovides enough base current to the N+-P-N-transistor tostay on. So after an initial kick-on, no further drive energyis required.Fig.8ThyristorThe classical thyristor is thus a latching device. Itsconstruction is normally not very fine and as a result thegate contact is too far away from the centre of the activearea to be able to switch it off. Also the current density ismuchhigher thaninabipolar transistor. The switchingtimeshoweverareverylong. Itsturn-onishamperedbyitsstructure since it takes quite a while for the whole crystalto become active. This seriously limits its dI/dt.Once a thyristor is on it will only turn-off after having zerocurrent for a fewmicroseconds. This is done by temporarilyforcing the current via a so-called commutation circuit.PANODEG G CP+N-N+Ip2Ip110Introduction Power Semiconductor ApplicationsPhilips SemiconductorsThe charge in the device originates from two sources: ThestandardNPNtransistor structureinjects holes intheN--layer (IP1inFig.8) andthe PNPtransistor injects a chargefromthe back (IP2in Fig.8). Therefore the total charge is bigand switching performance is very poor. Due to its slowswitching a normal thyristor is only suitable up to a fewkHz.A major variation on the thyristor is the GTO(Gate Turn OffThyristor). This is a thyristor where the structure has beentailoredtogivebetter speedbytechniquessuchas accuratelifetimekilling, finefinger orcell structuresand"anodeshorts" (short circuiting P+and N-at the back in order todecreasethecurrent gainof thePNPtransistor). As aresult,theproduct of thegainof bothNPNandPNPisjust sufficientto keep the GTO conductive. A negative gate current isenough to sink the hole current from the PNP and turn thedevice off.Fig.9The GTOA GTO shows much improved switching behaviour but stillhas the tail as described above. Lower power applications,especially resonant systems, are particularly attractive forthe GTO because the turn-off losses are virtually zero.The SIThThe SITh (Static Induction Thyristor) sometimes alsoreferredto as FCT(Field Controlled Thyristor) is essentiallya J-FET with an added P+back layer. In contrast to thestandard thyristor, charge is normally only injected fromtheback, so the total amount of charge is limited. However, apositive gate drive is possible which will reduce on-stateresistance.Active extraction of charge via the gate contact is possibleand switchingspeedsmaybereducedconsiderablybyapplying an appropriate negative drive as in the case of anHVT. As for theSITthe technological complexity isasevereFig.10The SIThdrawback, as is its negative drive requirements.Consequently mass production of this device is notavailable yet.The IGBTAn IGBT (Insulated Gate Bipolar Transistor) isan MOStransistor with P+at the back. Charge is injected from theback only, which limits the total amount of charge. Activecharge extraction is not possible, so the carrier lifetime shouldbechosencarefully, sincethat determinestheswitching losses. Again two ranges are available with bothfast and slow IGBTs.Fig.11The IGBTANODEG G G C CP P PN+ N+NP-+PANODEG G G C CNP-+N+ N+N+N+COLLECTORE GN-EN+ N+P PP+11Introduction Power Semiconductor ApplicationsPhilips SemiconductorsThe speed of the fast IGBT is somewhat better than that ofa GTO because a similar technology is used to optimisethe IGBT but only the back P+-layer is responsible for thecharge.The IGBT is gaining rapidly in popularity since itsmanufacturing is similar to producing PowerMOS and anincreasing market availability exists. Although the latchingof IGBTswasseen asaproblem, modernoptimiseddevicesdont suffer from latch-up in practical conditions.Refinements to the basic structureThe refinements outlined for 3 layer devices also apply to4 layer structures. In addition to these, an N+-layer may beinserted between the P+and N--layer. Without such a layerthe designer is limited in choice of starting material to Case3asexplainedinthediodesection. AddingtheextraN+-layer allows another combination of resistivity andthickness to be used, improving device performance. Anexample of this is the ASCR, the Asymmetric SCR, whichis much faster than normal thyristors. The reverse blockingcapability, however, is now reduced to a value of 10-20 V.Comparison of the Basic Devices.It is important to consider the properties of devicesmentioned when choosing the optimumswitch for aparticular application. Table 2 gives a survey of theessential device properties of devices capable ofwithstanding 1000 V. IGBTs have been classed in termsof fast and slow devices, however only the fast GTO andslowthyristor arerepresented. Thefast devicesareoptimised for speed, the slow devices are optimised for Onvoltage.CommentsThistableisvalidfor 1000 Vdevices. Lower voltagedeviceswill alwaysperformbetter, higher voltagedevicesareworse.A dot means an average value in between "+" and "-"The "(--)" for a thyristor means a "--" in cases where forcedcommutation is used; in case of natural commutation it is"+"Most figures are for reference only: in exceptional casesbetterperformancehasbeenachieved, but thefiguresquoted represent the state of the art.HVT J-FET MOS THY GTO IGBT IGBT Unitslow fastV(ON) 1 10 5 1.5 3 2 4 VPositive Drive Requirement - + + + + + + + = Simple toimplementTurn-Off requirement - - + (--) - + + + = Simple toimplementDrive circuit complexity - . + (-) . + + - = complexTechnology Complexity + . . + - - - - = complexDevice Protection - . + + - - - + = Simple toimplementDelay time (ts, tq) 2 0.1 0.1 5 1 2 0.5 sSwitching Losses . ++ ++ -- - - . + = goodCurrent Density 50 12 20 200 100 50 50 A/cm2Max dv/dt (Vin = 0) 3 20 10 0.5 1.5 3 10 V/nsdI/dt 1 10 10 1 0.3 10 10 A/nsVmax 1500 1000 1000 5000 4000 1000 1000 VImax 1000 10 100 5000 3000 400 400 AOver Current factor 5 3 5 15 10 3 312Introduction Power Semiconductor ApplicationsPhilips SemiconductorsMerged devicesMerged devices are the class of devices composed of twoor more of the above mentioned basic types. They dontoffer anybreakthroughindeviceperformance. Thisisunderstandable since the basic properties of the discusseddevicesarenot or arehardlyeffected. They maybebeneficial for the user though, primarily because they mayresult in lower positive and/or negative drive requirements.Darlingtons and BiMOSA darlington consists of two bipolar transistors. The emittercurrent of the first (the driver) forms the base current of theoutput transistor. The advantages of darlingtons may besummarised as follows. A darlington has a higher gain thanasingle transistor. It also switches faster because the inputtransistor desaturates the output transistor and lowerswitchinglossesaretheresult. However, theresultingVCE(sat)ishigher. Themain issue, especiallyforhigherpowers isthe savings indrive energy. This meansthatdarlingtonscanbeusedat considerablyhigher outputpowers than standard transistors. Modern darlingtons inhigh power packages can be used in 20 kHz motor drivesand power supplies.A BiMOS consists of a MOS driver and a bipolar outputtransistor. The positivedrive isthe sameas MOSbutturn-off is generally not so good. Adding a"speed-up" diodecoupled with some negative drive improves things.Fig.12The MCTMCTMCT stands for MOS Controlled Thyristor. This device iseffectively a GTO with narrow tolerances, plus a P-MOStransistor between gate and source (P+-N-P MOS, the lefthand gate in Fig.12) and an extra N-MOS to turn it on, theN-P-N--MOS shown underneath the right hand gate.Wherethe GTOwouldlike tobeswitchedoff with anegativegate, the internal GTO in an MCT can turn off by shortcircuiting its gate-cathode, due to its fine structure. Its drivetherefore is like a MOS transistor and its behaviour similarto a GTO. Looking closely at the device it is obvious thataGTOusingsimilar finegeometries with asuitable externaldrive can always perform better, at the cost of some drivecircuitry. The only plus point seems to be its ease of drive.Application areas of the various devicesThefollowingsectiongivesanindicationof wherethevarious devices are best placed in terms of applications. Itispossible for circuit designerstousevarioustrickstointegratedevicesandsystemsininnovativemanners,applying devices far outside their normal operatingconditions. As an example, it is generally agreedthat above100 kHz bipolars aretoo difficult touse. However, a450 kHz converter using bipolars has been alreadydescribed in the literature.As far as the maximum frequency is concerned a numberof arguments must be taken into account.First thedelaytimes, either occurringat turn-onor atturn-off, will limit themaximumoperatingfrequency. Areasonable rule of thumb for this is fMAX = 3 / tDELAY. (Thereisa dangerhereforconfusion: switchingtimestendtodepend heavily on circuit conditions, drive of the device andon current density. This may lead to a very optimistic orpessimistic expectation and care should be taken toconsider reasonable conditions.)Another factor istheswitchinglosseswhichareproportionalto the frequency. These power losses may be influencedby optimising the drive or by the addition of external circuitssuch as dV/dt or dI/dt networks. Alternatively the heatsinksizemaybeincreasedor onemaychoosetooperatedevices at a lower current density in orderto decreasepower losses. It isclear that thisargument isvery subjective.A third point is manufacturability. The use of fine structuresfor example, whichimprovesswitchingperformance, ispossible only for small silicon chip sizes: larger chips withvery fine MOS-like structures will suffer fromunacceptablelowfactory yields. Therefore high power systems requiringlargechipareasareboundtobemadewithlessfinestructures and will consequently be slower.The operating current density of the device will influenceits physical size. A lowcurrent density device aimed at highpower systems would need a large outline which tends tobeexpensive. Largeoutlines alsoincreasethephysical sizeof the circuit, which leads to bigger parasitic inductancesand associated problems.ANODENP-+NG C GP+ P+N N +P13Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.13Comparison of device operating regions10 MHz1 MHz100 kHz10 kHz1 kHz100 Hz100VA 1kVA 10kVA 100kVA 1MVA 10MVA 100MVADARLINGTONS HVTRESONANT SYSTEMSSQUARE WAVE SYSTEMSTHYRISTOR(fast)(fast)-IGBT-(slow)SITr SIThMOSGTO (slow)High power systems will, because of the mechanical size,be restricted in speed as explained earlier in the text . Thiscoincides well with the previously mentioned slowercharacter of higher power devices.Last but not least it is necessary to take the applicationtopology into account. Resonant systems allow the use ofconsiderablyhigher frequencies, sinceswitchinglossesareminimised. Square wave systems cause more losses in thedevices and thus restrict the maximumfrequency. To makea comparison of devicesand provide insight into whichpowers are realistic for which devices we have to take allthe above mentioned criteria into account.Figure 13 shows the optimumworking areas of the variousswitching devices as a function of switchable power andfrequency. The switchable power is defined as IAV timesVMAX as seen by the device.As an example, darlingtons will work at powers up to 1MVAi.e. 1000 V devices will switch 1000 A. The frequency isthenlimited to 2.5 kHz. At lower powers higher frequenciescan be achieved however above 50 kHz, darlingtons arenot expected to be used. One should use this table only asguidance; usingspecial circuit techniques, darlingtonshaveactuallybeen used at higher frequencies. Clearly operationat lower powers and frequencies is always possible.ConclusionsThestartingmaterial for activedevicesaimedat highvoltageswitching aremade on siliconof which theminimumresistivity and thickness are limited. This essentiallydetermines device performance, since all active switchesincorporate such a layer. Optimisation can be performedfor either minimum thickness, as required in the case ofHVTs, or for minimumresistance, as required for MOS andJ-FETs. The thickest variation(lowest resistivity) isrequiredin the case of some 4 layer devices.Basically three ways exist to control current through thedevices: feeding a base current into a P-layer (transistor),14Introduction Power Semiconductor ApplicationsPhilips Semiconductorsusing a voltage to pinch-off the current through openingsin the P-layer (J-FET) and by applying a voltage onto a gatewhich inverts the underlying P-layer (MOS).The HVT is severely limited in operating frequency due toits stored hole charge, but this at the same time allows agreater current density and a lower on-state voltage. It alsorequires more drive energy than both MOS and J-FET.When we add a P+-layer at the back of the three basic threelayer devices we make three basic four layer devices. TheP+-layer producesaPNPtransistor at thebackwhichexhibits hole storage. This leads to much improved currentdensities and lower on-state losses, at the cost of switchingspeed. The four layer devices can be optimised for lowon-state losses, in which case the switching will be poor,or for fast switching, in which case the on-state voltage willbe high.The properties of all six derived basic devices aredeterminedtoalargeextent by thedesignof thehighresistive area and can be optimised by applyingtechnological features in the devices such as lifetime killingand fine geometries.Resonant systems allowdevices to be used at much higherfrequenciesduetothelower switchinglossesandtheminimumon-timeswhichmaybelonger, comparedtosquarewaveswitchingsystems. Figure13givestheexpected maximum frequency and switching power for thediscusseddevices. Thedifferencefor squarewavesystemsand resonant systems is about a factor of 10.15Introduction Power Semiconductor ApplicationsPhilips SemiconductorsPower MOSFET17Introduction Power Semiconductor ApplicationsPhilips Semiconductors1.2.1PowerMOS IntroductionDevice structure and fabricationThe idea of a vertical channel MOSFET has been knownsince the 1930s but it was not until the mid 1970s that thetechnology of diffusion, ion implantation and materialtreatment hadreachedthelevel necessarytoproduceDMOSonacommercial scale. Thevertical diffusiontechniqueusestechnologymorecommonlyassociatedwith the manufacture of large scale integrated circuits thanwithtraditional power devices. Figure1(a) shows thevertical double implanted (DIMOS) channel structurewhichis the basis for all Philips power MOSFET devices.An N-channel PowerMOS transistorisfabricated onanN+substrate with a drain metallization applied to itsunderside. Above the N+substrate is an N-epi layer, thethickness and resistivity of which depends on the requireddrain-source breakdown voltage. The channel structure,formed froma double implant in to the surface epi material,is laid down in a cellular pattern such that many thousandsof cells go to make a single transistor. The N+polysilicongatewhich is embeddedin an isolating silicon dioxidelayer,is a single structure which runs between the cells acrossthe entire active region of the device. The sourcemetallizationalsocoverstheentirestructureandthusparallels all the individual transistor cells on the chip. Thelayout of a typical lowvoltage chip is shown in Fig.1(b). Thepolysilicon gate is contacted by bonding to the defined padareawhilethesourcewiresarebondeddirectlytothealuminium over the cellarray. The back of the chip ismetallizedwith atriplelayer of titanium/nickel/silver andthisenables the drain connection to be formed usinga standardalloy bond process.Theactivepart of the deviceconsists of many cellsconnectedinparallel togive ahigh current handlingcapability wherethe current flowisvertical through the chip.Cell density is determined by photolithographic tolerancerequirements in definingwindows inthe polysilicon andgate-source oxide and also by the width of the polysilicontrack between adjacent cells. The optimumvalue forpolysilicon track width and hence cell density varies as afunctionof device drain-source voltage rating, this isexplained in more detail further in the section. Typical celldensitiesare 1.6 million cells per square inchfor lowvoltagetypes and 350,000 cells per square inch for high voltagetypes. The cell array is surrounded by an edge terminationstructure to control the surface electric field distribution inthe device off-state.Fig.1(a)Power MOSFET cell structure.19Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.1(b)Plan view of a low voltage Power MOS chip20Introduction Power Semiconductor ApplicationsPhilips SemiconductorsA cross-section through a single cell of the array is shownin Fig.2. The channel length is approximately 1.5 micronsand is defined by the difference in the sideways diffusionof the N+source and the P-body. Both these diffusions areauto-aligned to the edge of the polysilicon gate during thefabricationprocess. All diffusionsareformedbyionimplantation followed by high temperature anneal/drive-intogivegoodparameter reproducibility. Thegateiselectrically isolated from the silicon by an 800 Angstromlayer of gate oxide (for standard types, 500 Angstrom forLogiclevel andfromthe overlyingaluminiumby athick layerof phosphorus doped oxide. Windows are defined in thelatter oxide layer to enable the aluminium layer to contactthe N+source and the P+diffusion in the centre of each cell.TheP+diffusionprovidesalowresistanceconnectionbetween the P-body and ground potential, thus inhibitingturn-on of the inherent parasitic NPN bipolar structure.Fig.2 Cross-section of a single cell.Device operationCurrent flow in an enhancement mode power MOSFET iscontrolled by the voltage applied betweenthe gate andsource terminals. The P-body isolates the source anddrainregions and forms two P-N junctions connectedback-to-back. With both the gate and source at zero voltsthere is no source-drain current flow and the drain sits atthe positive supply voltage. The only current which can flowfrom source to drain is the reverse leakage current.As the gate voltage is gradually made more positive withrespect to the source, holes are repelled and a depletedregionof silicon is formedinthe P-body belowthesilicon-gateoxideinterface. Thesiliconisnowinadepleted state, but there is still no significant current flowbetween the source and drain.When the gate voltage is further increased a very thin layerof electrons is formed at the interface between the P-bodyand the gate oxide. This conductive N-type channelenhanced by the positive gate-source voltage, nowpermitscurrent to flow from drain to source. The silicon in the P-body is referred to as being in an inverted state. A slightincreaseingatevoltagewill result inaverysignificantincrease in drain current and a corresponding rapiddecreasein drain voltage, assuminga normal resistive loadis present.Eventually the drain current will be limited by the combinedresistancesof theloadresistor andtheRDS(ON)of theMOSFET. The MOSFET resistance reaches a minimumwhen VGS= +10 volts (assuming a standard type).Subsequentlyreducingthegatevoltage tozerovoltsreverses the above sequence of events. There are nostored charge effects since power MOSFETS are majoritycarrier devices.Power MOSFET parametersThreshold voltageThe threshold voltage is normally measured by connectingthegate tothe drain andthen determiningthe voltagewhichmust beappliedacrossthedevicestoachieveadraincurrent of 1.0 mA. This method is simple to implement andprovides a ready indication of the point at which channelinversion occurs in the device.The P-body is formed by the implantation of boron throughthe tapered edge of the polysilicon followed by an annealanddrive-in. The main factors controlling threshold voltageare gate oxide thickness and peak surface concentrationin the channel, which is determined by the P-body implantdose. To allow for slight process variation a window isusually defined which is 2.1 to 4.0 volts for standard typesand 1.0 to2.0 volts for logic level types.Positivechargesinthegateoxide, forexampleduetosodium, can cause the threshold voltage to drift. Tominimise this effect it is essential that the gate oxide isgrownunder ultracleanconditions. Inadditionthepolysilicon gate and phosphorus doped oxide layer providea good barrier to mobile ions such as sodium and thus helpto ensure good threshold voltage stability.Drain-source on-state resistanceThe overall drain-sourceresistance, RDS(ON), of apowerMOSFET is composed of several elements, as shown inFig.3.The relative contribution from each of the elements varieswiththedrain-sourcevoltagerating. For lowvoltagedevices the channel resistance is very important while forN- EPI LayerN+ SubstrateDRAINSOURCEP- P-P+N+ N+GATE20 um21Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.3 Power MOSFET components of RDS(ON).the high voltage devices the resistivity and thickness of theepitaxial layer dominates. The properties of the variousresistive components will now be discussed:Channel. The unit channel resistance is determined by thechannel length, gate oxidethickness, carrier mobility,threshold voltage, and the actual gate voltage applied tothedevice. The channel resistance for agiven gatevoltagecan be significantly reduced by lowering the thickness ofthe gateoxide. This approach is used tofabricate the LogicLevel MOSFETtransistorsandenablesasimilarvalueRDS(ON) to be achieved with only 5 volts applied to the gate.Of course, the gate-source voltage rating must be reducedto allow for the lower dielectric breakdown of the thinneroxide layer.Theoverall channel resistanceof adeviceisinverselyproportional tochannel width, determinedbythetotalperipheryof thecell windows. Channel widthisover200 cmfor a 20 mm2lowvoltagechip. The overall channelresistance can be significantly reduced by going to highercell densities, sincethecell peripheryper unit areaisreduced.Accumulationlayer. The silicon interfaceunder the centreof the gate track is accumulated when the gate is biasedabovethethresholdvoltage. Thisprovides alowresistancepath for the electrons when they leave the channel, prior toentering the bulk silicon. This effect makes a significantcontribution towards reducing the overall RDS(ON).Parasitic JFET. After leaving the accumulation layer theelectrons flow vertically down between the cells into thebulk of the silicon. Associated with each P-Njunction thereis a depletion region which, in the case of the high voltagedevices, extends several micronsintotheNepitaxial region,even under zerobias conditions. Consequently the currentpath for the electrons is restricted by this parasitic JFETstructure. The resistance of the JFET structure can bereduced byincreasing the polysilicontrack width. Howeverthis reduces the cell density. The need for compromiseleads to an optimumvalue for the polysilicon track width fora given drain-source voltage rating. Since the zero-biasdepletion width is greater for low doped material, then awider polysilicon track width is used for high voltage chipdesigns.Spreading resistance. As the electrons move further intothe bulk of the silicon they are able to spread sideways andflow under the cells. Eventually paths overlap under thecentre of each cell.Epitaxial layer. The drain-source voltage ratingrequirements determine the resistivity and thickness of theepitaxial layer. For high voltage devices the resistance ofthe epitaxial layer dominates the overall value of RDS(ON).Substrate. Theresistanceof theN+substrateisonlysignificant in the case of 50 V devices.Wires and leads. In a completed device the wire and leadresistances contribute a fewmilli-ohms totheoverallresistance.For all the above components the actual level of resistanceis a function of the mobility of the current carrier. Since themobility of holes is much lower than that of electrons theresistance of P-Channel MOSFETs is significantly higherthan that of N-Channel devices. For this reason P-Channeltypes tend to be unattractive for most applications.Drain-source breakdown voltageThe voltage blocking junction in the PowerMOS transistoris formedbetween the P-body diffusion andthe N-epi layer.For any P-N junction there exists a maximum theoreticalbreakdown voltage, which is dependent on doping profilesand materialthickness. Forthe caseof theN-channelPowerMOStransistor nearlyall theblockingvoltageissupported by the N-epi layer. The ability of the N-epi layertosupport voltageisafunctionof its resistivityandthicknesswhereboth must increase to accommodate a higherbreakdownvoltage. Thishasobviousconsequencesinterms of drain-source resistance with RDS(ON)beingapproximatelyproportional toBVDSS2.5. It isthereforeimportant todesignPowerMOSdevicessuchthat thebreakdown voltageis as close as possible to the theoreticalmaximum otherwise thicker, higher resistivity material hasto be used. Computer models are used to investigate theinfluence of cell design and layout on breakdown voltage.Since these factors also influence the on-state andswitching performances a degree of compromise isnecessary.To achieve a high percentage of the theoretical breakdownmaximum it is necessary to build edge structures aroundthe activearea of the device. Theseare designed to reducethe electric fields which would otherwise be higher in theseregions and cause premature breakdown.22Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFor low voltage devices this structure consists of a fieldplate design, Fig.4. The plates reduce the electric fieldintensity at the corner of the P+guard ring which surroundsthe active cell area, and spread the field laterally along thesurface of the device. The polysilicon gate is extended toformthefirst fieldplate, whilst thealuminiumsourcemetallizationformsthesecondplate. Thepolysiliconterminationplate which is shorted to the drain in the cornersof thechip(not shownonthediagram) operatesasachannel stopper. This prevents any accumulation ofpositive charge at the surface of the epi layer and thusimproves stability. Aluminium overlaps the terminationplate and provides a complete electrostatic screen againstany external ionic charges, hence ensuring good stabilityof blocking performance.Fig.4 Field plate structure for low voltage devices.For high voltage devices aset of floatingP+rings, see Fig.5,is used to control the electric field distribution around thedevice periphery. The number of rings in the structuredepends on the voltage rating of the device, eight rings areused for a 1000 volt type such as the BUK456-1000A. Athree dimensional computer model enables the optimumringspacing tobedetermined sothat each ringexperiencesa similar field intensity as the structure approachesavalanchebreakdown. Theringsarepassivatedwithpolydox which acts as an electrostatic screen and preventsexternal ionic charges inverting the lightly doped N-interfacetoformP-channelsbetweentherings. Thepolydox is coated with layers of silicon nitride andphosphorus doped oxide.All types have a final passivation layer of plasma nitride,which acts as a further barrier to mobile charge and alsogives anti-scratch protection to the top surface.Fig.5 Ring structure for high voltage devices.Electrical characteristicsThe DC characteristicIf a dc voltage source is connected across the drain andsourceterminalsof anNchannel enhancement modeMOSFET, with the positive terminal connected to the drain,thefollowing characteristicscan beobserved. With the gateto source voltage held below the threshold level negligiblecurrent will flow when sweeping the drain source voltagepositive from zero. If the gate to source voltage is takenabove the threshold level, increasing the drain to sourcevoltage will cause current to flow in the drain. This currentwill increase as the drain-source voltage is increased up toapoint knownasthepinchoff voltage. Increasingthedrain-sourceterminal voltageabovethisvaluewill notproduce any significant increase in drain current.Thepinchoff voltagearisesfromarapidincreaseinresistance which for any particular MOSFET will dependon the combination of gate voltage and drain current. In itssimplest form, pinch off willoccur when the ohmic dropacross the channel region directly beneath the gatebecomes comparable to the gate to source voltage. Anyfurther increase in drain current would now reduce the netvoltage across the gate oxide to a level which is no longersufficient to induce a channel. The channel is thus pinchedoff at its edge furthest from the source N+(see Fig.6).Atypical set of output characteristics is shown in Fig.7. Thetwo regions of operation either side of the pinch off voltagecan be seen clearly. The region at voltages lower than thepinchoff valueisusuallyknownastheohmicregion.Saturation region is the term used to describe that part ofthe characteristic abovethe pinch-off voltage. (NBThisdefinition of saturation is different to that used for bipolardevices.)N- EPI LayerP+N+P-LOPOXLPCVD NITRIDEPOLYDOXP+P+ P+ P+SourceGuardRingFloating Guard RingsN- EPI LayerN+ SubstrateP+P-N+Guard RingPolysiliconSourceMetallizationGate Ring Source Ring PolysiliconTerminationPlate(Source)23Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.6Pinch off in a Power MOSFETFig.7A typical dc characteristic for an N-channelenhancement mode MOSFET.The switching characteristicsTheswitchingcharacteristicsof aPowerMOSFETaredetermined largely by the various capacitances inherent inits structure. These are shown in Fig.8.To turn the device on and off the capacitances have to bechargedanddischarged, therateat which thiscanbeachieved is dependent on the impedance and the currentsinking/sourcing capability of the drive circuit. Since it isonly the majority carriers that are involved in the conductionprocess, MOSFETs do not suffer from the same storagetime problems which limit bipolar devices where minoritycarriershavetoberemovedduringturn-off. For mostapplications therefore the switching times of the PowerFig.8. The internal capacitances of a Power MOSFET.MOSFET are limited only by the drive circuit and can bevery fast. Temperature has only a small effect on devicecapacitances therefore switching times are independent oftemperature.In Fig.9 typical gate-source and drain-source voltages fora MOSFET switching current through a resistive load areshown. The gate source capacitance needs to be chargedup to a threshold voltage of about 3 V before the MOSFETbegins toturn on. The time constant for this is CGS(RDR+RG)and the time taken is called the turn-on delay time (tD(ON)).As VGSstarts to exceed the threshold voltage the MOSFETbegins to turn on and VDSbegins to fall. CGD now needs tobe discharged as well as CGS being charged so the timeconstant is increased and the gradient of VGS is reduced.As VDS becomes less than VGS the value of CGD increasessharply since it is depletion dependent. A plateau thusoccurs in the VGS characteristic as the drive current goesinto the charging of CGD.VGS10 VOhmic Drop7 V3 V Net Gate to Channel10 V Gate to ChannelPolysilicon GateGate OxideP-SourceChannelN-Pinch OffId+DSGCgsCgdCds0VDS / VID / A BUK4y8-800A20 15 10 5 0 4564.55.51010 20 30VGS / V =24Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.9. The switching waveforms for a MOSFET.0 0.2 0.4 0.6 0.8 1 1.250 40 30 20 10 0 Time (Microseconds)Voltage (Volts)Drain-Source VoltageGate-Source VoltageTurn-on Turn-offWhen VDShas collapsed VGS continues to rise as overdriveis applied. Gate overdriveisnecessary toreduce theon-resistanceof the MOSFETandthereby keep power lossto a minimum.ToturntheMOSFEToff theoverdrivehasfirst toberemoved. The charging path for CGDand CDSnowcontainstheloadresistor (RL) andsotheturn-off timewill begenerally longer than the turn-on time.The Safe Operating AreaUnlike bipolar devices Power MOSFETs do not suffer fromsecond breakdown phenomena when operated within theirvoltagerating. Essentially therefore the safe operating areaof aPower MOSFETisdeterminedonlybythepowernecessary toraise its junctiontemperatureto theratedmaximum of 150 C or 175 C(which TJMAX depends onpackage and voltage rating). Whether a MOSFET is beingoperated safely with respect to thermal stress can thus bedetermined directly from knowledge of the power functionapplied and the thermal impedance characteristics.Asafeoperatingareacalculatedassumingamountingbasetemperature of 25 C is shown in Fig.10 for a BUK438-800device. This plot shows the constant power curves for avariety of pulse durations ranging from dc to 10 s. Thesecurves represent the power levels which will raise Tj up tothe maximum rating. Clearly for mounting basetemperatures higher than 25 C the safe operating area issmaller. In addition it is not usually desirable to operate the25Introduction Power Semiconductor ApplicationsPhilips Semiconductorsdevice at its TJMAX rating. These factors can be taken intoaccount quite simply where maximum power capability fora particular application is calculated from:Tj is the desired operating junction temperature (must beless than Tjmax)Tmb is the mounting base temperatureZth is the thermal impedance taken from the data curvesThe safe operating areais boundedby a peak pulse currentlimit and a maximum voltage. The peak pulse current isbased on a current above which internal connections maybe damaged. The maximumvoltage is an upper limit abovewhich the device may go into avalanche breakdown.Fig.10. The Safe Operating Area of the BUK438-800.In a real application the case temperature will be greaterthan25 Cbecauseof thefinitethermal impedanceofpractical heatsinks. Alsoajunctiontemperatureof between80 C and 125 Cwould be preferable since this improvesreliability. If anominal junctiontemperatureof 80 Cinstead of 150 C is used then the ability of the MOSFETto withstand current spikes is improved.Causes of Power LossThere are four main causes of power dissipation inMOSFETs.Conductionlosses - The conduction losses (PC) are givenby equation (1).It is important to note that the on-resistance of the MOSFETwhen it is operated in the Ohmic region is dependent onthe junction temperature. On-resistance roughly doublesbetween 25 C and 150 C, the exact characteristics areshown in the data sheets for each device.Switching losses - When a MOSFET is turned on or off itcarries a large current and sustains a large voltage at thesame time. There is therefore a large power dissipationduring the switching interval. Switching losses arenegligibleat lowfrequenciesbut aredominant at highfrequencies. The cross-over frequency depends on thecircuit configuration. For reasons explained in the sectionon switching characteristics, a MOSFET usually turns offmore slowly than it turns on so the losses at turn-off will belarger thanat turn-on. Switchinglosses arevery dependenton circuit configuration since the turn-off time is affected bythe load impedance.Turn-off losses maybereducedby the use of snubbercomponents connectedacross the MOSFETwhich limit therate of rise of voltage. Inductors can beconnected in serieswiththe MOSFETtolimit the rate of rise of current at turn-onand reduce turn-on losses. With resonant loads switchingcan take place at zero crossing of voltage or current soswitching losses are very much reduced.Diode losses - These losses only occur in circuits whichmake use of the antiparallel diode inherent in the MOSFETstructure. A good approximation to the dissipation in thediode is the product of the diode voltage dropwhich istypically less than 1.5 V and the average current carried bythe diode. Diode conduction can be useful in such circuitsas pulse width modulated circuits used for motor control, insomestepper motor drive circuits and in voltage fed circuitsfeeding a series resonant load.Gate losses - The losses in the gate are given in equation2whereRGistheinternal gateresistance, RDRistheexternaldrive resistance, VGSD is the gate drive voltage and CIP isthecapacitanceseenat theinput tothegateof theMOSFET.The input capacitance varies greatly with the gate drainvoltage so the expression in equation 3 is more useful.(3)Where QG is the peak gate charge.Parallel OperationIf power requirements exceed those of available devicesthenincreasedpower levelscan beachieved by parallellingdevices. Parallellingof devicesismadeeasier usingPmax (Tj Tmb)Zth10 1000VDS / VID / A100 10 1 0.1 100 us 1 ms10 msRDS(ON) = VDS/ID 100 ms DC 10 us tp =BUK438-800100ABPG CIP.VGSD2.f .RG(RG + RDR)(2)PG QG.VGSD.f .RG(RG + RDR)(3)PC ID2.RDS(ON)(1)26Introduction Power Semiconductor ApplicationsPhilips SemiconductorsMOSFETs becausethey havea positivetemperaturecoefficient of resistance. If oneparallelledMOSFETcarriesmorecurrent thantheothersit becomeshotter. Thiscauses the on-resistance of that particular device tobecome greater than that of the others and so the currentin it reduces. This mechanism opposes thermal runawayin one of the devices. The positive temperature coefficientalso helps to prevent hot spots within the MOSFET itself.Applications of Power MOSFETsPower MOSFETs are ideally suited for use in manyapplications, someof whicharelistedbelow. Furtherinformationonthe major applications is presented insubsequent chapters.Chapter 2: Switched mode power supplies (SMPS)Chapter 3: Variable speed motor control.Chapter 5: Automotive switching applications.ConclusionsIt can be seen that the operation of the Power MOSFET isrelatively easy to understand. The advantages of fastswitching times, ease of parallelling and low drive powerrequirements make the device attractive for use in manyapplications.27Introduction Power Semiconductor ApplicationsPhilips Semiconductors1.2.2Understanding Power MOSFET Switching BehaviourPower MOSFETs are well known for their ease of drive andfast switchingbehaviour. Being majoritycarrierdevicesmeans they are free of the charge storage effects whichinhibit the switching performance of bipolar products. Howfast a Power MOSFETwillswitch isdetermined by thespeed at which its internal capacitances can be chargedand discharged by the drive circuit. MOSFET switchingtimes are often quoted as part of the device data howeveras an indication as to the true switching capability of thedevice, these figures are largely irrelevant. The quotedvalues are only a snapshot showing what will be achievedunder the stated conditions.This report sets out to explain the switching characteristicsof Power MOSFETs. It will consider the main features ofthe switching cycle distinguishing between what is devicedeterminant and what can be controlled by the drive circuit.Therequirements for the drivecircuit are discussedintermsof the energy that it must supply as well as the currents itis required to deliver. Finally, howthe drive circuitinfluencesswitchingperformance, interms of switchingtimes, dV/dt and dI/dt will be reviewed.Voltage dependent capacitanceThe switching characteristics of the Power MOSFET aredetermined by its capacitances. These capacitances arenot fixed but are a function of the relative voltages betweeneach of the terminals. To fully appreciate Power MOSFETswitching, it is necessary to understand what gives rise tothis voltage dependency.Parallel plate capacitance is expressed by the well knownequationwherea istheareaof theplates, distheseparatingdistance and is the permittivity of the insulating materialbetween them. For a parallel plate capacitor, the plates aresurfaces on which charge accumulation / depletion occursin response to achange in the voltageapplied across them.In a semiconductor, static charge accumulation / depletioncan occur either across a PN junction or at semiconductorinterfaces either side of a separating oxide layer.i) P-N junction capacitanceThe voltage supporting capability of most powersemiconductors is providedby a reversebiased P-Njunction. The voltageis supportedeither side of the junctionby a region of chargewhich isexposedby the appliedvoltage. (Usually referredtoas thedepletionregionbecause it is depleted of majority carriers.) Fig.1 showshow the electric field varies across a typical P-N-junctionfor a fixed dc voltage. The shaded area beneath the curvemust be equal to the applied voltage. The electric fieldgradient is fixed, independent of the applied voltage,according to the concentration of exposed charge. (This isequal to the background doping concentration used duringdevice manufacture.) A slight increase in voltage abovethis dclevel will requirean extensionof thedepletion region,and hence more charge to be exposed at its edges, this isillustrated in Fig.1. Conversely a slight reduction in voltagewill cause the depletion region to contract with a removalof exposed charge at its edge. Superimposing a small acsignal on the dc voltage thus causes charge to be addedandsubtractedat either side of the depletion regionof widthd1. The effective capacitance per unit area isSince the depletion regionwidth is voltage dependent it canbe seen from Fig.1 that if the dc bias is raised to say V2,the junction capacitance becomesJunction capacitance is thus dependent on applied voltagewith an inverse relationship.Fig.1Voltage dependence of a PN junctioncapacitanceii) Oxide capacitanceFig.2 shows twosemiconductor layersseparated by aninsulating oxide. In this case the surface layer is polysilicon(representative of the PowerMOS gate structure) and thelowerlayer isaP-typesubstrate. Applyinganegativevoltagetotheupper layer withrespect tothelower will causepositive charge accumulation at the surface of the P-dopedC1 d12C2 d23Exd1d2V1V2 N type siliconP type siliconC ad129Introduction Power Semiconductor ApplicationsPhilips Semiconductorsmaterial(positivelycharged holesof the P materialareattracted by the negative voltage). Any changes in thisapplied voltage will cause a corresponding change in theaccumulation layer charge. The capacitance per unit areais thuswhere t = oxide thicknessApplyingapositivevoltagetothe gatewill causeadepletionlayer to form beneath the oxide, (ie the positively chargedholes of the P-material are repelled by the positive voltage).The capacitance will nowdecrease with increasing positivegate voltage as a result of widening of the depletion layer.Increasing the voltage beyond a certain point results in aprocessknownasinversion; electronspulledintotheconduction bandby theelectric fieldaccumulate at thesurface of the P-type semiconductor. (The voltageat whichthis occurs is the threshold voltage of the power MOSFET.)Once the inversion layer forms, the depletion layer widthwill not increase with additional dc bias andthe capacitanceisthusat itsminimumvalue. (NB theelectronchargeaccumulation at the inversion layer cannot follow a highfrequencyacsignal inthestructureof Fig.2, sohighfrequency capacitance is still determined by the depletionlayer width.) The solid line of Fig.3 represents thecapacitance-voltage characteristic of an MOS capacitor.Fig.2Oxide capacitanceIn a power MOSFET the solid line is not actually observed;the formation of the inversion layer in the P-type materialallows electrons to move fromthe neighbouring N+-source,the inversion layer can therefore respond to a highfrequency gate signaland the capacitance returns to itsmaximum value, dashed line of Fig.3.Fig.3C-V plot for MOS capacitancePower MOSFET capacitancesFig.4Parasitic capacitance modelThe circuit model of Fig.4 illustrates the parasiticcapacitances of the Power MOSFET. Most PowerMOSdata sheets do not refer to these components but to inputcapacitance Ciss, output capacitance Coss and feedbackcapacitance Crss. The data sheet capacitances relate tothe primary parasitic capacitances of Fig.4 as follows:Ciss: Parallel combination of Cgs and CgdCoss: Parallel combination of Cds and CgdCrss: Equivalent to CgdFig.5 shows the cross section of a power MOSFET cellindicatingwheretheparasiticcapacitances occur internally.CoxCBias Voltage(Polysilicon to P-type silicon)Cox t4CgdCdsCgsGSDtoxideP type siliconPolysilicon30Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.5Cross section of a single PowerMOS cell showinginternal capacitanceThecapacitancebetweendrainandsourceisaP-Njunctioncapacitance, varying in accordance with the width of thedepletion layer, which in turn depends on the voltage beingsupported by the device. The gate sourcecapacitanceconsists of the three components, CgsN+, CgsPand CgsM.Of these CgsPis across the oxide which will vary accordingto the applied gate source voltage as described above.Of particular interest is the feedback capacitance Cgd. Itisthiscapacitancewhichplaysadominant roleduringswitching and which is also the most voltage dependent.Cgd is essentially two capacitors in series such thatCgsN+CgsMOxidePolysiliconN+P-PN-N+MetalizationSourceDrainGateCgdbulkCgdoxCgsPCds Depletion Layer1Cgd 1Cgdox +1Cgdbulk5Fig.6How Cgd is affected by voltageOxidePolysiliconN+P-PN-N+MetalizationSourceDrainGateDepletion Layer Widths Area of Oxide Capacitance Exposedfor Voltages V1 & V2For Three Applied VoltagesWidth for Cgdbulkat Voltage V3V3V2V131Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.6illustrateshowthis capacitanceisaffectedbythedrainto gate voltage. With a large voltage drain to gate, Cgdbulkis very smalldue to the wide depletion region and thusmaintains Cgd at a low value. As the voltage is reducedthedepletionregionshrinks until eventuallytheoxidesemiconductor interface is exposed. This occurs as Vdgapproaches 0 V. Cgdox now dominates Cgd. As Vdg isfurther reduced the drain will become negative with respectto the gate (normal on-state condition) an increasing areaof the oxide-semiconductor interface is exposed and anaccumulation layer forms at the semiconductor surface.Thenowlargearea of exposedoxideresults inalarge valuefor Cgdox and hence Cgd. Fig.7 shows Cgd plotted as afunction of drain to gate voltage. This illustrates the almoststep increase in capacitance at the point where Vgs = Vgd.Fig.7How Cgd varies with drain to gate voltageCharging cycle - The Gate ChargeOscillogramThe switching cycle of a power MOSFET can be clearlyobserved by applying a constant current to the gate andusing a constant current source as the load, Fig.8. In thiscircuit the MOSFETisturned on by feeding a constantcurrent of 1 mA on to the gate, conversely the device isturned off by extracting a constant current of 1 mAfromthegate. The gate and drain voltages with respect to sourcecan be monitored on an oscilloscope as a function of time.Since Q = it, a 1 sec period equates to 1 nc of chargeapplied to the gate. The gate source voltage can thus beplotted as a function of charge on the gate. Fig.9 showssuch a plot for the turn-on of a BUK555-100A, also shownis the drain to source voltage. This gate voltage plot showsthe characteristic shape which results from charging of thepower MOSFETs input capacitance. This shape arises asfollows: (NBthefollowinganalysisusesthetwocircuitmodels of Fig.10 to represent a MOSFET operating in theactive region (a) and the ohmic region (b). In the activeregion the MOSFET is a constant current source where thecurrent isafunctionof thegate-sourcevoltage. Inthe ohmicregion the MOSFET is in effect just a resistance.)Fig.8Gate charge circuitAt time, t0 (Fig.9), the gate drive is activated. Current flowsinto the gate as indicated in Fig.11(a), charging both Cgsand Cgd. Afterashort periodthe thresholdvoltage isreached and current begins to rise in the MOSFET. Theequivalent circuit is now as shown in Fig.11(b). The drainsourcevoltage remains at the supply level as long as id < I0and the free wheeling diode D is conducting.Fig.9Gate charge plot for a BUK555-100A (Logic LevelFET)VddVdg 0Cdg0 10 20 30 4026 24 22 20 18 16 14 12 10 8 6 4 2 0 (V)(us)(1us = 1 nc for Vgs plot)VdsVgsBUK555-100A(@ Id = 25 A)t0 t1 t232Introduction Power Semiconductor ApplicationsPhilips SemiconductorsThe current in the MOSFET continues to rise until id = I0,since the device is still in its active region, the gate voltagebecomes clampedat this point, (t1). The entire gate currentnowflows through Cgd causing the drain-source voltage todrop as Cgd is discharged, Fig.11(c). The rate at whichVds falls is given by:As Vdg approaches zero, Cgd starts to increasedramatically, reaching its maximumas Vdg becomesnegative. dVds/dt is now greatly reduced giving rise to thevoltage tail.Once the drain-source voltage has completed its drop tothe on-state value of I0.RDS(ON), (point t2), the gate sourcevoltage becomes unclamped and continues to rise,Fig.11(d). (NB dVgs/dQ in regions 1 and 3 indicates theinput capacitance values.)Fig.10Equivalent circuits for a Power MOSFET duringswitchingGDSCgdCgsid = f(Vgs)GDSCgdCgsRds(on)(a)(b)dVdsdt dVdgdtigCgd6Fig.11Charging the parasitic capacitance during turn-onVddCgdCgsIo(a) VddCgdCgsid = f(Vgs)Io(b)VddCgdCgsid = f(Vgs)Io(c)VddCgdCgsRds(on)Io(d)33Introduction Power Semiconductor ApplicationsPhilips SemiconductorsThe gate charge oscillogram can be found in the data forall Philips PowerMOS devices. This plot can be used todetermine the required average gatedrive current for aparticular switching speed. The speed is set by how fastthe charge is supplied to the MOSFET.Energy consumed by the switching eventIn the majority of applications the power MOSFET will bedriven not from a constant current source but via a fixedgate drive impedance froma voltage source. Fig.13 showsthevoltageonavoltageindependent capacitor asafunctionof charge. The area beneath the charge vs voltage curveequals the stored energy (E = Q.V/2). The area above thecharge vs voltage curve (bounded by the supply voltage)istheamount of energy dissipatedduringthe chargingcyclefrom a fixed voltage source. The total energy delivered bythe supply is therefore Q.V, where 1/2 Q.V is stored on thecapacitor to be dissipated during the discharge phase.Fig.12Gate charging cyclet0 t1 t2 t3 t4 t5 t61a 2a 3a1b 2b3b4a4bVggVddOutput Capacitance34Introduction Power Semiconductor ApplicationsPhilips SemiconductorsAlthough the voltage vs charge relationship for theMOSFETs gate is not linear, energy loss is easily identified.The following discussion assumes a simple drive circuitconsisting of a voltage source and drive resistance.Fromt0 to t1 energy is stored in the gate capacitance whichis equal to the area of region 1a. Since this charge hasfallen through a voltage Vgg - Vgs(t), the area of region 1brepresents the energy dissipated in the drive resistanceduring its delivery. Between t1 and t2 all charge entersCgd, the area of region 2a represents the energy stored inCgdwhile 2b againcorresponds with the energy dissipationin the drive resistor. Finally, between t2 and t3 additionalenergy is stored by the input capacitance equal to the areaof region 3a.Fig.13Energy stored on a capacitorThetotal energy dissipated inthedrive resistanceat turn-onis therefore equal to the area 1b + 2b + 3b. Thecorresponding energy stored on the input capacitance is1a + 2a + 3a, thisenergywillbedissipatedinthe driveresistance at turn-off. The total energy expended by thegate drive for the switching cycle is Q.Vgg.As well as energy expended by the drive circuit, aswitchingcycle will also require energy to be expended by the draincircuit due to the charging and discharging of Cgd and Cdsbetween the supply rail and VDS(ON). Moving from t5 to t6the drain side of Cgd is charged fromIo.RDS(ON)to Vdd. Thedrain circuit must therefore supply sufficient current for thischarging event. The total charge requirement is given bythe plateau region, Q6 - Q5. The area 4a (Fig.12) underthedrain-source voltage curve represents the energystored by the drain circuit on Cgd during turn-on. Region4b represents the corresponding energy delivered to theload during this period. The energy consumed from thedrain supply tocharge and discharge Cgd over oneswitching cycle is thus given by:(The energystored on Cgdduring turn-off is dissipatedinternallyintheMOSFETduringturn-on.) Additional energyis also storedon Cds duringturn-off which again isdissipated in the MOSFET at turn-on.The energy lost by both the gate and drain supplies in thecharging and discharging of the capacitances is very smallover 1 cycle; Fig.9 indicates 40 nc is required to raise thegate voltageto 10 V, delivered froma 10 V supplythisequates to 400 nJ; to charge Cgd to 80 V from an 80 Vsupply will consume 12 nc x 80 V = 1.4 J. Only asswitching frequencies approach 1 MHz will this energy lossstart to become significant. (NB these losses only apply tosquare wave switching, the case for resonant switching issome-what different.)Switching performance1) Turn-onThe parameters likely to be of most importance during theturn-on phase are,turn-on timeturn-on losspeak dV/dtpeak dI/dt.Turn-on time is simply a matter of howquickly the specifiedcharge can be applied to the gate. The average currentthat must be supplied over the turn-on period isFor repetitive switching the average current requirement ofthe drive iswhere f = frequency of the input signalTurn-on loss occurs during the initial phase when currentflows in the MOSFET while the drain source voltage is stillhigh. To minimise this loss, a necessary requirement ofhigh frequency circuits, requires the turn-on time to be assmall aspossible. Toachievefast switchingthe drivecircuitmust be able to supply the initial peak current, given byequation 10.VoltageChargeStored EnergySupply VoltageIon Qton8I Q.f 9WDD (Q6 Q5).(VDD VDS(ON)) 735Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.14Bridge CircuitOneof the main problems associated with very fastswitching MOSFETs is the high rates of change in voltageandcurrent. Highvaluesof dV/dt cancouplethroughparasitic capacitances to give unwanted noise on signallines. Similarly ahigh dI/dt may react with circuit inductancetogive problematic transients andovershoot voltages inthepower circuit. dI/dt is controlled by the time taken to chargethe input capacitance up to the plateau voltage, while dV/dtisgoverned by therate at which the plateau regionismovedthrough.Particular care is required regarding dV/dt when switchingin bridge circuits, (Fig.14). The free wheeling diode willhave associated with it a reverse recovery current. Whenthe opposing MOSFET switches on, the drain current risesbeyond the loadcurrent valueIo toa valueIo + Irr.Consequently Vgs increases beyond Vgt(Io) to Vgt(Io + Irr)as shown in Fig.15. Once the diode has recoveredthereis arapid decrease in Vgs to Vgt(Io) and this rapid decreaseprovidesadditional current toCgdontopof that beingsupplied by the gate drive. This in turn causes Vdg andVds to decrease very rapidly during this recovery period.ThedV/dt inthisperiodisdeterminedbytherecoveryproperties of the diode in relation to the dI/dt imposed uponit by the turn-on of the MOSFET, (reducing dI/dt will reducethis dV/dt, however it is best to use soft recovery diodes).Fig.15Gate charging cycle for a bridge circuitii) Turn-offTheparametersof most importanceduringtheturn-offphase are,turn-off timeturn-off losspeak dVds/dtpeak dId/dt.Turn-off of a power MOSFET is more or less the inverse oftheturn-onprocess. Themaindifferenceisthat thecharging current for Cgd during turn-off must flow throughboth the gate circuit impedance and the load impedance.A highload impedancewillthusslow down the turn-offspeed.The speed at which the plateau region is moved throughdetermines the voltage rise time. In most applications thecharging current for Cgd will be limited by the gate drivecircuitry. The chargingcurrent, assumingnonegativedrive,is simplyand the length of the plateau region will beT1T2D1D2LoadVdd0Vdd00Vgt(Io)Vgt(Io + Irr) Gate Source VoltageDrain Source VoltageMOSFET Current0IoIo + IrrDiode Current0IoIrrtIpk VGGRg10dVdsdtigCgd VGG VGTRG.Cgd11i VgtRG12tp Q.RGVgt1336Introduction Power Semiconductor ApplicationsPhilips SemiconductorsThe implications for low threshold (Logic Level) MOSFETsare clear fromthe above equations. The lower value of Vgtwill mean aslower turn-off for agivengateimpedance whencomparedtoanequivalent standardthresholddevice.Equivalent switching therefore requires a lower driveimpedance to be used.ConclusionsIn theory the speed of a power MOSFET is limited only bythe parasitic inductances of its internal bond wires. Thespeed is essentially determined by how fast the internalcapacitances can be charged and discharged by the drivecircuit. Switching speeds quoted in data should be treatedwith caution since they only reflect performance for oneparticular drive condition. The gate charge plot is a moreuseful way of looking at switching capability since itindicates how much charge needs to be supplied by thedrive to turn the device on. How fast that charge should beapplieddepends on the application andcircuit performancerequirements.37Introduction Power Semiconductor ApplicationsPhilips Semiconductors1.2.3Power MOSFET Drive CircuitsMOSFETs are being increasingly used in many switchingapplications because of their fast switching times and lowdrive power requirements. The fast switchingtimes caneasilyberealisedbydrivingMOSFETswithrelativelysimple drive circuits. The following paragraphs outline therequirementsof MOSFETdrivecircuits andpresent variouscircuit examples. Alook at the special requirements of veryfast switching circuits is also presented, this can be foundin the latter part of this article.The requirements of the drive circuitThe switchingof aMOSFETinvolves the charginganddischargingof thecapacitancebetweenthegateandsource terminals. This capacitance is related to the size ofthe MOSFET chip used typically about 1-2 nF. Agate-source voltageof 6Visusuallysufficient toturn astandard MOSFET fully on. However further increases ingate-to-source voltage are usually employed to reduce theMOSFETs on-resistance. Therefore for switching times ofabout 50ns, applyinga10 VgatedrivevoltagetoaMOSFETwith a 2 nFgate-source capacitancewouldrequire the drive circuit to sink and source peak currents ofabout 0.5 A. Howeverit isonlynecessarytocarrythiscurrent during the switching intervals.The gate drive power requirements are given in equation(1)where QG is the peak gate charge, VGS is the peak gatesource voltage and f is the switching frequency.Incircuits whichuseabridgeconfiguration, thegateterminalsof the MOSFETsin thecircuit need tofloat relativetoeachother. Thegatedrivecircuitrythenneedstoincorporatesomeisolation. Theimpedanceof thegatedrivecircuit should not be so large that there is a possibility ofdV/dt turn on. dV/dt turn on canbe causedby rapidchangesof drain to source voltage. The charging current for thegate-drain capacitance CGD flows through the gate drivecircuit. Thischargingcurrent cancauseavoltagedropacross the gate drive impedance large enough to turn theMOSFET on.Non-isolated drive circuitsMOSFETs can be driven directly from a CMOS logic IC asshown in Fig.1.Fig.1 A very simple drive circuit utilizing a standardCMOS ICFaster switching speeds can be achieved by parallellingCMOS hex inverting (4049) or non-inverting (4050) buffersas shown in Fig.2.Fig.2 Driving Philips PowerMOS with 6 parallelledbuffered inverters.A push pull circuit can also be used as shown in Fig.3.Theconnections betweenthe drivecircuit andthe MOSFETshould be kept as short as possible and twisted together ifthe shortest switching times are required. If both the drivecircuit and the terminals of the MOSFET are on the samePCB, thentheinductanceof tracks, betweenthedrivetransistors and the terminals of the MOSFETs, should bekept as small as possible. This is necessary to reduce theimpedanceof thedrivecircuit inorder toreducetheswitching times and lessen the susceptibility of the circuit401140490 V15 VPG QG.VGS.f 139Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.3A drive circuit using a two transistor push pullcircuit.to dV/dt turn-on of the MOSFET. Attention to layout alsoimproves the immunity to spurious switching byinterference.One of the advantages of MOSFETs is that their switchingtimescanbeeasilycontrolled. For exampleit mayberequired tolimit the rate of change of drain current to reduceovershoot onthedrainsourcevoltagewaveform. Theovershoot may be caused by switching current in parasiticlead or transformer leakage inductance. The slowerswitching can be achieved by increasing the value of thegate drive resistor.The supply rails should be decoupled near to fast switchingelements suchas thepush-pull transistorsinFig.3. Anelectrolytic capacitor in parallel with aceramic capacitor arerecommended since the electrolytic capacitor will not be alow enough impedance to the fast edges of the MOSFETdrive pulse.Isolated drive circuitsSome circuits demand that the gate and source terminalsof MOSFETs arefloating with respect to those of otherMOSFETs in the circuit. Isolated drive to these MOSFETscan be provided in the following way:(a) Opto-isolators.A drive circuit using an opto-isolator is shown in Fig.4.Adiodeintheprimarysideof theopto-isolator emitsphotons when it is forward biased. These photons impingeon the base region of a transistor in the secondary side.This causes photogeneration of carriers sufficient to satisfythe base requirement for turn-on. In this way theopto-isolator provides isolation between the primary andsecondary of the opto-isolator. An isolated supply isrequiredfor thecircuitryonthesecondarysideof theopto-isolator. This supply can be derived, in some cases,fromthe drain-to-source voltageacrossthe MOSFETbeingdriven as shown in Fig.5. This is made possible by the lowdrive power requirements of MOSFETs.Fig.4. An isolated drive circuit using an opto-isolator.40490 V15 VOpto-Isolator5 V40Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.5. An opto-isolated drive circuit with the isolated power supply for the secondary derived from the drain sourcevoltage of the MOSFET.40490 V15 VOpto-Isolator5 VSomeopto-isolators incorporateaninternal screentoimprove the common mode transient immunity. Values ashigh as 1000 V/s are quoted for common mode rejectionwhichis equivalent torejecting a 300Vpeak-to-peaksinewave.Thefaster opto-isolatorsworkoff amaximumcollectorvoltage on the secondary side of 5V so some form of levelshifting may be required.(b) Pulse transformers.A circuit using a pulse transformer for isolation is shown inFig.6(a).When T2 switches on, voltageis applied across the primaryof the pulse transformer. The current through T2 consistsof thesumof thegatedrivecurrent for T1andthemagnetisingcurrent of thepulsetransformer. Fromthewaveforms of current and voltage around the circuit shownin Fig.6(b), it can be seen that after the turn off of T2 thevoltage across it rises to VD + VZ, where VZ is the voltageacross the zener diode ZD. The zener voltage VZ appliedacross the pulse transformer causes the flux in the core tobe reset. Thus the net volt second area across the pulsetransformer is zero over a switching cycle. The minimumnumber of turns on the primary is given by equation (2).where B is the maximum flux density, Ae is the effectivecross sectional area of the core and t is the time that T2 ison for.The circuit in Fig.6(a) is best suited for fixed duty cycleoperation. The zener diode has to be large enough so thatthe flux in the core will be reset during operation with themaximumdutycycle. For anydutycyclelessthanthemaximum there will be a period when the voltage acrossthe secondary is zero as shown in Fig.7.In Fig.8 a capacitor is used to block the dc components ofthe drive signal.Drive circuits using pulse transformers have problems if awidely varying duty cycle is required. This causes widelyvarying gate drive voltages when the MOSFET is off. Inconsequence there are variable switching times andvarying levels of immunity to dV/dt turn on andinterference.There are several possible solutions to this problem, someexamples are given in Figs.9 - 12.N V.tB.Ae241Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.6(a)A circuit using a pulse transformer for isolation.Fig.6(b)Waveforms associated with pulse transformer.Fig.7. The voltage waveforms associated with the circuitin Fig.6(a) with varying duty cycles.In the circuit shown in Fig.9 when A is positive with respectto B the input capacitance of T1 is charged through theparasitic diode of T2. The voltage across the secondary ofthe pulse transformer can then fall to zero and the inputcapacitance of T1 willremain charged. (It is sometimesnecessary to raise the effective input capacitance with anexternal capacitor as indicated by the dashed lines.) WhenB becomes positive with respect to A T2 will turn on andthe input capacitance of T2 will be discharged. The noiseimmunity of the circuit can be increased by using anotherMOSFET as shown in Fig.10.Fig.8. A drive circuit using a capacitor to block the dccomponent of the drive waveforms.Fig.9. A drive circuit that uses a pulse transformer forisolation which copes well with widely varying dutycycles.Fig.10. An isolated drive circuit with good performancewith varying duty cycles and increased noise immunity.In Fig.10 the potential at A relative to B has to be sufficientto charge the input capacitance of T3 and so turn T3 onbefore T1 can begin to turn on.T1T2ZDVd0 VT1PrimaryVoltageVoltageAcross T2timetimeT1ABT2timetimeHighDutyCycleLowDutyCycleSecondaryVoltageT1ABT2T342Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFig.11. A drive circuit that reduces the size of the pulse transformer.T1Q1h.f. clockdrive signalIn Fig.11 the drive signal is ANDed with a hf clock. If theclockhasafrequencymuchhigher thantheswitchingfrequency of T1 then the size of the pulse transformer isreduced. Thehf signal onthesecondaryof thepulsetransformer is rectified. Q1 provides a low impedance pathfor discharging the input capacitance of T1 when the hfsignal on the secondary of the pulse transformer is absent.Fig.12 Example of pulse transformer isolated drive with a latching buffer15 VZHEF400972k22k210T 20T47 pF18 k1 k c18vDC LinkO V100RFX38488 uF2n243Introduction Power Semiconductor ApplicationsPhilips SemiconductorsFigure 12 shows a hex non-inverting buffer connected onthe secondary side, with one of the six buffers configuredas a latch. The circuit operates such that the positive goingedge of the drive pulse will cause the buffers to latch intothe high state. Conversely the negative going edge of thedrive pulse causes the buffers to latch into the low state.With the component values indicated on the diagram thiscircuit can operate with pulse on-times as lowas 1 s. Theimpedance Z represents either the lowsideswitch in abridge circuit (which can be a MOSFET configured withidentical drive) or a low side load.The impedance of the gate drive circuit may be used tocontrol theswitchingtimes of the MOSFET. Increasinggatedrive impedance however can increase the risk of dV/dtturn-on. Totryandovercomethisproblemit maybenecessary to configure the drive as outlined in Fig.13.(a)(b)Fig.13. Two circuits that reduce the risk of dV/dt turn on.The diode in Fig.13(a) reduces the gate drive impedancewhenthe MOSFETis turned off. In Fig.13(b) when the drivepulse is taken away, the pnp transistor is turned on. Whenthepnptransistor is onit short-circuits the gatetothesourceand so reduces the gate drive impedance.High side drive circuitsThe isolated drive circuits in the previous section can beused for either high or low side applications. Not all highside applications however require an isolated drive. Twoexamples showing how a high side drive can be achievedsimply witha boot strap capacitor areshown in Fig.14. Boththese circuits depend upon the topping up of the charge onthe boot strap capacitor while the MOSFET is off. For thisreason these circuits cannot be used for dc switching. Theminimum operating frequency is determined by the size oftheboot strapcapacitor(andR1incircuit (a)), astheoperatingfrequency is increasedsothe valueof thecapacitor can be reduced. The circuit example in Fig. 14(a)has a minimum operating frequency of 500 Hz.Fig.14(a) Drive circuit for a low voltage half bridgecircuit.At high frequencies it may be necessary to replace R1 withthe transistor T3 as shown in Fig.14(b). This enables veryfast turn-off times which would be difficult to achieve withcircuit (a) since reducing R1 to a lowvalue would cause theboot strap capacitor to discharge during the on-period. Theimpedance Z represents either the low side switch part ofthe bridge or the load.Fig.14(b) Modification for fast turn-off.Very fast drive circuits for frequencies upto 1 MHzThe following drivecircuits canchargethe gatesourcecapacitance particularly fast and so realise extremely shortswitching times. These fast transition times are necessarytoreduce theswitchinglosses. Switchinglosses aredirectlyproportional totheswitchingfrequency andaregreater thanconduction losses above a frequency of about 500 kHz,VinT1T2C 6.8uFR1 47R10k22k1k0Z24V0VT1D1R1R2T124VVinT1T2CT3Z0V44Introduction Power Semiconductor ApplicationsPhilips Semiconductorsalthough this crossover frequency is dependent on circuitconfiguration. Thus for operationabove 500 kHz it isimportant to have fast transition times.At frequencies below 500 kHz the circuit in Fig.15 is oftenused. Above 500 kHz the use of the DS0026 instead of the4049 is recommended. The DS0026 has a high currentsinking and sourcing capability of 2.5 A. It is a NationalSemiconductor device and is capable of charging acapacitance of 100 pF in as short a time as 25 ns.Fig.15 A MOSFET drive circuit using a hex CMOSbuffered inverter ICIn Fig.16 the value of capacitor C1 is made approximatelyequal to the input capacitance of the d