power semiconductor device physics part 1 & 2 : prof. j.p. chante december 02 th, 2002 ñin...

Power semiconductor device physics Part 1 & 2 : Prof. J.P. Chante December 02th, 2002

DrainGate

P-substrate

N+ N+

Bulk

Source

In order to determine the electrical characteristics (threshold voltage) of the transistor, it is easier to study the MOS capacitor first.

Gate

Silicon

Bulk

The ideal Mos Capacitor


The MOS capacitor is a poly-Si/SiO2/Si structure.

Gate

P-typeSilicon

Bulk

P-type silicon substrate

Insulating layer SiO2

Back-side metallization

Gate-contact : polysilicon



VGB < 0

When negative voltage is applied to the gate with respect to the semiconductor :

Potential is applied between insulating layer and semiconductor Electric field appears toward the gate majority carriers (holes) are attracted to the surface of the p-type semiconductor

The semiconductor near the surface becomes more p-type : accumulation



VGB > 0

When positive voltage is applied to the gate with respect to the semiconductor :

Electric field appears toward the drain The positive voltage will induce a negative charge to appear near the surface

of the p-type semiconductor The semiconductor near the surface becomes less p-type :

depletion



VGB = Vth the threshold voltage Vth is defined as the applied voltage when the electron concentration is two times bigger than the initial hole concentration

the region near the surface in this case has conduction properties of n-type material the n-type surface layer is formed not by doping but instead by inversion of the originally p-type

material due to the applied voltage this inverted region separated from the underlying p-type material by a depletion layer is the basis of

MOSFET operation



VGB > 0 and more than Vth

With further increase in positively applied voltage, and higher than the threshold voltage Vth :

electric field remains toward the bulk electric field magnitude is high in the semiconductor minority carriers (electrons) are attracted towards the surface when the electron concentration is bigger than the hole concentration, a thin n-type layer is created the semiconductor near the surface becomes n-type :

inversion



Field-effect transistors (FET) operation is based on an electric field effect (established by a voltage applied to the control gate terminal)

FETs are also called unipolar transistor since the current is conducted by only one type of carrier

MOSFET stands for Metal-Oxide-Semiconductor FET even though all advanced VLSI processes uses polysilicon gate rather than metal gate

Properly bias of transistor is : source and bulk are short-

circuited and grounded gate to source voltage is VGS

drain to source voltage is VDS

The Mosfet Transistor

DrainGate

P-substrate

N+ N+

Bulk

Source


The MOSFET is a normally off device. With a small negative VGS, more holes will be attracted to

the surface underneath the gate. Source and bulk are grounded and then the source-

bulk junction is in equilibrium state drain voltage is positive and then drain-bulk junction is

reverse biased No current path exists.

The Mosfet Transistor (cont’d) : VGS < 0 and VDS > 0


With a small positive VGS, holes will be pushed away from the surface underneath the gate. Source-bulk junction is in equilibrium state Drain-bulk junction is reverse biased

No current or small current exists between drain and source.

The Mosfet Transistor (cont’d) : VGS > 0 and VDS > 0

(VGS < Vth )


Electrons will begin to accumulate, forming a conduction channel.

Small VDS has no influence on VGS bias and then the channel is uniform

Current path exists between drain and source

VGS influences the electron concentration in the conduction channel : as VGS increases, the concentration

increases, on-state resistance decreases linear variation of the current versus drain

voltage VDS

The Mosfet Transistor (cont’d) : VGS > 0 and small VDS > 0

(VGS > Vth )


As VDS increases, drain-bulk junction is highly reverse biased and then SCR is stretched

the potential difference between the gate and the drain decreases. The channel formed will no longer be uniform and begin to tapper off near the drain end. The voltage VDS is noted VDSsat

DrainGate

P-substrate

N+ N+

Source

Bulk

N+

+

VDS>0

+

V GS>V TH

The Mosfet Transistor (cont’d) : VGS > 0 and high VDS > 0

(VGS > Vth )


Eventually the channel at the drain end will disappear as VDGVTH.

The drain current will not shut off abruptly, but instead will remain at the same level called IDSsat.

The pinched channel can be considered as a choke point. This point moves toward the source as VDS increases.

Current is due to the electrons flow in the conduction channel, due to the electric field (Drain toward Source).

The Mosfet Transistor (cont’d) : VGS > 0 and high VDS > 0

(VGS > Vth )


MOSFETs have two regions of operation : the triode the saturation regions.

Mosfet Operation (cont’d)

vD S > vGS V TvD S< vGS V T

Saturation region(active region)

Triode(linear region)

V GS increease

VGS V T+1

VGS V T

vD S

iD


The threshold voltage can be changed by deliberately adjusting the doping concentration near the surface of the channel.

In the extreme, a channel can be formed (by ion-implantation) without an applied voltage. This type of MOSFET is called depletion mode device.



Drain current is proportional to the channel width Z, and inversely proportional to length L,

Current in the transistor is limited to few mA L should be as short as possible, and also the doping level

of the channel (in order to have a small Vth) :

source gate drain

LZ

N+ N+

P

bulk

SCR of drain-bulk junction can reach source-bulk junction even for small VDS voltage

Maximum voltage of VDS is limited

This structure is not suitable for power



High voltage device requires a low doped and thick layer. High current device needs numerous basic cell in parallel vertical structure is the solution

epitaxial

layer

source m etallization

polysilicongate

P w ell

drain m etallization

source cell

channel

N-

N+

The Mosfet transistor structure


High voltage device requires a low doped and thick layer. High current device needs numerous basic cell in parallel vertical structure is the solution

Conduction channel is formed in p-type region underneath the gate.

N-type low doped layer allows to achieve high breakdown voltage Electrons reach the n-type layer and then flow vertically toward

the drain Low doped region is resistive and then it is necessary to reduce

current density



As VDS increases, SCR stretches in n-type and p-type zone.

Conduction channel is pinched-off Electric field in SCR sweeps

the electrons toward the drain



Source

Gate

P+N+ N+

P

N-

R P

N+

RN

Drain

The Mosfet transistor equivalent circuit


Advantages and drawbacks of MOSFET Advantages

MOSFET transistor is unipolar deviceconduction is conducted by majority carriers lack of storage charge involves a high switching speed

MOSFET transistor is fast

Control is made through a voltage applied to the gate (capacitor)during steady state, voltage is sufficientduring transient switching, a dynamic current is required to load and unload the input capacitorControl energy is necessary only during the switchings

MOSFET transistor is easy to control

The Mos-Bipolar Power Devices


Drawbacks

Conduction assumed by majority carriers requires electric fieldvoltage drop in the layersthis voltage drop increases as :

breakdown voltage is highercurrent density is higher

losses are important in a power MOSFET

Conduction losses are important in MOSFET



Advantages and drawbacks of Bipolar Drawbacks

Conduction with minority carriers implies storage chargeduring transient switching, this charge needs to be loaded and unloadedswitching time is slow in bipolar transistor

Bipolar transistor is relatively slowcontrol of the device requires currentcontrol requires energy during all conduction periods

Control of Bipolar transistor requires energy



Advantages and drawbacks of Bipolar Advantages

Conduction is assumed by both type of carriersBasic principle of conduction is diffusion of carriers

electric field in the layers is lowsmall forward voltage dropsmall conduction losses

Conduction losses are small in bipolar transistor

In order to profit by advantages of both types of transistor :

MOS-Bipolar Power Devices



Top structure is identical to MOSFET Substrate is p-type

two kinds of IGBT :

with buffer layerhomogeneous base

Insulated Gate Bipolar Transistor (IGBT)


Forward bias of transistor is : emitter and bulk are short-circuited

and grounded gate to emitter voltage is VGE

collector to emittter voltage is VCE > 0

In forward mode, J1 is forward and J2 is reverse

n-type buffer layer allows to reduce the thickness of N- layer and avoid punch-through of J1

IGBT with buffer layer



Top structure is identical to the previous one

punch through is avoided thanks to a thick n-type layer

P+-layer is very thin

IGBT with homogeneous base



For both types of IGBT, a positive voltage VGE will involve a conduction channel in p-type layer underneath the gate

As VCE is higher than Vbi of J1, then MOS part of the device will inject electrons in n-type layer

N-type layer is the base of a PNP transistor, where J1 is collector-base and J2 is emitter-base junction

MOS part of the device supplies the base current of the bipolar PNP transistor Then junction J1 injects holes in n-type layer

Holes diffuse in n-type layer and are collected by J2



Em itter

Gate

P+N+ N+

P

N-

R P

P+

Collector

N-




High input impedance and high current gaIn

Turn off by zero gate voltage (remove the conducting channel)

Faster switching speed than BJT and can operate in medium power up to 20 kHz

Improved input and output capacitances

C

E

G



Turn off of the device can be divided in two parts : gate to emitter voltage VGE decrease will induce

the break of conduction of the MOS transistor

• bipolar transistor has then a non connected base

bipolar transistor will remove the storage charge either by collector current or recombination

• The decrease of the current is slower with a time constant depending on the lifetime of the minority carriers

Effect of the minority carrier lifetime on the current queue



Structure and circuit used for the turn off60 µm

30 µm

8 µm

1014 cm-3

10 µm/ 1016 cm-3

10 µm/ 1018 cm-3



Doping concentration in the device

P-type buried layer

Base

Buffer layer

Co

nce

ntr

atio

n [

cm-3]

depth [µm] width [µm]


Switching off of the IGBT : t = 0

Storage charge in the base is important (in the range of 1016 cm-3)

Electron distribution Hole distribution

Co

nce

ntr

atio

n [

cm-3]

Co

nce

ntr

atio

n [

cm-3]

depth [µm]width [µ

m]


m]


MOS part of the device stops supply the base current of the bipolar PNP transistor

SCR will stretch in the base by sweeping the carriers

Co

nce

ntr

atio

n [

cm-3]

Co

nce

ntr

atio

n [

cm-3]


m]


m]

Switching off of the IGBT : t = 80 ns


As reverse voltage increases, SCR is stretched Storage charge has drastically decreased

Co

nce

ntr

atio

n [

cm-3]

Co

nce

ntr

atio

n [

cm-3]


m]


m]

Switching off of the IGBT : t = 1 µs


Switching Characteristics

Ideal Switch : No power Limit (unlimited breakdown voltage and forward

current) Zero turn-on and turn-off times (infinite frequency of operation) No power dissipation (no on-resistance and no leakage current)

Practical switch : Limited power handling capabilities (max voltage and max

current) Delayed turning on and off (limited frequency of operation) On-resistance and off-leakage current (power dissipation)


Ideal Switching Characteristic Curves :

v sw V off

V on time

isw

Ioff

Ion

time

p ( t)

time


Non-Ideal Characteristic Curves :

v sw

V off

V ontime

isw

Ioff

Ion

time

p ( t)

time

P maxP min

• Different losses should be considered :

• conduction losses

• off losses

• switching losses


Power Diode

V F

V BR

IF

Is

iD

vD

vD

iD

ON

OFF

I-V characteristic

Typical I-V characteristic Ideal I-V characteristic


Thyristor

Forward currentcarrying(ON)

Forward voltageblocking(OFF)

Reverse voltageblocking

ON

iA

vA K


+

vAK

_

iA

ig

Anode (A)

Cathode (K)

iA

ig1

vA K

Forward blockingregion

Latching currentHolding current

Forward breakovervoltage

ig3>i g2>i g1

ig=0ig1ig1ig1ig1

Max reversevoltage

Reverse blockingregion

vA K

Reverseavalanche region

I-V characteristic


Bipolar Junction Transistor (BJT)

I-V characteristic

iC

vC E

Cut-OFF(OFF-state)

Saturation(OFF-state)

Active region Increasingbase

current iC

vC E

ON-state

OFF-state

Ideal switch characteristics


+

vC E

_

iC

iB


Power MOSFETI-V characteristic

vD S > vGS V TvD S< vGS V T

Saturation region(active region)

Triode(linear region)

V GS increease

VGS V T+1

VGS V T

vD S

iD

Typical I-V characteristic

+

vD S

_

Drain (D)

Source (S)

Gate (G)


Thermal model of the system

S em i-co nd uc teur

A l O32 D issip a teur

Q

C1

2

R 2

C 3C2 +2

R 3R 1

R c

T aQin

C1 C2+2

C 3

2

C1

6C2

6

C 3

6

Heat sinkPower Chip

Thermal flux

Substrate

In order to estimate the maximum junction temperature

power semiconductor device physics part 1 & 2 : prof. j.p. chante december 02 th, 2002 ñin...

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