1040 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008

Power Trench MOSFET Devices onMetal Substrates

Qi Wang, Minhua Li, Yuri Sokolov, Arthur Black, Hamza Yilmaz, Jan V. Mancelita, and Romel Nanatad

Abstract—Power trench MOSFET devices have been accom-plished on Cu substrates using a novel silicon-on-metal (SOM)technology. This technology transfers silicon trench MOSFETdevice layers from SOI wafers to metal substrates. The prototype30-V (drain-to-source voltage) n-channel SOM device with a pitchof 2.5 µm comprises a 5-µm device layer and an electroplatedCu substrate. These devices are the first of their kind exhibitinga negligible substrate drain contribution to their specific Rdsonand have a specific Rdson of 0.198 mΩ · cm2 at a gate voltage of10 V. This specific Rdson is 38% smaller than that of the samedevice on the silicon substrate. The dc–dc converter with SOMdevices shows 11% reduction in device power loss and an energyefficiency of about 2% higher than with the same Si-based devices.The operating temperature of the SOM die in the converter is also9 C lower than the Si-based die. The “cooler” SOM device is dueto primarily improved energy efficiency. The transient thermalresistance of the SOM device is 20 C/W, which is less than halfof 57.5 C/W for the Si-based device at a pulse duration of 10 s.

Index Terms—High energy efficiency, low specific on-resistance,low transient thermal resistance, silicon-on-metal (SOM),substrate transfer.

I. INTRODUCTION

POWER TRENCH MOSFET (UMOSFET) devices havebeen used in laptop computers, cell phones, and other

portable devices for their ability to achieve low specific on-resistances (specific Rdson) [1]–[3]. The main effort in reduc-ing the UMOSFET specific Rdson so far has been devotedto device lateral scaling or pitch reduction. This approachis effective in reducing the channel resistance [1]. The pitchreduction, however, causes gate charge increase, which de-teriorates the UMOSFET switching performance. Aggressivepitch reduction also manifests the silicon substrate contributionto the specific Rdson because silicon substrate is part of theUMOSFET drain [4]. Our previous study shows that 30-V(drain-to-source rating) n-channel UMOSFET devices with apitch of 4.0 µm have specific Rdsons of which only 25% isfrom the silicon substrate (with resistivities of 3.5 mΩ · cm andthicknesses of 200 µm) [5]. For the same device, reducing thepitch to 1 µm gives rise to a 60% substrate contribution to thedevice specific Rdson. Therefore, minimizing silicon substrate

Manuscript received February 19, 2008; revised March 21, 2008. The reviewof this letter was arranged by Editor S.-H. Ryu.

Q. Wang, M. Li, and Y. Sokolov are with Fairchild Semiconductor Corpora-tion, West Jordan, UT 84088 USA (e-mail: qi.wang@fairchildsemi.com).

A. Black and H. Yilmaz are with Fairchild Semiconductor Corporation,San Jose, CA 95134 USA.

J. V. Mancelita and R. Nanatad are with Fairchild Semiconductor Corpora-tion, MEPZA, Lapulapu 6015, Philippines.

Color versions of one or more of the figures in this letter are available onlineat http:ieeexplore.ieee,org.

Digital Object Identifier 10.1109/LED.2008.2000603

contribution is more effective in reducing the specific Rdsonof small-pitch UMOSFET devices. Moreover, reducing siliconsubstrate contribution results in no device gate charge increase,which usually accompanies the pitch reduction.

This letter presents a technology to transfer UMOSFETsilicon device layers to metal substrates at the end of the devicefabrication, which is referred to as silicon-on-metal (SOM)technology. The prototype SOM devices exhibit significantlyimproved specific Rdson, energy efficiency, thermal conduc-tance, and comparable gate charge.

II. DEVICE FABRICATION

Instead of doing backside patterning, as shown in most sub-strate transfer works [6]–[8], the SOM technology utilizes theSOI wafer to eliminate silicon substrate at wafer level [9]. Theprototype 30-V n-channel devices had a pitch of 2.5 µm andwere fabricated on 6-in wafers. The technology has two mainsteps, as shown in Fig. 1. The first step is device fabrication onSOI wafers [Fig. 1(a)]. The SOI wafer comprises a buried oxidelayer (BOX) that is 0.3-µm thick over a lightly boron-dopedhandle wafer, a heavily As-doped silicon layer (2 × 1019cm−3)that is 1.5-µm thick over the BOX, and an epitaxial layer withthe required thickness and resistivity over the As-doped layer.The second step is the handle wafer elimination and the Cusubstrate formation [Fig. 1(b)]. The front side of the processedwafer was first bonded to a Pyrex glass carrier using temporaryadhesive. The handle wafer was then ground to 60 µm, followedby a chemical etch until the BOX layer. The BOX layer wasremoved next by HF etching to expose the As-doped layer.The contact/barrier metal layers Ti and Ni were subsequentlysputtered onto the As-doped layer followed by a Cu seed layer.A thick Cu layer was then electroplated onto the Cu seed layerand served as both drain electrode and mechanical support forthe device layer. Once the thick Cu layer was complete, thewhole structure was released from the glass carrier and theSOM wafer was formed. A stained SEM cross-section image ofthe SOM device is shown in Fig. 1(c). The device structure ishighlighted with a clearly defined source, well, and trench gate.The total silicon device layer is 5 µm. The lower left inset inFig. 1(c) is a TEM cross-section image of the interface betweensilicon and contact/barrier metals. No defect that might changeelectrical characteristics was observed. The Ti layer is 0.22 µm,and the Ni layer is 0.12 µm.

The comparison devices were built on conventional As-doped silicon wafers with a carrier concentration of 2 ×1019cm−3. The final wafer thickness was 200 µm. Both SOMand conventional wafers were diced and packaged in the type

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WANG et al.: POWER TRENCH MOSFET DEVICES ON METAL SUBSTRATES 1041

Fig. 1. SOM device fabrication schematic and its structure. (a) Device fabri-cation on SOI structure. (b) Handle wafer removal and Cu support substrateformation. (c) SEM cross-section image of the prototype SOM device. Thedevice structure consists of a 5-µm device layer on Cu substrate. The inset isthe TEM cross section of the interface between silicon and contact (Ti)/barrier(Ni) metals.

of TO-252 [10]. All the device characterizations were donein the packaged form. Transient junction-to-ambient thermalresistance measurement was carried out by mounting the SOMand Si-based dies on a minimum Cu TO-220 case.

III. DEVICE CHARACTERIZATION

Fig. 2 shows the output conductance and reverse blockingvoltage of the SOM devices. The breakdown voltage is 34.23 V,which is slightly higher than that of the same Si-based device.The leakage level is < 10 nA at a reverse bias voltage of 25 V.Table I summarizes the measured electrical properties of

Fig. 2. I–V characteristics of SOM devices under (left side) forward bias atdifferent gate voltages (Vgs − Vth) and (right side) reverse bias.

both SOM and Si-based devices. The average leakage currentof SOM dies, which is 2.75 nA, although higher than the1.32 nA of its Si-based counterparts in the same experiment,is still comparable to that of a typical trench MOSFET.

The threshold voltage of the SOM devices is lower than itsSi-based counterparts. This discrepancy is proven in the laterexperiments due to the process variation. The Si-based dieshave specific Rdsons of 0.378 and 0.319 mΩ · cm2 at gatevoltages (Vgs) of 4.5 and 10 V, respectively. The correspondingspecific Rdsons of the SOM dies are 0.244 and 0.198 mΩ · cm2,which are about 38% smaller. Moreover, the SOM deviceshave a total gate charge (Qg) of 22.1 nC and a gate-to-draincharge (Qgd) of 8.35 nC, which is comparable to a Qg of22.8 nC and Qgd of 8.50 nC for the Si-based devices. At theVgs of 10 V, the substrate contribution to the specific Rdsonis 35% for the Si-based device [5]. These results show thatSOM technology eliminates the substrate contribution to thespecific Rdson without increasing gate charge. The figure ofmerit (FOM) of the SOM device is 96.5 mΩ · nC, which is38% smaller than that of the Si-based dies [11], [12], and isproportional to the specific Rdson improvement. To study theefficiency improvement in their switching applications, SOMdies were applied to a single phase dc–dc synchronous buckconverter with input voltage, output voltage, and switchingfrequency of 12 V, 1.2 V, and 250 kHz, respectively [13], [14].The high side switch of the converter used the 30-V Si-baseddie. Either a SOM or a Si-based die was used as low sideswitch for comparison. Fig. 3(a) shows measured efficiency forboth SOM and Si-based dies. At a very low output current,the converter with either SOM or Si-based dies shows almostidentical efficiency because, at this current level, the high sideswitching loss dominates the efficiency. At an output currentof 30 A, compared to its Si-based counterpart, the SOM diereduced the converter energy loss by 11% from 9.78 to 8.68 Wand exhibited 2% higher energy efficiency. This improvementdirectly results from the significantly reduced specific Rdsonof the SOM dies. This improvement also leads to a muchreduced device operating temperature. The maximum operatingtemperature for a SOM die at 30 A is 75.2 C, compared to84.2 C for the Si-based die. The cooler SOM die may alsobenefit from a possible thermal resistance (rth) reduction.

The thermal characterization shows that the SOM devicestructure exhibits a much reduced transient rth [Fig. 3(b)]. At

1042 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 9, SEPTEMBER 2008

TABLE IELECTRICAL PROPERTIES OF 30-V UMOSFET ON BOTH Si AND Cu SUBSTRATES. SEE [11] AND [12] FOR FOM DEFINITION

Fig. 3. (a) Energy efficiency versus output current in synchronous buck converter and (b) transient thermal resistance versus current pulse duration time for bothSOM and its Si-based counterpart devices. Solid line: SOM die. Dashed line: Si-based die.

a pulse duration of 10 s, the rth of the SOM die is 20 C/W,compared to 57.5 C/W for its Si-based counterpart. At a pulseduration of 1000 s, the rth’s of SOM and Si-based dies are74 and 77.5 C/W, respectively. The difference is 3.5 C/W.This difference may indicate a junction-case rth reduction forthe SOM die and is due to a better thermal conductivity of Cudrain/substrate.

IV. CONCLUSION

For the first time, metal drain UMOSFETs have been suc-cessfully fabricated by using the SOM technology. This deviceconsists of a 5-µm silicon device layer and a 60-µm Cu sub-strate. Without increasing the gate charge, the SOM structurehas eliminated the silicon substrate drain contribution to spe-cific Rdson, which leads to a 38% specific-Rdson reduction forthe prototype device. The SOM structure also has a drasticallyimproved rth compared to the Si-based structure. The improvedspecific Rdson of SOM dies gives rise to a 2% energy efficiencyimprovement and 11% energy loss reduction than its Si-basedcounterpart in a dc–dc converter.

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